An LED chip structure and a preparation method thereof

Abstract

The present disclosure relates to the technical field of LED chips, and in particular, to an LED chip structure and a manufacturing method thereof. The present disclosure provides an LED chip structure and a manufacturing method thereof. Among them, the structure includes: a substrate, and a nucleation layer, a buffer layer, and an n-type GaN layer stacked in sequence on the substrate; an isolation layer located on the n-type GaN layer; a nano-column array penetrating the isolation layer, where the nano-column array includes a plurality of nano-column units arranged in an array, and each nano-column unit includes a plurality of nano-columns with different diameters. By forming a nano-column array on the LED chip, since the nano-column array contains nano-columns with a variety of different diameters, the emission of light with different wavelengths can be achieved, so that high-pixel and high-light-efficiency full-color display of the LED chip can be realized; and because full-color display is integrated on the LED chip, the massive transfer and bonding technologies used in traditional LED display manufacturing are avoided, significantly improving the yield of the LED chip and significantly reducing the manufacturing cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field of LED chips, and particularly to an LED chip structure and a preparation method thereof. Background Art

[0002] The size of Micro-LED (micro light-emitting diode) chips is usually below 50 micrometers, and they have advantages such as low power consumption, high contrast, high responsiveness, long lifespan, and high reliability. They are known as the "new generation display technology" and have received extensive attention from the academic and industrial circles at home and abroad.

[0003] The key to realizing the large-scale commercialization of Micro-LED chips lies in high-quality material epitaxial growth, high-precision and high-yield chip mass transfer printing, and the full-color technology based on red, green, and blue trichromatic Micro-LEDs. One of the most critical challenges restricting the application of full-color Micro-LED displays is the mass transfer printing technology, that is, how to batch transfer and integrate the full-color Micro-LED chips of red, green, and blue trichromatic colors onto the driving circuit substrate. Existing transfer printing technologies such as roller transfer printing and self-assembly transfer printing still have certain deficiencies in realizing batch and high-precision selective transfer printing. Therefore, there is an urgent need to develop a preparation method for full-color Micro-LED chips with large batch size, controllable process, and low cost.

[0004] Since full-color Micro-LED displays generally require high-yield and high-light-efficiency red, green, and blue trichromatic Micro-LED chips, blue III-nitride Micro-LEDs are generally used for actual production and preparation. However, as the emission wavelength gradually shifts to green and red, due to problems such as wavelength uniformity and spectral broadening caused by quantum well composition and structural fluctuations, the luminous efficiency of green and red Micro-LEDs decreases and their optoelectronic performance deteriorates, hindering the application process of III-nitride Micro-LED full-color displays. Therefore, how to achieve high-light-efficiency full-color Micro-LEDs is one of the problems that need to be solved by those skilled in the art. Summary of the Invention

[0005] The present disclosure provides an LED chip structure and a preparation method thereof to at least solve the above technical problems existing in the prior art.

[0006] According to the first aspect of the present disclosure, an LED chip structure is provided, wherein the structure includes:

[0007] a substrate, and a nucleation layer, a buffer layer, and an n-type GaN layer sequentially stacked on the substrate;

[0008] an isolation layer located on the n-type GaN layer;

[0009] A nanowire array penetrating the isolation layer, wherein the nanowire array includes a plurality of nanowire units arranged in an array, and each nanowire unit includes a plurality of nanowires with different diameters.

[0010] In one implementable embodiment, in each nanowire unit, the plurality of nanowires with different diameters are arranged in the order of diameter size along a first direction, wherein the first direction is a direction parallel to the substrate plane; or,

[0011] In each nanowire unit, the plurality of nanowires with different diameters are arranged in a polygon.

[0012] In one implementable embodiment, the plurality of nanowire units are arranged in an array along a row direction and a column direction, wherein the nanowire units in adjacent rows and adjacent columns are respectively aligned with each other.

[0013] In one implementable embodiment, the plurality of nanowire units are arranged in an array along a row direction and a column direction, wherein the nanowire units in adjacent rows and adjacent columns are respectively arranged in a staggered manner, and the nanowire units separated by one row and one column are respectively aligned with each other.

[0014] In one implementable embodiment, the material of the isolation layer includes at least one of silicon dioxide or aluminum oxide.

[0015] In one implementable embodiment, the diameter range of the nanowires is 0.05 - 50 μm, and the distance between two adjacent nanowires is 0.1 - 10 μm.

[0016] In one implementable embodiment, the height of the nanowires is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nanowires and the height of the isolation layer is less than or equal to 30 nm.

[0017] In one implementable embodiment, the shape of the projection of the nanowires in the direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

[0018] In one implementable embodiment, the nanowires include a stress buffer layer, an active region light-emitting layer, an electron blocking layer, and a p-type GaN layer stacked in sequence.

[0019] In one implementable embodiment, the structure further includes:

[0020] A transparent conductive layer located on the isolation layer;

[0021] A first electrode located on the transparent conductive layer and a second electrode located on the n-type GaN layer;

[0022] A passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode, and the second electrode;

[0023] A distributed Bragg reflector layer located on the passivation layer;

[0024] A first pad and a second pad located on the distributed Bragg reflector layer, the first pad being connected to the first electrode and the second pad being connected to the second electrode.

[0025] According to a second aspect of the present disclosure, a method for fabricating an LED chip structure is provided, wherein the method includes:

[0026] Providing a substrate;

[0027] Forming a nucleation layer, a buffer layer, and an n-type GaN layer stacked in sequence on the substrate;

[0028] Forming an isolation layer on the n-type GaN layer;

[0029] Forming a plurality of through holes penetrating the isolation layer;

[0030] Forming nanocolumns in each of the through holes, the plurality of nanocolumns forming a nanocolumn array, wherein the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each nanocolumn unit includes a plurality of nanocolumns with different diameters.

[0031] In an implementable embodiment, the forming a plurality of through holes penetrating the isolation layer; forming nanocolumns in each of the through holes includes:

[0032] Forming a photoresist layer on the isolation layer;

[0033] Using a photolithography process to lithograph the photoresist layer to form a plurality of through hole positions located in the photoresist layer, wherein the through holes include a variety of different diameters;

[0034] Via the through hole positions, etching away the isolation layer not covered by the photoresist layer, and stopping the etching on the upper surface of the n-type GaN layer to form the through holes;

[0035] Forming nanocolumns in each of the through holes.

[0036] In an implementable embodiment, the forming a plurality of through holes penetrating the isolation layer; forming nanocolumns in each of the through holes includes:

[0037] Forming a first photoresist layer on the isolation layer;

[0038] Using a photolithography process to lithograph the first photoresist layer to form a plurality of first through hole positions located in the first photoresist layer, wherein the first through holes have a first diameter;

[0039] Through the position of the first through-hole, etch away the isolation layer that is not covered by the first photoresist layer, and stop the etching on the upper surface of the n-type GaN layer to form the first through-hole;

[0040] Form nanocolumns with a first diameter in each of the first through-holes;

[0041] Remove the first photoresist layer;

[0042] Form a second photoresist layer on the isolation layer;

[0043] Use a lithography process to lithograph the second photoresist layer to form a plurality of second through-hole positions in the second photoresist layer, wherein the second through-hole has a second diameter;

[0044] Through the position of the second through-hole, etch away the isolation layer that is not covered by the second photoresist layer, and stop the etching on the upper surface of the n-type GaN layer to form the second through-hole;

[0045] Form nanocolumns with a second diameter in each of the second through-holes;

[0046] And so on until the preparation of all nanocolumns is completed.

[0047] In an implementable embodiment, forming nanocolumns in each of the through-holes includes:

[0048] Form a stress buffer layer, an active region light-emitting layer, an electron blocking layer, and a p-type GaN layer stacked in sequence in the through-hole.

[0049] In an implementable embodiment, in each nanocolumn unit, a plurality of nanocolumns with different diameters are arranged in the first direction in the order of diameter size, wherein the first direction is a direction parallel to the substrate plane; or,

[0050] In each nanocolumn unit, a plurality of nanocolumns with different diameters are arranged in a polygon.

[0051] In an implementable embodiment, a plurality of the nanocolumn units are arranged in an array in the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are respectively aligned with each other.

[0052] In an implementable embodiment, a plurality of the nanocolumn units are arranged in an array in the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are respectively arranged in a staggered manner, and the nanocolumn units separated by one row and one column are respectively aligned with each other.

[0053] In an implementable embodiment, the diameter range of the nanocolumns is 0.05 - 50 μm, and the distance between adjacent two nanocolumns is 0.1 - 10 μm.

[0054] In one possible implementation, the height of the nanocolumns is equal to or lower than the height of the isolation layer, where the difference between the height of the nanocolumns and the height of the isolation layer is less than or equal to 30 nm.

[0055] In one possible implementation, the shape of the projection of the nanocolumns in the direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

[0056] In one possible implementation, the method further includes:

[0057] Forming a transparent conductive layer on the isolation layer;

[0058] Forming a first electrode on the transparent conductive layer and a second electrode on the n-type GaN layer;

[0059] Forming a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode, and the second electrode;

[0060] Forming a distributed Bragg reflector layer on the passivation layer;

[0061] Forming a first window and a second window passing through the distributed Bragg reflector layer and the passivation layer, where the first window exposes the first electrode and the second window exposes the second electrode;

[0062] Forming a first pad on the first window, where the first pad is connected to the first electrode;

[0063] Forming a second pad on the second window, where the second pad is connected to the second electrode.

[0064] For the LED chip structure and its manufacturing method of the present disclosure, by forming a nanocolumn array on the LED chip, since the nanocolumn array includes nanocolumns with various different diameters, the nanocolumns with different diameters can achieve the emission of light with different wavelengths, so that high-pixel and high-light-efficiency full-color display of the LED chip can be realized; and because full-color display is integrated on the LED chip, the massive transfer and bonding technologies used in the manufacturing of traditional LED displays are avoided, the yield of the LED chip is greatly improved, and the manufacturing cost is significantly reduced.

[0065] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. Description of the Drawings

[0066] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understandable. In the drawings, several embodiments of the present disclosure are shown in an exemplary but non-limiting manner, where:

[0067] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0068] Figure 1 It is a schematic structural diagram of the LED chip structure provided by the present disclosure;

[0069] Figure 2 It is a perspective view of the nanorod array provided by the present disclosure;

[0070] Figure 3 It is a schematic structural diagram of the nanorod provided by the embodiment of the present disclosure;

[0071] Figures 4 to 6 They are different arrangement modes of the nanorod array, where,

[0072] Figure 4 It is Arrangement Mode 1 of the nanorod array;

[0073] Figure 5 It is Arrangement Mode 2 of the nanorod array;

[0074] Figure 6 It is Arrangement Mode 3 of the nanorod array;

[0075] Figure 7 It is a flowchart of the preparation method of the LED chip structure provided by the embodiment of the present disclosure;

[0076] Figures 8 to 15 It is a schematic diagram of the LED chip structure provided by the embodiment of the present disclosure during the preparation process, where,

[0077] Figure 8 It is a schematic diagram of the LED chip structure provided by the embodiment of the present disclosure during the preparation process Figure 1 ;

[0078] Figure 9 It is a schematic diagram of the LED chip structure provided by the embodiment of the present disclosure during the preparation process Figure 2 ;

[0079] Figure 10 It is a schematic diagram of the LED chip structure provided by the embodiment of the present disclosure during the preparation process Figure 3 ;

[0080] Figure 11 It is a schematic diagram of the LED chip structure provided by the embodiment of the present disclosure during the preparation process Figure 4 ;

[0081] Figure 12 Schematic diagram during the preparation process of the LED chip structure in the embodiment of the present disclosure Figure 5 ;

[0082] Figure 13 Schematic diagram during the preparation process of the LED chip structure in the embodiment of the present disclosure Figure 6 ;

[0083] Figure 14 Schematic diagram during the preparation process of the LED chip structure in the embodiment of the present disclosure Figure 7 ;

[0084] Figure 15 Schematic diagram during the preparation process of the LED chip structure in the embodiment of the present disclosure Figure 8 ;

[0085] Figures 16 to 21 Preparation method of the nanowire provided by another embodiment of the present disclosure, wherein,

[0086] Figure 16 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 1 ;

[0087] Figure 17 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 2 ;

[0088] Figure 18 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 3 ;

[0089] Figure 19 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 4 ;

[0090] Figure 20 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 5 ;

[0091] Figure 21 Schematic diagram during the preparation process of the nanowire in another embodiment of the present disclosure Figure 6 。

[0092] Reference numerals:

[0093] 11, substrate; 12, nucleation layer; 13, buffer layer; 14, n-type GaN layer;

[0094] 20, isolation layer; 200, through hole; 201, first through hole; 202, second through hole; 203, third through hole;

[0095] 30. Nanopillar array; 31. Nanopillar unit; 311. Nanopillar; 3111. Stress buffer layer; 3112. Active region light-emitting layer; 3113. Electron blocking layer; 3114. p-type GaN layer;

[0096] 40. Transparent conductive layer;

[0097] 51. First electrode; 52. Second electrode;

[0098] 60. Passivation layer;

[0099] 70. Distributed Bragg reflector layer;

[0100] 81. First pad; 82. Second pad. Detailed implementation manners

[0101] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0102] Traditional full-color display requires batch transferring and integrating red, green, and blue tri-color Micro-LEDs onto a driving circuit substrate, and precisely and quickly interconnecting different Micro-LED chips corresponding to different colors with a driving backplane through a bonding technology. As the size of the Micro-LED chips shrinks, the number of Micro-LED chips in the same display area increases geometrically, which poses higher requirements for the transfer accuracy, transfer efficiency, bonding yield, and reliability of the manufacturing process. There is still much room for improvement in the existing mass transfer and bonding technologies.

[0103] Based on this, the present disclosure provides an LED chip structure. Figure 1 It is a schematic structural diagram of the LED chip structure provided by the present disclosure. Figure 2 It is a three-dimensional view of the nanopillar array provided by the present disclosure, as Figure 1 and Figure 2 shown. The structure includes:

[0104] A substrate 11, and a nucleation layer 12, a buffer layer 13, and an n-type GaN layer 14 stacked in sequence on the substrate 11;

[0105] An isolation layer 20 on the n-type GaN layer 14;

[0106] The nano-pillar array 30 penetrates through the isolation layer 20, wherein the nano-pillar array 30 includes a plurality of nano-pillar units 31 arranged in an array, and each nano-pillar unit 31 includes a plurality of nano-pillars 311 with different diameters.

[0107] In one embodiment, the substrate 11 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 11 can be a sapphire substrate or a silicon substrate, etc.

[0108] In one embodiment, the nucleation layer 12 includes at least one of an AlN layer or a GaN layer.

[0109] When the nucleation layer 12 is an AlN layer, the thickness of the AlN layer is 5 - 15 nm; when the nucleation layer 12 is a GaN layer, the thickness of the GaN layer is 5 - 15 nm; when the nucleation layer 12 is a mixed nucleation layer of an AlN layer and a GaN layer, the thickness of the AlN layer is 5 - 10 nm, and the thickness of the GaN layer is 5 - 10 nm.

[0110] The nucleation layer 12 can alleviate the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, promote the transformation of the epitaxial material growth from a three-dimensional mode to a two-dimensional mode, obtain high-quality epitaxial materials, and improve the crystal quality of the epitaxial materials of the Micro-LED chip.

[0111] In one embodiment, the buffer layer 13 can be a GaN buffer layer, and the thickness of the GaN buffer layer is 1.5 - 3 μm.

[0112] In one embodiment, the n-type GaN layer 14 is an n-type doped GaN layer, and the thickness of the n-type doped GaN layer is 1 - 2 μm.

[0113] In one embodiment, the material of the isolation layer 20 includes at least one of silicon dioxide or aluminum oxide. The isolation layer 20 can provide an insulating isolation effect for adjacent nano-pillars to avoid crosstalk between adjacent nano-pillars.

[0114] The role of these materials in the LED chip structure is to provide effective isolation and protection, improve the performance and reliability of the chip. By selecting appropriate isolation layer materials, the electrical performance and thermal stability of the LED chip can be improved.

[0115] When selecting the isolation layer material, one or a combination of two materials, silicon dioxide or aluminum oxide, can be chosen according to specific application requirements. Silicon dioxide has good electrical insulation properties and thermal stability and is suitable for applications in high-temperature environments. Aluminum oxide, on the other hand, has excellent mechanical strength and corrosion resistance and is suitable for applications that require high strength and durability. In addition, the performance of the isolation layer can be optimized by adjusting the ratio of silicon dioxide and aluminum oxide to meet the requirements of different application scenarios.

[0116] As Figure 2 shown, the nanocolumn array 30 in the present disclosure includes a plurality of nanocolumn units 31 arranged in an array, and each of the nanocolumn units 31 includes a plurality of nanocolumns 311 with different diameters.

[0117] In the embodiment of the present disclosure, as Figure 2 shown, the nanocolumn unit 31 includes three nanocolumns 311 with different diameters. It can be understood that the nanocolumn unit can also include more than three nanocolumns with different diameters, which can be specifically set according to actual requirements.

[0118] Figure 3 It is a schematic structural diagram of the nanocolumn provided by the embodiment of the present disclosure.

[0119] As Figure 3 shown, the nanocolumn 311 includes a stress buffer layer 3111, an active region light-emitting layer 3112, an electron blocking layer 3113, and a p-type GaN layer 3114 stacked in sequence.

[0120] The stress buffer layer 3111 can be an n-type doped In x Ga 1-x N layer (0 < x < 0.05) or an In x Ga 1-x N / GaN (0 < x < 0.05) superlattice layer. Among them, the thickness of the n-type doped In x Ga 1-x N layer is 10 - 20 nm, and the number of periods of the In x Ga 1-x N / GaN superlattice layer is 1 - 7.

[0121] The stress buffer layer 3111 can relieve the lattice mismatch between different epitaxial layers, further improve the crystal quality of the epitaxial material, and obtain a high-performance and high-light-efficiency Micro-LED chip.

[0122] The active region light-emitting layer 3112 is the key part for the Micro-LED chip to emit light and is responsible for generating light. It is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers. The In x Ga 1-xThe thickness of the N quantum well layer is 1.5 to 3.5 nm, the thickness of the GaN quantum barrier layer is 9 to 15 nm, In x Ga 1-x The number of periods of the InGaN quantum well and the GaN quantum barrier is 3 to 7.

[0123] The electron blocking layer 3113 is used to prevent electron leakage and improve the luminous efficiency. The electron blocking layer 3113 is composed of Al x Ga 1-x N, and its thickness is about 15 to 30 nm.

[0124] The p-type GaN layer 3114 is a P-type doped GaN layer, which is the upper layer of the nanowire layer and provides charge carriers. The thickness of the p-type GaN layer 3114 is about 20 to 50 nm.

[0125] Through the sequential stacking of these layers, the nanowires can achieve high-efficiency light emission and maintain structural stability.

[0126] In one embodiment, the height of the nanowire 311 composed of the stress buffer layer 3111, the active region light-emitting layer 3112, the electron blocking layer 3113, and the p-type GaN layer 3114 is equal to or lower than the height of the isolation layer 20, wherein the difference between the height of the nanowire 311 and the height of the isolation layer 20 is less than or equal to 30 nm. The height of the nanowire is equal to or lower than the height of the isolation layer, so that the nanowire is supported and fixed by the isolation layer around it, and the stability is improved, which is beneficial to enhancing the process stability and device performance.

[0127] In one embodiment, in the nanowires 311 with different diameters, the proportion of indium atom components is different.

[0128] Specifically, according to the diameter of the nanowire and the proportion of indium atom components in the active region light-emitting layer 3112 can be adjusted synergistically, so as to design different proportions of indium atom components for nanowires with different diameters. The emission wavelength of the Micro-LED chip is related to the nanowire array. By reducing the diameter of the nanowire, the stress of epitaxial growth can be reduced, which is beneficial to incorporating more indium atom components into the epitaxial layer, thereby obtaining a longer emission wavelength, so that nanowires with different emission wavelengths can be integrated in the nanowire array.

[0129] Figures 4 to 6 are different arrangement modes of the nanowire array.

[0130] In one embodiment, in each of the nanowire units 31, a plurality of nanowires 311 with different diameters are arranged in the order of diameter size along the first direction, wherein the first direction is parallel to the plane of the substrate 11; or,

[0131] In each of the nanowire units 31, a plurality of nanowires 311 with different diameters are arranged in a polygon.

[0132] Specifically, as Figure 4 shown, the three different-diameter nanocolumns 311 are arranged in the first direction in ascending order of diameter. It can be understood that they can also be arranged in the first direction in descending order of diameter.

[0133] As Figure 5 and Figure 6 shown, the three different-diameter nanocolumns 311 are arranged in a triangular pattern. It can be understood that the nanocolumn unit can include more than three different-diameter nanocolumns. For example, when the nanocolumn unit includes four different-diameter nanocolumns, they can be arranged in a quadrilateral pattern.

[0134] In the present disclosure, the performance of the LED chip structure is improved by optimizing the arrangement of the nanocolumn array. By arranging them in order of diameter or in a polygonal pattern, it is possible to ensure the uniform distribution and reasonable spacing of the nanocolumns in the LED chip structure, thereby reducing light scattering and reflection losses, and thus improving the optoelectronic performance and luminous efficiency.

[0135] In one embodiment, multiple said nanocolumn units 31 are arranged in an array in the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are respectively aligned with each other.

[0136] Specifically, as Figure 4 and Figure 5 shown, the nanocolumn units 31 in adjacent rows are aligned with each other, and the nanocolumn units 31 in adjacent columns are aligned with each other.

[0137] In one embodiment, multiple said nanocolumn units 31 are arranged in an array in the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are respectively staggered, and the nanocolumn units 31 separated by one row and the nanocolumn units 31 separated by one column are respectively aligned with each other.

[0138] Specifically, as Figure 6 shown, the nanocolumn units 31 in adjacent rows are staggered, and the nanocolumn units 31 separated by one row are aligned with each other; the nanocolumn units 31 in adjacent columns are staggered, and the nanocolumn units 31 separated by one column are aligned with each other.

[0139] This staggered arrangement can not only increase the arrangement density of the nanocolumn units, but also reduce the mutual interference between the nanocolumns, improving the luminous efficiency and uniformity of the LED chip. In this way, the arrangement problem of the nanocolumn units in the row and column directions can be effectively solved, ensuring the high efficiency and stability of the LED chip in practical applications.

[0140] It can be understood that Figures 4 to 6 only several possible arrangement patterns are shown, and there can also be other arrangement patterns for the nanocolumn array.

[0141] In one embodiment, the diameter of the nanocolumn 311 ranges from 0.05 to 50 μm, and the distance between two adjacent nanocolumns 311 is from 0.1 to 10 μm.

[0142] In a specific embodiment, for example, the nanocolumn unit 31 includes nanocolumns 311 with three different diameters. Among them, the diameter of the nanocolumn 311 with the smallest diameter is, for example, from 0.05 to 10 μm, the diameter of the nanocolumn 311 with the medium diameter is, for example, from 10 to 30 μm, and the diameter of the nanocolumn with the largest diameter is, for example, from 30 to 50 μm.

[0143] As the diameter of the nanocolumn decreases continuously, the stress in the heteroepitaxial growth process can be effectively released. On the one hand, it is beneficial to reduce the density of structural defects such as dislocations, which is conducive to obtaining high-quality group III nitride Micro-LEDs. On the other hand, the reduction of stress is beneficial to the incorporation of more indium atoms into the epitaxial layer, ultimately realizing longer wavelength emission and covering a wider wavelength band of light. In addition, reducing stress helps to reduce the influence of the in-plane polarization electric field, can confine electrons and holes at the center of the quantum well, reduces the spatial separation of the wave function, and improves the radiative recombination probability and luminescence efficiency.

[0144] In the present disclosure, the nanocolumns 311 with different diameters emit light with different wavelengths. The smaller the diameter, the longer the wavelength of the emitted light. Therefore, red light can be emitted through the nanocolumn 311 with the smallest diameter, green light can be emitted through the nanocolumn 311 with the medium diameter, and blue light can be emitted through the nanocolumn 311 with the largest diameter.

[0145] Since the nanocolumn array includes nanocolumns with multiple different diameters and different diameters of nanocolumns can realize the emission of light with different wavelengths, red, green, and blue tri-color Micro-LED chips can be integrated on a single epitaxial wafer, thereby realizing high-pixel and high-light-efficiency full-color display; and because full-color display is integrated on the LED chip, the massive transfer and bonding technologies used in traditional LED display manufacturing are avoided, greatly improving the yield of the LED chip and significantly reducing the manufacturing cost.

[0146] Selecting nanocolumns with a specific diameter in a specific area of the chip can realize the emission of light with a specific wavelength in the selected area, and the area of the selected area is related to the area occupied by the nanocolumns with the corresponding diameter.

[0147] In one embodiment, the shape of the projection of the nanocolumn 311 in the direction perpendicular to the plane of the substrate 11 includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

[0148] Such as Figures 4 to 6As shown, the projected shape of the nanocolumn 311 is circular. In some other embodiments, the projected shape of the nanocolumn can also be any one of a triangle, a quadrilateral, and a pentagon. It can be understood that the projected shape of the nanocolumn is not limited thereto, and can also be other shaped structures.

[0149] In one embodiment, as Figure 1 shown, the structure further includes: a transparent conductive layer 40 located on the isolation layer 20;

[0150] a first electrode 51 located on the transparent conductive layer 40 and a second electrode 52 located on the n-type GaN layer 14;

[0151] a passivation layer 60 covering the transparent conductive layer 40, the n-type GaN layer 14, the first electrode 51, and the second electrode 52;

[0152] a distributed Bragg reflector layer 70 located on the passivation layer 60;

[0153] a first pad 81 and a second pad 82 located on the distributed Bragg reflector layer 70, the first pad 81 passing through the distributed Bragg reflector layer 70 and the passivation layer 60 and connecting to the first electrode 51, and the second pad 82 passing through the distributed Bragg reflector layer 70 and the passivation layer 60 and connecting to the second electrode 52.

[0154] The material of the transparent conductive layer 40 includes but is not limited to indium tin oxide (ITO). A low-resistance ohmic contact is formed between the transparent conductive layer 40 and the P-type GaN layer 3114.

[0155] As Figure 1 shown, the isolation layer 20 does not completely cover the n-type GaN layer 14, but exposes a part of the n-type GaN layer 14, so that the second electrode 52 can be formed on the n-type GaN layer 14.

[0156] The first electrode 51 not only includes the part located on the transparent conductive layer 40, but also includes the part passing through the distributed Bragg reflector (DBR) layer 70 and the passivation layer 60; the second electrode not only includes the part located on the n-type GaN layer, but also includes the part passing through the distributed Bragg reflector (DBR) layer 70 and the passivation layer 60.

[0157] The first electrode 51 and the second electrode 52 have different conduction types. For example, the first electrode 51 is a p electrode and the second electrode 52 is an n electrode.

[0158] The materials of the first electrode 51 and the second electrode 52 may include at least one of Cr, Au, Ti, Ag, and Pt.

[0159] In the present disclosure, the Micro-LEDs based on the nanocolumn array 30 share a first electrode, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0160] The passivation layer 60 may be selected from dielectric layers such as Al2O3, SiO2, and SiN x and the like.

[0161] The distributed Bragg reflector layer 70 is an optical distributed Bragg reflector layer.

[0162] The distributed Bragg reflector layer 70 may be composed of SiO2 and Ti2O5, or may be composed of SiO2, Ti2O5, and Al2O3.

[0163] The conduction types of the first pad 81 and the second pad 82 are different and correspond to the conduction types of the first electrode 51 and the second electrode 52. For example, when the first electrode 51 is a p electrode, the first pad 81 is a p pad, and when the second electrode 52 is an n electrode, the second pad 82 is an n pad.

[0164] In the present disclosure, by forming a nanocolumn array on the LED chip, since the nanocolumn array contains nanocolumns of multiple different diameters, the nanocolumns of different diameters can emit light of different wavelengths, so that full-color display with high pixels and high luminous efficiency of the LED chip can be achieved; and because full-color display is integrated on the LED chip, the massive transfer and bonding technologies used in traditional LED display manufacturing are avoided, the yield of the LED chip is greatly improved, and the manufacturing cost is significantly reduced.

[0165] The embodiment of the present disclosure also provides a preparation method of an LED chip structure, Figure 7 which is a flowchart of the preparation method of the LED chip structure provided by the embodiment of the present disclosure. As Figure 7 shown, the method includes:

[0166] Step 701: Provide a substrate;

[0167] Step 702: Form a nucleation layer, a buffer layer, and an n-type GaN layer stacked in sequence on the substrate;

[0168] Step 703: Form an isolation layer on the n-type GaN layer;

[0169] Step 704: Form a plurality of through holes penetrating the isolation layer;

[0170] Step 705: Form nanocolumns in each of the through holes, and a plurality of the nanocolumns form a nanocolumn array. Among them, the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each nanocolumn unit includes a plurality of nanocolumns with different diameters.

[0171] The preparation method of the LED chip structure provided by the embodiments of the present disclosure will be further described in detail below in conjunction with specific embodiments. Figures 8 to 15 It is a schematic diagram during the preparation process of the LED chip structure provided by the embodiments of the present disclosure.

[0172] First, refer to Figure 8 , and perform Step 701 to provide a substrate 11.

[0173] In one embodiment, the substrate 11 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 11 can be a sapphire substrate or a silicon substrate, etc.

[0174] Next, continue to refer to Figure 8 , and perform Step 702 to form a nucleation layer 12, a buffer layer 13, and an n-type GaN layer 14 stacked in sequence on the substrate 11.

[0175] The nucleation layer 12, the buffer layer 13, and the n-type GaN layer 14 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0176] In a preferred embodiment, the nucleation layer 12, the buffer layer 13, and the n-type GaN layer 14 can be deposited by metal-organic chemical vapor deposition (MOCVD) technology.

[0177] The nucleation layer 12 includes at least one of an AlN layer or a GaN layer.

[0178] Specifically, when the nucleation layer 12 is an AlN layer, the AlN layer is a sputtered AlN layer. The AlN layer can be formed by a magnetron sputtering device using a high-purity aluminum target as the aluminum source for magnetron sputtering, and a 5-15 nm thick AlN layer is sputtered on the substrate 11.

[0179] When the nucleation layer 12 is a GaN layer, the GaN layer is a low-temperature GaN layer. The GaN layer is grown on the substrate 11 with a thickness of 5 - 15 nm by a metalorganic chemical vapor deposition (MOCVD) apparatus.

[0180] When the nucleation layer 12 is a mixed nucleation layer of an AlN layer and a GaN layer, the mixed nucleation layer is composed of a sputtered AlN layer and a low-temperature GaN layer. Among them, the thickness of the sputtered AlN layer is 5 - 10 nm, and the growth thickness of the low-temperature GaN layer is 5 - 10 nm.

[0181] The nucleation layer 12 can relieve the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, promote the transformation of the epitaxial material growth from a three-dimensional mode to a two-dimensional mode, obtain high-quality epitaxial materials, and improve the crystal quality of the epitaxial materials of the Micro-LED chip.

[0182] In one embodiment, the buffer layer 13 can be a GaN buffer layer, and the thickness of the GaN buffer layer is 1.5 - 3 μm.

[0183] In one embodiment, the n-type GaN layer 14 is an n-type doped GaN layer, and the thickness of the n-type doped GaN layer is 1 - 2 μm.

[0184] Next, referring to Figure 9 , perform step 703 to form an isolation layer 20 on the n-type GaN layer 14.

[0185] The isolation layer 20 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods. In a preferred embodiment, plasma-enhanced chemical vapor deposition (PECVD) technology can be used to form the isolation layer 20 on the n-type GaN layer 14.

[0186] After depositing the isolation layer 20, the surface of the entire epitaxial wafer is modified to convert the hydrophilicity of the surface of the isolation layer 20 into hydrophobicity, so that the subsequently formed photoresist can adhere better to the isolation layer 20.

[0187] In one embodiment, the material of the isolation layer 20 includes at least one of silicon dioxide or aluminum oxide. The isolation layer 20 can provide an insulating isolation effect for the subsequently formed nanocolumns to avoid crosstalk between adjacent nanocolumns.

[0188] Next, referring to Figure 10 andFigure 11 Step 704 is performed to form a plurality of through-holes 200 penetrating the isolation layer 20, and step 705 is performed to form nano-columns 311 in each of the through-holes 200. The plurality of nano-columns 311 form a nano-column array 30. Among them, the nano-column array 30 includes a plurality of nano-column units 31 arranged in an array, and each nano-column unit 31 includes a plurality of nano-columns 311 with different diameters.

[0189] There are two implementation manners for forming the nano-columns 311 in the isolation layer 20. One is as shown in Figure 10 and Figure 11 , and the other is as shown in Figures 16 to 21 . Next, the implementation manners shown in Figure 10 and Figure 11 will be described in detail.

[0190] As shown in Figure 10 and Figure 11 , forming a plurality of through-holes 200 penetrating the isolation layer 20; forming nano-columns 311 in each of the through-holes 200 includes:

[0191] Forming a photoresist layer (not shown in the figure) on the isolation layer 20;

[0192] Using a photolithography process to lithograph the photoresist layer to form a plurality of through-hole positions in the photoresist layer, where the through-holes include various different diameters;

[0193] Via the through-hole positions, etching away the isolation layer 20 not covered by the photoresist layer, and stopping the etching on the upper surface of the n-type GaN layer 14 to form the through-holes 200;

[0194] Forming nano-columns 311 in each of the through-holes 200.

[0195] In actual operation, a layer of photoresist is uniformly spin-coated on the surface of the epitaxial wafer on which the isolation layer 20 is deposited, and then placed on a hot plate for pre-baking to evaporate the moisture inside the photoresist and complete the shaping. After spin-coating the photoresist, ultraviolet exposure and development are performed. After the development is completed, the epitaxial wafer is washed with deionized water, and after hard baking, it is washed with a plasma asher. The above-mentioned epitaxial wafer is placed in an inductively coupled plasma (ICP) etcher, and the epitaxial wafer is dry-etched successively with SF6 and Cl2 / BCl3 gases to etch away all the isolation layer 20 without photoresist protection until the upper surface of the n-type GaN layer 14 is exposed, forming through-holes 200 with various different diameters.

[0196] Remove the remaining photoresist layer and spin-dry the surface moisture in a spin dryer, thereby realizing the preparation of nano-columns 311 in the through-holes 200.

[0197] Next, a detailed description will be given of the Figures 16 to 21 illustrated embodiment.

[0198] As Figures 16 to 21 illustrated, forming a plurality of through holes penetrating the isolation layer 20; forming nanocolumns 311 in each of the through holes, including:

[0199] Forming a first photoresist layer (not shown in the figure) on the isolation layer 20;

[0200] Using a photolithography process to photolithograph the first photoresist layer to form a plurality of first through hole positions in the first photoresist layer, wherein the first through hole has a first diameter;

[0201] Via the first through hole positions, etching away the isolation layer 20 not covered by the first photoresist layer, and stopping the etching on the upper surface of the n-type GaN layer 14 to form the first through holes 201;

[0202] Forming nanocolumns 311 having a first diameter in each of the first through holes 201;

[0203] Removing the first photoresist layer;

[0204] Forming a second photoresist layer (not shown in the figure) on the isolation layer 20;

[0205] Using a photolithography process to photolithograph the second photoresist layer to form a plurality of second through hole positions in the second photoresist layer, wherein the second through hole has a second diameter;

[0206] Via the second through hole positions, etching away the isolation layer 20 not covered by the second photoresist layer, and stopping the etching on the upper surface of the n-type GaN layer 14 to form the second through holes 202;

[0207] Forming nanocolumns 311 having a second diameter in each of the second through holes 202;

[0208] And so on until the preparation of all the nanocolumns 311 is completed.

[0209] In actual operation, taking the formation of nanocolumns with three diameters as an example. Design mask plates with three diameters for the preparation of nanocolumns with three diameters.

[0210] First, use a mask plate with a first diameter to form the first through holes. Specifically, first refer to Figure 16, a first photoresist layer (not shown in the figure) is spin-coated evenly on the surface of the epitaxial wafer with the isolation layer 20 deposited, and then placed on a hot plate for pre-baking to evaporate the moisture inside the first photoresist layer and complete the shaping. After spin-coating the photoresist, ultraviolet exposure and development are carried out. After the development is completed, the epitaxial wafer is washed with deionized water and then washed with a plasma asher after hard baking. The above-mentioned epitaxial wafer is placed in an inductively coupled plasma etching machine, and the isolation layer 20 without the protection of the first photoresist layer is etched dry successively through SF6 and Cl2 / BCl3 gases until the upper surface of the n-type GaN layer 14 is exposed, forming a first through hole 201 with a first diameter.

[0211] Next, refer to Figure 17 , the remaining first photoresist layer is removed, and the surface moisture is dried in a spin dryer, thereby realizing the preparation of the nanorods 311 with the first diameter in the first through hole 201.

[0212] Next, a second through hole is formed using a mask with a second diameter. Specifically, first refer to Figure 18 , a second photoresist layer (not shown in the figure) is spin-coated evenly on the surface of the epitaxial wafer with the isolation layer 20 deposited, and then placed on a hot plate for pre-baking to evaporate the moisture inside the second photoresist layer and complete the shaping. After spin-coating the photoresist, ultraviolet exposure and development are carried out. After the development is completed, the epitaxial wafer is washed with deionized water and then washed with a plasma asher after hard baking. The above-mentioned epitaxial wafer is placed in an inductively coupled plasma etching machine, and the isolation layer 20 without the protection of the second photoresist layer is etched dry successively through SF6 and Cl2 / BCl3 gases until the upper surface of the n-type GaN layer 14 is exposed, forming a second through hole 202 with a second diameter.

[0213] Next, refer to Figure 19 , the remaining second photoresist layer is removed, and the surface moisture is dried in a spin dryer, thereby realizing the preparation of the nanorods 311 with the second diameter in the second through hole 202.

[0214] Next, a third through hole is formed using a mask with a third diameter. Specifically, first refer to Figure 20 , a third photoresist layer (not shown in the figure) is spin-coated evenly on the surface of the epitaxial wafer with the isolation layer 20 deposited, and then placed on a hot plate for pre-baking to evaporate the moisture inside the third photoresist layer and complete the shaping. After spin-coating the photoresist, ultraviolet exposure and development are carried out. After the development is completed, the epitaxial wafer is washed with deionized water and then washed with a plasma asher after hard baking. The above-mentioned epitaxial wafer is placed in an inductively coupled plasma etching machine, and the isolation layer 20 without the protection of the third photoresist layer is etched dry successively through SF6 and Cl2 / BCl3 gases until the upper surface of the n-type GaN layer 14 is exposed, forming a third through hole 203 with a third diameter.

[0215] Next, referring to Figure 21 , the remaining third photoresist layer is removed, and the surface moisture is dried in a spin dryer, so as to fabricate the nanocolumns 311 with a third diameter in the third through hole 203.

[0216] Since the full-color display effect based on Micro-LEDs is mainly affected by the pixel density, the higher the pixel density per unit area, the better the display effect and the clearer the image. However, as the density increases, the size of the Micro-LED chips becomes smaller, and the perimeter-area ratio of the devices increases accordingly, thereby causing the small-size effect. In the prior art, during the process of fabricating nanocolumns, a stacked structure containing nanocolumn materials is first formed, and then the stacked structure is etched using plasma dry etching, and then an isolation layer is formed. In the traditional fabrication method, the smaller the size, the more serious the sidewall damage, the greater the impact on the optoelectronic performance of the device, and finally the luminous efficiency of the Micro-LED chips under low current density injection conditions drops significantly, seriously affecting the full-color display brightness, resolution, and color uniformity.

[0217] In the present disclosure, an isolation layer is first formed, then the isolation layer is etched to form through holes, and then nanocolumns are formed in the through holes, thus avoiding the sidewall damage caused by the process of defining each Micro-LED by etching the epitaxial wafer in the traditional Micro-LED fabrication, and avoiding the negative impact of the defects caused by the sidewall damage on the luminous efficiency and service life of the Micro-LEDs.

[0218] In the embodiment of the present disclosure, the nanocolumn unit 31 includes nanocolumns 311 with three different diameters. It can be understood that the nanocolumn unit may also include more than three different diameters of nanocolumns, which can be specifically set according to actual requirements.

[0219] In one embodiment, as Figure 3 shown, forming the nanocolumns 311 in each of the through holes 200 includes:

[0220] Forming a stress buffer layer 3111, an active region light-emitting layer 3112, an electron blocking layer 3113, and a p-type GaN layer 3114 stacked in sequence in the through hole 200.

[0221] The stress buffer layer 3111, the active region light-emitting layer 3112, the electron blocking layer 3113, and the p-type GaN layer 3114 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0222] In a preferred embodiment, a metalorganic chemical vapor deposition (MOCVD) process can be used to form a stress buffer layer 3111, an active region light-emitting layer 3112, an electron blocking layer 3113, and a p-type GaN layer 3114.

[0223] The stress buffer layer 3111 can be an n-type doped In x Ga 1-x N layer (0 < x < 0.05) or an In x Ga 1-x N / GaN (0 < x < 0.05) superlattice layer, where the thickness of the n-type doped In x Ga 1-x N layer is 10 - 20 nm, and the number of periods of the In x Ga 1-x N / GaN superlattice layer is 1 - 7.

[0224] The stress buffer layer 3111 can relieve the lattice mismatch between different epitaxial layers, further improve the crystal quality of the epitaxial material, and obtain a high-performance and high-light-efficiency Micro-LED chip.

[0225] The active region light-emitting layer 3112 is the key part for the Micro-LED chip to emit light, and is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers. The thickness of the In x Ga 1-x N quantum well layer is 1.5 - 3.5 nm, the thickness of the GaN quantum barrier layer is 9 - 15 nm, and the number of periods of the In x Ga 1-x N quantum well and the GaN quantum barrier is 3 - 7.

[0226] The electron blocking layer 3113 is composed of Al x Ga 1-x N, and its thickness is about 15 - 30 nm.

[0227] The p-type GaN layer 3114 is a P-type doped GaN layer, and the thickness of the p-type GaN layer 3114 is about 20 - 50 nm.

[0228] In Figures 16 to 21 the illustrated embodiment, since the nanocolumns with different diameters are formed separately, the proportion of indium atom components in the active region light-emitting layer 3112 can be adjusted according to the diameter of the nanocolumns and synergistically, so as to design different proportions of indium atom components for nanocolumns with different diameters. The emission wavelength of the Micro-LED chip is related to the nanocolumn array. By reducing the diameter of the nanocolumns, the stress of epitaxial growth can be reduced, which is beneficial to incorporating more indium atom components in the epitaxial layer, obtaining a longer emission wavelength, and thus enabling nanocolumns with different emission wavelengths to be integrated in the nanocolumn array.

[0229] In one embodiment, the smaller the diameter of the nanocolumns, the higher the proportion of indium atomic components. However, the proportion of indium atomic components can also be adjusted in combination with the diameter of the nanocolumns according to the requirements of the specific light wavelength.

[0230] For the Micro-LED chip in the present disclosure, its emission wavelength can be continuously regulated throughout the visible light range only by corresponding adjustments of the nanocolumns, such as the shape, diameter, period or thickness of the quantum well, the proportion of indium atomic components, etc. The quantum well epitaxial growth conditions of Micro-LED chips with different wavelengths are completely the same, without changing conditions such as growth temperature and gas flow rate, which simplifies the setting of growth condition parameters in the epitaxial growth process; for the Micro-LED based on the nanocolumn array, long-wavelength emission and integration of different wavelengths can be achieved only by changing the nanocolumn structure, avoiding problems such as material deterioration caused by reducing the epitaxial growth temperature and performance attenuation of the Micro-LED chip.

[0231] In one embodiment, the height of the nanocolumn 311 composed of the stress buffer layer 3111, the active region light-emitting layer 3112, the electron blocking layer 3113, and the p-type GaN layer 3114 is equal to or lower than the height of the isolation layer 20, wherein the difference between the height of the nanocolumn 311 and the height of the isolation layer 20 is less than or equal to 30 nm. The height of the nanocolumn is equal to or lower than the height of the isolation layer, so that the isolation layer supports and fixes the periphery of the nanocolumn, improving the stability, which is beneficial to enhancing the process stability and device performance.

[0232] In one embodiment, in each of the nanocolumn units 31, a plurality of nanocolumns 311 with different diameters are arranged in the order of diameter size along the first direction, wherein the first direction is parallel to the plane of the substrate 11; or,

[0233] In each of the nanocolumn units 31, a plurality of nanocolumns 311 with different diameters are arranged in a polygon.

[0234] Specifically, as Figure 4 shown, three nanocolumns 311 with different diameters are arranged in the order of increasing diameter along the first direction. It can be understood that it can also be arranged in the order of decreasing diameter along the first direction.

[0235] As Figure 5 and Figure 6 shown, three nanocolumns 311 with different diameters are arranged in a triangle. It can be understood that the nanocolumn unit can include more than three nanocolumns with different diameters. For example, when the nanocolumn unit includes four nanocolumns with different diameters, it can be arranged in a quadrilateral, and when the nanocolumn unit includes five nanocolumns with different diameters, it can be arranged in a pentagon.

[0236] In one embodiment, the plurality of nanocolumn units 31 are arranged in an array in the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are respectively aligned with each other.

[0237] Specifically, as Figure 4 and Figure 5 shown, the nanocolumn units 31 in adjacent rows are aligned with each other, and the nanocolumn units 31 in adjacent columns are aligned with each other.

[0238] In one embodiment, the plurality of nanocolumn units 31 are arranged in an array in the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are respectively staggered, and the nanocolumn units 31 in every other row and every other column are respectively aligned with each other.

[0239] Specifically, as Figure 6 shown, the nanocolumn units 31 in adjacent rows are staggered, and the nanocolumn units 31 in every other row are aligned with each other; the nanocolumn units 31 in adjacent columns are staggered, and the nanocolumn units 31 in every other column are aligned with each other.

[0240] It can be understood that Figures 4 to 6 only several possible arrangement manners are shown, and there may be other arrangement manners for the nanocolumn array.

[0241] In one embodiment, the diameter range of the nanocolumns 311 is 0.05 - 50 μm, and the distance between two adjacent nanocolumns 311 is 0.1 - 10 μm.

[0242] In a specific embodiment, for example, when the nanocolumn unit 31 includes three different diameters of nanocolumns 311, wherein the diameter of the nanocolumn 311 with the smallest diameter is, for example, 0.05 - 10 μm, the diameter of the nanocolumn 311 with the medium diameter is, for example, 10 - 30 μm, and the diameter of the nanocolumn with the largest diameter is, for example, 30 - 50 μm. When the nanocolumn unit 31 includes four different diameters of nanocolumns 311, in ascending order of diameter, the diameter of each nanocolumn can be, for example, 0.05 - 5 μm, 5 - 20 μm, 20 - 35 μm, 35 - 50 μm respectively.

[0243] As the diameter of the nanocolumn continuously decreases, the stress in the heteroepitaxial growth process can be effectively released. On the one hand, it is beneficial to reduce the density of structural defects such as dislocations, which is beneficial to obtaining high-quality group III nitride Micro-LEDs. On the other hand, the reduction of stress is beneficial to more indium atoms being incorporated into the epitaxial layer, ultimately realizing longer wavelength emission and covering a wider wavelength band of light. In addition, reducing stress helps to reduce the influence of the in-plane polarization electric field, can confine electrons and holes at the center of the quantum well, reduces the spatial separation of the wave function, and improves the radiative recombination probability and luminescence efficiency.

[0244] In the present disclosure, the nanocolumns 311 with different diameters emit light of different wavelengths. The smaller the diameter, the longer the wavelength of the emitted light. Therefore, red light can be emitted by the nanocolumns 311 with the smallest diameter, green light can be emitted by the nanocolumns 311 with medium diameters, and blue light can be emitted by the nanocolumns 311 with the largest diameters.

[0245] Since the nanocolumn array includes nanocolumns with a variety of different diameters, and the nanocolumns with different diameters can achieve the emission of light of different wavelengths, red, green, and blue tri-color Micro-LED chips can be integrated on a single epitaxial wafer, thereby achieving full-color display with high pixels and high luminous efficiency; and because full-color display is integrated on the LED chip, the massive transfer and bonding technologies used in the manufacture of traditional LED displays are avoided, the yield of the LED chip is greatly improved, and the manufacturing cost is significantly reduced.

[0246] By selecting nanocolumns with a specific diameter in a specific area of the chip, light of a specific wavelength can be emitted within the selected area, and the area of the selected area is related to the area occupied by the nanocolumns with the corresponding diameter.

[0247] In one embodiment, the shape of the projection of the nanocolumn 311 in a direction perpendicular to the plane of the substrate 11 includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

[0248] As Figures 4 to 6 shown, the projection shape of the nanocolumn 311 is a circle. In some other embodiments, the projection shape of the nanocolumn can also be any one of a triangle, a quadrilateral, and a pentagon. It can be understood that the projection shape of the nanocolumn is not limited to this, and can also be other shaped structures.

[0249] Next, referring to Figures 12 to 15 , the method further includes:

[0250] Forming a transparent conductive layer 40 on the isolation layer 20;

[0251] Forming a first electrode 51 on the transparent conductive layer 40, and forming a second electrode 52 on the n-type GaN layer 14;

[0252] Forming a passivation layer 60 covering the transparent conductive layer 40, the n-type GaN layer 14, the first electrode 51, and the second electrode 52;

[0253] Forming a distributed Bragg reflector layer 70 on the passivation layer 60;

[0254] A first window (not shown in the figure) and a second window (not shown in the figure) are formed through the distributed Bragg reflector layer 70 and the passivation layer 60, the first window exposing the first electrode 51 and the second window exposing the second electrode 52;

[0255] A first pad 81 is formed on the first window, and the first pad 81 is connected to the first electrode 51;

[0256] A second pad 82 is formed on the second window, and the second pad 82 is connected to the second electrode 52.

[0257] In actual operation, first refer to Figure 12 , a transparent conductive layer 40 is evaporated on the isolation layer 20 and the p-type GaN layer 3114, and annealed in a nitrogen atmosphere to form a low-resistance ohmic contact between the transparent conductive layer 40 and the p-type GaN layer 3114.

[0258] The material of the transparent conductive layer 40 includes but is not limited to indium tin oxide (ITO).

[0259] Next, refer to Figure 13 , part of the transparent conductive layer 40 and the isolation layer 20 are etched away by an inductively coupled plasma (ICP) process to expose the n-type GaN layer 14, thereby forming a mesa structure.

[0260] Specifically, a layer of photoresist can be uniformly spin-coated on the surface of the epitaxial wafer on which the transparent conductive layer 40 is deposited, and placed on a hot plate for pre-baking to evaporate the moisture inside the photoresist and complete the shaping. After spin-coating the photoresist, ultraviolet exposure and development are carried out. After the development is completed, the epitaxial wafer is washed with deionized water, and after hardening, it is washed with a plasma asher. The above-mentioned epitaxial wafer is placed in an inductively coupled plasma (ICP) etching machine, and the transparent conductive layer 40 without photoresist protection is dry-etched successively through SF6 and Cl2 / BCl3 gases until the upper surface of the n-type GaN layer 14 is exposed, forming a mesa structure.

[0261] Continue to refer to Figure 13 , metal electrodes are sputtered on the transparent conductive layer 40 and the n-type GaN layer 14 by electron beam evaporation technology to form a first electrode 51 and a second electrode 52 respectively.

[0262] The conduction types of the first electrode 51 and the second electrode 52 are different. For example, the first electrode 51 is a p electrode and the second electrode 52 is an n electrode.

[0263] The materials of the first electrode 51 and the second electrode 52 can include at least one of Cr, Au, Ti, Ag, and Pt.

[0264] In the present disclosure, the Micro-LEDs based on the nanocolumn array 30 share a first electrode, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0265] Next, referring to Figure 14 , a passivation layer 60 covering the transparent conductive layer 40, the n-type GaN layer 14, the first electrode 51, and the second electrode 52 is formed.

[0266] The passivation layer 60 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0267] In a preferred embodiment, the passivation layer 60 is deposited and formed by a plasma enhanced chemical vapor deposition (PECVD) process, and the passivation layer 60 covers the entire epitaxial layer.

[0268] The passivation layer 60 can be selected from dielectric layers such as Al2O3, SiO2, SiN x and the like.

[0269] Next, continue to refer to Figure 14 , and a distributed Bragg reflector layer 70 is further deposited and formed.

[0270] The distributed Bragg reflector layer 70 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.

[0271] In a preferred embodiment, the distributed Bragg reflector layer 70 is deposited and formed by a plasma enhanced chemical vapor deposition (PECVD) process.

[0272] The distributed Bragg reflector layer (DBR) 70 is an optical distributed Bragg reflector layer. The distributed Bragg reflector layer 70 can be composed of SiO2 and Ti2O5, or can be composed of SiO2, Ti2O5, and Al2O3.

[0273] Next, referring to Figure 15, a first window (not shown in the figure) and a second window (not shown in the figure) passing through the distributed Bragg reflector layer 70 and the passivation layer 60 are formed by dry etching. The first window exposes the first electrode 51, and the second window exposes the second electrode 52. Then, a metal electrode is deposited in the first window, which can be a part of the first electrode 51, and a metal electrode is also deposited in the second window, which can be a part of the second electrode 52. Then, a first pad 81 and a second pad 82 are formed on the distributed Bragg reflector layer 70. The first pad 81 is connected to the first electrode 51, and the second pad 82 is connected to the second electrode 52.

[0274] The conduction types of the first pad 81 and the second pad 82 are different and correspond to the conduction types of the first electrode 51 and the second electrode 52. For example, when the first electrode 51 is a p electrode, the first pad 81 is a p pad, and when the second electrode 52 is an n electrode, the second pad 82 is an n pad.

[0275] In the present disclosure, a nano-pillar array for realizing emission of different wavelengths is integrated in the chip structure. By changing the nano-pillars in the array, the stress caused by lattice mismatch during the epitaxial growth process of the group III nitride material can be regulated. On the one hand, the crystal quality of the epitaxial material can be improved, and the defect density in the material can be reduced, so as to obtain a high-brightness, high-efficiency, and high-performance Micro-LED chip. On the other hand, the emission wavelength of the Micro-LED chip is closely related to the nano-pillars in the array. Reducing the nano-pillar diameter is beneficial to stress release, so that more indium atoms can be incorporated into the quantum well layer, and finally the emission of long wavelengths can be realized.

[0276] It can be understood that the Micro-LED chip formed in the present disclosure is of the InGaN material system, but the LED chip structure and the preparation method provided by the embodiments of the present disclosure can also be applied to the AlInGaP material system, except that the epitaxial materials and the materials of the stacked structures used are different.

[0277] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps described in the present disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. No limitation is made herein.

[0278] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0279] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. An LED chip structure, characterized in that, The structure includes: a substrate, and a nucleation layer, a buffer layer, and an n-type GaN layer stacked in sequence on the substrate; an isolation layer on the n-type GaN layer; a nano-column array penetrating the isolation layer, wherein the nano-column array includes a plurality of nano-column units arranged in an array, and each nano-column unit includes a plurality of nano-columns with different diameters; in each nano-column unit, the plurality of nano-columns with different diameters are arranged in the order of diameter size along a first direction, wherein the first direction is a direction parallel to the plane of the substrate; or, in each nano-column unit, the plurality of nano-columns with different diameters are arranged in a polygon; the smaller the diameter of the nano-column, the higher the proportion of indium atoms in the nano-column, and the longer the emission wavelength corresponding to the nano-column.

2. The LED chip structure according to claim 1, wherein: a plurality of the nano-column units are arranged in an array along a row direction and a column direction, wherein the nano-column units in adjacent rows and adjacent columns are respectively aligned with each other.

3. The LED chip structure according to claim 1, wherein: a plurality of the nano-column units are arranged in an array along a row direction and a column direction, wherein the nano-column units in adjacent rows and adjacent columns are respectively arranged in a staggered manner, and the nano-column units separated by one row and one column are respectively aligned with each other.

4. The LED chip structure according to claim 1, wherein: the material of the isolation layer includes at least one of silicon dioxide or aluminum oxide.

5. The LED chip structure according to claim 1, wherein: the diameter range of the nano-column is 0.05 - 50 μm, and the distance between two adjacent nano-columns is 0.1 - 10 μm.

6. The LED chip structure according to claim 1, wherein: the height of the nano-column is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nano-column and the height of the isolation layer is less than or equal to 30 nm.

7. The LED chip structure according to claim 1, wherein: the shape of the projection of the nano-column in the direction perpendicular to the plane of the substrate includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

8. The LED chip structure according to claim 1, wherein: the nano-column includes a stress buffer layer, an active region light-emitting layer, an electron blocking layer, and a p-type GaN layer stacked in sequence.

9. The LED chip structure according to claim 1, wherein, The structure further includes: a transparent conductive layer on the isolation layer; a first electrode on the transparent conductive layer and a second electrode on the n-type GaN layer; a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode, and the second electrode; a distributed Bragg reflector layer on the passivation layer; a first pad and a second pad on the distributed Bragg reflector layer, the first pad is connected to the first electrode, and the second pad is connected to the second electrode.

10. A method for preparing an LED chip structure, characterized in that, The method includes: providing a substrate; forming a nucleation layer, a buffer layer, and an n-type GaN layer stacked in sequence on the substrate; forming an isolation layer on the n-type GaN layer; Form a plurality of through holes penetrating the isolation layer; Form nanocolumns in each of the through holes, and the plurality of nanocolumns form a nanocolumn array. Among them, the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each nanocolumn unit includes a plurality of nanocolumns with different diameters; in each nanocolumn unit, the plurality of nanocolumns with different diameters are arranged in the order of diameter size along a first direction, where the first direction is a direction parallel to the substrate plane; alternatively, in each nanocolumn unit, the plurality of nanocolumns with different diameters are arranged in a polygon; the smaller the diameter of the nanocolumn, the higher the proportion of indium atom components in the nanocolumn, and the longer the emission wavelength corresponding to the nanocolumn.

11. The method according to claim 10, wherein The forming a plurality of through holes penetrating the isolation layer; forming nanocolumns in each of the through holes includes: Form a photoresist layer on the isolation layer; Use a photolithography process to lithograph the photoresist layer to form a plurality of through hole positions in the photoresist layer, where the through holes include a variety of different diameters; Via the through hole positions, etch away the isolation layer not covered by the photoresist layer, and the etching stops on the upper surface of the n-type GaN layer to form the through holes; Form nanocolumns in each of the through holes.

12. The method according to claim 10, wherein The forming a plurality of through holes penetrating the isolation layer; forming nanocolumns in each of the through holes includes: Form a first photoresist layer on the isolation layer; Use a photolithography process to lithograph the first photoresist layer to form a plurality of first through hole positions in the first photoresist layer, where the first through holes have a first diameter; Via the first through hole positions, etch away the isolation layer not covered by the first photoresist layer, and the etching stops on the upper surface of the n-type GaN layer to form the first through holes; Form nanocolumns with a first diameter in each of the first through holes; Remove the first photoresist layer; Form a second photoresist layer on the isolation layer; Use a photolithography process to lithograph the second photoresist layer to form a plurality of second through hole positions in the second photoresist layer, where the second through holes have a second diameter; Via the second through hole positions, etch away the isolation layer not covered by the second photoresist layer, and the etching stops on the upper surface of the n-type GaN layer to form the second through holes; Form nanocolumns with a second diameter in each of the second through holes; And so on until all the nanocolumns are prepared.

13. The method according to any one of claims 10-12, wherein The forming nanocolumns in each of the through holes includes: Form a stress buffer layer, an active region light-emitting layer, an electron blocking layer, and a p-type GaN layer stacked in sequence in the through hole.

14. The method according to claim 10, wherein The plurality of nanocolumn units are arranged in an array along the row direction and the column direction, and the nanocolumn units in adjacent rows and adjacent columns are respectively aligned with each other.

15. The method according to claim 10, wherein A plurality of the nano-column units are arranged in an array in the row direction and the column direction, wherein the nano-column units in adjacent rows and adjacent columns are staggered respectively, and the nano-column units separated by one row and one column are aligned with each other respectively.

16. The method according to claim 10, wherein the diameter range of the nano-columns is 0.05 - 50 μm, and the distance between two adjacent nano-columns is 0.1 - 10 μm.

17. The method according to claim 10, wherein the height of the nano-columns is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nano-columns and the height of the isolation layer is less than or equal to 30 nm.

18. The method according to claim 10, wherein the shape of the projection of the nano-columns in the direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral, and a pentagon.

19. The method according to claim 10, characterized in that, The method further comprises: forming a transparent conductive layer on the isolation layer; forming a first electrode on the transparent conductive layer, and forming a second electrode on the n-type GaN layer; forming a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode, and the second electrode; forming a distributed Bragg reflector layer on the passivation layer; forming a first window and a second window passing through the distributed Bragg reflector layer and the passivation layer, the first window exposing the first electrode, and the second window exposing the second electrode; forming a first pad on the first window, the first pad being connected to the first electrode; forming a second pad on the second window, the second pad being connected to the second electrode.

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