Pixel driving circuit film layer, display screen and display equipment

Abstract

The embodiment of the invention provides a pixel driving circuit film layer, a display screen and display equipment. The pixel driving circuit film layer comprises a grid electrode part, an interlayer dielectric layer, a first wiring layer, a second wiring layer and a first planarization layer, the interlayer dielectric layer is arranged on the gate portion, the first wiring layer is arranged on the side, away from the gate portion, of the interlayer dielectric layer, the second wiring layer is arranged on the side, away from the gate portion, of the first wiring layer, and the first planarization layer is arranged on the side, away from the gate portion, of the second wiring layer; the first wiring layer and the second wiring layer are electrically connected, the first wiring layer and the second wiring layer are used for connecting a power supply voltage positive electrode and a data signal, equivalently, the cross sectional area of the wiring is increased or the wiring is connected in parallel, so that the resistance of the Vdd wiring and the Vdata wiring is reduced, the IR drop phenomenon can be relieved, the screen load is reduced, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit film layer, a display screen and a display device. Background Art

[0002] IR drop (voltage drop) refers to a phenomenon in which the power supply voltage drops in an integrated circuit. The main reason for the IR drop phenomenon is the voltage division of the metal wiring of the power supply network. It is caused by the resistance voltage division of the metal wiring, which causes the power supply voltage drop when the current passes through the internal power metal wiring.

[0003] For existing display screens, especially large and long screens, due to the long metal traces, there is a situation where the resistance of the Vdd (positive power supply voltage) and Vdata (data signal) metal traces is too large, resulting in serious IR drop and excessive screen load. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a pixel driving circuit film layer, a display screen and a display device to alleviate the IR drop phenomenon and reduce the screen load. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a pixel driving circuit film layer, comprising:

[0006] Gate part, interlayer dielectric layer, first wiring layer, second wiring layer and first planarization layer

[0007] The interlayer dielectric layer is arranged on the gate portion, the first wiring layer is arranged on a side of the interlayer dielectric layer away from the gate portion, the second wiring layer is arranged on a side of the first wiring layer away from the gate portion, and the first planarization layer is arranged on a side of the second wiring layer away from the gate portion;

[0008] The first routing layer and the second routing layer are electrically connected, and the first routing layer and the second routing layer are used to connect the positive electrode of the power supply voltage and the data signal.

[0009] In a possible implementation manner, the pixel driving circuit film layer further includes an anode layer and a pixel definition layer;

[0010] The anode layer is disposed on a side of the first planarization layer away from the gate portion, and the pixel definition layer is disposed on a side of the anode layer away from the gate portion.

[0011] In a possible implementation, the first wiring layer is a first source-drain electrode layer, and the second wiring layer is a second source-drain electrode layer; the first source-drain electrode layer and the second source-drain electrode layer both adopt a titanium / aluminum / titanium hierarchical structure.

[0012] In a possible embodiment, the pixel driving circuit film layer also includes a second planarization layer, the second planarization layer is arranged between the first source and drain layer and the second source and drain layer, a via is opened on the second planarization layer, and the first source and drain layer and the second source and drain layer are electrically connected through the via.

[0013] In a possible implementation manner, the area of ​​the via hole on the second planarization layer is not less than 75 μm 2 .

[0014] In a possible implementation manner, the via hole on the second planarization layer does not overlap with a projection of the pixel definition layer on the gate portion.

[0015] In a possible implementation manner, the second source-drain electrode layer is stacked on a side of the first source-drain electrode layer away from the gate portion, and projections of the first source-drain electrode layer and the second source-drain electrode layer on the gate portion at least partially overlap.

[0016] In a possible implementation manner, a projection of the second source-drain electrode layer on the gate portion is included in a projection of the first source-drain electrode layer on the gate portion.

[0017] In a possible implementation, the first routing layer is a first source and drain layer, and the second routing layer is a first gate layer; the first source and drain layer adopts a titanium / aluminum / titanium hierarchical structure, and the first gate layer is a molybdenum metal layer; the projections of the first source and drain layer and the first gate layer on the gate part at least partially overlap.

[0018] In a possible implementation manner, a projection of the first gate layer on the gate portion is included in a projection of the first source-drain layer on the gate portion.

[0019] In a possible implementation, the gate portion includes: a polysilicon layer, a first insulating layer, a third gate layer, a second insulating layer, and a second gate layer;

[0020] The first insulating layer is arranged on the polysilicon layer, the third gate layer is arranged on a side of the first insulating layer away from the polysilicon layer, the second insulating layer is arranged on a side of the third gate layer away from the polysilicon layer, and the second gate layer is arranged on a side of the second insulating layer away from the polysilicon layer.

[0021] In a possible implementation manner, the line width of the portion of the positive power supply voltage routing and the data signal routing of the first routing layer and the second routing layer corresponding to the via hole is not less than 5 μm.

[0022] In a second aspect, an embodiment of the present application provides a display screen, comprising any pixel driving circuit film layer described in the present application.

[0023] In a third aspect, an embodiment of the present application provides a display device, comprising any display screen described in the present application.

[0024] Beneficial effects of the embodiments of the present application:

[0025] The pixel driving circuit film layer provided in the embodiment of the present application includes: a gate portion, an interlayer dielectric layer, a first routing layer, a second routing layer and a first planarization layer; the interlayer dielectric layer is arranged on the gate portion, the first routing layer is arranged on a side of the interlayer dielectric layer away from the gate portion, the second routing layer is arranged on a side of the first routing layer away from the gate portion, and the first planarization layer is arranged on a side of the second routing layer away from the gate portion; the first routing layer and the second routing layer are electrically connected, and the first routing layer and the second routing layer are used to connect the positive electrode of the power supply voltage and the data signal, which is equivalent to increasing the cross-sectional area or connecting the routing in parallel. When the added second routing layer is made of the same material as the first routing layer, it can be regarded as increasing the conductor cross-sectional area S. According to the above resistance formula It can be seen that when the resistivity ρ and the conductor length L remain unchanged, the resistance R decreases when the conductor cross-sectional area S is increased. When the added second routing layer is made of a different material from the first routing layer, it can be regarded as a parallel routing (resistance). Assuming that the resistance of the first routing layer is R1 and the resistance of the second routing layer is R2, the total resistance of the parallel circuit is R = R1×R2 / (R1+R2), and R1×R2 / (R1+R2) is always less than R1, so R<R1, that is, the total resistance decreases after the parallel routing. Thereby reducing the resistance of the Vdd routing and the Vdata routing, the IR drop phenomenon can be alleviated, and the screen load can be reduced; and when the IRdrop phenomenon can be alleviated, the stability of the voltage of the Vdd routing and the Vdata routing can be increased, thereby increasing the display effect.

[0026] Of course, implementing any product or method of the present application does not necessarily require achieving all of the above advantages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0028] Figure 1 A schematic diagram of a pixel driving circuit film layer in the related art;

[0029] Figure 2 This is a first schematic diagram of a pixel driving circuit film layer according to an embodiment of the present application;

[0030] Figure 3 This is a second schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0031] Figure 4 This is a third schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0032] Figure 5a This is a fourth schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0033] Figure 5b In the embodiment of this application Figure 5a The pixel driving circuit film layer shown Figure 1 A comparison diagram of the Vdd routing and the Vdata routing of the pixel drive circuit film layer;

[0034] Figure 6 A schematic diagram of a via hole in the second planarization layer of an embodiment of the present application;

[0035] Figure 7 This is a fifth schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0036] Figure 8 This is a sixth schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0037] Figure 9a This is a seventh schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0038] Figure 9b In the embodiment of this application Figure 9a The pixel driving circuit film layer shown Figure 1 A comparison diagram of the Vdd routing and the Vdata routing of the pixel drive circuit film layer;

[0039] Fig.10 This is a schematic diagram of a completely overlapping projection in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of partially overlapping projections in an embodiment of the present application;

[0041] Fig.12 This is a schematic diagram of a projection 2 included in projection 1 in an embodiment of the present application;

[0042] Fig.13a This is an eighth schematic diagram of the pixel driving circuit film layer of an embodiment of the present application;

[0043] Fig.13b In the embodiment of this application Fig.13a The pixel driving circuit film layer shown Figure 1 A comparison diagram of the Vdd routing and the Vdata routing of the pixel drive circuit film layer;

[0044] Fig.14 A schematic diagram of the cross-sectional direction of a plan view of each pixel driving circuit film layer in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0046] In the relevant display screen, the metal traces of Vdd (positive power supply voltage) and Vdata (data signal) are as follows: Figure 1 As shown in the figure, the wiring resistance value is large, resulting in a more serious IR drop phenomenon, especially for large and long screens, the IR drop phenomenon is more obvious, the screen load is too large, and the display effect is poor.

[0047] In order to solve at least one of the above problems, the present application embodiment provides a pixel driving circuit film layer, see Figure 2 ,include:

[0048] Gate portion 01, interlayer dielectric layer (ILD, Inter Layer Dielectric) 02, first wiring layer 03, second wiring layer 04 and first planarization layer 05;

[0049] The interlayer dielectric layer 02 is arranged on the gate portion 01, the first wiring layer 03 is arranged on a side of the interlayer dielectric layer 02 away from the gate portion 01, the second wiring layer 04 is arranged on a side of the first wiring layer 03 away from the gate portion 01, and the first planarization layer 05 is arranged on a side of the second wiring layer 04 away from the gate portion 01;

[0050] The first wiring layer 03 and the second wiring layer 04 are electrically connected, and the first wiring layer 03 and the second wiring layer 04 are used to connect the positive electrode of the power supply voltage and the data signal.

[0051] The gate portion 01 is a composite film layer, which is used to realize part of the functions of the transistor in the pixel driving circuit. In a possible implementation, see Figure 3The gate portion 01 includes: a Poly layer (polysilicon layer) 011, a first insulating layer 012, a third gate layer 013, a second insulating layer 014, and a second gate layer 015; the first insulating layer 012 is arranged on the polysilicon layer 011, the third gate layer 013 is arranged on a side of the first insulating layer 012 away from the polysilicon layer 011, the second insulating layer 014 is arranged on a side of the third gate layer 013 away from the polysilicon layer 011, and the second gate layer 015 is arranged on a side of the second insulating layer 014 away from the polysilicon layer 011.

[0052] Among them, the Poly layer 011 is a transistor layer generated after the silicon wafer is doped in various ways, and the third gate layer 013 and the second gate layer 015 are routing layers, which can be used to arrange other routings other than Vdd routing and Vdata routing, such as Vss routing (negative power routing) or gate routing, etc.; the third gate layer 013 and the second gate layer 015 can be used to arrange horizontal routing and vertical routing respectively. The GI layer (insulating layer) is an insulating layer between the gate metal and the semiconductor in the transistor, which is usually made of SiNx or SiOx materials and is also called a gate insulating layer. The first insulating layer 012 is used to prevent the polysilicon layer 011 from short-circuiting with the third gate layer 013, and the second insulating layer 014 is used to prevent the third gate layer 013 from short-circuiting with the second gate layer 015; there may be no vias on the insulating layer, but in some scenarios, based on the actual needs of circuit planning, vias may also be provided on the first insulating layer 012 and the second insulating layer 014 to achieve electrical connection between the routings planned in the circuit design.

[0053] In one possible implementation, see Figure 4 The pixel driving circuit film layer also includes an Anode layer (anode layer) 06 and a PDL layer (pixel definition layer) 07; the anode layer 06 is arranged on a side of the first planarization layer 05 away from the gate part 01, and the pixel definition layer 07 is arranged on a side of the anode layer 06 away from the gate part 01.

[0054] The anode layer 06 is used to inject holes into the highest energy level full orbit of the organic material. Therefore, the anode layer 06 needs to use a metal or transparent conductive oxide with a higher work function to match the energy of the valence band of the organic material. The material of the anode layer 06 needs to meet four conditions: first, good conductivity; second, excellent chemical and physical stability; third, a work function that matches the energy level of the highest energy level full orbit of the hole injection material; fourth, high transparency in the visible light region. The materials of the anode layer 06 are mainly transparent conductive oxides and metals. In one example, the anode layer 06 can use ITO (indium tin oxide). The pixel definition layer is used to make the formation of the electroluminescent layer more convenient, avoid the mixing of organic light-emitting material layers between adjacent light-emitting devices, and provide a highly controllable and simple way to set the area, shape, and arrangement of the pixel unit. The pixel definition layer is generally set to two layers, one layer is a hydrophobic material and the other layer is a hydrophilic material.

[0055] In addition to the above-mentioned film layers, the pixel driving circuit film layer in the embodiment of the present application may also include a cathode layer (not shown in the figure) or an electroluminescent layer (not shown in the figure) and other film layers to realize the pixel light-emitting function, which are no longer listed one by one in the embodiment of the present application.

[0056] The first wiring layer 03 and the second wiring layer 04 include a Vdd wiring and a Vdata wiring, wherein the Vdd wiring is connected to the positive electrode of the power supply voltage, the positive electrode of the power supply voltage is used to provide the light-emitting voltage for the light-emitting element, and the Vdata wiring is connected to the data signal, and the data signal is used to control the light-emitting brightness of the light-emitting element. Generally, the light-emitting element in the pixel driving circuit includes a red light-emitting element, a green light-emitting element, and a blue light-emitting element, which can be specifically set according to actual needs. The first wiring layer 03 and the second wiring layer 04 are electrically connected, that is, the Vdd wiring of the first wiring layer 03 is electrically connected to the Vdd wiring of the second wiring layer 04, the Vdata wiring of the first wiring layer 03 is electrically connected to the Vdata wiring of the second wiring layer 04, and there is no electrical connection relationship between the Vdd wiring and the Vdate wiring.

[0057] The resistance calculation formula is: Where ρ is the resistivity, L is the conductor length, and S is the conductor cross-sectional area. In order to reduce the resistance of the trace, Figure 1Compared with the prior art shown in the figure, in the embodiment of the present application, it is equivalent to increasing the cross-sectional area or connecting the wiring in parallel. When the added second wiring layer 04 is made of the same material as the first wiring layer 03, it can be regarded as increasing the conductor cross-sectional area S. It can be seen from the above resistance formula that when the resistivity ρ and the conductor length L remain unchanged, the resistance R decreases when the conductor cross-sectional area S is increased. When the added second wiring layer 04 is made of a different material from the first wiring layer 03, it can be regarded as connecting the wiring (resistance) in parallel. Assuming that the resistance of the first wiring layer 03 is R1 and the resistance of the first wiring layer 03 is R2, the total resistance of the parallel circuit is R=R1×R2 / (R1+R2), and R1×R2 / (R1+R2) is always less than R1, so R<R1, that is, the total resistance decreases after the parallel wiring. Thereby, the resistance of the Vdd and Vdata lines is reduced, the IR drop phenomenon can be alleviated, and the screen load is reduced; and while the IR drop phenomenon can be alleviated, the stability of the voltage of the Vdd and Vdata lines can be increased, thereby improving the display effect.

[0058] The first routing layer 03 and the second routing layer 04 can be film layers of the same material; in a possible implementation, the first routing layer 03 is a first SD layer (first source and drain layer), and the second routing layer 04 is a second SD layer (second source and drain layer); the first source and drain layer and the second source and drain layer both adopt a Ti / Al / Ti (titanium / aluminum / titanium) hierarchical structure.

[0059] It can be seen from the above resistance calculation formula that, under the condition that ρ and L have been determined, the resistance can be reduced by increasing the conductor cross-sectional area S. The first wiring layer 03 and the second wiring layer 04 are made of the same material, which is equivalent to increasing the conductor cross-sectional area S, thereby reducing the resistance of the Vdd wiring and the Vdata wiring, alleviating the IR drop phenomenon, reducing the screen load, and increasing the display effect.

[0060] A PLN layer (planarization layer) may be disposed between the first source-drain electrode layer and the second source-drain electrode layer. In a possible implementation, see Figure 5a and Figure 5b ,in, Figure 5a is a cross-sectional view of a pixel driving circuit film layer including a second planarization layer 08, Figure 5b for Figure 5a The pixel driving circuit film layer shown is Figure 1 A top view of the Vdd routing and the Vdata routing in the pixel driving circuit film layer is shown; the pixel driving circuit film layer also includes a second planarization layer 08, the second planarization layer 08 is arranged between the first source and drain layer and the second source and drain layer, and a via is opened on the second planarization layer 08, and the first source and drain layer and the second source and drain layer are electrically connected through the via.

[0061] The material of the planarization layer can be an organic material, such as polyimide, etc. The planarization layer can flatten the in-plane height difference caused by various layer patterns on the display substrate, and can play a buffering role when the substrate is squeezed to protect the fragile film layer in the substrate. The first source and drain layer are electrically connected to the second source and drain layer through the vias of the second planarization layer 08, that is, the Vdd wiring of the first source and drain layer is electrically connected to the Vdd wiring of the second source and drain layer through the vias of the second planarization layer 08, and the Vdata wiring of the first source and drain layer is electrically connected to the Vdata wiring of the second source and drain layer through the vias of the second planarization layer 08. Whether in the same layer or across layers, the Vdd wiring is not connected to the Vdata wiring.

[0062] Furthermore, the wiring resistance can be reduced by reducing the via resistance. In a possible implementation, the area of ​​the via on the second planarization layer 08 is not less than 75 μm 2 .

[0063] In the related technology, the PLN layer generally adopts 3x3μm 2 Via or 12μm 2 In the embodiment of the present application, a large-area PLN via is used. The large-area PLN via here refers to an area of ​​75 μm 2 Up to 128μm 2 The use of large-area PLN vias can increase the contact area between the first source-drain layer and the second source-drain layer, and by increasing the contact area between the first source-drain layer and the second source-drain layer, the resistance of the Vdd routing and the Vdata routing is reduced. Since the large-area PLN vias are large in area, if integrated vias are used, it will affect the flatness of the film layers above the second PLN layer, such as the Anode layer, thereby affecting the display effect. In order to alleviate this problem, in an example, the large-area PLN vias are not continuous and can be distributed discontinuously along the Vdd routing or the Vdata routing, for example Figure 6 As shown. Through the discontinuous distribution design of large-area PLN vias, the uniformity of the film layer can be increased, especially when the PLN process flatness is poor, the discontinuous distribution design is adopted to increase the flatness of the Anode layer defined by the PDL layer opening area above the second PLN layer, thereby improving the display uniformity of the light-emitting device and alleviating the color deviation caused by poor Anode flatness. When the PLN process flatness is good, the PLN vias can also be opened below the PDL opening area to reduce the resistance of the Vdd and Vdata traces.

[0064] In one example, the large-area PLN via 09 needs to be within the common projection range of the first source-drain layer and the second source-drain layer. The cross-sectional view is as follows: Figure 7As shown. The projections of the first source-drain electrode layer and the second source-drain electrode layer on the gate portion 01 at least partially overlap, and the projection of the PLN via on the gate portion 01 is within the overlapping portion. The projections of the first source-drain electrode layer and the second source-drain electrode layer on the gate portion 01 at least partially overlap, including the cases where the projections completely overlap, the projections partially overlap, and one projection falls entirely within the other projection.

[0065] When the process level is high, the second planarization layer 08 does not affect the flatness of the Anode layer, so there is no need to specially set the position of the via. However, when the process level is limited, in order to ensure the flatness of the Anode layer, in an example, the via on the second planarization layer 08 does not overlap with the projection of the pixel definition layer 07 on the gate portion 01.

[0066] The vias on the second planarization layer 08 will affect the flatness of the film layer. The PDL layer 07 is used to define the pixel light-emitting portion. In order to ensure the display quality of the display substrate, it is necessary to ensure the flatness of the Anode layer of the pixel light-emitting portion defined by the PDL layer 07. In the embodiment of the present application, the large-area PLN vias 09 on the second planarization layer 08 avoid the bottom of the PDL layer 07 (there is no overlap in the projection direction on the gate portion 01), thereby improving the flatness of the Anode layer. In order to achieve that the large-area PLN vias 09 avoid the bottom of the PDL layer 07, that is, the vias on the second planarization layer 08 do not overlap with the projection of the pixel definition layer 07 on the gate portion 01, in one example, the large-area PLN vias 09 on the second planarization layer 08 are not continuous, and can be intermittently distributed along the Vdd routing or the Vdata routing, for example Figure 6 As shown, however, it is necessary to ensure that the large-area PLN via 09 is within the common projection range of the first source and drain layer and the second source and drain layer. The cross-sectional view is as shown in FIG. Figure 8 shown.

[0067] In the embodiment of the present application, the large-area PLN vias 09 are intermittently distributed along the Vdd routing or the Vdata routing, and the first projection (the projection of the large-area PLN vias 09 on the gate portion 01) is within the range of the second projection (the overlapping portion of the projections of the first source and drain layer and the second source and drain layer on the gate portion 01). This can reduce the resistance of the Vdd routing and the Vdata routing, alleviate the IR drop phenomenon, and reduce the screen load, while ensuring the flatness of the Anode layer of the pixel light-emitting portion defined by the PDL layer 07 to increase the display effect.

[0068] In addition, the resistance of the Vdd routing and the Vdata routing can be reduced by other means. In one example, in order to further reduce the resistance and slow down the IR drop phenomenon, the line width of the positive power voltage routing and / or the data signal routing in the first routing layer 03 and the second routing layer 04 can be increased, and the width of at least a portion of the positive power voltage routing and the data signal routing is set to be no less than 5 μm.

[0069] It can be seen from the above resistance calculation formula that under the condition that ρ and L have been determined, the resistance can be reduced by increasing the conductor cross-sectional area S. Therefore, the line width of the Vdd routing and the Vdata routing can be widened to more than 5μm in a location with sufficient space. By increasing the line width of the Vdd and Vdata routing, the routing resistance can be reduced to achieve the purpose of slowing down the IR drop phenomenon, reducing the screen load, and increasing the display effect. In a possible implementation, the line width of the part corresponding to the via in the positive power supply voltage routing and the data signal routing of the first routing layer and the second routing layer is not less than 5μm. In the embodiment of the present application, the first source and drain layer are overlapped with the second source and drain layer through a large-area PLN hole, relative to Figure 1 The design scheme shown adopts the pixel driving circuit film layer design of the embodiment of the present application. The resistance values ​​of the Vdd routing and the Vdata routing of a single sub-pixel are reduced by 57.26% and 25.89% respectively. It can be seen that the pixel driving circuit film layer in the embodiment of the present application reduces the resistance of the Vdd routing and the Vdata routing, can alleviate the IR drop phenomenon, reduce the screen load, and increase the display effect.

[0070] The second source-drain electrode layer may also be directly stacked on the first source-drain electrode layer. In a possible implementation, see Figure 9a and Figure 9b ,in, Figure 9a It is a cross-sectional view of a pixel driving circuit film layer in which a second source-drain electrode layer is directly stacked on the first source-drain electrode layer. Figure 9b for Figure 9a The pixel driving circuit film layer shown is Figure 1 A top view of the Vdd and Vdata wirings in the pixel driving circuit film layer shown in FIG. Figure 9a and Figure 9b As shown, the second source-drain electrode layer is stacked on a side of the first source-drain electrode layer away from the gate portion 01 , and projections of the first source-drain electrode layer and the second source-drain electrode layer on the gate portion 01 at least partially overlap.

[0071] The projections of the first source-drain layer and the second source-drain layer on the gate portion 01 at least partially overlap, including the case where the projections completely overlap, the projections partially overlap, and one projection completely falls within the other projection. For example, the projections of the first source-drain layer and the second source-drain layer on the gate portion 01 are projection 1 and projection 2, respectively. At least partially overlapping means that projection 1 and projection 2 have overlapping parts, including the case where projection 1 and projection 2 completely overlap (such as Fig.10 As shown), projection 1 and projection 2 only partially overlap (as shown Fig.11 ), and the case where one projection is completely within the other projection (as shown in Fig.12 As shown). Compared with the solution of setting a PLN layer between the first source-drain electrode layer and the second source-drain electrode layer, the second source-drain electrode layer is stacked on the first source-drain electrode layer, which can save a Mask process and reduce the thickness of the pixel driving circuit film layer; and because the first source-drain electrode layer is in direct contact with the second source-drain electrode layer, its resistance will also be smaller. However, because there is no flattening layer between the first source-drain electrode layer and the second source-drain electrode layer, the first source-drain electrode layer is in "hard" contact with the second source-drain electrode layer, which will lead to the problem that the display substrate is not flat and is easily damaged when facing external pressure.

[0072] In a possible implementation manner, the projection of the second source-drain electrode layer on the gate portion 01 is included in the projection of the first source-drain electrode layer on the gate portion 01. In the embodiment of the present application, the first source-drain electrode layer and the second source-drain electrode layer are directly stacked and deposited without vias, which can save a Mask process compared to the solution of setting a PLN layer between the first source-drain electrode layer and the second source-drain electrode layer; Figure 1 As shown in the design, the resistance value of the Vdd line and the Vdata line of a single sub-pixel is reduced by about 50% under this scheme. It can be seen that the pixel driving circuit film layer in the embodiment of the present application reduces the resistance of the Vdd line and the Vdata line, which can alleviate the IR drop phenomenon, reduce the screen load, and increase the display effect.

[0073] The first wiring layer 03 and the second wiring layer 04 can be film layers of different materials; in a possible implementation manner, see Fig.13a and Fig.13b ,in, Fig.13a This is a cross-sectional view of the pixel drive circuit film layer. Fig.13b for Fig.13a The pixel driving circuit film layer shown is Figure 1A top view of the Vdd routing and the Vdata routing in the pixel driving circuit film layer is shown; the first routing layer 03 is the first source and drain layer, and the second routing layer 04 is the first gate layer; the first source and drain layer adopts a titanium / aluminum / titanium hierarchical structure, and the first gate layer is a molybdenum metal layer; the projections of the first source and drain layer and the first gate layer on the gate part 01 at least partially overlap.

[0074] The projections of the first source and drain layer and the second source and drain layer on the gate portion 01 overlap at least partially, including complete overlap, partial overlap, and one projection completely falling within the other projection. After the first source and drain layer process is completed, Mo (molybdenum) metal, i.e., the first gate layer, can be deposited directly on the first source and drain layer. The projection of the Mo metal layer overlaps with the first source and drain layer without adding a via layer. Figure 8 The solution shown can save a Mask process. When the added second wiring layer 04 is made of different materials from the first wiring layer 03, it can be considered as parallel wiring (resistance), and the total resistance after parallel wiring is less than any one of the two resistors, that is, the resistance of the Vdd wiring and the Vdata wiring is reduced, which can alleviate the IR drop phenomenon and reduce the screen load; and in the case of being able to alleviate the IR drop phenomenon, the stability of the Vdd wiring and the Vdata wiring voltage can be increased, thereby improving the display effect.

[0075] In a possible implementation manner, the projection of the first gate layer on the gate portion 01 is included in the projection of the first source-drain layer on the gate portion 01. In the embodiment of the present application, the first gate layer of Mo metal is directly stacked and deposited on the first source-drain layer. Figure 1 In the design shown, the resistance values ​​of the Vdd and Vdata lines of a single sub-pixel are reduced by 9.05% and 9.11% respectively. It can be seen that the pixel driving circuit film layer in the embodiment of the present application reduces the resistance of the Vdd and Vdata lines, can alleviate the IR drop phenomenon, reduce the screen load, and increase the display effect.

[0076] It can be understood that the cross-sectional direction of the cross-sectional view of the pixel driving circuit film layer in the embodiment of the present application is as follows: Fig.14 Indicated by the direction of the arrow.

[0077] The embodiment of the present application also provides a display screen, including any pixel driving circuit film layer described in the present application. In addition, the display screen may also include a touch film layer and other parts. The specific structure of the touch film layer can refer to the relevant technology and is not specifically limited in the present application.

[0078] An embodiment of the present application also provides a display device, comprising any display screen described in the present application.

[0079] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0080] Each embodiment in this specification is described in a related manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0081] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A pixel driving circuit film layer, characterized in that, it includes: a gate part, an interlayer dielectric layer, a first wiring layer, a second wiring layer and a first planarization layer; The interlayer dielectric layer is disposed on the gate part, the first wiring layer is disposed on a side of the interlayer dielectric layer away from the gate part, the second wiring layer is disposed on a side of the first wiring layer away from the gate part, and the first planarization layer is disposed on a side of the second wiring layer away from the gate part; The first wiring layer and the second wiring layer are electrically connected, and the first wiring layer and the second wiring layer are used for connecting the positive electrode of the power supply voltage and the data signal.

2. The pixel driving circuit film layer according to claim 1, characterized in that, the pixel driving circuit film layer further includes an anode layer and a pixel definition layer; The anode layer is disposed on a side of the first planarization layer away from the gate part, and the pixel definition layer is disposed on a side of the anode layer away from the gate part.

3. The pixel driving circuit film layer according to claim 2, characterized in that, the first wiring layer is a first source-drain layer, and the second wiring layer is a second source-drain layer; both the first source-drain layer and the second source-drain layer adopt a titanium / aluminum / titanium hierarchical structure.

4. The pixel driving circuit film layer according to claim 3, characterized in that, the pixel driving circuit film layer further includes a second planarization layer, the second planarization layer is disposed between the first source-drain layer and the second source-drain layer, a via hole is formed on the second planarization layer, and the first source-drain layer and the second source-drain layer are electrically connected through the via hole.

5. The pixel driving circuit film layer according to claim 4, characterized in that, The area of the via in the second planarization layer is not less than 75 μm 2 .

6. The pixel driving circuit film layer according to claim 4, characterized in that, the via hole on the second planarization layer does not overlap with the projection of the pixel definition layer on the gate part.

7. The pixel driving circuit film layer according to claim 3, characterized in that, the second source-drain layer is stacked on a side of the first source-drain layer away from the gate part, and at least a part of the projections of the first source-drain layer and the second source-drain layer on the gate part overlap.

8. The pixel driving circuit film layer according to claim 7, characterized in that, the projection of the second source-drain layer on the gate part is included in the projection of the first source-drain layer on the gate part.

9. The pixel driving circuit film layer according to claim 1, characterized in that, the first wiring layer is a first source-drain layer, and the second wiring layer is a first gate layer; the first source-drain layer adopts a titanium / aluminum / titanium hierarchical structure, the first gate layer is a molybdenum metal layer; at least a part of the projections of the first source-drain layer and the first gate layer on the gate part overlap.

10. The pixel driving circuit film layer according to claim 9, characterized in that, the projection of the first gate layer on the gate part is included in the projection of the first source-drain layer on the gate part.

11. The pixel driving circuit film layer according to claim 1, characterized in that, The gate portion includes: a polysilicon layer, a first insulating layer, a third gate layer, a second insulating layer, and a second gate layer; The first insulating layer is disposed on the polysilicon layer, the third gate layer is disposed on a side of the first insulating layer away from the polysilicon layer, the second insulating layer is disposed on a side of the third gate layer away from the polysilicon layer, and the second gate layer is disposed on a side of the second insulating layer away from the polysilicon layer.

12. The pixel driving circuit film layer according to claim 4, wherein, in the positive power supply voltage trace and the data signal trace of the first trace layer and the second trace layer, the line width of the portion corresponding to the via is not less than 5 μm.

13. A display screen, wherein, it includes the pixel driving circuit film layer according to any one of claims 1-12.

14. A display device, wherein, it includes the display screen according to claim 13.

Images