A display panel and display device

Abstract

This disclosure relates to a display panel and display device, belonging to the field of display technology, comprising: a pixel circuit group including a first pixel circuit column and a second pixel circuit column, with data signal lines disposed between the first pixel circuit column and the second pixel circuit column; a first data writing module electrically connected to the data signal lines via a first switch, and a second data writing module electrically connected to the data signal lines via a second switch; the first switch is connected to a first control signal line, the second switch is connected to a second control signal line, each first control signal line is connected to a flexible circuit board via a first switch control line, and each second control signal line is connected to the flexible circuit board via a second switch control line. This reduces the number of data signal lines by half and decreases the number of multi-channel distribution units, which is beneficial for achieving a narrow bezel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] As display resolutions increase, the number of pixels also increases, leading to a rise in the number of data lines. Current display products typically use Demux circuits to connect these data lines to pads. However, Demux circuits are not conducive to achieving narrow bezels and can increase power consumption. Therefore, achieving both narrow bezels and reduced data lines in display products has become one of the most pressing technical challenges. Summary of the Invention

[0004] To address the aforementioned technical issues, this disclosure provides a display panel and display device that simultaneously achieve narrow bezels and reduce data cables in display products.

[0005] In a first aspect, this disclosure provides a display panel, comprising: a plurality of pixel circuit groups arranged along a first direction, the pixel circuit groups including a first pixel circuit column and a second pixel circuit column adjacent to each other along the first direction, the first pixel circuit column and the second pixel circuit column each including a plurality of pixel circuits arranged along a second direction, the first direction and the second direction intersecting;

[0006] In the pixel circuit group, a data signal line extending along the second direction is provided between the first pixel circuit column and the second pixel circuit column, and the pixel circuits in the first pixel circuit column and the second pixel column are electrically connected to the same data signal line;

[0007] The pixel circuit includes a data writing module. In the first pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line through a first switch. In the second pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line through a second switch. The first switch and the second switch are turned on in a time-division manner.

[0008] The display panel includes a first control signal line and a second control signal line extending along the second direction. The first switches corresponding to different pixel circuits in the first pixel circuit column are connected to the same first control signal line, and the second switches corresponding to different pixel circuits in the second pixel circuit column are connected to the same second control signal line.

[0009] The display panel includes a display area and a non-display area located on at least one side of the display area, the non-display area including a flexible circuit board;

[0010] The non-display area includes a first switch control line and a second switch control line extending along the first direction. Each of the first control signal lines is connected to the flexible circuit board through a first switch control line, and each of the second control signal lines is connected to the flexible circuit board through a second switch control line.

[0011] In a second aspect, this disclosure provides a display device including a display panel as described in the first aspect.

[0012] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0013] By setting a switch between the data writing module of the pixel circuit group and the corresponding data signal line, time-division conduction of adjacent pixel circuit columns can be achieved, and the number of data signal lines in the display panel can be halved, thereby reducing costs. By connecting each control signal line in different pixel circuit groups to its corresponding switch control line, and further connecting it to a flexible circuit board, the layout of multi-channel distribution units can be reduced, which is conducive to achieving a narrow bezel design and reducing power consumption. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 The diagram shown is a connection diagram of a display panel in the related art;

[0017] Figure 2 The diagram shown is a connection schematic of a display panel provided in an embodiment of this disclosure;

[0018] Figure 3 for Figure 2 Diagram of the middle pixel circuit connection;

[0019] Figure 4 The diagram shown is a wiring diagram of a data cable and connecting segments provided in an embodiment of this disclosure;

[0020] Figure 5 The diagram shown illustrates the relative positions of a data signal line, a control signal line, and a connecting trace, according to an embodiment of this disclosure.

[0021] Figure 6 The diagram shown is a schematic representation of the relative positional relationship between a first connecting line segment and a second connecting line segment according to an embodiment of this disclosure.

[0022] Figure 7 The diagram shown is a schematic representation of the film layer of a display panel according to an embodiment of this disclosure;

[0023] Figure 8 The diagram shown illustrates the relative positions of a second metal layer and a third metal layer according to an embodiment of this disclosure.

[0024] Figure 9 The diagram shown is a circuit layout provided in an embodiment of this disclosure;

[0025] Figure 10 The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0027] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0028] Figure 1 The diagram shown is a connection schematic of a display panel in related technologies. Please refer to it. Figure 1The display panel 100' includes a display area AA' and a non-display area NA', with the non-display area NA' located on at least one side of the display area AA'. The display area AA' includes multiple data lines D0' extending along a second direction D2' and arranged along a first direction D1'. The display area AA' includes a first display area AA1' and a second display area AA2', with the second display area AA2' located on at least one side of the first display area AA1'. The data lines D0' in the second display area AA2' extend to the first display area AA1' via connecting traces L0' and are then connected to fan-out traces S0' in the non-display area NA'. The connecting traces L0' include a first connecting segment L1' and a second connecting segment L2'. The non-display area NA' includes a multiplexing unit F0', which includes a switching element T'. A bonding area B0' is located on the side of the multiplexing unit F0' away from the display area AA', and the bonding area B0' includes multiple conductive pads P0' for bonding with a control chip. The switching element T' includes a control terminal, an input terminal, and an output terminal. Figure 1 Taking a multiplexing unit F0' comprising two switching elements T' as an example, the input terminals of the two switching elements T' in the same multiplexing unit F0' are connected together to connect to the same conductive pad P0'; the output terminals of the switching elements T' are connected one-to-one with the data lines D0' through fan-out traces S0', and the control terminals of the two switching elements T' in the same multiplexing unit F0' are connected one-to-one with two switch control lines K0'. That is, the conductive pad P0' is electrically connected to the data lines D0' through the switching elements T' in the multiplexing unit F0'. Related technologies achieve signal transmission of the data lines D0' by setting up multiplexing units F0' and connecting traces L0'. As the pixel density of display products increases, the number of data lines D0' increases. The setting of multiplexing units F0' is not conducive to the realization of narrow bezels and will lead to an increase in the power consumption of display products.

[0029] To address the aforementioned issues, this disclosure provides a display panel 100 that reduces the number of data cables, achieves a narrow bezel, and lowers production costs. Figure 2 The diagram shown is a connection schematic of a display panel provided in an embodiment of this disclosure. Figure 3 for Figure 2 Please refer to the schematic diagram of the mid-pixel circuit connection. Figure 2 and Figure 3 The present disclosure provides a display panel 100, including: a plurality of pixel circuit groups B0 arranged along a first direction D1, the pixel circuit group B0 including a first pixel circuit column B1 and a second pixel circuit column B2 adjacent along the first direction D1, the first pixel circuit column B1 and the second pixel circuit column B2 respectively including a plurality of pixel circuits B01 arranged along a second direction D2, the first direction D1 and the second direction D2 intersect. Figure 2This illustration only shows a portion of the pixel circuit groups B0 included on the display panel 100, and does not limit the actual number of pixel circuit groups B0 included on the display panel 100. Figure 2 The following is an example of how the first pixel circuit column B1 is located on one side of the second pixel circuit column B2 along the first direction D1. Figure 2 The pixel circuit B01 in the display panel 100 is only illustrated with a rectangular frame structure, and the actual structure of the pixel circuit B01 contained in the display panel 100 is not limited.

[0030] In pixel circuit group B0, a data signal line D0 extending along the second direction D2 is provided between the first pixel circuit column B1 and the second pixel circuit column B2, and the pixel circuit B01 in the first pixel circuit column B1 and the second pixel circuit column B2 is electrically connected to the same data signal line D0. Figure 2 and Figure 3 This illustration only shows a portion of the pixel circuits B01 included in the pixel circuit column on the display panel 100, and does not limit the actual number of pixel circuits B01 included in the pixel circuit column. It should be noted that the electrical connection mentioned in the embodiments of the present invention can be a direct connection between two connecting bodies, a signal connection between two connecting bodies formed by other line segments, or a signal connection between two connecting bodies formed by switching elements (such as transistors), etc.

[0031] Please refer to Figure 3 Pixel circuit B01 includes a data writing module X. The first pixel circuit column B1 includes a first pixel circuit B11, and the first data writing module X1 in each first pixel circuit B11 is electrically connected to the data signal line D0 via a first switch Y1. The second pixel circuit column B2 includes a second pixel circuit B12, and the second data writing module X2 in each second pixel circuit B12 is electrically connected to the data signal line D0 via a second switch Y2. The first switch Y1 and the second switch Y2 are time-divisionally activated; that is, the first pixel circuit column B1 and the second pixel circuit column B0 in the same pixel circuit group B0 are... The B2 columns share a single data signal line D0. By setting a switch Y between the data signal line D0 and the data writing module X in each pixel circuit B01, the first pixel circuit column B1 and the second pixel circuit column B2 can be time-divisionally turned on. This allows adjacent pixel circuit columns to share the data signal line D0, halving the number of data signal lines D0 in the display panel 100, thereby reducing costs. Halving the number of data signal lines D0 eliminates the need for a multiplexing unit, or reduces the number of switches in the multiplexing unit, which is beneficial for achieving a narrow bezel compared to related technologies.

[0032] Optionally, the pixel circuit B01 further includes a first reset transistor T5, a compensation transistor T4, a driving transistor T3, a write transistor T2, a first light-emitting control transistor T1, a second light-emitting control transistor T6, a second reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The two plates of the storage capacitor Cst are connected to the power signal line PVDD and the first node N1, respectively. The two terminals of the first reset transistor T5 are connected to the first reset signal line Vref1 and the first node N1, respectively, and the gate of the first reset transistor T5 is connected to the first scan line S1N. The two terminals of the compensation transistor T4 are connected to the third node N3 and the first reset transistor T5, respectively, and the gate of the write transistor T2 is connected to the second scan line S2N. The two terminals of the write transistor T2 are connected to the data signal line D0 and the second node N2, respectively, wherein a switch Y is included between the write transistor T2 and the data signal line D0, and the gate of the write transistor T2 is connected to the third scan line SP. The two terminals of the first light-emitting control transistor T1 are connected to the power signal line PVDD and the second node N2, respectively, and the gate of the first light-emitting control transistor T1 is connected to the light-emitting control line EMIT, respectively. The second light-emitting control transistor T6 has its terminals connected to the third node N3 and the fourth node N4, respectively, and its gate connected to the light-emitting control line EMIT. The second reset transistor T7 has its terminals connected to the second reset signal line Vref2 and the fourth node N4, respectively. The fourth node N4 is connected to the anode of the light-emitting element, and its gate is connected to the fourth scan line SP*. The bias transistor T8 has its terminals connected to the bias signal line VDH and the second node N2, respectively, and its gate connected to the fourth scan line SP*. It should be noted that in this embodiment, the driving circuit is described using P-type transistors as an example, but the type of transistor is not limited. Furthermore, Figure 3 The structure of the pixel driving circuit shown is for illustrative purposes only, and this disclosure is not intended to limit it.

[0033] It should be noted that, Figure 3 The diagram illustrates the correspondence between a first pixel circuit B11 in the first pixel circuit column B1 and a second pixel circuit B12 in the second pixel circuit column B2 and the data signal line D0. The correspondences between other pixel circuits B01 in the first pixel circuit column B1 and the second pixel circuit column B2 and the data signal line D0 can be referenced elsewhere. Figure 3 .

[0034] Please refer to Figure 2 and Figure 3 The display panel 100 includes a first control signal line S1 and a second control signal line S2 extending along the second direction D2. The first switches Y1 corresponding to different pixel circuits B01 in the first pixel circuit column B1 are connected to the same first control signal line S1, and the second switches Y2 corresponding to different pixel circuits B01 in the second pixel circuit column B2 are connected to the same second control signal line S2. Figure 2This illustration only shows a portion of the control signal lines S0 included on the display panel 100, and does not limit the actual number of control signal lines S0 included on the display panel 100. Figure 2 The explanation is based on the first control signal line S1 and the second control signal line S2 being located on both sides of the data signal line D0 along the first direction D1.

[0035] The display panel 100 includes a display area AA and a non-display area NA located on at least one side of the display area AA. The non-display area NA includes a flexible circuit board 01. The non-display area NA includes a first switch control line K1 and a second switch control line K2 extending along a first direction D1. Each first control signal line S1 is connected to the flexible circuit board 01 through a first switch control line K1, and each second control signal line S2 is connected to the flexible circuit board 01 through a second switch control line K2.

[0036] Specifically, in the first pixel circuit column B1, the first switch Y1 corresponding to each pixel circuit B01 is connected to the first control signal line S1. The first switch Y1 can be configured to be turned on or off by the first switch control signal applied by the first control signal line S1. In the second pixel circuit column B2, the second switch Y2 corresponding to each pixel circuit B01 is connected to the second control signal line S2. The second switch Y2 can be configured to be turned on or off by the second switch control signal applied by the second control signal line S2. The first control signal line S1 in different pixel circuit groups B0 is connected to a first switch control line K1 located in the non-display area NA, and the second control signal line S2 in different pixel circuit groups B0 is connected to a second switch control line K2 located in the non-display area NA. The first switch control line K1 and the second switch control line K2 extend along the first direction D1 and are respectively connected to the flexible circuit board 01. Optionally, the flexible circuit board 01 includes a control chip. The control chip can send control signals to the corresponding control signal line S0 through a conductive pad, a switch control line K0 electrically connected to the conductive pad, and a control signal line S0 connected to the switch control line K0 to realize the time-division conduction of the first switch Y1 and the second switch Y2. The display panel 100 also includes a driver chip 02. The driver chip 02 sends data signals to the corresponding data signal line D0. Through the time-division conduction of the first switch Y1 and the second switch Y2, the time-division conduction of the first pixel circuit column B1 and the second pixel circuit column B2 is realized, thereby realizing data signal transmission. In other words, in this embodiment of the present disclosure, it is not necessary to deploy a multi-way distribution unit in the non-display area NA to realize the data signal transmission from the flexible circuit board 01 to the data signal line D0, thereby providing space for the bezel of the display panel 100 and the display device to be compressed, which is conducive to realizing a further narrow bezel design of the display panel 100 and the display device and improving the user experience.

[0037] Thus, by setting a switch Y between the data writing module X of pixel circuit group B0 and the corresponding data signal line D0, time-division conduction of adjacent pixel circuit columns can be achieved, and the number of data signal lines D0 in the display panel 100 can be halved, thereby reducing costs. By connecting each control signal line S0 in different pixel circuit groups B0 to its corresponding switch control line K0, and further connecting it to the flexible circuit board 01, the layout of multi-channel distribution units can be reduced, which is beneficial for achieving a narrow bezel design and reducing power consumption.

[0038] It should be noted that, Figure 2 The connection between the first switch control line K1 and the second switch control line K2 and the flexible circuit board 01 is only shown in the illustration. The points where the first switch control line K1 and the second switch control line K2 are led out and connected to the flexible circuit board 01 can be located below the first display area AA1. This disclosure does not limit this.

[0039] Please continue to refer to Figure 2 and Figure 3 This disclosure provides a display panel 100, in which, between the first pixel circuit column B1 and the second pixel circuit column B2, along the first direction D1, the first control signal line S1 and the second control signal line S2 are respectively located on both sides of the data signal line D0.

[0040] Specifically, the pixel circuit group B0 includes a first pixel circuit column B1 and a second pixel circuit column B2. The first pixel circuit column B1 includes a plurality of first pixel circuits B11 arranged along the second direction D2, and the second pixel circuit column B2 includes a plurality of second pixel circuits B12 arranged along the second direction D2. The pixel circuit B01 includes a data writing module X. In the first pixel circuit column B1, the first data writing module X1 of each first pixel circuit B11 is connected to the data signal line D0 via a first switch Y1. In the second pixel circuit column B2, the second data writing module X2 of each second pixel circuit B12 is connected to the data signal line D0 via a second switch Y2. Each first switch Y1 is connected to the same first control signal line S1, and each second switch Y2 is connected to the same second control signal line S2. That is, in a pixel circuit group B0, there is a first control signal line S1, a second control signal line S2, and a data signal line D0. The first control signal line S1, the second control signal line S2, and the data signal line D0 are located between the first pixel circuit column B1 and the second pixel circuit column B2. Along the first direction D1, the data signal line D0 is located between the first control signal line S1 and the second control signal line S2, so that the distance from the data signal line D0 to the first control signal line S1 is the same as the distance from the data signal line D0 to the second control signal line S2, minimizing the influence of signal coupling and facilitating normal display. Thus, by placing the data signal line D0 between the first pixel circuit column B1 and the second pixel circuit column B2, the connection between the first control signal line S1 and the second control signal line S2 and the data signal line D0 can be facilitated. This ensures that the distance between the data signal line D0 and the first control signal line S1 and the second control signal line S2 is consistent, reducing the influence of signal coupling caused by unequal distances and facilitating the normal display of the display panel 100.

[0041] Figure 4 The diagram shown is a wiring schematic of a data cable and connecting segments provided in an embodiment of this disclosure. Please refer to it. Figure 2 and Figure 4 This disclosure provides a display panel 100, wherein a display area AA includes connecting line segments L0, and a non-display area NA includes fan-out traces S0; the non-display area NA includes a fan-out area A1 located on one side of the display area AA along a second direction D2, and the fan-out area A1 includes multiple fan-out traces S0; the display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located on at least one side of the first display area AA1 along a first direction D1. Optionally, in this embodiment, the first display area AA1 is located in the middle region of the display panel 100, and the second display area AA2 is located on one or both sides of the display panel 100 along the first direction D1. Figure 2 and Figure 4The following explanation will be based on the example of having a second display area AA2 on both sides of the first display area AA1.

[0042] The data signal line D0 includes a first data signal line D1 and a second data signal line D2. The first data signal line D1 is located in the first display area AA1, and the second data signal line D2 is located in the second display area AA2. The first data signal line D1 is electrically connected to the fan-out trace S0, and the second data signal line D2 is electrically connected to the fan-out trace S0 through the connecting trace L0. The connecting trace L0 is located in the display area AA and includes a first connecting segment L1 extending along the first direction D1 and a second connecting segment L2 extending along the second direction D2. The second data signal line D2 is electrically connected to the second connecting segment L2 located in the first display area AA1 through the first connecting segment L1. In the first display area AA1, the second connecting segment L2 is electrically connected to the fan-out trace S0.

[0043] Specifically, the first connecting segment L1 extends along the first direction D1 and connects to the second data signal line D2 in the second display area AA2. The second connecting segment L2 extends along the second direction D2 and connects to the fan-out trace S0 in the non-display area NA. The first data signal line D1 in the first display area AA1 is directly connected to the fan-out trace S0 in the non-display area NA. That is, the second data signal line D2 in the second display area AA2 is connected to the fan-out trace S0 through the connecting segment L0 to obtain a signal, and the first signal line in the first display area AA1 can be directly connected to the fan-out trace S0 to obtain a signal. In this way, by setting the connecting segment L0, it is not necessary to run wiring on the lower left and / or lower right bezel of the display panel 100. Instead, the second data signal line D2 is electrically connected to the fan-out trace S0 through the second connecting segment L2 in the first display area AA1. This provides compressed space for the lower left and / or lower right bezels of the display panel 100, which is beneficial for achieving a narrow bezel design of the product.

[0044] It should be noted that when the first connecting line segment L1 extends along the first direction D1, it means that the overall extension trend of the first connecting line segment L1 is in the first direction D1, and it does not require that the first connecting line segment L1 must be a straight line. Similarly, when the second connecting line segment L2 extends along the second direction D2, it means that the overall extension trend of the second connecting line segment L2 is in the second direction D2, and it does not require that the second connecting line segment L2 must be a straight line.

[0045] Please refer to Figure 4This disclosure provides a display panel 100, which further includes a plurality of first dummy line segments L01 extending along a first direction D1 and a plurality of second dummy line segments L02 extending along a second direction D2. The first dummy line segments L01 are disposed on the same layer as the first connecting line segment L1 and are insulated from the first connecting line segment L1 and the second connecting line segment L2. The second dummy line segments L02 are disposed on the same layer as the second connecting line segment L2 and are insulated from the second connecting line segment L2 and the first connecting line segment L1.

[0046] Specifically, when the first dummy line segment L01 and the first connecting line segment L1 are placed on the same film layer, these segments can be formed in the same process, which simplifies the wiring process. However, if the first dummy line segment L01 is not placed on the film layer containing the first connecting line segment L1, and the film layer containing the first connecting line segment L1 only contains the first connecting line segment L1, the uneven metal density of the film layer may lead to a mutagenesis effect due to differences in the reflective properties of the metal in different areas. Furthermore, this uneven metal density may result in poor uniformity of exposure and etching during the manufacturing process, leading to uneven linewidth of the first connecting line segment L1, which in turn increases the difference in capacitive load in different areas, affecting display uniformity. In this embodiment, a first dummy line segment L01 is provided on the film layer where the first connecting line segment L1 is located, and the extension direction of the first dummy line segment L01 is the same as the extension direction of the first connecting line segment L1. Furthermore, the first dummy line segment L01 is insulated from the first connecting line segment L1 and the second connecting line segment L2. This improves the uniformity of the metal density in the film layer where the first connecting line segment L1 is located, thereby mitigating the screen-off mura phenomenon that may result from uneven metal density and enhancing the display uniformity of the display panel 100. Similarly, when the second connecting line segment L2 and the second dummy line segment L02 are located on the same film layer, these segments can be formed in the same process, simplifying the wiring process. In this embodiment, a second dummy line segment L02 is provided in the film layer where the second connecting line segment L2 is located, and the extension direction of the second dummy line segment L02 is the same as the extension direction of the second connecting line segment L2. Furthermore, the second dummy line segment L02 is insulated from the first connecting line segment L1 and the second connecting line segment L2. This improves the uniformity of the metal density in the film layer where the second connecting line segment L2 is located, and helps to mitigate the screen-off mura phenomenon that may result from uneven metal density. Thus, by placing the first dummy line segment L01 in the same layer as the first connecting line segment L1 and insulated from it, and placing the second dummy line segment L02 in the same layer as the second connecting line segment L2 and insulated from it, the exposure and etching uniformity of the film layer etching can be improved, effectively improving the metal density of the film layer and enhancing display uniformity.

[0047] Please continue to refer to Figure 4This disclosure provides a display panel 100 in which, along a first direction D1, a data signal line D0 and a second connecting line segment L2 are located between a first control signal line S1 and a second control signal line S2 in at least a portion of the pixel circuit group B0; and in at least a portion of the pixel circuit group B0, along the first direction D1, a data signal line D0 and a second dummy line segment L02 are located between the first control signal line S1 and the second control signal line S2.

[0048] Specifically, in one optional embodiment provided in this disclosure, the second connecting segment L2 is located in the first display area AA1, at least a portion of the second dummy segment L02 is located in the first display area AA1, and at least a portion of the second dummy segment L02 is located in the second display area AA2. The second dummy segment L02 and the second connecting segment L2 extend in the same direction, are disposed in the same layer, and are insulated from each other. In the second display area AA2, along the first direction D1, a data signal line D0 and a second dummy segment L02 are included between the first control signal line S1 and the second control signal line S2; in the first display area AA1, along the first direction D1, at least a portion of the first control signal line S1 and the second control signal line S2 include a data signal line D0 and a second connecting segment L2, and at least a portion of the first control signal line S1 and the second control signal line S2 include a data signal line D0 and a second dummy segment L02; that is, a second connecting segment L02 can be provided between the first control signal line S1 and the second control signal line S2 in the second display area AA2 where the second connecting segment L2 is not provided. A dummy line segment L02 can be set between the first control signal line S1 and the second control signal line S2 in the first display area AA1 where no second connecting line segment L2 is set. Alternatively, a second connecting line segment L2 can be set between the first control signal line S1 and the second control signal line S2 in a portion of the first display area AA1, forming traces extending along the second direction D2 and uniformly distributed in the metal layer. This improves the uniformity of the trace arrangement in the metal layer, the uniformity of the metal density of the film layer where the second connecting line segment L2 is located, and the uniformity of exposure and etching of the film layer, effectively improving the metal density of the film layer and thus enhancing display uniformity. Therefore, by setting a second dummy line segment L02 between the first control signal line S1 and the second control signal line S2 where no second connecting line segment L2 is set, the uniformity of the trace arrangement in the metal layer can be improved, the metal density of the film layer can be effectively improved, and the display uniformity of the display panel 100 can be enhanced.

[0049] Figure 5 The diagram shown illustrates the relative positions of data signal lines, control signal lines, and connection traces according to an embodiment of this disclosure. Please refer to it. Figures 4 to 5 This disclosure provides a display panel 100 in which data signal line D0, first control signal line S1, second connection line segment L2, second control signal line S2 and second dummy line segment L02 are arranged on the same layer in at least a portion of the pixel circuit group B0.

[0050] Specifically, in one optional embodiment provided in this disclosure, the data signal line D0, the first control signal line S1, the second control signal line S2, and the second connecting segment L2 are arranged in the same layer. That is, the second dummy segment L02 is also located in the third metal layer M3. When the data signal line D0, the first control signal line S1, the second control signal line S2, the second connecting segment L2, and the second dummy segment L02 are arranged in the same layer, there is no need to introduce new film layers for the first control signal line S1 and the second control signal line S2, nor for the second connecting segment L2 and the second dummy segment L02. The first control signal line S1, the second control signal line S2, the second connecting segment L2, and the second dummy segment L02 can be fabricated in one production process using a single mask while the data signal line D0 is being fabricated. This simplifies the overall film layer structure of the display panel 100, reduces the number of masks in the process, and improves the production efficiency of the display panel 100. In this way, by setting the data signal line D0, the first control signal line S1, the second control signal line S2, the second connecting line segment L2, and the second dummy line segment L02 on the same layer, the above-mentioned wiring can be completed using only one mask in one production process, which simplifies the film layer structure and improves production efficiency.

[0051] Figure 6 The diagram shown illustrates the relative positional relationship between a first connecting segment and a second connecting segment according to an embodiment of this disclosure. Please refer to the provided text. Figures 4 to 6 This disclosure provides a display panel 100 in which the first connecting line segment L1 in each connecting line L0 is arranged on the same layer, the second connecting line segment L2 in each connecting line L0 is arranged on the same layer, and the first connecting line segment L1 and the second connecting line segment L2 are arranged on different layers.

[0052] Specifically, in one optional embodiment provided in this disclosure, the first connecting segments L1 are all located in the second metal layer M2, and the second connecting segments L2 are all located in the third metal layer M3. By placing the first connecting segments L1 and the second connecting segments L2 in different layers, the routing density in the third metal layer M3 can be reduced to avoid excessive congestion. Furthermore, it eliminates the need to consider short circuits between the first connecting segment L1 and different second connecting segments L2; ​​the first connecting segment L1 can simply be electrically connected to the corresponding second connecting segment L2 via a via, simplifying the routing of the first connecting segments L1 and L2. In addition, placing the first connecting segment L1 in the second metal layer M2 and the second connecting segment L2 in the third metal layer M3 reduces the number of insulating layers between the first connecting segment L1 and the second connecting segment L2, facilitating the via connection between them. Thus, by setting the first connecting segment L1 and the second connecting segment L2 on different layers, the probability of short circuit between the first connecting segment L1 and different second connecting segments L2 can be reduced, which helps to simplify the wiring difficulty.

[0053] Please refer to Figure 4 and Figure 6 This disclosure provides a display panel 100, wherein at least one first dummy line segment L01 is floating; and / or, at least one second dummy line segment L02 is floating.

[0054] Specifically, to simplify the manufacturing process, when both the first connecting segment L1 and the first dummy segment L01 are simultaneously provided in the film layer containing the first connecting segment L1, at least one of the first dummy segments L01 introduced into the film layer can be floated without being connected to other signal lines, thereby simplifying the manufacturing process such as drilling in the display panel 100. Alternatively, when both the second connecting segment L2 and the second dummy segment L02 are simultaneously provided in the film layer containing the second connecting segment L2, at least one of the second dummy segments L02 introduced into the film layer can be floated without being connected to other signal lines, which also helps to simplify the manufacturing process such as drilling in the display panel 100. Optionally, all the first dummy segments L01 in the film layer containing the first connecting segment L1 are floated, and all the second dummy segments L02 in the film layer containing the second connecting segment L2 are floated. In this way, while improving the uniformity of the metal density of the film layer, drilling can be reduced, further simplifying the manufacturing process.

[0055] Figure 7 The diagram shown is a schematic representation of the film layer of a display panel according to an embodiment of this disclosure. Figure 8 The diagram shown illustrates the relative positions of a second metal layer and a third metal layer according to an embodiment of this disclosure. Figure 9 The diagram shown is a circuit layout provided in an embodiment of this disclosure. Please refer to it. Figure 5 , Figure 7 and Figure 9This disclosure provides a display panel 100, which includes a substrate 00 and a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 disposed on the substrate 00. Along the thickness direction of the display panel 100, the capacitor metal layer MC is located on the side of the first metal layer M1 facing away from the substrate 00. The first metal layer M1 may be, for example, a gate metal layer, and the gate of a transistor T in the display panel 100 may be disposed on the first metal layer M1. The second metal layer M2 is located on the side of the capacitor metal layer MC facing away from the substrate 00, and the capacitor metal layer MC is used to form a capacitor structure with the first metal layer M1 or the second metal layer M2. The third metal layer M3 is located on the side of the second metal layer M2 facing away from the substrate 00, and the fourth metal layer M4 is located on the side of the third metal layer M3 facing away from the substrate 00. The display panel 100 further includes a metal layer M0 and a semiconductor layer poly. The metal layer M0 is located on the side of the first metal layer M1 facing the substrate, and serves to shield light and improve the anti-static capability of the display panel 100. The semiconductor layer poly is located on the side of the first metal layer M1 facing the substrate 00. In some other embodiments, the semiconductor layer poly may also be located on the side of the first metal layer M1 away from the substrate 00; this disclosure does not limit this. The semiconductor layer poly includes a source region and a drain region, which are formed by doping with N-type or P-type impurity ions. The source electrode s and drain electrode d of the transistor T in the display panel 100 may be located on the second metal layer M2, and the source electrode s and drain electrode d of the transistor T are electrically connected to the semiconductor layer poly through contact holes. Signal traces or dummy traces can be arranged on the second metal layer M2, the third metal layer M3, and the fourth metal layer M4. In an optional embodiment provided in this disclosure, the data signal line D0, the second connection segment L2, and the second dummy segment L02 are located on the third metal layer M3.

[0056] Specifically, if the data signal line D0, the second connecting segment L2, and the second dummy segment L02 are located on the same layer, such as the third metal layer M3, it simplifies the connection between the second data signal line D02 and the second connecting segment L2, reducing the need for vias. By placing the data signal lines D0, the second connecting segment L2, and the second dummy segment L02, all extending in the same direction, on the third metal layer M3, it is unnecessary to add an additional film layer for the second connecting segment L2 and the second dummy segment L02. The aforementioned traces can be fabricated simultaneously using only one photomask, simplifying the process and improving the uniformity of the metal density in the third metal layer M3. Please refer to [reference needed]. Figure 8 The power signal line PVDD can also be placed on the third metal layer M3. It should be noted that the power signal line PVDD must be insulated from the data signal line D0.

[0057] Please refer to Figures 5 to 9This disclosure provides a display panel 100, wherein a first connecting line segment L1 and a first dummy line segment L01 are located in a second metal layer M2.

[0058] Specifically, in one optional embodiment provided in this disclosure, the connecting segment L0 includes a first connecting segment L1 and a second connecting segment L2. The second connecting segment L2 and the second dummy segment L02 are located in the third metal layer M3, while the first connecting segment L1 and the first dummy segment L01 are located in the second metal layer M2. This allows for the fabrication of the source (s), drain (d), second connecting segment L2, and second dummy segment L02 using only a single mask, simplifying the process and improving the uniformity of the metal density in the second metal layer M2, thereby enhancing display uniformity. The first connecting segment L1 and the second connecting segment L2 are disposed in different layers and connected via vias, reducing the routing density of the third metal layer M3. Thus, by placing the first connecting segment L1 and the first dummy segment L01 in the second metal layer M2, the wiring density of the third metal layer M3 can be reduced, decreasing the probability of a short circuit between the first dummy segment L01 and the second connecting segment L2 or the second dummy segment L02, which is beneficial for improving display performance.

[0059] Please refer to Figure 2 , Figure 3 and Figure 9 This disclosure provides a display panel 100 in which the first pixel circuit column B1 and the second pixel circuit column B2, which are connected to the same data signal line D0, are arranged in a mirror image.

[0060] Specifically, within the same pixel circuit group B0, the first pixel circuit B11 in the first pixel circuit column B1 and the second pixel circuit B12 in the second pixel circuit column B2 can have substantially the same structure. Furthermore, the structures of the first pixel circuit B11 in the first pixel circuit column B1 and the second pixel circuit B12 in the second pixel circuit column B2 can be symmetrical to each other. For example, the first pixel circuit B11 in the first pixel circuit column B1 includes transistors T1 to T8, a storage capacitor Cst, and a light-emitting element. The transistors T1 to T8, the storage capacitor Cst, and the light-emitting element in the first pixel circuit column B1 can be configured to be symmetrical with those in the second pixel circuit column B2. Thus, by arranging the first pixel circuit column B1 and the second pixel circuit column B2, which are connected to the same data signal line D0, in a mirror image, it facilitates the connection of the newly introduced switch Y to both the data signal line D0 and the data writing module X, reducing wiring.

[0061] Please refer to Figure 3 and Figure 9This disclosure provides a display panel 100, and a data writing module X including a writing transistor T5, wherein no other transistors are disposed between the writing transistor T5 and the first switch Y1, and / or, no other transistors are disposed between the writing transistor T5 and the second switch Y2.

[0062] Specifically, in one optional embodiment provided in this disclosure, the write transistor T5 in the first pixel circuit column B1 is directly connected to the first switch Y1; in another optional embodiment provided in this disclosure, the write transistor T5 in the second pixel circuit column B2 is directly connected to the second switch Y2; in yet another optional embodiment provided in this disclosure, the write transistor T5 in the first pixel circuit column B1 is directly connected to the first switch Y1, and the write transistor T5 in the second pixel circuit column B2 is directly connected to the second switch Y2. That is, no other transistors are provided between the write transistor T5 in the first pixel circuit B11 and the first switch Y1, allowing data signals to be directly transmitted to the first pixel circuit B11 through the conduction of the first switch Y1 without passing through other switching elements; similarly, no other transistors are provided between the write transistor T5 in the second pixel circuit B12 and the second switch Y2, allowing data signals to be directly transmitted to the second pixel circuit B12 through the conduction of the second switch Y2 without passing through other switching elements, which is beneficial for improving signal transmission efficiency and increasing pixel density.

[0063] Figure 10 The diagram shown is a schematic representation of a display device according to an embodiment of this disclosure. Please refer to it. Figure 10 This disclosure provides a display device 200, including the display panel 100 as described above. The display device 200 provided in this disclosure can be any electronic device with display functionality, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this disclosure has the beneficial effects of the display panel 100 provided in this disclosure. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these descriptions will not be repeated here.

[0064] Understandable, Figure 10 The shape of the display device 200 is illustrated using only a right-angled rectangle structure as an example. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it in this regard.

[0065] In summary, the display panel and display device provided in this disclosure, by setting a switch between the data writing module of the pixel circuit group and the corresponding data signal line, can achieve time-division multiplexing of adjacent pixel circuit columns and halve the number of data signal lines in the display panel, thereby reducing costs. By connecting each control signal line in different pixel circuit groups to its corresponding switch control line and further connecting it to a flexible circuit board, the layout of multi-channel distribution units can be reduced, which is beneficial for achieving a narrow bezel design and reducing power consumption. By setting the data signal line between the first control signal line and the second control signal line, the distance between the data signal line and the first and second control signal lines can be made consistent, reducing the influence of signal coupling caused by unequal distances. By setting the connecting line segment, there is no need for wiring on the lower left and / or lower right bezels of the display panel, providing compressed space for the lower left and / or lower right bezels of the display panel, which is beneficial for achieving a narrow bezel design. By placing the first dummy line segment and the first connecting line segment in the same layer and insulating them, and by placing the second dummy line segment and the second connecting line segment in the same layer and insulating them, the exposure and etching uniformity of the film layer can be improved, effectively improving the metal density of the film layer and enhancing display uniformity. By setting the first dummy line segment and the second dummy line segment, the uniformity of the wiring arrangement in the metal layer can be improved, effectively enhancing the metal density of the film layer. Placing the data signal line, the first control signal line, the second control signal line, the second connecting line segment, and the second dummy line segment in the same layer allows the fabrication of the above wiring to be completed using only one mask in a single production process, simplifying the film layer structure and improving production efficiency. By placing the first connecting line segment and the second connecting line segment in different layers, the probability of short circuits between the first connecting line segment and different second connecting line segments can be reduced, which helps simplify wiring complexity. By placing the first connecting segment L1 and the first dummy segment in the second metal layer, the wiring density of the third metal layer can be reduced, the probability of short circuit between the first dummy segment and the second connecting segment or the second dummy segment can be reduced, which is beneficial to improving display performance.

[0066] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: A plurality of pixel circuit groups arranged along a first direction, the pixel circuit group including a first pixel circuit column and a second pixel circuit column adjacent along the first direction, the first pixel circuit column and the second pixel circuit column each including a plurality of pixel circuits arranged along a second direction, the first direction and the second direction intersecting; In the pixel circuit group, a data signal line extending along the second direction is provided between the first pixel circuit column and the second pixel circuit column, and the pixel circuits in the first pixel circuit column and the second pixel circuit column are electrically connected to the same data signal line. The pixel circuit includes a data writing module. In the first pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line through a first switch. In the second pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line through a second switch. The first switch and the second switch are turned on in a time-division manner. The display panel includes a first control signal line and a second control signal line extending along the second direction. The first switches corresponding to different pixel circuits in the first pixel circuit column are connected to the same first control signal line, and the second switches corresponding to different pixel circuits in the second pixel circuit column are connected to the same second control signal line. The display panel includes a display area and a non-display area located on at least one side of the display area, the non-display area including a flexible circuit board; The non-display area includes a first switch control line and a second switch control line extending along the first direction. Each of the first control signal lines is connected to the flexible circuit board through a first switch control line, and each of the second control signal lines is connected to the flexible circuit board through a second switch control line.

2. The display panel as described in claim 1, characterized in that, Between the first pixel circuit column and the second pixel circuit column, along the first direction, the first control signal line and the second control signal line are respectively located on both sides of the data signal line.

3. The display panel as described in claim 1, characterized in that, The display area includes connecting traces, and the non-display area includes fan-out traces; The non-display area includes a fan-out area located on one side of the display area along the second direction, and the fan-out area includes multiple fan-out traces; The display area includes a first display area and a second display area, the second display area being located on at least one side of the first display area along the first direction; the data signal line includes a first data signal line and a second data signal line, the first data signal line being located in the first display area, the second data signal line being located in the second display area, the first data signal line being electrically connected to the fan-out routing line, and the second data signal line being electrically connected to the fan-out routing line through the connecting routing line; The connection trace is located in the display area and includes a first connection segment extending along the first direction and a second connection segment extending along the second direction. The second data signal line is electrically connected to the second connection segment located in the first display area through the first connection segment. In the first display area, the second connecting line segment is electrically connected to the fan-out routing line.

4. The display panel as described in claim 3, characterized in that, The display panel further includes multiple first dummy line segments extending along the first direction and multiple second dummy line segments extending along the second direction. The first dummy line segments are disposed on the same layer as the first connecting line segments and are insulated from the first connecting line segments and the second connecting line segments. The second dummy line segments are disposed on the same layer as the second connecting line segments and are insulated from the second connecting line segments and the first connecting line segments.

5. The display panel as described in claim 4, characterized in that, In at least a portion of the pixel circuit group, along the first direction, the data signal line and the second connection segment are located between the first control signal line and the second control signal line; In at least a portion of the pixel circuit group, along the first direction, the data signal line and the second dummy line segment are located between the first control signal line and the second control signal line.

6. The display panel as described in claim 4, characterized in that, In at least a portion of the pixel circuit group, the data signal line, the first control signal line, the second connection segment, the second control signal line, and the second dummy segment are arranged on the same layer.

7. The display panel as described in claim 4, characterized in that, The first connecting segment in each of the aforementioned connecting traces is arranged on the same layer, the second connecting segment in each of the aforementioned connecting traces is arranged on the same layer, and the first connecting segment and the second connecting segment are arranged on different layers.

8. The display panel as described in claim 4, characterized in that, At least one of the first dummy line segments is floating; And / or, at least one of the second dummy segments is floating.

9. The display panel as described in claim 4, characterized in that, The display panel includes a substrate and a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer and a fourth metal layer disposed on the substrate. Along the thickness direction of the display panel, the capacitor metal layer is located on the side of the first metal layer away from the substrate, and the second metal layer is located on the side of the capacitor metal layer away from the substrate. The third metal layer is located on the side of the second metal layer that is away from the substrate, and the fourth metal layer is located on the side of the third metal layer that is away from the substrate; The data signal line, the second connecting segment, and the second dummy segment are located in the third metal layer.

10. The display panel as claimed in claim 9, characterized in that, The first connecting line segment and the first dummy line segment are located in the second metal layer.

11. The display panel as claimed in claim 1, characterized in that, The first pixel circuit column and the second pixel circuit column, which are connected to the same data signal line, are arranged in a mirror image.

12. The display panel as claimed in claim 1, characterized in that, The data writing module includes a data writing transistor, and no other transistors are disposed between the data writing transistor and the first switch, and / or no other transistors are disposed between the data writing transistor and the second switch.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

Images