Antenna switching receiver system for radar applications

Abstract

The invention relates to an antenna switching receiver system for radar applications. In an example, a system is provided that includes a first antenna sub-circuit (105), a second antenna sub-circuit (110), and a receiver sub-circuit (115). The first antenna sub-circuit (105) is configured to be coupled to a first antenna (101) and includes a first balun (106), a first transistor (107), and a first low noise amplifier (LNA) (109). The second antenna sub-circuit (110) is configured to be coupled to a second antenna (102) and includes a second balun (111), a second transistor (112), and a second LNA (114). The receiver sub-circuit (115) includes a transformer (117), a mixer (118), a first amplifier (119), a second amplifier (120), and an analog-to-digital converter (121). The receiver sub-circuit (115) is configured to receive a signal from the first antenna sub-circuit or the second antenna sub-circuit based on a state of the first transistor and the second transistor.

Description

Technical Field

[0001] This disclosure generally relates to antenna switching, and more particularly, to using a shared receiver channel for multiple antennas. Background Art

[0002] Radio frequency (RF) signal transmitting and receiving systems are used across a wide range of application areas, including telecommunications, telemetry, aerospace applications, wireless data transmission, satellite and radar imaging, etc. Such systems may include receiver circuitry that can interface with and receive signals from an antenna. The system may also include transmitter circuitry that can interface with the antenna to transmit signals from the antenna to a downstream system.

[0003] Various applications may employ receiver channel components to obtain signals from an antenna for processing. There are many antenna-receiver solutions for capturing antenna signals. However, many such solutions utilize one receiver channel per antenna. In other words, each antenna may be coupled to an independent receiver channel contained in an individual interconnect with a separate local oscillator. These solutions may require a relatively large amount of silicon area, consume higher power, and thus have a higher cost.

[0004] Various other solutions may employ switching elements to utilize multiple antennas per single receiver channel, which can reduce the silicon area requirements and cost relative to non-switching architectures. One example switching technique involves using a single-pole multiple-throw (SPMT) to couple one of multiple antennas to a single shared receiver channel. This technique can reduce the amount of silicon area. However, it may introduce problems such as high RF front-end losses, poor isolation between antennas, etc. when receiving antenna signals, because a single receiver channel is used for multiple antennas. Another example switching technique involves using a switch after the mixer in the receiver channel. This technique can improve the RF front-end noise performance and isolation. However, it may consume more power and silicon area than other switching techniques. Summary of the Invention

[0005] Various embodiments disclosed herein relate to antenna switching in a radar receiver system, and more particularly, to interfacing a shared receiver sub-circuit with multiple antenna interfacing sub-circuits that receive signals from corresponding antennas. An antenna switching system may include a plurality of antenna sub-circuits, each antenna sub-circuit capable of interfacing with an individual antenna and receiving signals from the corresponding antenna. Each of the antenna sub-circuits may be further coupled to a receiver sub-circuit. However, a switching mechanism may be included before a low-noise amplifier in each of the antenna sub-circuits such that the receiver sub-circuit receives signals from only one of the antenna sub-circuits.

[0006] In one example, a system is provided that includes a first antenna sub-circuit, a second antenna sub-circuit, and a receiver sub-circuit. The first antenna sub-circuit is configured to be coupled to a first antenna and includes a first balun, a first transistor, and a first low-noise amplifier. The second antenna sub-circuit is configured to be coupled to a second antenna and includes a second balun, a second transistor, and a second low-noise amplifier. The receiver sub-circuit includes: a transformer having a first set of terminals coupled to the first low-noise amplifier and the second low-noise amplifier and a second set of terminals coupled to a mixer; a mixer; a first amplifier; a second amplifier; and an analog-to-digital converter. The receiver sub-circuit is configured to receive a signal from the first antenna sub-circuit or the second antenna sub-circuit based on the states of the first transistor and the second transistor.

[0007] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. It is understood that this summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Illustrates an antenna receiver system that may be used according to an embodiment.

[0009] Figure 2 Illustrates an antenna receiver system that may be used according to an embodiment.

[0010] Figure 3 Illustrates a transceiver and receiver system that may be used according to an embodiment.

[0011] Figure 4 Illustrates an example graphical representation related to the gain produced by an antenna receiver system according to an embodiment.

[0012] Figure 5 Illustrates an example graphical representation related to the noise produced by an antenna receiver system according to an embodiment.

[0013] Figure 6 Illustrates an example graphical representation related to the power produced by an antenna receiver system according to an embodiment.

[0014] The figures are not necessarily drawn to scale. In the figures, like reference numerals throughout the several views indicate corresponding parts. In some embodiments, components or operations may be separated into different blocks or combined into a single block. DETAILED DESCRIPTION

[0015] This document discusses enhanced components, techniques, and systems related to antenna switching in receiver and transceiver systems. RF and radar circuits are often designed to receive and transmit signals at varying frequencies and with variable gains from more than one antenna. For example, an RF circuit uses antenna signals as inputs and uses electronic components to output different signals to downstream systems with different bandwidths, sometimes using the same or different antennas. However, to save silicon area and cost, many systems include a single receiver channel that can handle incoming radar signals from multiple antennas. Thus, an antenna switching component can be implemented to switch between antennas to process certain data at a given time.

[0016] Existing antenna switching designs can use switching elements either before any processing circuitry or after the mixing circuitry. However, although saving design space and cost, the first of these solutions may not isolate each channel, increase losses in the RF front end, and result in poor signal-to-noise ratio (SNR). The latter of these solutions can improve channel-to-channel (i.e., antenna channel-to-antenna channel) isolation and SNR, but will occupy a large silicon area and consume an increased amount of power during operation. Thus, there is a need for an antenna switching circuit that can provide sufficient isolation and gain to reduce the noise sensitivity in the system, match the impedance of the antenna signals, and minimize power consumption and design area requirements.

[0017] Disclosed herein is an antenna switching system that includes: individual antenna signal receiving sub-circuits, each having a respective differential low-noise amplifier (LNA) and a shunt transistor switch between the differential inputs of the LNA; and a combined receiver sub-circuit that is capable of mixing the received signals and converting the received signals into digital signals. Based on the signal applied to the control gate of the transistor, the transistor can operate as an open switch or a closed switch. When one transistor is in the open state, the other transistor can be in the closed state. When the transistor is "on" or in the closed state, the antenna signal may not flow to the corresponding LNA. On the other hand, the transistor of another antenna signal receiving sub-circuit can be in the "off" or open state, and its corresponding LNA can be operative to amplify and impedance-match the received signal. Only the operative LNA can operate and provide such signals to the receiver sub-circuit for further processing, such as mixing and conversion. Advantageously, the disclosed system can: enable one antenna and the corresponding antenna sub-circuit at a time, which can reduce power consumption, reduce noise, and increase antenna-channel isolation; and use a single shared receiver sub-circuit to mix and convert the antenna signals, which can reduce the required design area while improving gain and band matching, among other benefits.

[0018] In an example embodiment, a system is provided that includes a first antenna sub-circuit, a second antenna sub-circuit, and a receiver sub-circuit. The first antenna sub-circuit is configured to be coupled to a first antenna and includes a first balun, a first transistor, and a first low-noise amplifier. The second antenna sub-circuit is configured to be coupled to a second antenna and includes a second balun, a second transistor, and a second low-noise amplifier. The receiver sub-circuit includes: a transformer having a first set of terminals coupled to the first low-noise amplifier and the second low-noise amplifier and a second set of terminals coupled to a mixer; a mixer; a first amplifier; a second amplifier; and an analog-to-digital converter. The receiver sub-circuit is configured to receive a signal from the first antenna sub-circuit or the second antenna sub-circuit based on the states of the first transistor and the second transistor.

[0019] In another example embodiment, a system is provided that includes a first antenna, a second antenna, a first antenna sub-circuit, a second antenna sub-circuit, and a receiver sub-circuit. The first antenna sub-circuit is configured to be coupled to the first antenna and includes a first balun, a first transistor, and a first low-noise amplifier. The second antenna sub-circuit is configured to be coupled to the second antenna and includes a second balun, a second transistor, and a second low-noise amplifier. The receiver sub-circuit includes: a transformer having a first set of terminals coupled to the first low-noise amplifier and the second low-noise amplifier and a second set of terminals coupled to a mixer; a mixer; a first amplifier; a second amplifier; and an analog-to-digital converter. The receiver sub-circuit is configured to receive a signal from the first antenna sub-circuit or the second antenna sub-circuit based on the states of the first transistor and the second transistor.

[0020] In yet another example embodiment, a system is provided that includes a receiver circuit and a transceiver circuit. The receiver circuit is configured to be coupled to a first antenna and a second antenna, and the transceiver circuit is configured to be coupled to a third antenna and the receiver circuit. The receiver circuit includes a first antenna sub-circuit, a second antenna sub-circuit, and a receiver sub-circuit. The first antenna sub-circuit includes a first balun, a first transistor, and a first low-noise amplifier. The second antenna sub-circuit includes a second balun, a second transistor, and a second low-noise amplifier. The receiver sub-circuit includes: a transformer having a first set of terminals coupled to the first low-noise amplifier and the second low-noise amplifier and a second set of terminals coupled to a mixer; a mixer; a first amplifier; a second amplifier; and an analog-to-digital converter. The receiver sub-circuit is configured to receive a signal from the first antenna sub-circuit or the second antenna sub-circuit based on the states of the first transistor and the second transistor. The transceiver circuit is configured to receive the mixed signal from the mixer of the receiver sub-circuit and transmit the mixed signal via the third antenna.

[0021] Figure 1Shows an antenna receiver system that can be used according to an embodiment. Figure 1 Includes system 100, which includes antennas 101, 102, antenna sub-circuit 105, antenna sub-circuit 110, and receiver sub-circuit 115. Antenna sub-circuit 105 includes a balun 106, a transistor 107, and a low-noise amplifier (LNA) 109. Antenna sub-circuit 110 includes a balun 111, a transistor 112, and an LNA 114. Receiver sub-circuit 115 includes a transformer 117, a mixer 118, a local oscillator buffer amplifier 119, an intermediate frequency (IF) amplifier 120, and an analog-to-digital converter (ADC) 121.

[0022] System 100 represents a circuit capable of performing the following operations: receiving signals from antennas 101 and 102, selectively enabling one of antenna sub-circuits 105 and 110 to amplify the signal from the corresponding antenna, providing the amplified signal to receiver sub-circuit 115 using the enabled one of antenna sub-circuits 105 or 110, and processing and converting the amplified signal into a digital signal. For example, each of antenna sub-circuits 105 and 110 may include a switch (transistors 107 and 112, respectively), which can be opened or closed to enable the use of one of antenna sub-circuits 105 or 110. Thus, system 100 can implement antenna switching using a shared receiver sub-circuit 115 for antenna sub-circuits 105 and 110.

[0023] Antennas 101 and 102 represent antennas capable of receiving signals from a radio, satellite, or another device and converting the signals into currents that are provided to components of system 100. Antennas 101 and 102 can operate in various bandwidths and radio frequencies. Antennas 101 and 102 may also be capable of transmitting signals to a radio, satellite, or another device.

[0024] In system 100, antenna sub-circuit 105 is configured to be coupled to antenna 101, and antenna sub-circuit 110 is configured to be coupled to antenna 102. In various instances, antenna sub-circuits 105 and 110 may be part of a system-on-chip (SoC). Antennas 101 and 102 may be coupled to components of antenna sub-circuits 105 and 110 via pins, ports, or other connection points of the package. Thus, antennas 101 and 102 may be off-chip or on the package. Additional antennas and antenna sub-circuits may be included in other instances.

[0025] The antenna sub - circuit 105 includes a balun 106, a transistor 107, and an LNA 109. Similarly, the antenna sub - circuit 110 includes a balun 111, a transistor 112, and an LNA 114. The baluns 106 and 111 may represent electrical devices that can provide an interface between the antennas 101 and 102, respectively, and the other components of the antenna sub - circuits 105 and 110. The baluns 106 and 111 may be configured to provide differential signals (i.e., a first signal and a second signal having an opposite polarity with respect to the first signal) to the other components based on the signals received from the respective antennas. The baluns 106 and 111 may each include two inductors that form a DC decoupling between a single - ended input and a differential output, which can provide electrostatic discharge (ESD), match the impedance of the antenna signal, and generate a positive signal and a negative signal based on the antenna signal. Each of the inductors of the baluns 106 and 111 has two terminals. The first inductor of the balun 106 may have a first terminal configured to be coupled to the antenna 101 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 106 may include a first terminal coupled to the drain of the transistor 107 and a second terminal coupled to the source of the transistor 107. The second inductor may further include a center - tap node that may be coupled to receive a DC bias voltage (e.g., 0.7V when in the "on" state) for the LNA 109. Similarly, the first inductor of the balun 111 may have a first terminal configured to be coupled to the antenna 102 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 111 may include a first terminal coupled to the drain of the transistor 112 and a second terminal coupled to the source of the transistor 112. The second inductor may further include a center - tap node that may be coupled to receive a different DC bias voltage (e.g., 0V when in the "off" state) for the LNA 114.

[0026] Transistors 107 and 112 may be n-type metal-oxide semiconductor field effect transistors (MOSFETs). However, other types of transistors may be included in system 100. Accordingly, each of transistors 107 and 112 includes a gate, a drain, and a source. Transistor 107 may receive a positive signal from balun 106 at its drain and a negative signal from balun 106 at its source. The drain of transistor 107 may be further coupled to a first input of LNA 109, and the source of transistor 107 may be further coupled to a second input of LNA 109. The gate of transistor 107 may be coupled to a controller, a processor, or other control device or logic device capable of providing a signal to the gate of transistor 107. Transistor 112 may receive a positive signal from balun 111 at its drain and a negative signal from balun 111 at its source. The drain of transistor 112 may be further coupled to a first input of LNA 114, and the source of transistor 112 may be further coupled to a second input of LNA 114. The gate of transistor 112 may also be coupled to a controller, a processor, or other control device or logic device capable of providing a signal to the gate of transistor 112.

[0027] In various examples, a processor (e.g., a CPU) may provide an inverted enable signal 108 to the gate of transistor 107 and a non-inverted version of the enable signal 113 to the gate of transistor 112. The inverted enable signal 108 may have a first value, and the enable signal 113 may have a second value that is opposite to the first value. In other words, the inverted enable signal 108 and the enable signal 113 are opposite to each other. The value of the inverted enable signal 108 may affect the operation of transistor 107 such that when the inverted enable signal 108 has a value of 0, transistor 107 may be in an off state or operate as an open switch, and the corresponding balun 106 is capable of providing a non-zero differential signal to the LNA 109. However, when the value of the inverted enable signal 108 has a value of 1, transistor 107 may be in a closed state or operate as a closed switch, and the current through transistor 107 may prevent the balun 106 from providing a non-zero differential signal to the LNA 109. The value of the enable signal 113 may affect the operation of transistor 112 such that when the enable signal 113 has a value of 0, transistor 112 may be in an off state or operate as an open switch, and the corresponding balun 111 is capable of providing a non-zero differential signal to the LNA 114. However, when the value of the enable signal 113 has a value of 1, transistor 112 may be in a closed state or operate as a closed switch, and the current through transistor 112 may prevent the balun 111 from providing a non-zero differential signal to the LNA 114. Because the inverted enable signal 108 and the enable signal 113 have opposite values, only one of the LNAs 109 and 114 may be in operation or active at a time. Thus, transistors 107 and 112 may be used as switching elements that determine which antenna subcircuit provides a signal to the receiver subcircuit 115.

[0028] LNAs 109 and 114 represent low noise amplifiers that are capable of amplifying differential signals from baluns 106 and 111, respectively, while minimizing degradation of the signal-to-noise ratio of the antenna signals and matching the impedance of the differential signals to improve power transmission of the differential signals. In various examples, LNAs 109 and 114 may be configured to operate in a common source configuration.

[0029] LNAs 109 and 114 may each include two output ports coupled to a transformer 117 of the receiver subcircuit 115. More specifically, the transformer 117 may have a first set of terminals and a second set of terminals. The first set of terminals may include a first end and a second end, and the second set of terminals may include a first end and a second end. The first output ports of LNAs 109 and 114 may be coupled to the first end of the first set of terminals of the transformer 117. The second output ports of LNAs 109 and 114 may be coupled to the second end of the first set of terminals of the transformer 117.

[0030] In operation, LNA 109 or LNA 114 may provide a differential signal to transformer 117 of receiver sub-circuit 115 based on the states of transistors 107 and 112, or in other words, based on the values of the inverting enable signal 108 and the enable signal 113.

[0031] Receiver sub-circuit 115 represents a receiver channel in system 100 that may be configured to receive signals from antenna sub-circuit 105 or antenna sub-circuit 110, mix, down-convert, amplify, and perform similar operations on the signals, and provide the signals downstream to other systems or sub-circuits (e.g., digital signal processors, differential front-ends) (not shown). In various examples, receiver sub-circuit 115 may include transformer 117, mixer 118, local oscillator buffer amplifier 119, IF amplifier 120, and ADC 121.

[0032] As mentioned, transformer 117 includes a first set of terminals and a second set of terminals, each set of terminals including a first end and a second end. The second set of terminals may be coupled to mixer 118. Mixer 118 represents an electronic device capable of combining two or more different differential signals into a combined differential signal, such as a differential signal from one of LNAs 109 or 114 and a differential signal from local oscillator buffer amplifier 119. More specifically, local oscillator buffer amplifier 119 may be coupled to receive clock signal 116 from a local oscillator (not shown). Clock signal 116 may be a differential clock signal that may be fed into an input of local oscillator buffer amplifier 119. Local oscillator buffer amplifier 119 may include an intermediate frequency amplifier or another type of amplifier. Local oscillator buffer amplifier 119 may amplify or convert clock signal 116 and provide clock signal 116 to mixer 118. Mixer 118 may then combine clock signal 116 with the differential signal received at transformer 117. In various examples, mixer 118 may operate as a down-converter, however, in other examples, mixer 118 may be used as an up-converter.

[0033] Mixer 118 may be further coupled to IF amplifier 120. IF amplifier 120 may be configured to further amplify the down-converted differential signal in receiver sub-circuit 115. The IF amplifier may include two output ports coupled to two input ports of ADC 121 and may provide the signal to ADC 121.

[0034] ADC 121 is included in receiver sub-circuit 115 to convert the modulated and mixed differential signal from analog to digital. ADC 121 may convert the positive signal into output 125 and the negative signal into output 126. ADC 121 may provide outputs 125 and 126 downstream.

[0035] In various examples, system 100 can be used in applications with time division multiplexing. For example, enable signal 113 and inverted enable signal 108 can be provided to transistors 112 and 107 respectively in fixed order time periods. More specifically, a first value of the signal can be provided at a first time to receive a signal from antenna 101 via antenna sub-circuit 105, and subsequently, a second value of the signal can be provided at a second time to receive a signal from antenna 102 via antenna sub-circuit 110. In such examples, the time periods can be predetermined values provided to the processor to enable the antenna sub-circuits. However, in some cases, the time periods can be target specific, antenna specific, or dynamically changed based on the desired capture of radar data of antennas 101 and 102.

[0036] Figure 2 An antenna receiver system that can be used according to an embodiment is shown. Figure 2 It includes system 200, which includes antennas 201, 202, 203, and 204, antenna sub-circuits 205, 210, 215, and 220, and receiver sub-circuit 230. Antenna sub-circuit 205 includes a balun 206, a transistor 207, and a low noise amplifier (LNA) 209. Antenna sub-circuit 210 includes a balun 211, a transistor 212, and an LNA 214. Antenna sub-circuit 215 includes a balun 216, a transistor 217, and an LNA 219. Antenna sub-circuit 220 includes a balun 221, a transistor 222, and an LNA 224. Receiver sub-circuit 230 includes a transformer 232, a mixer 233, a local oscillator buffer amplifier 234, an intermediate frequency (IF) amplifier 235, and an analog-to-digital converter (ADC) 236.

[0037] System 200 represents a circuit capable of performing the following operations: receiving signals from antennas 201, 202, 203, and 204, selectively enabling one of antenna sub-circuits 205, 210, 215, and 220 to amplify the signal from the corresponding antenna, using the enabled one of the antenna sub-circuits to provide the amplified signal to receiver sub-circuit 230, and processing and converting the amplified signal into a digital signal. For example, each of antenna sub-circuits 205, 210, 215, and 220 can include a switch (transistors 207, transistor 212, transistor 217, and transistor 222 respectively), and the switches can be opened or closed to enable the use of one of antenna sub-circuits 205, 210, 215, or 220. Thus, system 200 can implement antenna switching using a shared receiver sub-circuit 230 among four different antennas.

[0038] Antennas 201, 202, 203, and 204 represent antennas that are capable of receiving signals from a radio, satellite, or another device and converting the signals into an electric current that is provided to components of system 200. Each of the antennas may operate in various bandwidths and radio frequencies. Antennas 201, 202, 203, and 204 may also be capable of transmitting signals to a radio, satellite, or another device.

[0039] In system 200, antenna sub-circuit 205 is configured to couple to antenna 201, antenna sub-circuit 210 is configured to couple to antenna 202, antenna sub-circuit 215 is configured to couple to antenna 203, and antenna sub-circuit 220 is configured to couple to antenna 204. In various examples, all of the antenna sub-circuits may be part of a system-on-chip (SoC). Antennas 201, 202, 203, and 204 may be coupled to components of antenna sub-circuits 205, 210, 215, and 220, respectively, via pins, ports, or other connection points of a circuit board. Thus, antennas 201, 202, 203, and 204 may be off-chip or on-package. Additional or fewer antennas and antenna sub-circuits may be included in other examples.

[0040] The antenna sub-circuit 205 includes a balun 206, a transistor 207, and an LNA 209. The antenna sub-circuit 210 includes a balun 211, a transistor 212, and an LNA 214. The antenna sub-circuit 215 includes a balun 216, a transistor 217, and an LNA 219. And the antenna sub-circuit 220 includes a balun 221, a transistor 222, and an LNA 224. The baluns 206, 211, 216, and 221 (collectively referred to as baluns) may represent electrical devices that can provide an interface between the antennas 201, 202, 203, and 204 and other components of the respective antenna sub-circuits. The baluns may be configured to provide a differential signal (i.e., a first signal and a second signal having an opposite polarity with respect to the first signal) to other components based on the signals received from the respective antennas. Each balun may include two inductors that form a DC decoupling between a single-ended input and a differential output, which can provide electrostatic discharge (ESD), match the impedance of the antenna signal, and generate a positive signal and a negative signal based on the antenna signal. Each inductor of the balun has two terminals. The first inductor of the balun 206 may have a first terminal configured to be coupled to the antenna 201 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 206 may include a first terminal coupled to the drain of the transistor 207 and a second terminal coupled to the source of the transistor 207. The second inductor may further include a center tap node that may be coupled to receive a DC bias voltage (e.g., 0.7V). The first inductor of the balun 211 may have a first terminal configured to be coupled to the antenna 202 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 211 may include a first terminal coupled to the drain of the transistor 212 and a second terminal coupled to the source of the transistor 212. The second inductor may further include a center tap node that may be coupled to receive a different DC bias voltage. The first inductor of the balun 216 may have a first terminal configured to be coupled to the antenna 203 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 216 may include a first terminal coupled to the drain of the transistor 217 and a second terminal coupled to the source of the transistor 217. The second inductor may further include a center tap node that may be coupled to receive a different DC bias voltage. The first inductor of the balun 221 may have a first terminal configured to be coupled to the antenna 204 and a second terminal configured to be coupled to a ground node. The second inductor of the balun 221 may include a first terminal coupled to the drain of the transistor 222 and a second terminal coupled to the source of the transistor 222.The second inductor may further include a center tap node, which may be coupled to receive different DC bias voltages.

[0041] Each of the transistors may be an n-type metal-oxide semiconductor field effect transistor (MOSFET). However, other types of transistors may be included in system 200. Thus, each of the transistors includes a gate, a drain, and a source. Each of the transistors may receive a positive signal from a corresponding balun at its drain and a negative signal from the corresponding balun at its source. The drain of the transistor may be further coupled to a first input of a corresponding LNA (one of LNA 209, 214, 219, or 224), and the source of the transistor may be further coupled to a second input of the corresponding LNA.

[0042] The gate of the transistor may be coupled to a controller, a processor, or other control device or logic device capable of providing a corresponding enable signal to the gate (e.g., EN1, EN2, EN3, EN4). In various examples, a processor (e.g., a CPU) may enable signals 208, 213, 218, or 223 at the gates of the transistors. For example, the processor may provide signal 208 to transistor 207, signal 213 to transistor 212, signal 218 to transistor 217, and signal 223 to transistor 222. In some cases, the signals may be configured such that only one of the antenna subcircuits 205, 210, 215, and 220 operates at a time (e.g., the set of enable signals may be one-hot).

[0043] The value of the signal provided to the transistor can affect the operation of the transistor. For example, the value of signal 208 can affect the operation of transistor 207 such that when signal 208 or EN1 has a value of 0, transistor 207 can be in an off state or operate as an open switch, and the corresponding balun 206 can provide a non-zero differential signal to LNA 209. However, when the value of signal 208 has a value of 1, transistor 207 can be in a closed state or operate as a closed switch, and the current through transistor 207 can prevent the balun 206 from providing a non-zero differential signal to LNA 209. The value of signal 213 can affect the operation of transistor 212 such that when signal 213 or EN2 has a value of 1, transistor 212 can be in a closed state or operate as a closed switch, and the corresponding balun 211 can provide a non-zero differential signal to LNA 214. However, when the value of signal 213 has a value of 0, transistor 207 can be in an off state or operate as an open switch, and the current through transistor 212 can prevent the balun 211 from providing a non-zero differential signal to LNA 214. Similarly, signal 218 or EN3 and signal 223, EN4 can control the operation and state of transistors 217 and 222 respectively. In various examples, only one of signals 208, 213, 218, and 223 can have a value of "0" at a given time, and thus it follows that only one of LNAs 209, 214, 219, or 224 can be in operation or operating at a time, while the others can be out of operation. Thus, transistors 207, 212, 217, and 222 can be used as switching elements that determine which antenna sub-circuit provides a signal to amplifiers 225 and 226.

[0044] LNAs 209, 214, 219, and 224 (collectively referred to as LNAs) represent low noise amplifiers that are capable of amplifying the differential signal from the corresponding balun while minimizing degradation of the signal-to-noise ratio of the antenna signal and matching the impedance of the differential signal to improve power transmission of the differential signal. In various examples, each of the LNAs can be configured to operate in a common source configuration.

[0045] Each LNA can include two output ports coupled to the input port of amplifier 225 or amplifier 226. For example, LNAs 209 and 214 can be coupled to amplifier 225, and LNAs 219 and 224 can be coupled to amplifier 226. Amplifiers 225 and 226 can be included to further amplify the differential signal from the antenna sub-circuit. Amplifiers 225 and 226 can increase the RF front-end gain and improve the noise figure of the receiver channel, among other benefits. Amplifiers 225 and 226 can be coupled to transformer 232 of receiver sub-circuit 230.

[0046] The transformer 232 may have a first set of terminals and a second set of terminals. The first set of terminals may include a first end and a second end, and the second set of terminals may include a first end and a second end. The first output ports of amplifiers 225 and 226 may be coupled to the first end of the first set of terminals, and the second output ports of amplifiers 225 and 226 may be coupled to the second end of the first set of terminals.

[0047] In operation, one of amplifiers 225 or 226 may provide a signal from one of the LNAs to the transformer 232 of the receiver subcircuit 230 based on the state of the transformer, or in other words, based on the values of signals 208, 213, 218, and 223.

[0048] The receiver subcircuit 230 represents a receiver channel in the system 200, which may be configured to receive a signal from one of the antenna subcircuits 205, 210, 215, or 220, mix, down-convert, amplify, and perform similar operations on the signal, and provide the signal downstream to other systems or subcircuits (e.g., a digital signal processor, a differential front end) (not shown). In various examples, the receiver subcircuit 230 may include a transformer 232, a mixer 233, a local oscillator buffer amplifier 234, an IF amplifier 235, and an ADC 236.

[0049] As mentioned, the transformer 232 includes a first set of terminals and a second set of terminals, each set of terminals including a first end and a second end. The second set of terminals may be coupled to the mixer 233. The mixer 233 represents an electronic device capable of combining two different differential signals into a combined differential signal, such as a differential signal from one of amplifiers 225 and 226 and a differential signal from the local oscillator buffer amplifier 234. More specifically, the local oscillator buffer amplifier 234 may be coupled to receive a clock signal 231 from a local oscillator (not shown). The clock signal 231 may be a differential clock signal that may be fed to the input of the local oscillator buffer amplifier 234. The local oscillator buffer amplifier 234 may include an intermediate frequency amplifier or another type of amplifier. The local oscillator buffer amplifier 234 may amplify the clock signal 231 and provide the clock signal 231 to the mixer 233. The mixer 233 may then combine the clock signal 231 with the differential signal received at the transformer 232. In various examples, the mixer 233 may operate as a down-converter, however, in other examples, the mixer 233 may be used as an up-converter.

[0050] The mixer 233 may be further coupled to the IF amplifier 235. The IF amplifier 235 may be configured to further amplify the down-converted differential signal in the receiver subcircuit 230. The IF amplifier may include two output ports coupled to two input ports of the ADC 236, and may provide the signal to the ADC 236.

[0051] An ADC 236 is included in the receiver sub-circuit 230 to convert the modulated and mixed differential signal from analog to digital. The ADC 236 can convert the positive signal into output 240 and the negative signal into output 241. The ADC 236 can provide outputs 240 and 241 downstream.

[0052] In some examples, the system 200 may include additional receiver sub-circuits. For example, the system may include two receiver sub-circuits. One receiver sub-circuit can be used to process the antenna signals from the antenna sub-circuits 205 and 210, and the second receiver sub-circuit can be used to process the antenna signals from the antenna sub-circuits 215 and 220. Any combination or variation of antenna sub-circuits and receiver sub-circuits can be included in the system.

[0053] Figure 3 A transceiver and receiver system that can be used according to an embodiment is shown. Figure 3 Includes a system 300, which includes antennas 301, 302, and 303, antenna sub-circuits 305 and 310, a receiver sub-circuit 315, a synthesizer 330, a ramp generator 331, and a transmitter sub-circuit 325. The antenna sub-circuit 305 includes a balun 306, a transistor 307, and a low-noise amplifier (LNA) 309. The antenna sub-circuit 310 includes a balun 311, a transistor 312, and an LNA 314. The receiver sub-circuit 315 includes a transformer 317, a mixer 318, a local oscillator buffer amplifier 319, an intermediate frequency (IF) amplifier 320, and an analog-to-digital converter (ADC) 321. The transmitter sub-circuit 325 includes a local oscillator buffer amplifier 326 and a power amplifier 327.

[0054] The system 300 represents a circuit capable of receiving signals from antennas 301 and 302 and transmitting signals from antenna 303. The components of the system 300 can selectively enable one of the antenna sub-circuits 305 and 310 to amplify the signals from the corresponding antennas, provide the amplified signals to the receiver sub-circuit 315, process the amplified signals into digital signals, and further provide the amplified signals to the transmitter sub-circuit 325. For example, each of the antenna sub-circuits 305 and 310 may include switches (transistors 307 and transistor 312 respectively), which can be opened or closed to enable the use of one of the antenna sub-circuits 305 or 310. Thus, the system 300 can implement antenna switching using a shared receiver sub-circuit 315 for the antenna sub-circuits 305 and 310.

[0055] Antennas 301, 302, and 303 represent antennas capable of receiving or transmitting signals from a radio, satellite, or another device and converting the signals into currents provided to the components of the system 300. The antennas can operate in various bandwidths and radio frequencies.

[0056] In system 300, antenna sub-circuit 305 is configured to couple to antenna 301, and antenna sub-circuit 310 is configured to couple to antenna 302. In various examples, antenna sub-circuits 305 and 310 can be on and as part of a system-on-chip (SoC). For example, antenna sub-circuits 305 and 310 can be on a circuit board. Antennas 301 and 302 can be coupled to components of antenna sub-circuits 305 and 310, respectively, via pins, ports, or other connection points of the circuit board. Thus, antennas 301 and 302 can be off-chip. Additional antennas and antenna sub-circuits can be included in other examples.

[0057] Antenna sub-circuit 305 includes balun 306, transistor 307, and LNA 309, and similarly, antenna sub-circuit 310 includes balun 311, transistor 312, and LNA 314. Baluns 306 and 311 can represent electrical devices that can provide an interface between antennas 301 and 302 and other components of antenna sub-circuits 305 and 310, respectively. Baluns 306 and 311 can be configured to provide differential signals (i.e., a first signal and a second signal having an opposite polarity with respect to the first signal) to other components based on signals received from the respective antennas. Baluns 306 and 311 can each include two inductors that form a DC decoupling between a single-ended input and a differential output, which can provide electrostatic discharge (ESD), match the impedance of the antenna signal, and generate a positive signal and a negative signal based on the antenna signal. Each inductor of baluns 306 and 311 has two terminals. The first inductor of balun 306 can have a first terminal configured to couple to antenna 301 and a second terminal configured to couple to a ground node. The second inductor of balun 306 can include a first terminal coupled to the drain of transistor 307 and a second terminal coupled to the source of transistor 307. The second inductor can further include a center tap node that can be coupled to receive a DC bias voltage (e.g., 0.7V). Similarly, the first inductor of balun 311 can have a first terminal configured to couple to antenna 302 and a second terminal configured to couple to a ground node. The second inductor of balun 311 can include a first terminal coupled to the drain of transistor 312 and a second terminal coupled to the source of transistor 312. The second inductor can further include a center tap node that can be coupled to receive a different DC bias voltage (e.g., 0V).

[0058] Transistors 307 and 312 may be n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). However, other types of transistors may be included in system 300. Thus, each of transistors 307 and 312 includes a gate, a drain, and a source. Transistor 307 may receive a positive signal from balun 306 at its drain and a negative signal from balun 306 at its source. The drain of transistor 307 may be further coupled to a first input of LNA 309, and the source of transistor 307 may be further coupled to a second input of LNA 309. The gate of transistor 307 may be coupled to a controller, a processor, or other control device or logic device capable of providing a signal to the gate of transistor 307. Transistor 312 may receive a positive signal from balun 311 at its drain and a negative signal from balun 311 at its source. The drain of transistor 312 may be further coupled to a first input of LNA 314, and the source of transistor 312 may be further coupled to a second input of LNA 314. The gate of transistor 312 may also be coupled to a controller, a processor, or other control device or logic device capable of providing a signal to the gate of transistor 312.

[0059] In various examples, a processor (e.g., a CPU) may provide an inverted enable signal 308 to the gate of transistor 307 and a non-inverted version of enable signal 313 to the gate of transistor 312. The inverted enable signal 308 may have a first value, and the enable signal 313 may have a second value that is opposite to the first value. In other words, the inverted enable signal 308 and the enable signal 313 are opposite to each other. The value of the inverted enable signal 308 may affect the operation of transistor 307 such that when the inverted enable signal 308 has a value of 0, transistor 307 may be in an off state or operate as an open switch, and balun 306 is capable of providing a non-zero differential signal to LNA 309. However, when the value of the inverted enable signal 308 has a value of 1, transistor 307 may be in a closed state or operate as a closed switch, and the current through transistor 307 may prevent balun 306 from providing a non-zero differential signal to LNA 309. The value of the enable signal 313 may affect the operation of transistor 312 such that when the enable signal 313 has a value of 1, transistor 312 may be in a closed state or operate as a closed switch, and the current through transistor 312 may prevent balun 311 from providing a non-zero differential signal to LNA 314. However, when the value of the enable signal 313 has a value of 0, transistor 307 may be in an off state or operate as an open switch, and balun 311 is capable of providing a non-zero differential signal to LNA 314. Because the inverted enable signal 308 and the enable signal 313 have opposite values, only one of LNAs 309 and 314 may be active or operating at a time. Accordingly, transistors 307 and 312 may be used as switching elements that determine which antenna subcircuit provides a signal to receiver subcircuit 315.

[0060] LNAs 309 and 314 represent low noise amplifiers that are capable of amplifying differential signals from baluns 306 and 311, respectively, while minimizing degradation of the signal-to-noise ratio of the antenna signal and matching the impedance of the differential signal to improve power transmission of the differential signal. In various examples, LNA 309 may be configured to operate in a common source configuration.

[0061] LNAs 309 and 314 may each include two output ports coupled to a transformer 317 of receiver subcircuit 315. More specifically, transformer 317 may have a first set of terminals and a second set of terminals. The first set of terminals may include a first end and a second end, and the second set of terminals may include a first end and a second end. The first output ports of LNAs 309 and 314 may be coupled to the first end of the first set of terminals of transformer 317. The second output ports of LNAs 309 and 314 may be coupled to the second end of the first set of terminals of transformer 317.

[0062] In operation, LNA 309 or LNA 314 may provide a differential signal to transformer 317 of receiver sub-circuit 315 based on the states of transistors 307 and 312, or in other words, based on the values of the inverted enable signal 308 and the enable signal 313.

[0063] Receiver sub-circuit 315 represents a receiver channel in system 300, which may be configured to receive signals from antenna sub-circuit 305 or antenna sub-circuit 310, mix, down-convert, amplify, and perform similar operations on the signals, and provide the signals downstream to other systems or sub-circuits (e.g., a digital signal processor, a differential front end) (not shown). In various examples, receiver sub-circuit 315 may include transformer 317, mixer 318, local oscillator buffer amplifier 319, IF amplifier 320, and ADC 321.

[0064] As mentioned, transformer 317 includes a first set of terminals and a second set of terminals, each set of terminals including a first end and a second end. The second set of terminals may be coupled to mixer 318. Mixer 318 represents an electronic device capable of combining two or more different differential signals into a combined differential signal, such as a differential signal from one of LNA 309 or 314 and a differential signal from local oscillator buffer amplifier 319. More specifically, local oscillator buffer amplifier 319 may be coupled to receive a clock signal from synthesizer 330. The clock signal may be a differential clock signal generated by ramp generator 331 and fed by synthesizer 330 to receiver sub-circuit 315, and the differential clock signal may be further fed to the input of local oscillator buffer amplifier 319. Local oscillator buffer amplifier 319 may amplify or convert the clock signal and provide the clock signal to mixer 318. Mixer 318 may then combine the clock signal with the differential signal received at transformer 317. In various examples, mixer 318 may operate as a down-converter, however, in other examples, mixer 318 may be used as an up-converter.

[0065] Mixer 318 may be coupled to IF amplifier 320. IF amplifier 320 may be configured to further amplify the down-converted differential signal in receiver sub-circuit 315. The IF amplifier may include two output ports coupled to two input ports of ADC 321, and may provide the signal to ADC 321.

[0066] ADC 321 is included in receiver sub-circuit 315 to convert the modulated and mixed differential signal from analog to digital. ADC 321 may convert the positive signal to output 322 and the negative signal to output 323. ADC 321 may provide outputs 322 and 323 downstream.

[0067] The receiver sub - circuit 315 and the synthesizer 330 may also be coupled to the local oscillator buffer amplifier 326 of the transmitter sub - circuit 325. The transmitter sub - circuit 325 represents various devices, components, circuits, and the like that are capable of processing and synchronizing signals from the mixer 318 to transmit signals downstream via the antenna 303. In one example, the components of the transmitter sub - circuit 325 form a transmission - generating circuitry. The transmitter sub - circuit 325 may include the local oscillator buffer amplifier 326 and the power amplifier 327, as well as other components not shown.

[0068] The synthesizer 330 may include a phase - locked loop (PLL) coupled to the local oscillator buffer amplifier 326 of the transmitter sub - circuit 325. The PLL represents a circuit that is capable of changing the frequency of a reference signal (e.g., a clock signal) provided by a reference circuit such as a ramp generator 331. For example, the PLL may increase the frequency of the reference signal and provide the reference signal to the transmitter sub - circuit 325 and the receiver sub - circuit 315.

[0069] The ramp generator 331 represents a circuit that is capable of generating a frequency - modulated continuous - wave (FMCW) radar signal based on timing information and a reference signal provided by a timing circuit or other components (not shown) for transmission via the antenna 303. The ramp generator 331 may provide the FMCW radar signal to the synthesizer 330.

[0070] The local oscillator buffer amplifier 326 receives a signal from the synthesizer 330, amplifies the signal, and provides the amplified signal to the power amplifier 327. The power amplifier 327 is included to further amplify the signal provided by the local oscillator buffer amplifier 326 via the synthesizer 330 and the ramp generator 331 for transmission via the antenna 303. The power amplifier 327 may provide the amplified signal to the antenna 303 at a specific time (i.e., the time specified by a timing circuit or other components). Subsequently, the antenna 303 may transmit the radar signal downstream.

[0071] Figure 4 An example graphical representation related to the maximum gain generated by the low - noise amplifier of the antenna receiver system according to an embodiment is shown. Figure 4 A graphical representation 400 is shown that includes samples of the gain 401 of the components with respect to the frequency 402 measured at the nodes of an antenna receiver system such as the system 100 for reference Figure 1 of the elements relative to the frequency 402 measured at the nodes of an antenna receiver system such as the system 100 for reference Figure 1 of the elements relative to the frequency 402 measured at the nodes of an antenna receiver system such as the system 100 for reference

[0072] Outputs 405 and 406 represent sample gain results measured at a first node between the balun 106 and the transistor 107 (i.e., the input to the transistor 107) and at a second node between the LNA 109 and the receiver sub-circuit 115 (i.e., the output of the LNA 109) when the frequency 402 is applied to the first node. Output 405 shows such results in a system without a switch or without the transistor 107 in the antenna sub-circuit 105. Output 406 shows such results in a system that includes the transistor 107 in a turned-off state, such as the system 100. At various values of the frequency 402, the value of the gain 401 in the system that includes the transistor 107 can be slightly lower (e.g., 0.3 dB), as demonstrated by comparing output 405 and output 406. Thus, using the transistor 107 as a switch placed before the LNA 109 for antenna switching can have only a slight impact on the gain 401.

[0073] Figure 5 Shows an example graphical representation related to noise generated by a low-noise amplifier of an antenna-switching receiver system according to an embodiment. Figure 5 Shows a graphical representation 500 that includes reference Figure 1 of the elements with respect to the minimum achievable noise figure 501 of the frequency 502 measured at nodes of an antenna receiver system such as the Figure 1 system 100 etc.

[0074] Outputs 505 and 506 represent sample noise figure results measured at a first node between the balun 106 and the transistor 107 (i.e., the input to the transistor 107) and at a second node between the LNA 109 and the receiver sub-circuit 115 (i.e., the output of the LNA 109) when the frequency 502 is applied to the first node. Output 505 shows such results in a system without a switch or without the transistor 107 in the antenna sub-circuit 105. Output 506 shows such results in a system that includes the transistor 107 in a turned-off state, such as the system 100 etc. At various values of the frequency 502, the value of the noise 501 in the system that includes the transistor 107 can be slightly higher (e.g., 0.1 dB), as demonstrated by comparing output 505 and output 506. Thus, using the transistor 107 as a switch placed before the LNA 109 for antenna switching can have only a slight impact on the minimum achievable noise figure 501.

[0075] Figure 6 Shows an example graphical representation related to power generated by an antenna receiver system according to an embodiment. Figure 6 Shows a graphical representation 600 that includes reference Figure 1 of the elements with respect to the Figure 1Sample results of the power 601 at frequency 602 measured at a node of an antenna receiver system such as system 100.

[0076] Output 605 represents the power measured at the first node between the balun 106 and the transistor 107 (i.e., the input to the transistor 107). Outputs 606 and 607 respectively represent the sample power results without and with the transistor 107 measured at the second node between the LNA 109 and the receiver subcircuit 115 (i.e., the output of the LNA 109) when the frequency 502 is applied to the first node.

[0077] In various examples, isolation can be measured by comparing the power at the second node of the antenna subcircuit 105 when the antenna subcircuit 105 is "on" (i.e., the transistor 107 is in the off state) and the antenna subcircuit 110 is "off" (i.e., the transistor 112 is in the closed state) with the power at the second node of the antenna subcircuit 110. In an ideal scenario, no current would flow through the antenna subcircuit 110 when the antenna subcircuit is off, and thus, the isolation between the output at the second node and the input at the first node would be infinite. However, in a real scenario, leakage signals can flow through the LNA 114 to the receiver subcircuit 115, so the value of the isolation can be a real value.

[0078] Output 606 indicates the value of the power 601 across the varying value of the frequency 602 in a system without switches or without the transistors 107 and 112. The difference or isolation of the power 601 values between output 605 and 606 can be approximated as 18.5 dB. Output 607 indicates the value of the power 601 across the varying value of the frequency 602 in a system with switches or with the transistors 107 and 112 such as system 100. The difference or isolation of the power 601 values between output 605 and 607 can be approximated as 31 dB. Thus, the use of the transistors 107 and 112 placed respectively before the LNAs 109 and 114 in the system can increase the isolation within the system across the varying value of the frequency 602.

[0079] Although some examples provided herein are described in the context of an antenna switching system, a receiver subcircuit, an antenna subcircuit, a component, a device, an element, an architecture, or an environment, the systems, circuits, and methods described herein are not limited to these embodiments and can be applied to a variety of other processes, systems, applications, devices, and the like.

[0080] Unless the context clearly requires otherwise, throughout the description and claims, the words "comprising", "including", and the like shall be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, as "including but not limited to". As used herein, the terms "connected", "coupled", or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical, or a combination thereof. Additionally, the words "herein", "above", "below", and words of similar import, when used in this application, shall refer to the entire application and not to any particular part of the application. Where context permits, the singular or plural words used in the above detailed description may also include the plural or singular respectively. The word "or", when referring to a list of two or more items, covers all of the following interpretations of that word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0081] Phrases such as "in some embodiments", "according to some embodiments", "in the illustrated embodiments", "in other embodiments", etc. generally mean that the particular feature, structure, or characteristic following the phrase is included in at least one implementation of the technology of the present invention and may be included in more than one implementation. Additionally, such phrases do not necessarily refer to the same or different embodiments.

[0082] The above detailed description of examples of the technology is not intended to be exhaustive or to limit the technology to the exact forms disclosed above. While specific examples of the technology have been described above for illustrative purposes, as will be recognized by those skilled in the relevant art, various equivalent modifications can be made within the scope of the technology. For example, while a process or elements are presented in a given order, alternative embodiments may execute the routines with steps in a different order or employ a system with elements or components in a different order, and some processes or elements may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or sub - combinations. Each of these processes or elements can be implemented in a variety of different ways. Additionally, any particular numbers mentioned herein are merely examples; alternative embodiments may employ different values or ranges.

[0083] The teachings of the technology provided herein can be applied to other systems, not necessarily the systems described above. The elements and actions of the various examples described above can be combined to provide further implementations of the technology. Some alternative implementations of the technology may include not only additional elements of the above - described implementations but also fewer elements.

[0084] In view of the foregoing detailed description, these and other changes may be made to the technology. Although the foregoing describes certain examples of the technology and describes the best mode contemplated, no matter how detailed the above appears in this document, the technology may be practiced in many ways. The details of the system may vary considerably in its specific implementation while still being encompassed by the technology disclosed herein. As noted above, the particular terms used when describing certain features or aspects of the technology should not be construed to imply that the term is hereby redefined to be limited to any specific characteristic, feature, or aspect of the technology associated with that term. In general, unless the specific embodiments section above clearly defines such terms, the terms used in the appended claims should not be construed to limit the technology to the specific examples disclosed in the specification. Thus, the actual scope of the technology not only covers the disclosed examples, but also includes all equivalent ways of practicing or implementing the technology under the claims.

[0085] To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates the aspects of the technology in any number of claim forms. For example, although only one aspect of the technology is recited as a computer-readable medium claim, other aspects may equally be embodied as a computer-readable medium claim, or in other forms, such as in a means-plus-function claim. Any claim intended to be treated under 35 U.S.C. § 112(f) will begin with "means for", but the use of the term "for" in any other context is not intended to invoke treatment under 35 U.S.C. § 112(f). Thus, the applicant reserves the right to seek additional claims after the filing of this application, seeking such additional claim forms in this application or a continuing application.

Claims

1. A system comprising: a first antenna subcircuit configured to couple to a first antenna; a second antenna subcircuit configured to couple to a second antenna; as well as a receiver subcircuit coupled to each of the first antenna subcircuit and the second antenna subcircuit; The first antenna sub-circuit comprises: a first balun configured to be coupled to the first antenna; a first transistor coupled to the first balun; and a first low noise amplifier coupled to the first transistor; The second antenna sub-circuit comprises: a second balun configured to couple to the second antenna; a second transistor coupled to the second balun; and a second low noise amplifier coupled to the second transistor; and Wherein the receiver subcircuit comprises: a transformer comprising a first set of terminals coupled to the first low noise amplifier and the second low noise amplifier and a second set of terminals coupled to a mixer; the mixer coupled to the second set of terminals of the transformer, the first amplifier, and the second amplifier; the first amplifier coupled to the mixer and the local oscillator; the second amplifier coupled to the mixer and the analog-to-digital converter; and The analog / digital converter.

2. The system of claim 1, wherein: The first balun comprises a first terminal and a second terminal; The first low noise amplifier comprises a first input coupled to the first terminal of the first balun and a second input coupled to the second terminal of the first balun; and The first transistor comprises: a drain coupled to the first terminal of the first balun and the first input of the first low noise amplifier; and A source is coupled to the second terminal of the first balun and the second input of the first low noise amplifier.

3. The system of claim 2, wherein: The second balun comprises a first terminal and a second terminal; The second low noise amplifier comprises a first input coupled to the first terminal of the second balun and a second input coupled to the second terminal of the second balun; and The second transistor comprises: a drain coupled to the first terminal of the second balun and the first input of the second low noise amplifier; and A source is coupled to the second terminal of the second balun and the second input of the second low noise amplifier.

4. The system of claim 1, wherein: The first low noise amplifier includes a first output coupled to the first set of terminals of the transformer and a second output coupled to the first set of terminals of the transformer; and The second low noise amplifier includes a first output coupled to the first output of the first low noise amplifier and the first set of terminals of the transformer and a second output coupled to the second output of the second low noise amplifier and the first set of terminals of the transformer. 5 . The system of claim 1 , wherein each of the first low noise amplifier and the second low noise amplifier is configured to operate in a common source configuration.

6. The system of claim 1 , wherein the mixer of the receiver subcircuit is configured to generate a mixed signal based on an impedance matching signal from one of the first antenna subcircuit and the second antenna subcircuit and a clock signal from the first amplifier via the local oscillator, and to provide the mixed signal to the second amplifier. 7 . The system of claim 6 , wherein the second amplifier is configured to generate an amplified mixed signal based on the mixed signal and provide the amplified mixed signal to the analog-to-digital converter, wherein the second amplifier is an intermediate frequency amplifier.

8. The system of claim 7, wherein the analog-to-digital converter is configured to generate a digital signal based on the amplified mixed signal and provide the digital signal downstream.

9. The system of claim 1, further comprising: a third antenna subcircuit configured to couple to a third antenna; as well as a fourth antenna subcircuit configured to couple to a fourth antenna; Wherein the third antenna sub-circuit comprises: a third balun configured to be coupled to the third antenna; a third transistor coupled to the third balun; and a third low noise amplifier coupled to the third transistor; The fourth antenna sub-circuit comprises: a fourth balun configured to be coupled to the fourth antenna; a fourth transistor coupled to the fourth balun; and A fourth low noise amplifier is coupled to the fourth transistor.

10. The system of claim 9, further comprising: a third amplifier coupled to the first low noise amplifier of the first antenna subcircuit, the second low noise amplifier of the second antenna subcircuit, and the first set of terminals of the transformer of the receiver subcircuit; as well as A fourth amplifier is coupled to the third low noise amplifier of the third antenna sub-circuit, the fourth low noise amplifier of the fourth antenna sub-circuit, and the first set of terminals of the transformer of the receiver sub-circuit.

11. The system of claim 9, wherein: The third balun comprises a first terminal and a second terminal; The third low noise amplifier comprises a first input coupled to the first terminal of the third balun and a second input coupled to the second terminal of the third balun; and The third transistor comprises: a drain coupled to the first terminal of the third balun and to the first input of the third low noise amplifier; and A source is coupled to the second terminal of the third balun and the second input of the third low noise amplifier.

12. The system of claim 11, wherein: The fourth balun comprises a first terminal and a second terminal; The fourth low noise amplifier comprises a first input coupled to the first terminal of the fourth balun and a second input coupled to the second terminal of the fourth balun; and The fourth transistor comprises: a drain coupled to the first terminal of the fourth balun and to the first input of the fourth low noise amplifier; and A source is coupled to the second terminal of the fourth balun and the second input of the fourth low noise amplifier.

13. A system comprising: First antenna; Second antenna; a first antenna subcircuit configured to couple to the first antenna; a second antenna subcircuit configured to couple to the second antenna; as well as a receiver subcircuit coupled to each of the first antenna subcircuit and the second antenna subcircuit; The first antenna sub-circuit comprises: a first balun configured to be coupled to the first antenna; a first transistor coupled to the first balun; and a first low noise amplifier coupled to the first transistor; The second antenna sub-circuit comprises: a second balun configured to couple to the second antenna; a second transistor coupled to the second balun; and a second low noise amplifier coupled to the second transistor; and Wherein the receiver subcircuit comprises: a transformer comprising a first set of terminals coupled to the first low noise amplifier and the second low noise amplifier and a second set of terminals coupled to a mixer; the mixer coupled to the second set of terminals of the transformer, the first amplifier, and the second amplifier; the first amplifier coupled to the mixer and the local oscillator; the second amplifier coupled to the mixer and the analog-to-digital converter; and The analog / digital converter.

14. The system of claim 13, wherein: The first balun comprises a first terminal and a second terminal; The first low noise amplifier comprises a first input coupled to the first terminal of the first balun and a second input coupled to the second terminal of the first balun; and The first transistor comprises: a drain coupled to the first terminal of the first balun and the first input of the first low noise amplifier; and A source is coupled to the second terminal of the first balun and the second input of the first low noise amplifier.

15. The system of claim 14, wherein: The second balun comprises a first terminal and a second terminal; The second low noise amplifier comprises a first input coupled to the first terminal of the second balun and a second input coupled to the second terminal of the second balun; and The second transistor comprises: a drain coupled to the first terminal of the second balun and the first input of the second low noise amplifier; and A source is coupled to the second terminal of the second balun and the second input of the second low noise amplifier.

16. The system of claim 13, wherein: The first low noise amplifier includes a first output coupled to the first set of terminals of the transformer and a second output coupled to the first set of terminals of the transformer; and The second low noise amplifier includes a first output coupled to the first output of the first low noise amplifier and the first set of terminals of the transformer and a second output coupled to the second output of the second low noise amplifier and the first set of terminals of the transformer.

17. A system comprising: a receiver circuit configured to couple to the first antenna and the second antenna; as well as a transceiver circuit configured to be coupled to a third antenna and to the receiver circuit; Wherein the receiver circuit comprises: a first antenna subcircuit configured to couple to the first antenna; a second antenna subcircuit configured to couple to the second antenna; and a receiver subcircuit coupled to each of the first antenna subcircuit and the second antenna subcircuit; The first antenna sub-circuit comprises: a first balun configured to be coupled to the first antenna; a first transistor coupled to the first balun; and a first low noise amplifier coupled to the first transistor; The second antenna sub-circuit comprises: a second balun configured to couple to the second antenna; a second transistor coupled to the second balun; and a second low noise amplifier coupled to the second transistor; and Wherein the receiver subcircuit comprises: a transformer comprising a first set of terminals coupled to the first low noise amplifier and the second low noise amplifier and a second set of terminals coupled to a mixer; the mixer coupled to the first and second amplifiers of the receiver subcircuit and to a transceiver amplifier of the transceiver circuit; the first amplifier coupled to the mixer and the local oscillator; the second amplifier coupled to the mixer and the analog-to-digital converter; and The analog / digital converter.

18. The system of claim 17, wherein: The first balun comprises a first terminal and a second terminal; The first low noise amplifier comprises a first input coupled to the first terminal of the first balun and a second input coupled to the second terminal of the first balun; and The first transistor comprises: a drain coupled to the first terminal of the first balun and the first input of the first low noise amplifier; and A source is coupled to the second terminal of the first balun and the second input of the first low noise amplifier.

19. The system of claim 18, wherein: The second balun comprises a first terminal and a second terminal; The second low noise amplifier comprises a first input coupled to the first terminal of the second balun and a second input coupled to the second terminal of the second balun; and The second transistor comprises: a drain coupled to the first terminal of the second balun and the first input of the second low noise amplifier; and A source is coupled to the second terminal of the second balun and the second input of the second low noise amplifier.

20. The system of claim 17, wherein: The first low noise amplifier includes a first output coupled to the first set of terminals of the transformer and a second output coupled to the first set of terminals of the transformer; and The second low noise amplifier includes a first output coupled to the first output of the first low noise amplifier and the first set of terminals of the transformer and a second output coupled to the second output of the second low noise amplifier and the first set of terminals of the transformer.

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