Front-end reading circuit of boron nitride neutron detector

Abstract

The embodiment of the invention discloses a front-end readout circuit of a boron nitride neutron detector, the front-end readout circuit is a CMOS circuit, and the front-end readout circuit of the boron nitride neutron detector comprises a charge sensitive preamplifier, a filtering shaping circuit and a voltage discrimination circuit; wherein the charge sensitive pre-amplifier circuit is used for acquiring a charge signal output by the boron nitride neutron detector and converting the charge signal into a voltage signal; the filtering shaping circuit is used for converting the waveform of the voltage signal output by the charge sensitive pre-amplifier circuit into a Gaussian waveform; and the voltage discrimination circuit is used for converting the filtered and shaped signal output by the filtering and shaping circuit into a pulse to be output.

Description

Technical Field

[0001] The present invention relates to the technical field of positron annihilation, and particularly to a front-end readout circuit of a boron nitride neutron detector. Background Art

[0002] For new neutron radiation detectors represented by boron nitride (BN) detectors, due to their high sensitivity to neutrons and excellent selectivity, they can efficiently detect trace neutron radiation. Boron nitride wide-bandgap semiconductor detectors are highly sensitive to neutrons and can directly measure neutron counts and energy spectra without an additional neutron conversion layer, thus quickly and accurately reflecting changes in neutron dose. In related technologies, currently, the mainstream detector readout circuits are implemented using board-level discrete components, but the circuits built with discrete components have relatively high power consumption. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a front-end readout circuit of a boron nitride neutron detector.

[0004] The technical solution of the embodiment of the present invention is realized as follows:

[0005] An embodiment of the present invention provides a front-end readout circuit of a boron nitride neutron detector. The front-end readout circuit is a complementary metal-oxide-semiconductor (CMOS) circuit, and the front-end readout circuit includes: a charge-sensitive preamplifier, a filter shaping circuit, and a voltage discrimination circuit; wherein,

[0006] The charge-sensitive preamplifier circuit is configured to obtain the charge signal output by the boron nitride neutron detector and convert it into a voltage signal;

[0007] The filter shaping circuit is configured to change the waveform of the voltage signal output by the charge-sensitive preamplifier circuit into a Gaussian waveform;

[0008] The voltage discrimination circuit is configured to change the filtered and shaped signal output by the filter shaping circuit into a pulse output.

[0009] In the above solution, the charge-sensitive preamplifier circuit includes:

[0010] A reference current source circuit configured to provide a bias current input for the charge-sensitive preamplifier circuit.

[0011] In the above solution, the charge-sensitive preamplifier circuit includes:

[0012] A gain bootstrap circuit composed of multiple N-type metal-oxide-semiconductor (NMOS) transistors.

[0013] In the above solution, the charge-sensitive preamplifier circuit includes:

[0014] A cascode structure circuit composed of multiple NMOS transistors.

[0015] In the above solution, the charge sensitive preamplifier circuit includes:

[0016] A cascode current mirror structure circuit composed of multiple NMOS transistors.

[0017] In the above solution, the reference current source circuit includes:

[0018] A 5-transistor active load differential pair OTA and a triode, with the two input terminals of the 5-transistor OTA respectively connected to the collectors of the triode.

[0019] In the above solution, the filter shaping circuit includes: a pole-zero cancellation circuit and a shaping circuit, and the pole-zero cancellation circuit is connected to the output terminal of the charge sensitive preamplifier and the input terminal of the shaping circuit.

[0020] In the above solution, the pole-zero cancellation circuit includes a first resistor, a second resistor, and a first capacitor, and the first resistor and the capacitor are connected in parallel and then connected to the second resistor.

[0021] In the above solution, the shaping circuit includes an amplifier, a second capacitor, and a third resistor, and the amplifier is connected in parallel with the second capacitor and the third resistor.

[0022] In the above solution, the voltage discrimination circuit includes:

[0023] A third capacitor, an inverter composed of two MOS transistors, multiple MOS transistors in diode connection mode, and multiple MOS transistors in positive feedback structure.

[0024] The front-end readout circuit of the boron nitride neutron detector in the embodiment of the present application includes: a charge sensitive preamplifier, a filter shaping circuit, and a voltage discrimination circuit. Among them, the front-end readout circuit is a CMOS circuit. The charge sensitive preamplifier circuit is used to obtain the charge signal output by the boron nitride neutron detector and convert it into a voltage signal. The filter shaping circuit is used to change the waveform of the voltage signal output by the charge sensitive preamplifier circuit into a Gaussian waveform. The voltage discrimination circuit is used to convert the filtered and shaped signal output by the filter shaping circuit into a pulse output, so as to count the output pulse and obtain the neutron dose. The front-end readout circuit in the embodiment of the present application is a chip-level CMOS circuit, which has the advantages of high integration, low power consumption, and the ability to integrate analog and digital circuits on the same chip. Brief Description of the Drawings

[0025] The drawings here are incorporated into the specification and form a part of this specification. These drawings show the embodiments that conform to the present invention and are used together with the specification to explain the technical solutions of the present invention.

[0026] Figure 1 Schematic diagram of the front-end readout circuit of a boron nitride neutron detector provided by the present invention;

[0027] Figure 2 Schematic diagram of another front-end readout circuit of a boron nitride neutron detector provided by the present invention;

[0028] Figure 3 Schematic diagram of a reference current source circuit provided by an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of a charge-sensitive preamplifier circuit provided by an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of a voltage discrimination circuit provided by an embodiment of the present invention. Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0032] In the following descriptions, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. The terms "first / second" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein are only for the purpose of describing the present invention and are not intended to limit the present invention.

[0034] A neutron detector is a device that detects neutrons by using charged particles generated after the interaction between neutrons and boron or uranium to ionize gas or by the activation of the material itself after neutron irradiation. Neutron detectors are widely used for reactor nuclear power measurement or core neutron fluence rate distribution measurement.

[0035] New neutron radiation detectors represented by boron nitride (BN) detectors are highly sensitive to neutrons and have excellent selectivity. They can efficiently detect trace neutron radiation and show excellent performance especially when capturing low-energy neutrons. In neutron detection and neutron beam monitoring, especially in the monitoring of the out-of-core neutron flux in the nuclear energy field, the 3He tube is expected to be replaced by a BN semiconductor detector to directly measure neutron counts and neutron energy spectra, quickly and accurately reflect changes in neutron dose, and have good application prospects in personal and environmental neutron dose monitoring. With the continuous development of nuclear power plants, nuclear medicine treatment, and space radiation measurement, neutron radiation protection has gradually attracted people's attention, and personal neutron dose monitoring has become the main focus.

[0036] The boron nitride wide-bandgap semiconductor detector is highly sensitive to neutrons and can directly measure neutron counts and energy spectra without an additional neutron conversion layer, thus quickly and accurately reflecting changes in neutron dose. This shows excellent application prospects in personal and environmental neutron dose monitoring. In related technologies, the current mainstream detector readout circuit is implemented using board-level discrete components, but the circuit built with discrete components has high power consumption. With the progress of technology, the chip-level nuclear detection readout circuit has gradually become a research hotspot. It has the advantages of high integration, low power consumption, and the ability to integrate analog and digital circuits on the same chip.

[0037] Aiming at the shortcomings of the above-mentioned related technologies, the present invention provides a front-end readout circuit for a boron nitride neutron detector, which can analyze thick and irregular samples and measure internal defects of materials.

[0038] Figure 1 The structural schematic diagram of a front-end readout circuit for a boron nitride neutron detector provided by the present invention is as Figure 1 shown. The front-end readout circuit 10 of the boron nitride neutron detector includes: a charge-sensitive preamplifier 11, a filter shaping circuit 12, and a voltage discrimination circuit 13; the front-end readout circuit is a Complementary Metal Oxide Semiconductor (CMOS) circuit, where

[0039] The charge-sensitive preamplifier circuit 11 is used to acquire the charge signal output by the boron nitride neutron detector and convert it into a voltage signal;

[0040] The filter shaping circuit 12 is used to change the waveform of the voltage signal output by the charge-sensitive preamplifier circuit into a Gaussian waveform;

[0041] The voltage discrimination circuit 13 is used to change the filtered and shaped signal output by the filter shaping circuit into a pulse output.

[0042] Among them, the front-end readout circuit can be designed and manufactured using the SMIC 55nm CMOS process, with a working voltage of 1.2V and a single-channel current of 186μA. The circuit is optimized for a boron nitride neutron detector with a capacitance of 20pF. By combining a gain bootstrap structure, an optimized noise model, and a special layout design, the gain of the circuit is increased while ensuring low power consumption, high gain, and low noise. The front-end circuit converts the charge signal of the detector into a voltage signal, which is shaped and amplified and then outputs a pulse signal through a voltage discrimination circuit. Finally, the STM32 single-chip microcomputer counts the output pulses.

[0043] Since the output signal of the detector is generally relatively small, a preamplifier, that is, a preamplifier, can be added between the detector and the amplifier. Since the output amplitude reflects the magnitude of the input charge and is independent of the input capacitance, it can be called a charge-sensitive preamplifier. Among them, the charge-sensitive preamplifier circuit, as the first stage of the electronics circuit, is responsible for obtaining the charge signal output by the detector and converting the charge signal into a voltage signal.

[0044] Among them, filtering is to select the required signal from many mixed signals, and shaping is to make the output signal have a certain waveform. The filtering and shaping circuit filters out noise to improve the signal-to-noise ratio, and changes the rise and fall time and amplification factor of the waveform output by the preamplifier to make the waveform into a Gaussian waveform.

[0045] The voltage discrimination circuit can be used as a waveform generation and conversion circuit to compare the shaped output voltage with the externally input threshold voltage, and convert the Gaussian waveform into a pulse waveform output. The filtered and shaped signal is converted into a pulse output through the voltage discrimination circuit.

[0046] The front-end readout circuit of this embodiment is applied to a boron nitride neutron detector, and the output charge of the boron nitride neutron detector is about 50 - 100 fC. The output of the boron nitride neutron detector after coupling is connected to the input of a charge-sensitive amplifier (Charge Sensitive Amplifier, CSA) to complete the preliminary amplification of the signal and convert it into a voltage signal. The filtering and shaping circuit filters out the circuit noise, further amplifies the signal, and changes the waveform into a Gaussian waveform. The shaped output voltage is compared with the externally input threshold voltage, and the Gaussian waveform is converted into a pulse waveform output.

[0047] The front-end readout circuit of the boron nitride neutron detector according to the embodiments of the present application includes: a charge-sensitive preamplifier, a filter shaping circuit, and a voltage discrimination circuit. Among them, the front-end readout circuit is a CMOS circuit. The charge-sensitive preamplifier circuit is used to obtain the charge signal output by the boron nitride neutron detector and convert it into a voltage signal. The filter shaping circuit is used to change the waveform of the voltage signal output by the charge-sensitive preamplifier circuit into a Gaussian waveform. The voltage discrimination circuit is used to convert the filtered and shaped signal output by the filter shaping circuit into a pulse output, so as to count the output pulses and obtain the neutron dose. The front-end readout circuit according to the embodiments of the present application is a chip-level CMOS circuit, which has the advantages of high integration, low power consumption, and the ability to integrate analog and digital circuits on the same chip.

[0048] As Figure 2 shown, Figure 2 The circuit schematic diagram of a front-end readout circuit provided by an embodiment of the present invention. The front-end readout circuit includes a charge-sensitive preamplifier, a filter shaping circuit, and a voltage discrimination circuit. Among them, the charge-sensitive preamplifier includes a CSA amplifier, a resistor Rf, and a capacitor Cf. The filter shaping circuit includes a resistor Rpz, a capacitor Cpz, a resistor Rsh, an amplifier shaper, a resistor Ri, and a capacitor Ci. The voltage discrimination circuit includes a comparator comparator.

[0049] Among them, CSA is the open-loop gain of the amplifier, Cf is the feedback capacitor, and the parallel Rf is the feedback resistor.

[0050] In one embodiment, the charge-sensitive preamplifier circuit includes:

[0051] A reference current source circuit for providing a bias current input to the charge-sensitive preamplifier circuit.

[0052] Among them, the reference current source circuit can generate a zero temperature coefficient current to provide a temperature-independent bias current for the entire circuit.

[0053] In one embodiment, the reference current source circuit includes:

[0054] A 5-transistor OTA and a triode, and the two input terminals of the 5-transistor OTA are respectively connected to the collector of the triode.

[0055] The 5-transistor OTA (active load differential pair) is an op-amp structure used in analog circuit design, which consists of five transistors, including two input transistors (M23 and M24), two current mirror transistors (M27 and M28), and one tail current transistor (M16).

[0056] Among them, two NMOS transistors (M23 and M24) serve as differential input pair transistors, two PMOS transistors (M27 and M28) form an active current mirror as the load, and another NMOS transistor (M16) serves as the tail current transistor.

[0057] NMOS and PMOS are two common field-effect transistors, but their principles are different. NMOS is an N-type field-effect transistor (N-type channel, P-type substrate), and PMOS is a P-type field-effect transistor (P-type channel, N-type substrate).

[0058] This structure realizes single-ended output through an active current mirror load while retaining the advantages of the differential pair. When the input signal changes, the current change of the input transistor is transmitted to the output end through the current mirror to achieve single-ended output. The change of the active load (M27 and M28) makes the output current contain the change of the input current, thus maintaining a high gain.

[0059] The triode is a PNP triode. Figure 3 In [circuit], two PNP triodes with a ratio of 1:8 are used, and N2 is composed of 8 triodes identical to N1 in parallel.

[0060] As Figure 3 shown, Figure 3 is a circuit schematic diagram of a reference current source circuit provided by an embodiment of the present invention. Figure 3 On the left end, a 5-transistor OTA and a first-stage common-source circuit form a two-stage amplifier. The two input terminals of the OTA are respectively connected to the collectors of the PNP triodes, clamping the two collectors to have the same potential. The reference current source uses two PNP triodes with a ratio of 1:8 to generate a zero-temperature coefficient current. PNP triode N2 is composed of 8 triodes identical to N1 in parallel. The negative temperature coefficient voltage is generated by VBE, and the voltage ΔVBE across resistor R2 generates a negative temperature coefficient. The positive temperature coefficient current I1 and the negative temperature coefficient I2 are added to obtain a zero-temperature coefficient current.

[0061] Figure 3 In [circuit], PNP triode N1 is connected in parallel with resistor R1 and connected to the drain of PMOS transistor M18; the gate of M18 is connected to the gate of PMOS transistor M19 and the output terminal of the 5-transistor OTA amplifier; the drain of M19 is connected to resistor R2 and resistor R3; resistor R2 is connected to PNP triode N2; the gate of M19 is connected to the drain-gate of PMOS transistor M20; the drain of M20 is connected to the drain and gate of NOMS transistor M30; the gate of M30 is connected to the gate of NMOS transistor M31; the drain of M31 is the output current terminal of the reference current source circuit.

[0062] In one embodiment, the charge-sensitive preamplifier circuit includes:

[0063] A gain bootstrap circuit composed of multiple N-type metal oxide semiconductor (NMOS) transistors.

[0064] As Figure 4 shown, Figure 4 is a circuit schematic diagram of a charge-sensitive preamplifier circuit provided by an embodiment of the present invention. Among them, NMOS transistors M1, M2, and M3 are configured to form a gain bootstrap circuit, which can indirectly increase the transconductance of the input transistor.

[0065] The NMOS bootstrap drive circuit is a special circuit mainly used to drive NMOS transistors to work at a high level. Its basic working principle is to utilize the energy storage characteristic of a capacitor. When the transistor is turned on, the power supply voltage is boosted to a higher level through the capacitor, thereby driving the NMOS transistor to work at a high level. When the transistor is turned off, the capacitor discharges through a discharge circuit to reduce the voltage to a low level for the next drive. Through the bootstrap circuit, the voltage of the gate can be increased relative to the source, and the NMOS transistor can be smoothly powered on and start working.

[0066] In one embodiment, the charge-sensitive preamplifier circuit includes:

[0067] A cascode structure circuit composed of multiple NMOS transistors.

[0068] The biggest feature of the cascode structure (CSCG) is its large output impedance. In a high-gain operational amplifier, the cascode structure can be used as an input transistor and an output load transistor to increase the voltage gain. In the common-gate stage, the input signal of the common-gate stage can be a current. And in the common-source stage, the transistor can convert a voltage signal into a current signal. The cascaded structure of the common-source stage and the common-gate stage is the cascode stage.

[0069] As Figure 4 shown, the combination of M12 and M13 forms a cascode structure to provide current for M1. PMOS transistors M4 and M5 are connected to form a cascode structure circuit, and M6 and M7 are also connected to form a cascode structure circuit, which can increase the output resistance and improve the circuit gain. Capacitor Cc changes the capacitance of the output node, thereby increasing the phase margin of the circuit and ensuring good stability of the circuit without oscillation.

[0070] In one embodiment, the charge-sensitive preamplifier circuit includes:

[0071] A cascode current mirror structure circuit composed of multiple NMOS transistors.

[0072] In a cascode current mirror, two transistors are connected together in an effective manner to form a closed loop: the source of the transistor at the input end and the gate of the transistor at the output end are shared. The transistor at the output end amplifies the source current of the transistor at the input end and outputs it to the load end, thereby forming a current mirror. The structure of the cascode current mirror is simple, with high stability, feedback strength, and high current mirror accuracy. The circuit can be effectively integrated to save space, reduce manufacturing and maintenance costs, and can efficiently convert the input current into an almost equal output current.

[0073] As Figure 4 shown, the combination of NMOS transistors M8, M9, M10, and M11 forms the structure of a cascode current mirror to provide current biasing for the circuit.

[0074] Figure 4 In it, the drain of the input transistor NMOS M1 is connected to the gate of NMOS transistor M2 and the source of M3; the drain of M2 is connected to the gate of M3; the drain of M3 is connected to the drain of PMOS transistor M4 and capacitor Cc; the source of M4 is connected to the drain of PMOS transistor M5; the gate of M4 is connected to the gates of M7, M9, M10, and M13 transistors, and the gate of M5 is connected to the gates of M6, M8, M11, and M12.

[0075] The gate of M1 is used for the input end of the circuit, the drain of M3 is used for the output end of the circuit, the source of M5 (PMOS) is connected to the power input of the circuit, and the source of M1 (NMOS) is grounded.

[0076] In one embodiment, the filter shaping circuit includes: a pole-zero cancellation circuit and a shaping circuit, and the pole-zero cancellation circuit is connected to the output end of the charge sensitive preamplifier and the input end of the shaping circuit.

[0077] The signal input pole-zero cancellation circuit can eliminate the undershoot caused when differentiating the probe signal, making the pulse monotonically return to the baseline. It improves the effects of count rate overload and pulse amplitude superposition, and is suitable for high-resolution and high-count rate spectrometer systems.

[0078] In one embodiment, the pole-zero cancellation circuit includes a first resistor, a second resistor, and a first capacitor, and the first resistor and the capacitor are connected in parallel and then connected to the second resistor.

[0079] As Figure 2 shown, the pole-zero cancellation circuit includes a first resistor Rpz, a second resistor Rsh, and a first capacitor Cpz, and the first resistor Rpz is connected in parallel with the first capacitor Cpz and then connected to the second resistor Rsh.

[0080] In one embodiment, the shaping circuit includes an amplifier, a second capacitor, and a third resistor, and the amplifier is connected in parallel with the second capacitor and the third resistor.

[0081] As Figure 2 shown, the shaping circuit includes an amplifier shaper, a second capacitor Ci, and a third resistor Ri, and the amplifier shaper is connected in parallel with the second capacitor Ci and the third resistor Ri.

[0082] In one embodiment, the voltage discrimination circuit includes:

[0083] A third capacitor, an inverter composed of two MOS transistors, multiple MOS transistors connected in a diode configuration, and multiple MOS transistors forming a positive feedback structure.

[0084] The voltage discrimination circuit can be used as a waveform generation and transformation circuit to compare the shaped output voltage with the threshold voltage input from the outside, and change the Gaussian waveform into a pulse waveform for output.

[0085] In a MOS transistor, the channel resistance is the resistance generated when current passes through the channel. Since electrons interact with the lattice when moving in the channel, thermal noise is generated. This thermal noise is a random process, and its voltage or current fluctuations are related to temperature. A positive feedback circuit is a circuit that feeds back a part of the output signal to the input terminal to enhance the original signal. When the feedback signal is in phase with the input signal, it is called positive feedback. MOS positive feedback means introducing the thermal noise generated by the channel resistance of the MOS transistor as a positive feedback source into the circuit to enhance or stabilize the signal.

[0086] The diode connection method of a PMOS transistor is to short-circuit the source and the gate together, and the drain serves as one extreme of the diode, and the other extreme can be connected to the negative power supply or ground as needed. This connection method is called source follower. In the source follower connection method, the gate and the source of the PMOS transistor are connected in a short-circuited manner, forming a common-source structure, and the drain serves as the output terminal. When an input signal is applied to the gate, the drain of the PMOS transistor will output an amplified and opposite-polarity signal. The source follower connection method can be used for applications such as voltage amplifiers and buffers. In a circuit, the source follower connection method can achieve the level conversion between the input and the output, and adjust the change of the output voltage by controlling the gate voltage, so as to achieve the amplification or reduction of the signal.

[0087] An inverter can reverse the phase of the input signal by 180 degrees, and a CMOS inverter circuit is composed of two enhancement-type MOS field-effect transistors.

[0088] As Figure 5 shown, Figure 5It is a circuit schematic diagram of a voltage discrimination circuit provided by an embodiment of the present invention. The drain of NMOS transistor M45 is connected to the sources of NMOS transistors M39 and M40;

[0089] The drain of M39 is connected to the drain of PMOS transistor M33, and the drain of M40 is connected to the drain of PMOS transistor M36;

[0090] The gate of M33 is connected to the drain of M33, which is connected to the gate of M35 and the drain of M34. The gate of M36 is connected to the drain of M36 and is connected to the gate of M34 and the drain of M35;

[0091] The drain of M40 is connected to the third capacitor C2 and an inverter composed of PMOS transistors M41 and M42.

[0092] Among them, MOS transistors M41 and M42 form an inverter. PMOS transistors M33 and M36 are in diode connection mode. PMOS transistors M34 and M35 form a positive feedback structure, which can improve the circuit gain to improve the accuracy of the voltage comparator (voltage discrimination circuit).

[0093] The front-end readout circuit of the embodiment of the present application is applied to a neutron detector. The output charge of the detector is about 50 - 100 fC. The output after coupling of the boron nitride neutron detector is connected to the input of the charge-sensitive amplifier to complete the preliminary amplification of the signal and convert it into a voltage signal. To ensure low power consumption, 1.8V is used as the highest power supply voltage. At the same time, to ensure high gain of the circuit while using the 1.8V power supply voltage, a gain bootstrap structure and a cascode structure are used. The filter shaping circuit filters out the circuit noise, further amplifies the signal, and transforms the waveform into a Gaussian waveform. The shaped output voltage is compared with the externally input threshold voltage, and the Gaussian waveform is changed into a pulse waveform for output.

[0094] The low-power and low-noise front-end CMOS readout circuit based on the SMIC 0.55nm process in the embodiment of the present application can solve the problem of high power consumption of the circuit built with discrete components, can achieve a single-channel power consumption of less than one milliwatt, and counts and outputs the signals detected by the detector.

[0095] Based on the same inventive concept, the present invention also provides a detector front-end readout method, which is applied to a boron nitride neutron detector. The method is implemented based on the front-end readout circuit in the above embodiment. The method includes:

[0096] The step of collecting the output signal of the detector;

[0097] The step of converting the output signal of the detector into a voltage signal;

[0098] The step of improving the signal-to-noise ratio of the voltage signal to obtain an amplified signal;

[0099] Steps of converting an analog signal into a pulse signal for output.

[0100] The front-end readout method of the detector may further include:

[0101] Steps of obtaining the current of the bias circuit.

[0102] The various embodiments / implementations provided by the present invention can be combined with each other without contradiction. The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0103] The features, structures or characteristics described above can be combined in any suitable manner in one or more embodiments. If possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to give a full understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present invention.

[0104] In this specification, the terms "a", "one", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising", "including" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are only used as labels and are not a limitation on the quantity of their objects.

[0105] It should be understood that the present invention does not limit its application to the detailed structures and arrangements of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more separate features mentioned or obvious in the text and / or drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A front-end readout circuit of a boron nitride neutron detector, wherein the front-end readout circuit is a complementary metal oxide semiconductor (CMOS) circuit, characterized in that: include: Charge sensitive preamplifier, filter shaping circuit and voltage discrimination circuit; wherein, A charge-sensitive preamplifier circuit, used for acquiring the charge signal output by the boron nitride neutron detector and converting it into a voltage signal; A filter shaping circuit, used for converting the waveform of the voltage signal output by the charge sensitive preamplifier circuit into a Gaussian waveform; The voltage discrimination circuit is used to convert the filtered and shaped signal output by the filtering and shaping circuit into a pulse output.

2. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The charge sensitive preamplifier circuit comprises: The reference current source circuit is used to provide a bias current input for the charge sensitive preamplifier circuit.

3. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The charge sensitive preamplifier circuit comprises: The invention relates to a gain bootstrap circuit composed of a plurality of N-type metal oxide semiconductor (NMOS) tubes.

4. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The charge sensitive preamplifier circuit comprises: A common-source and common-gate structure circuit composed of multiple NMOS tubes.

5. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The charge sensitive preamplifier circuit comprises: A common-source and common-gate current mirror structure circuit composed of multiple NMOS tubes.

6. The front-end readout circuit of the boron nitride neutron detector according to claim 2, characterized in that: The reference current source circuit comprises: The 5-tube active load differential pair OTA and a transistor, the two input ends of the 5-tube OTA are respectively connected to the collectors of the transistors.

7. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The filtering shaping circuit comprises: a pole-zero cancellation circuit and a shaping circuit, wherein the pole-zero cancellation circuit is connected to the output end of the charge sensitive preamplifier and the input end of the shaping circuit.

8. The front-end readout circuit of the boron nitride neutron detector according to claim 7, characterized in that: The pole-zero cancellation circuit comprises a first resistor, a second resistor and a first capacitor, wherein the first resistor and the capacitor are connected in parallel and then connected to the second resistor.

9. The front-end readout circuit of the boron nitride neutron detector according to claim 7, characterized in that: The shaping circuit includes an amplifier, a second capacitor and a third resistor, and the amplifier is connected in parallel with the second capacitor and the third resistor.

10. The front-end readout circuit of the boron nitride neutron detector according to claim 1, characterized in that: The voltage discrimination circuit comprises: A third capacitor, an inverter composed of two MOS tubes, a plurality of MOS tubes in a diode connection mode, and a plurality of MOS tubes in a positive feedback structure.

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