Controller of flash memory and memory block read number recording method

Abstract

The invention discloses a controller of a flash memory and a memory block read number recording method. The controller comprises a first storage unit used for persistently storing a total table of the number of read times, and the total table of the number of read times not only records the number of read times of each storage block contained in each logic group, but also records the maximum number of read times of each logic group; the hardware circuit unit is used for receiving result feedback of the flash memory particles to the read instruction, increasing the number of read times of a target storage block and updating the maximum number of read times of a logic group where the target storage block is located according to the target storage block determined by the result feedback, and when it is judged that the maximum number of read times of the logic group where the target storage block is located exceeds a first number of read times threshold value, sending the read instruction to the flash memory particles; a processor interrupt is initiated to perform data check and migration on the storage blocks in the corresponding logical groups by a predetermined software processing program. According to the embodiment of the invention, the occupation of processor resources is reduced, and the error of the reading frequency statistical value is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and in particular, to a controller for a flash memory and a method for recording the read count of a storage block. Background Art

[0002] A flash memory is a non-volatile memory. Read disturbance is a common phenomenon in flash memories, which can cause errors or damage to the data in the memory. When reading a storage unit (usually referred to as a Page) in a flash memory, the read operation generates a voltage to read the data in the storage unit. However, this voltage may spread to adjacent storage units through current, causing the charge states of these adjacent storage units to change. The degree of influence of read disturbance on storage units is related to multiple factors. The more the number of reads, the greater the interference to adjacent storage units, and the higher the possibility of data errors.

[0003] To address the problems caused by read disturbance, the controller of a flash memory usually records the read count of each storage block. When a certain threshold is reached, the data on the corresponding storage block is moved to other idle storage blocks.

[0004] In the prior art, the above work is completed by the firmware of the controller. Since the number of storage blocks is very large, counting the number of read operations for each storage block not only requires a relatively large amount of storage space, but also consumes a lot of processor resources, affecting the overall performance. In addition, due to the characteristics of the flash memory storage medium, the controller will merge some read operations to reduce the actual number of reads, and the firmware cannot predict this behavior, resulting in a large error in the read count statistics. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a controller for a flash memory and a method for recording the read count of a storage block to at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present disclosure provides a controller for a flash memory. The flash memory includes flash memory particles coupled to the controller. Each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, and all storage blocks are divided into multiple logical groups. The controller includes:

[0007] A first storage unit for persistently storing a read count summary table, which not only records the read count of each storage block included in each logical group, but also records the maximum read count of each logical group;

[0008] A hardware circuit unit, configured to receive the result feedback of the flash memory particles on a read instruction, increase the read count of the target storage block according to the target storage block determined by the result feedback, and update the maximum read count of the logical group where the target storage block is located. When it is determined that the maximum read count of the logical group where the target storage block is located exceeds a first read count threshold, a processor interrupt is triggered, so that a predetermined software processing program performs data checking and relocation on the storage blocks within the corresponding logical group.

[0009] In a second aspect, an embodiment of the present disclosure provides a controller for a flash memory. The flash memory includes flash memory particles coupled to the controller. Each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, and all storage blocks are divided into multiple logical groups. The controller includes:

[0010] A first storage unit, configured to persistently store a read count summary table, where the read count summary table records the maximum read count of each logical group;

[0011] A second storage unit, configured to cache a read count temporary table, where the read count temporary table records the read count of each storage block within a period of time and the maximum read count of the logical group where each storage block is located within the corresponding time;

[0012] A hardware circuit unit, configured to: receive the result feedback of the flash memory particles on a read instruction, update or add a record of the target storage block to the read count temporary table according to the target storage block determined by the result feedback, and when the maximum read count of the logical group where the target storage block is located in the read count temporary table exceeds a second read count threshold, update the maximum read count of the corresponding logical group in the read count summary table based on the record of the target storage block in the read count temporary table; and when it is determined that the maximum read count of the logical group where the target storage block is located in the read count summary table exceeds the first read count threshold, trigger a processor interrupt, so that a predetermined software processing program performs data checking and relocation on the storage blocks within the corresponding logical group.

[0013] Optionally, when adding a record of the target storage block to the read count temporary table, the hardware circuit unit uses the idle storage space in the second storage unit to store the record of the target storage block; or, updates the maximum read count of the corresponding logical group in the read count summary table based on the record with the longest current usage time or the lowest usage frequency in the read count temporary table, and then uses the corresponding storage space to store the record of the target storage block.

[0014] Optionally, after updating the maximum read count of the corresponding logical group in the read count summary table, clear the storage space occupied by the corresponding record in the second storage unit, or mark the corresponding record as invalid.

[0015] Optionally, the storage blocks with the same serial number on all planes are divided into the same logical group.

[0016] Optionally, the first storage unit is a non-volatile storage medium, and the second storage unit is a volatile storage medium.

[0017] In a third aspect, an embodiment of the present disclosure provides a controller for a flash memory. The flash memory includes flash memory particles coupled to the controller. Each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, and all storage blocks are divided into multiple logical groups. The controller includes:

[0018] A first storage unit for persistently storing a read count summary table that records the maximum read count of each logical group;

[0019] A second storage unit for caching a read count temporary table that records the read count of each storage block within a period of time and the maximum read count of the logical group where each storage block is located during the corresponding time;

[0020] A hardware circuit unit for receiving the result feedback of the flash memory particles on the read instruction, and updating or adding a record of the target storage block to the read count temporary table according to the target storage block determined by the result feedback;

[0021] Firmware for updating the maximum read count of the corresponding logical group in the read count summary table based on the maximum read count of each logical group in the read count temporary table, and when the maximum read count of a specific logical group in the read count summary table is greater than a first read count threshold, notifying a predetermined processing program to perform data check and migration on the storage blocks within the corresponding logical group.

[0022] In a fourth aspect, an embodiment of the present disclosure provides a method for recording the read count of a storage block, which is applied to a controller of a flash memory. The flash memory includes flash memory particles coupled to the controller. Each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, and all storage blocks are divided into multiple logical groups. The method includes:

[0023] Receiving the result feedback of the flash memory particles on the read instruction;

[0024] Increasing the read count of the target storage block and updating the maximum read count of the logical group where the target storage block is located according to the target storage block determined by the result feedback; and

[0025] When it is determined that the maximum read count of the logical group where the target storage block is located exceeds the first read count threshold, sending a notification to a predetermined program so that the predetermined program performs data check and migration on the storage blocks within the corresponding logical group.

[0026] Optionally, in the step of increasing the read count of the target storage block and updating the maximum read count of the logical group where the target storage block is located,

[0027] a read count temporary table is used to store the read count of the target storage block and the maximum read count of the logical group where the target storage block is located. When the maximum read count of the logical group where the target storage block is located exceeds the second read count threshold, the maximum read count of the logical group where the target storage block is located in the read count temporary table is increased to the maximum read count of the logical group where the target storage block is located in the read count total table, and the read count total table only records the maximum read count of each logical group.

[0028] In a fifth aspect, an embodiment of the present disclosure provides a flash memory, including a storage medium and a controller, and the controller is the above-mentioned controller.

[0029] According to the embodiments of the present disclosure, read count statistics are performed based on result feedback. By not counting the optimized merged read operations, the read count is reduced. At the same time, using a hardware circuit unit can more conveniently accumulate the read count than firmware and software programs, and detect whether the read count reaches the maximum threshold. Further, through the cache design of the read count temporary table, it is updated to the read count total table only after multiple operations are accumulated, thereby reducing the update frequency of the total table and reducing the system resource occupancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Through the description of the embodiments of the present disclosure with reference to the following drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0031] Figure 1 is a structural diagram of a host system;

[0032] Figure 2 is a schematic diagram of a controller of a flash memory provided by an embodiment of the present disclosure;

[0033] Figure 3 is Figure 2 an example diagram of a read count total table used in the embodiment of ;

[0034] Figure 4 is a schematic diagram of a controller of a flash memory provided by another embodiment of the present disclosure;

[0035] Figure 5 and Figure 6 is Figure 4 an example diagram of a read count temporary table and a read count total table used in the embodiment of ;

[0036] Figure 7 is a schematic diagram of a controller of a flash memory provided by yet another embodiment of the present disclosure;

[0037] Figure 8 It is a flowchart of a method for recording the read count of a storage block provided by an embodiment of the present disclosure. Detailed implementation manners

[0038] The present disclosure will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0039] The present invention will be described based on embodiments below, but the present invention is not limited to these embodiments only. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these detail parts. In order to avoid obscuring the essence of the present invention, well-known methods, processes, flows, elements and circuits are not described in detail.

[0040] Unless the context clearly requires otherwise, the words such as "including", "comprising" and the like in the whole specification and claims should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, the meaning of "including but not limited to". In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0041] Figure 1 It is a schematic block diagram of a host system 100. The host system 100 is, for example, a personal computer, a laptop computer, or a server.

[0042] The host system 100 includes a host device 110 (for example, a computer system including a main processor and a memory) and a storage device. The host device 110 can issue host commands to the storage device so that the storage device manages the data stored in the storage device according to the commands. For example, the host device 110 can be communicatively connected to the storage device (for example, through a host interface 121) and issue various commands (such as READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.) to the storage device. The storage device can store, update, read and / or otherwise manage the host data according to the address range prompted by the command. Once the command is executed, the storage device can transmit a response to the host device 110, thereby indicating that the command has been successfully completed.

[0043] The storage device consists of a controller 120 and a storage medium 130. The controller 120 parses host commands, converts the host commands into instructions adapted to the storage medium 130, then executes the instructions and feeds back the instruction results to the host device 110. The controller 120 is composed of various software and hardware. The hardware includes, for example, a (micro) processor, cache units such as SRAM and DRAM, and interface circuits. The software includes, for example, a series of software programs for performing management functions, including but not limited to data read / write, bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0044] There are multiple channels (such as CH0 and CH1) between the controller 120 and the storage medium 130, and the controller 120 and the storage medium 130 perform data interaction through each channel. Currently, the mainstream type of the storage medium 130 is a flash storage medium (a storage device using a flash storage medium is called a flash memory). Each channel (such as CH0 or CH1 in the figure) is usually coupled to N (N is 2, 4, 8, etc.) flash memory granules, and the controller 120 needs to operate the corresponding flash memory granules through each channel. Each flash memory granule is divided into multiple planes, and each plane is further divided into multiple storage blocks. In the figure, the storage blocks are identified as Block 0 to N.

[0045] As Figure 2 shown, in an embodiment of the present disclosure, a hardware circuit unit 1201 is added to the controller 120, and the hardware circuit unit 1201 maintains a total read count table 1202. Since the total read count table 1202 needs to be persistently stored, it is stored in the storage medium 130, or in the SRAM, or a part is stored in the storage medium 130 and a part is stored in the SRAM. The storage blocks included in the storage medium 130 are previously divided into multiple logical groups, and the read counts of the storage blocks in the same logical group are usually relatively close. The total read count table 1202 not only records the read counts of the storage blocks included in each logical group, but also records the maximum read count of each logical group. Since the read counts of the storage blocks with the same serial number in different planes (such as block 0 in plane 1 and plane 2 in the figure) are usually relatively close, the storage blocks with the same serial number in different planes can be placed in the same logical group. Figure 3 An example of the total read count table 1202 is given. According to Figure 3 , the total read count table 1202 stores n records, and the n records respectively record the read counts and the maximum read counts of the storage blocks from Group 0 to Group n - 1.

[0046] The hardware circuit unit 1201 receives the result feedback of executing a read instruction on a storage block, determines the target storage block operated by the read instruction according to the result feedback, then increments the read count of the target storage block in the read count statistics table 1202, and simultaneously updates the maximum read count of the logical group where the target storage block is located. The hardware circuit unit 1201 also determines whether the maximum read count of the logical group where the target storage block is located exceeds the first read count threshold. If so, an interrupt is triggered for the processor 1203 to execute a predetermined software processing program. The predetermined software processing program performs data checking and migration on the logical group where the target storage block is located. The predetermined software processing program can be formed in the FTL and exist as firmware.

[0047] To further improve the processing efficiency of the controller 120, as Figure 4 shown, a temporary read count table 1204 is added to the hardware circuit unit 1201. The temporary read count table 1204 stores the read counts of each storage block in some logical groups within the current period of time. The size of the cache unit for caching the temporary read count table 1204 can be specified by firmware. For example, it is specified that the cache unit has M (M = 8) cache lines, and each line caches the record of one logical group. Moreover, based on the temporary read count table 1204, a total read count table 1202 as Figure 6 shown is also designed. It can be seen from the figure that the design of this table is different from that of Figure 2 the total read count table 1202 in Figure 6 which only records the maximum read count of each logical group and no longer records the read counts of each storage block.

[0048] Figure 4The hardware circuit unit 1201 therein performs the following functions: receiving the result feedback of the read instruction from the storage block, determining the target storage block read according to the result feedback, if there is a record of the target storage block in the temporary read count table 1204, updating the read count of the target storage block in the temporary read count table 1204 and the maximum read count of the logical group where the target storage block is located, if there is no record of the target storage block in the temporary read count table 1204, adding a record including the read count of the target storage block and the maximum read count of the logical group where the target storage block is located to the temporary read count table 1204; when it is determined that the maximum read count of the logical group where the target storage block in the temporary read count table 1204 exceeds the second read count threshold, increasing the maximum read count of the logical group where the target storage block in the temporary read count table 1204 to the maximum read count of the target storage block in the total read count table 1202; and when it is determined that the maximum read count of the logical group where the target storage block in the total read count table 1202 exceeds the first read count threshold, triggering an interrupt for the processor 1203 to execute a predetermined software processing program, and the predetermined software processing program performs data check and transfer on the logical group where the target storage block is located. The second read count threshold is usually set relatively small (for example, 8), and moreover, the second read count threshold is less than the first read count threshold.

[0049] More specifically, the update logic of the temporary read count table and the total read count table of the hardware circuit unit 1201 is as described below:

[0050] 1) After monitoring that a read instruction of the target storage block is completed, query the temporary read count table, find the corresponding cache line where the logical group is located in the cache unit, increment the read count by 1 at the corresponding count position of the target storage block, and synchronously update the maximum read count in this cache line;

[0051] 2) If the number of the corresponding logical group is not found in the cache unit, then select an idle cache line from the cache unit, clear this cache line, then increment the read count by 1 at the corresponding count position of the target storage block, and synchronously update the maximum read count in this cache line;

[0052] 3) If the number of the corresponding logical group is not found in the cache unit and all cache lines are occupied, then flush the record in the cache line with the longest usage time or the lowest usage frequency to the total read count table, and then clear this cache line to record new data;

[0053] 4) Before or after flushing the records in the cache line with the longest usage time or the lowest usage frequency to the total read count table, determine whether the maximum read count of the corresponding logic group in the total read count table reaches the set first read count threshold (the first read count threshold is generally set to tens of thousands to hundreds of thousands of times). If the judgment is made before flushing, and if the set first read count threshold is reached, do not update the total read count table, clear the records of the corresponding cache line in the total read count table and the temporary read count table, and initiate an interrupt to notify the processor. If the judgment is made after flushing, directly clear the records of the corresponding cache line in the total read count table and the temporary read count table;

[0054] 5) If the read count value of a certain storage block in the cache unit reaches the second read count threshold (generally 8 times) after completing the current accumulation operation, then flush the read count of this cache line to the total read count table and clear the records in this cache line at the same time.

[0055] Among them, flushing the records of the cache line to the total read count table means adding the maximum read count of this line to the maximum read count of the corresponding logic group in the total read count table.

[0056] Figure 7 An embodiment variation based on Figure 4 is given. As Figure 7 shown, the controller 120 includes a hardware circuit unit 1201 and a software program 1205, and the software program 1205 can be implemented as firmware. In this embodiment, the hardware circuit unit 1201 is only responsible for maintaining the temporary read count table 1204, including: receiving the result feedback of the read instruction from the flash memory particle, determining the target storage block according to the result feedback, and updating or adding the record of the target storage block to the temporary read count table. The software program 1205 reads records one by one from the temporary read count table 1204, updates the maximum read count of the corresponding logic group in the total read count table 1202 according to the maximum read count of the logic group in each record, and when the maximum read count of the logic group of a certain record in the total read count table is greater than the first read count threshold, notify the predetermined processing program to perform data check and relocation on the storage blocks within the corresponding logic group.

[0057] The software program 1205 can also operate like this: first add the maximum read count of the logic group of each record in the temporary read count table 1204 to the maximum read count of the corresponding logic group in the total read count table 1202. If the sum of the two is not greater than the first read count threshold, update the maximum read count of the corresponding logic group in the total read count table 1202 based on the sum of the two. If the sum of the two is greater than the first read count threshold, do not update the total read count table 1202, but directly notify the predetermined processing program.

[0058] In some embodiments, the software program 1205 or the hardware circuit unit 1201 may also perform numerical compensation on the maximum read count of the corresponding logic group in the external general statistical table, including: adding the compensation value to the maximum read count of the general table read, and determining whether the first read count threshold is reached. If the threshold is reached, the general table is not updated, and an interrupt is initiated to notify a predetermined processing program; if the threshold is not reached, the general table is updated.

[0059] Correspondingly, an embodiment of the present disclosure also proposes a method for recording the read count of a storage block. This embodiment can be implemented by a software program or a hardware circuit unit. Figure 8 The flowchart of the method is given, including the following steps.

[0060] In step S801, receive the result feedback of the flash memory particle to the read instruction.

[0061] In step S802, according to the target storage block determined by the result feedback, increase the read count of the target storage block and update the maximum read count of the logic group where the target storage block is located.

[0062] In step S803, determine whether the maximum read count of the logic group where the target storage block is located exceeds the first read count threshold.

[0063] In step S804, send a notification to a predetermined software processing program so that the predetermined software processing program can perform data checking and migration on the storage blocks in the corresponding logic group.

[0064] The method described in this embodiment is applied to a controller of a flash memory. The flash memory includes flash memory particles coupled to the controller. Each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, and all storage blocks are divided into multiple logic groups. This grouping is usually based on the host device's reading data habits for storage blocks, grouping storage blocks with similar read counts in the same logic group. Therefore, usually, storage blocks with different serial numbers in all planes are grouped in the same logic group.

[0065] The method described in this embodiment also records the read count of each storage block and the maximum read count of the logic group where the storage block is located according to the result feedback of the read instruction returned from the flash memory particle, similar to Figure 3 as shown.

[0066] To improve the processing efficiency, this embodiment can also be implemented through the read count temporary table and the total read count table as shown in Figure 5. That is, when receiving the result feedback of the read instruction from the flash memory particle, it is first updated or added to the read count temporary table. Then, when the maximum read count of the corresponding logical group in the read count temporary table exceeds the second read count threshold, it is added to the total read count table. Moreover, according to the stored data requirements, the read count temporary table can be stored in a volatile or non-volatile storage medium, such as DRAM or SRAM, and the total read count table is usually stored in a non-volatile storage medium, such as SRAM.

[0067] Although the embodiments of the present disclosure are disclosed above as preferred embodiments, they are not used to limit the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims of the present invention.

[0068] The above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, the present disclosure can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A controller for a flash memory, the flash memory comprising flash memory particles coupled to the controller, each flash memory particle being divided into a plurality of planes, each plane being divided into a plurality of storage blocks, all storage blocks being divided into a plurality of logical groups, the controller comprising: A first storage unit is used to persistently store a total read count table, wherein the total read count table not only records the read count of each storage block included in each logical group, but also records the maximum read count of each logical group; The hardware circuit unit is used to receive the result feedback of the flash memory particle on the read instruction, increase the read count of the target storage block and update the maximum read count of the logical group where the target storage block is located according to the target storage block determined by the result feedback, and when it is determined that the maximum read count of the logical group where the target storage block is located exceeds a first read count threshold, trigger a processor interrupt so that a predetermined software processing program can check and move data on the storage blocks in the corresponding logical group.

2. A controller for a flash memory, the flash memory comprising flash memory particles coupled to the controller, each flash memory particle being divided into a plurality of planes, each plane being divided into a plurality of storage blocks, all storage blocks being divided into a plurality of logical groups, the controller comprising: A first storage unit is used to persistently store a total table of read times, wherein the total table of read times records a maximum number of read times of each logical group; A second storage unit is used to cache a temporary table of read times, wherein the temporary table of read times records the number of reads of each storage block within a period of time and the maximum number of reads of the logical group to which each storage block belongs within a corresponding time; The hardware circuit unit is used to: receive the result feedback of the flash memory particle on the read instruction, update or add the record of the target storage block to the temporary table of read times according to the target storage block determined by the result feedback, and when the maximum read count of the logical group where the target storage block in the temporary table of read times is located exceeds a second read count threshold, update the maximum read count of the corresponding logical group in the total table of read times based on the record of the target storage block in the temporary table of read times; When it is determined that the maximum read count of the logical group where the target storage block in the read count total table is located exceeds a first read count threshold, a processor interrupt is triggered so that a predetermined software processing program can check and move data on the storage blocks in the corresponding logical group.

3. The controller according to claim 2, wherein: When the hardware circuit unit adds the record of the target storage block to the temporary table of read times, the free storage space in the second storage unit is used to store the record of the target storage block; or, based on the record with the longest current usage time or the lowest usage frequency in the temporary table of read times, the maximum number of reads of the corresponding logical group in the total table of read times is updated, and then the corresponding storage space is used to store the record of the target storage block.

4. The controller according to claim 2 or 3, wherein: After the maximum number of reads of the corresponding logical group in the total number of reads table is updated, the storage space occupied by the corresponding record in the second storage unit is cleared, or the corresponding record is marked as invalid.

5. The controller according to claim 2, wherein: Storage blocks with the same sequence number in all planes are divided into the same logical group.

6. The controller according to claim 2, wherein: The first storage unit is a non-volatile storage medium, and the second storage unit is a volatile storage medium.

7. A controller for a flash memory, the flash memory comprising flash memory particles coupled to the controller, each flash memory particle being divided into a plurality of planes, each plane being divided into a plurality of storage blocks, all storage blocks being divided into a plurality of logical groups, the controller comprising: A first storage unit is used to persistently store a total table of read times, wherein the total table of read times records a maximum number of read times of each logical group; A second storage unit is used to cache a temporary table of read times, wherein the temporary table of read times records the number of reads of each storage block within a period of time and the maximum number of reads of the logical group to which each storage block belongs within a corresponding time; A hardware circuit unit, configured to receive feedback of a result of the flash memory particle in response to a read instruction, and update or add a record of the target storage block to the temporary table of read times according to the target storage block determined by the feedback of the result; Firmware, used to update the maximum read times of the corresponding logical groups in the total read times table based on the maximum read times of each logical group in the temporary read times table, and when the maximum read times of a specific logical group in the total read times table is greater than a first read times threshold, notify a predetermined processing program to check and move data on the storage blocks in the corresponding logical group.

8. A method for recording the number of storage block reads, applied to a controller of a flash memory, wherein the flash memory comprises flash memory particles coupled to the controller, each flash memory particle is divided into a plurality of planes, each plane is divided into a plurality of storage blocks, and all storage blocks are divided into a plurality of logical groups, the method comprising: Receive feedback from the flash memory particle on the result of the read instruction; According to the target storage block determined by the result feedback, increase the read count of the target storage block and update the maximum read count of the logical group where the target storage block is located; as well as When it is determined that the maximum read count of the logic group where the target storage block is located exceeds the first read count threshold, a notification is sent to a predetermined program so that the predetermined program checks and moves data on the storage blocks in the corresponding logic group.

9. The method for recording the number of storage block reads according to claim 8, wherein: In the step of increasing the number of reads of the target storage block and updating the maximum number of reads of the logical group where the target storage block is located, A temporary read count table is used to store the read count of the target storage block and the maximum read count of the logical group where the target storage block is located, and when the maximum read count of the logical group where the target storage block is located exceeds a second read count threshold, the maximum read count of the logical group where the target storage block is located in the temporary read count table is added to the maximum read count of the logical group where the target storage block is located in the total read count table, and the total read count table only records the maximum read count of each logical group.

10. A flash memory, comprising a storage medium and a controller, wherein the controller is the controller according to any one of claims 1 to 8, and the storage medium comprises flash memory particles coupled to the controller, each flash memory particle is divided into multiple planes, each plane is divided into multiple storage blocks, all storage blocks are divided into multiple logical groups, and storage blocks with the same serial number in all planes are divided into the same logical group.

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