Instruction distribution method and system of solid state disk main control chip

Abstract

The invention discloses an instruction distribution method and system for a main control chip of a solid state disk, relates to the technical field of chip management and control, and is used for solving the problems of low data processing efficiency and slow instruction response speed in the prior art. The method comprises the following steps of: receiving all operation instructions of a main control chip of the solid state disk, sequentially analyzing the operation instructions to obtain corresponding instruction attribute dimensions, establishing a metadata label of each operation instruction, creating a to-be-responded task of the corresponding operation instruction, performing dynamic weight calculation on the to-be-responded task to divide the task priority, establishing a hierarchical buffer queue, and storing the to-be-responded task in the hierarchical buffer queue. The hierarchical buffer queue is processed based on the preemptive scheduling rule, the channel resources corresponding to the to-be-responded task of each channel on the main control chip are scheduled, whether scheduling conflicts exist or not is judged, the conflicts are solved when the conflicts exist, and efficient processing and distribution of the operation instruction are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip control, and specifically to an instruction allocation method and system for a solid-state drive main control chip. Background Art

[0002] In the current technical field of chip control, the data processing efficiency and instruction response speed of a solid-state drive main control chip are the key factors restricting its performance. When the existing solid-state drive main control chips process operation instructions, they usually adopt a fixed instruction allocation method. This allocation method often fails to effectively divide the priorities and schedule resources for different operation instructions, resulting in low data processing efficiency and slow instruction response speed. In addition, when multiple operation instructions request chip resources simultaneously, resource scheduling conflicts are likely to occur, further affecting the stability and reliability of the system.

[0003] Therefore, how to improve the data processing efficiency and instruction response speed of a solid-state drive main control chip has become an urgent problem to be solved in this field. Summary of the Invention

[0004] In order to solve the above problems, the purpose of the present invention is to provide an instruction allocation method and system for a solid-state drive main control chip.

[0005] The purpose of the present invention can be achieved through the following technical solutions: An instruction allocation method for a solid-state drive main control chip includes the following steps: Step S1: Receive all the operation instructions created by the solid-state drive main control chip, parse each operation instruction in sequence to obtain the corresponding instruction attribute dimensions, establish a metadata tag corresponding to each operation instruction, and create a to-be-responded task for the corresponding operation instruction according to the metadata tag; Step S2: Perform dynamic weight calculation on each to-be-responded task, and then divide the task priorities of the to-be-responded tasks, establish a hierarchical buffer queue, and process the hierarchical buffer queue based on the preemptive scheduling rule to schedule the channel resources corresponding to the to-be-responded tasks of each channel on the main control chip; Step S3: Determine whether there are conflicts in the scheduling of channel resources, and solve the scheduling conflicts based on the address remapping algorithm.

[0006] Further, the process of receiving all the operation instructions created by the solid-state drive main control chip and parsing each operation instruction in sequence to obtain the corresponding instruction attribute dimensions includes: Set an instruction creation period, an instruction verification period, and an instruction parsing period; During the instruction creation period, the solid-state drive main control chip creates several types of operation instructions according to the operating logic of the operating system; During the instruction verification period, receive all the operation instructions created by the solid-state drive main control chip in sequence for security verification; During the instruction parsing period, each operation instruction after passing the security verification is parsed in sequence, and the corresponding instruction attribute dimension of each operation instruction is obtained.

[0007] Furthermore, the process of establishing metadata tags corresponding to each operation instruction and creating a task to be responded to for the corresponding operation instruction based on the metadata tags includes: Obtain the usage permission of the metadata engine, call the metadata engine to perform additional analysis on each operation instruction. The additional analysis includes physical mapping analysis, timing feature analysis, and business association analysis. The data features of each operation instruction are obtained through physical mapping analysis, timing feature analysis, and business association analysis; After obtaining all the data features of the operation instruction, establish the corresponding metadata tag; Bind each operation instruction with the metadata tag, create a task descriptor corresponding to each operation instruction, map all the data features of the metadata tag to the corresponding operation instruction, and then create a task to be responded to for each operation instruction; Assign a task route to each task to be responded to, and the task route is initially a blank route.

[0008] Furthermore, the process of performing dynamic weight calculation on each task to be responded to and then dividing the task priority of the task to be responded to includes: Perform dynamic weight calculation on each task to be responded to in sequence to obtain the task weight corresponding to each task to be responded to. The dynamic weight calculation is carried out under a weight evaluation system, and the weight evaluation system consists of time urgency, resource utilization rate, wear degree, and data value; Set a secondary weight interval and a primary weight interval, denoted as Ω1 and Ω2 respectively; Denote the task weight of the task to be responded to as η; When η ∈ Ω1, divide the task priority of the task to be responded to as general priority, and change the task route from the blank route to the general route; When η ∈ Ω2, divide the task priority of the task to be responded to as important priority, and change the task route from the blank route to the important route.

[0009] Furthermore, the process of processing the hierarchical buffer queue based on the preemptive scheduling rule and scheduling the channel resources corresponding to the tasks to be responded to for each channel on the scheduling master chip includes: Establish a hierarchical buffer queue composed of a real-time queue, a mixed queue, and a batch processing queue; Define the respective subclasses, priority ranges, and scheduling policies of the real-time queue, the mixed queue, and the batch processing queue, process the operation hierarchical buffer queue based on the preemptive scheduling rule, and determine whether the preemptive condition is triggered; If so, adjust the channel resources corresponding to the task to be responded to on the corresponding channel that triggers the preemption condition on the main control chip; if not, do nothing.

[0010] Further, the process of determining whether the preemption condition is triggered includes: When the following sub-conditions are all satisfied, it is determined that the preemption condition is triggered; otherwise, it is not triggered; Priority sub-condition: New task priority > current executing task priority + preemption threshold; Timeliness sub-condition: Remaining response time of new task < expected completion time of current task + context switching overhead; Resource compatibility sub-condition: The channel / Die resources required by the new task have no conflict with the current task.

[0011] Further, to determine whether there is a conflict in the scheduling of channel resources, the process of resolving the scheduling conflict based on the address remapping algorithm includes: Define different types of resource conflict scenarios. The resource conflict scenarios include multiple tasks accessing the same channel concurrently, voltage interference caused by mixed read and write operations, and multiple tasks triggering high-voltage programming operations simultaneously. If any resource conflict scenario is detected, it is determined that there is a conflict in the scheduling of channel resources; otherwise, it is determined that there is no conflict in the scheduling of channel resources for the time being. When there is a conflict in the scheduling of channel resources, resolve the resource scheduling conflict occurring at the corresponding channel based on the address mapping algorithm. When there is no conflict in the scheduling of channel resources, do nothing.

[0012] Further, an instruction allocation system for a solid-state drive main control chip, the system includes: An instruction parsing and task creation module, which is used to receive all operation instructions created by the solid-state drive main control chip, sequentially parse each operation instruction to obtain the corresponding instruction attribute dimension, establish a metadata label for each operation instruction, and create a task to be responded to for the corresponding operation instruction according to the metadata label; A priority division and resource scheduling module, which is used to calculate the dynamic weight of each task to be responded to, and then divide the task priority of the task to be responded to, establish a hierarchical buffer queue, process the hierarchical buffer queue based on the preemptive scheduling rule, and schedule the channel resources corresponding to the task to be responded to on each channel of the main control chip; A conflict judgment and processing module, which is used to judge whether there is a conflict in the scheduling of channel resources and resolve the scheduling conflict based on the address remapping algorithm.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: Through the attribute dimension analysis of operation instructions and the establishment of metadata tags, the refined management of operation instructions is realized, which helps to improve the data processing efficiency; The dynamic weight calculation method is adopted to divide the priorities of tasks to be responded, enabling the main control chip to allocate resources according to the importance of tasks, thereby improving the instruction response speed; A hierarchical buffer queue is established and the hierarchical buffer queue is processed based on the preemptive scheduling rule, effectively ensuring the priority execution of high-priority tasks and further optimizing the data processing efficiency. By judging whether there is a conflict in the channel resource scheduling and using the address remapping algorithm to solve the scheduling conflict, the stability and reliability are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a flowchart of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] As Figure 1 shown, an instruction allocation method for a solid-state drive main control chip includes the following steps: Step S1: Receive all operation instructions created by the solid-state drive main control chip, parse each operation instruction in sequence to obtain the corresponding instruction attribute dimension, establish a metadata tag corresponding to each operation instruction, and create a task to be responded for the corresponding operation instruction according to the metadata tag; Step S2: Perform dynamic weight calculation on each task to be responded, and then divide the task priorities of the tasks to be responded, establish a hierarchical buffer queue, process the hierarchical buffer queue based on the preemptive scheduling rule, and schedule the channel resources corresponding to the tasks to be responded on each channel of the main control chip; Step S3: Judge whether there is a conflict in the scheduling of channel resources, and solve the scheduling conflict based on the address remapping algorithm.

[0016] It should be further noted that in the specific implementation process, the process of receiving all operation instructions created by the solid-state drive main control chip and parsing each operation instruction in sequence to obtain the corresponding instruction attribute dimension includes: Set the instruction creation period, instruction verification period, and instruction parsing period; During the instruction creation period, the solid-state drive main control chip creates several types of operation instructions according to the operating logic of the operating system, and binds an authentication identifier and a data flow path to each operation instruction; During the instruction verification period, receive all the operation instructions created by the solid-state drive main control chip in sequence, and perform security verification on each operation instruction in sequence, judge whether the authentication identifier of the operation instruction is tampered with. If so, directly determine that the security verification fails. If not, continue to judge whether the data flow path of the operation instruction is compliant; If so, it is determined that the security verification of the current operation instruction passes; If not, it is determined that the security verification of the current operation instruction fails, and the current operation instruction is destroyed; During the instruction parsing period, each operation instruction that passes the security verification is parsed in sequence, and the corresponding instruction attribute dimensions of each operation instruction are obtained. The instruction attribute dimensions include the operation type, instruction address, data volume, and creation timestamp of the operation instruction.

[0017] It should be further noted that in the specific implementation process, the process of establishing the metadata tag corresponding to each operation instruction and creating the task to be responded to for the corresponding operation instruction includes: Obtain the usage permission of the metadata engine, and call the metadata engine to perform additional analysis on each operation instruction. The additional analysis includes physical mapping analysis, timing feature analysis, and business association analysis. The data features of each operation instruction are obtained through physical mapping analysis, timing feature analysis, and business association analysis; The physical mapping analysis is marked by querying the physical page number mapping table through the FTL layer of the solid-state drive main control chip. The obtained data features include the target flash channel number, the target Die / Plane hierarchical structure, and the remaining PE cycles of the current block; The timing feature analysis calculates the historical execution records of the operation instruction through the metadata engine. The obtained data features include the average processing duration of similar instructions and the minimum interval duration between adjacent instructions; The business association analysis is used to obtain data features including the sequential access mark of the operation instruction and the instruction access frequency; After obtaining all the data features of the operation instruction, establish the corresponding metadata tag; The field composition of the metadata tag is as follows: | Opcode (4b) | Urgency (3b) | Channel number (4b) | Die mask (8b) | Estimated duration (16b) | Wear level (4b) | Data correlation (8b) | Reserved bit (5b) | CRC check (8b) |; Among them, "|" represents the field separator, opcode, urgency,..., CRC check, etc. represent field types, and 4b, 3b, and 8b in () represent the number of bits corresponding to different field types of fields; Bind each operation instruction to the metadata tag, create a task descriptor corresponding to each operation instruction, and map all the data features corresponding to the metadata tag to the corresponding operation instruction, thereby creating a task to be responded to for each operation instruction; The task descriptor serves as the task differentiation identifier for the task to be responded to; A task routing is assigned to each task to be responded to, and the task routing is initially a blank routing.

[0018] It should be further noted that in the specific implementation process, the process of dynamically calculating the weight of each task to be responded to and then dividing the task priority of the task to be responded to includes: The online learning engine is used to identify all task descriptors, and the dynamic weight of the task to be responded to corresponding to each task descriptor is calculated in turn, so as to obtain the task weight corresponding to each task to be responded to; The dynamic weight calculation is carried out under the weight evaluation system; The weight evaluation system consists of time urgency, resource utilization rate, wear degree and data value; The coefficient factor reflecting time urgency is denoted as α, and the calculation formula of α is expressed as follows: α = 1 / (T_remaining - T_current + ε); Among them, T_remaining represents the latest completion timestamp, T_current represents the current system clock count, and ε represents the anti-zero protection constant (usually taken as 1 μs); The coefficient factor reflecting resource utilization rate is denoted as β, and the calculation formula of β is expressed as follows: β = 1 - (Channel_busy_cycles / Total_cycles); Among them, Channel_busy_cycles represents the occupied duration of the target channel in the past N cycles, and Total_cycles represents the total number of cycles of the window; The coefficient factor reflecting wear degree is denoted as γ, and the calculation formula of γ is expressed as follows: γ = 1 - (Wear_level / Max_PE); Among them, Wear_level represents the number of consumed PE cycles of the target flash block, and Max_PE represents the maximum number of PE times specified by the flash memory specification; The coefficient factor reflecting data value is denoted as δ, and the calculation formula of δ is expressed as follows: δ = Logistic(Hotness_Score - Threshold); Among them, Logistic() represents the linear regression analysis function, Hotness_Score is the heat score based on the LBA access frequency (0 - 255), and Threshold represents the dynamically adjusted hot and cold data demarcation threshold; Normalize the coefficient factors α, β, γ, and δ, and assign proportion weights to the coefficient factors after each normalization process. The proportion weights of α, β, γ, and δ are z1, z2, z3, and z4 respectively; Then the task weight of the task to be responded is expressed as follows: Task weight = α × z1 + β × z2 + γ × z3 + δ × z4; Among them, z1, z2, z3, and z4 are all real numbers between (0, 1); And z1 + z2 + z3 + z4 = 1; Set the secondary weight interval and the primary weight interval; Denote the secondary weight interval as Ω1, Ω1 = [a, b] Denote the primary weight interval as Ω2, Ω2 = (b, c]; Among them, 0 ≤ a < b < c ≤ 1; Denote the task weight of the task to be responded as η, and the value range of η is [0, 1]; When η ∈ Ω1, classify the task priority of the task to be responded as the general priority, and change the task routing from the blank routing to the general routing; When η ∈ Ω2, classify the task priority of the task to be responded as the important priority, and change the task routing from the blank routing to the important routing; The important routing is executed prior to the general routing.

[0019] It should be further noted that in the specific implementation process, a hierarchical buffer queue is established, and the hierarchical buffer queue is processed based on the preemptive scheduling rule. The process of scheduling the channel resources corresponding to the tasks to be responded for each channel on the scheduling master chip includes: Establish a hierarchical buffer queue composed of a real-time queue, a mixed queue, and a batch processing queue; Define the subclasses, priority ranges, and scheduling policies of the real-time queue, the mixed queue, and the batch processing queue respectively, process and operate the hierarchical buffer queue based on the preemptive scheduling rule, and determine whether the preemptive condition is triggered. Specifically as follows: When the following sub-conditions are all satisfied simultaneously, it is determined that the preemptive condition is triggered, otherwise, it is not triggered; Priority sub-condition: New task priority > Current task priority + Preemption threshold; Timeliness sub-condition: Remaining response time of new task < Estimated completion time of current task + Context switching overhead; Resource compatibility sub-condition: Channel / Die resources required by the new task have no conflict with the current task; If so, regulate the channel resources corresponding to the tasks to be responded for the channels on the scheduling master chip that trigger the preemptive condition accordingly. If not, no operation is performed.

[0020] It should be noted that the respective subclasses, priority ranges, and scheduling policy correspondences of the real-time queue, hybrid queue, and batch processing queue included in the hierarchical buffer queue are as follows: The subclasses of the real-time queue include the emergency event response queue and the high-priority IO queue; The priority range of the emergency event response queue is 0.95 - 1.0, and the corresponding scheduling policy is: directly triggered by hardware interrupt; the priority range of the high-priority IO queue is 0.8 - 0.94, and the corresponding scheduling policy is: strict time slice rotation; The subclasses of the hybrid queue include the adaptive equalization queue and the background maintenance queue; The priority range of the adaptive equalization queue is 0.6 - 0.79, and the corresponding scheduling policy is: dynamic adjustment of weights; the priority range of the background maintenance queue is 0.4 - 0.59, and the corresponding scheduling policy is: batch processing during idle periods; The subclasses of the batch processing queue include the sequential optimization queue and the delay-tolerant queue; The priority range of the sequential optimization queue is 0.2 - 0.39, and the corresponding scheduling policy is: instruction merging; the priority range of the delay-tolerant queue is 0.0 - 0.19, and the corresponding scheduling policy is: triggered when resources are idle.

[0021] It should be further noted that in the specific implementation process, to determine whether there is a conflict in the scheduling of channel resources, the process of resolving the scheduling conflict based on the address remapping algorithm includes: Define different types of resource conflict scenarios. The resource conflict scenarios include multi-task concurrent access to the same channel, read-write mixed operations causing voltage interference, and multi-tasks simultaneously triggering high-voltage programming operations. If any resource conflict scenario is detected, it is determined that there is a conflict in the scheduling of channel resources; otherwise, it is determined that there is no conflict in the scheduling of channel resources for the time being; The respective conflict detection metrics for the multi-task concurrent access to the same channel, read-write mixed operations causing voltage interference, and multi-tasks simultaneously triggering high-voltage programming operations are as follows: For multi-task concurrent access to the same channel, its conflict detection metric is: the instruction timings of different Dies within the same channel overlap; for read-write mixed operations causing voltage interference, its conflict detection metric is: electrical signal conflicts of Planes / Cells within the same Die; for multi-tasks simultaneously triggering high-voltage programming operations, its conflict detection metric is: the channel voltage fluctuation exceeds a preset safety threshold (e.g., ±5%); When there is a conflict in the scheduling of channel resources, resolve the resource scheduling conflict occurring at the corresponding channel based on the address mapping algorithm. When there is no conflict in the scheduling of channel resources, no operation is performed.

[0022] The present invention also provides an instruction distribution system for a solid-state drive main control chip, which system comprises: An instruction parsing and task creation module, configured to receive all operation instructions created by the solid-state drive main control chip, sequentially parse each operation instruction to obtain corresponding instruction attribute dimensions, establish metadata tags corresponding to each operation instruction, and create a to-be-responded task for the corresponding operation instruction according to the metadata tags; A priority division and resource scheduling module, configured to perform dynamic weight calculation on each to-be-responded task, thereby dividing the task priorities of the to-be-responded tasks, establish a hierarchical buffer queue, process the hierarchical buffer queue based on a preemptive scheduling rule, and schedule the channel resources corresponding to the to-be-responded tasks of each channel on the main control chip; A conflict judgment and handling module, configured to judge whether there is a conflict in the scheduling of channel resources, and solve the scheduling conflict based on an address remapping algorithm.

[0023] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for distributing instructions to a solid state drive main control chip, characterized in that: The following steps are involved: Step S1: receiving all operation instructions created by the main control chip of the solid-state drive, parsing each operation instruction in turn to obtain the corresponding instruction attribute dimension, and establishing a metadata tag corresponding to each operation instruction, and creating a task to be responded to the corresponding operation instruction according to the metadata tag; Step S2: Dynamically calculate the weight of each task to be responded to, and then divide the task priority of the task to be responded to, establish a hierarchical buffer queue, process the hierarchical buffer queue based on the preemptive scheduling rule, and schedule the channel resources corresponding to the task to be responded to of each channel on the main control chip; Step S3: Determine whether there is a scheduling conflict in channel resources, and resolve the scheduling conflict based on an address remapping algorithm.

2. The method for distributing instructions to a solid state drive main control chip according to claim 1, characterized in that: The process of receiving all operation instructions created by the main control chip of the solid-state drive and parsing each operation instruction in turn to obtain the corresponding instruction attribute dimension includes: Set the instruction creation period, instruction verification period, and instruction parsing period; During the instruction creation period, the main control chip of the solid-state drive creates several types of operation instructions according to the operation logic of the operating system; During the instruction verification period, all operation instructions created by the SSD main control chip are received in sequence for security verification; During the instruction parsing period, each operation instruction that has passed the security verification is parsed in turn, and the instruction attribute dimension corresponding to each operation instruction is obtained.

3. The method for distributing instructions to a solid state hard disk master chip according to claim 2, characterized in that: The process of establishing metadata tags corresponding to each operation instruction and creating a task to be responded to according to the metadata tags includes: Obtain the permission to use the metadata engine, call the metadata engine to perform additional analysis on each operation instruction, the additional analysis includes physical mapping analysis, timing feature analysis and business association analysis, and obtain the data features of each operation instruction through physical mapping analysis, timing feature analysis and business association analysis; After obtaining all data features of the operation instruction, the corresponding metadata tags are established; Bind each operation instruction with a metadata tag, create a task descriptor corresponding to each operation instruction, associate and map all data features of the metadata tag to the corresponding operation instruction, and then create a task to be responded to corresponding to each operation instruction; A task route is assigned to each task to be responded to. The task route is initially a blank route.

4. The method for distributing instructions to a solid state hard disk main control chip according to claim 3, characterized in that: The process of dynamically calculating the weight of each task to be responded to and then dividing the task priority of the task to be responded to includes: Perform dynamic weight calculation on each pending task in turn to obtain the task weight corresponding to each pending task. The dynamic weight calculation is performed under the weight evaluation system, which is composed of time urgency, resource utilization, wear and tear, and data value. Set the secondary weight interval and the primary weight interval, denoted as Ω1 and Ω2 respectively; The task weight of the task to be responded to is recorded as η; When η∈Ω1, the task priority of the task to be responded is divided into general priority, and the task route is changed from blank route to general route; When η∈Ω2, the task priority of the task to be responded is divided into important priority, and the task route is changed from the blank route to the important route.

5. The method for distributing instructions to a solid state hard disk main control chip according to claim 4, characterized in that: The process of establishing a hierarchical buffer queue, processing the hierarchical buffer queue based on a preemptive scheduling rule, and scheduling channel resources corresponding to the tasks to be responded to in each channel on the main control chip includes: Establish a hierarchical buffer queue consisting of real-time queue, mixed queue and batch queue; Define the subclasses, priority ranges, and scheduling policies of real-time queues, mixed queues, and batch queues, process the hierarchical buffer queues based on preemptive scheduling rules, and determine whether preemption conditions are triggered; If yes, then adjust the channel resources corresponding to the task to be responded to of the channel that triggers the preemption condition on the main control chip; if no, do not perform any operation.

6. The method for distributing instructions to a solid state hard disk main control chip according to claim 5, characterized in that: The process of determining whether the preemption condition is triggered includes: When the following sub-conditions are met at the same time, the preemption condition is determined to be triggered, otherwise, it is not triggered; Priority sub-condition: New task priority > current execution task priority + preemption threshold; Timeliness sub-condition: the remaining response time of the new task < the estimated completion time of the current task + the context switching overhead; Resource compatibility sub-condition: The channel / Die resources required by the new task do not conflict with the current task.

7. The method for distributing instructions to a solid state hard disk main control chip according to claim 6, characterized in that: Determine whether there is a scheduling conflict in channel resources. The process of resolving scheduling conflicts based on the address remapping algorithm includes: Different types of resource conflict scenarios are defined. The resource conflict scenarios include multiple tasks concurrently accessing the same channel, mixed read-write operations causing voltage interference, and multiple tasks simultaneously triggering high-voltage programming operations. If any resource conflict scenario is detected, it is determined that there is a conflict in the scheduling of channel resources. Otherwise, it is determined that there is no conflict in the scheduling of channel resources. When there is a conflict in the scheduling of channel resources, the resource scheduling conflict occurring at the corresponding channel is resolved based on the address mapping algorithm. When there is no conflict in the scheduling of channel resources, no operation is performed.

8. An instruction distribution system for a solid state hard disk main control chip, used to implement the instruction distribution method according to any one of claims 1 to 7, characterized in that: The system includes: The instruction parsing and task creation module is used to receive all the operation instructions created by the SSD main control chip, parse each operation instruction in turn to obtain the corresponding instruction attribute dimension, establish the metadata tag corresponding to each operation instruction, and create the corresponding operation instruction's pending response task according to the metadata tag; The priority division and resource scheduling module is used to dynamically calculate the weight of each task to be responded to, and then divide the task priority of the task to be responded to, establish a hierarchical buffer queue, process the hierarchical buffer queue based on the preemptive scheduling rule, and schedule the channel resources corresponding to the task to be responded to in each channel of the main control chip; The conflict judgment and processing module is used to judge whether there is a conflict in the scheduling of channel resources and resolve the scheduling conflict based on the address remapping algorithm.

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