Ipc-based software and hardware joint debugging method, electronic device and medium

Abstract

The application relates to the chip technical field, in particular to a software and hardware joint debugging method based on an IPC, electronic equipment and a medium, the method comprises the following steps: S1, obtaining N software test case sets which need to be run on a to-be-tested chip design in parallel; S2, assigning a corresponding process group (B1 n , B2 n ) to each A n , assigning a corresponding interaction identifier P n to each process group based on an IPC protocol; S3, starting all B1 n in parallel, each B1 n starts to execute the corresponding A n , meanwhile, the chip RTL code performs a chip initialization operation, B1 n generates A n corresponding register configuration instructions based on the corresponding A n , and enters a waiting state; S4, after the to-be-tested chip design completes the chip initialization operation, B1 n and B2 n perform inter-process communication based on the corresponding P n , and A n is run on the to-be-tested chip design. The application reduces the cross-stage verification cost of the software test case and improves the chip verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a hardware and software integration method, electronic device, and medium based on IPC. Background Technology

[0002] Chip development involves various verification phases. Typically, hardware-level verification begins with the chip's Register Transfer Level (RTL) code. After basic hardware verification, a hardware accelerator or physical chip is developed, followed by system-level verification. Once system-level verification is successful, software-level verification is performed using the accelerator or physical chip. Current technology requires developing separate verification platforms for each phase, and these platforms can only verify test cases for their corresponding phases, not cross-phase test cases. However, chip development often necessitates running software test cases directly on the chip's RTL code. For example, if a software test case encounters problems on a software testing platform, it's desirable to run the same test case on the chip's RTL code for verification and debugging. Software test cases are often very complex and require parallel execution. Verifying these test cases on the RTL code using hardware test cases is extremely costly and inefficient. Therefore, how to directly implement the execution of software test cases on the chip's RTL code, reduce the cost of cross-stage verification of software test cases, and improve chip verification efficiency has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a software and hardware integration debugging method, electronic device, and medium based on IPC, which enables the execution of software test cases on chip RTL code through software and hardware integration debugging, thereby reducing the cost of cross-stage verification of software test cases and improving chip verification efficiency.

[0004] According to a first aspect of the present invention, a hardware / software integration debugging method based on IPC is provided, comprising:

[0005] Step S1: Obtain a set of N software test cases {A1, A2, ..., A...} that need to be run in parallel on the chip design under test. n ,...,A N}, A n This is the nth software test case, where n ranges from 1 to N. The chip under test is designed based on RTL code implementation.

[0006] Step S2, for each A n Assign the corresponding process group (B1) n B2 n B1n For A n The corresponding first process, B2 n For A n The corresponding second process assigns a corresponding interaction identifier P to each process group based on the IPC protocol. n The IPC protocol is an inter-process communication protocol;

[0007] Step S3: Start all B1 in parallel n Each B1 n Start executing the corresponding A n Simultaneously, the chip's RTL code performs chip initialization operations, B1 n Based on the corresponding A n Generate A n The corresponding register configuration instruction will trigger a wait state.

[0008] Step S4: After the chip initialization operation is completed, B1 n B2 n Based on the corresponding P n To perform inter-process communication, A n It runs on the chip design under test.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the software and hardware integration method, electronic device, and medium based on IPC provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0012] This invention is based on dual-process communication, enabling the direct execution of software test cases on the RTL code-implemented chip design for verification. Furthermore, through multiple sets of parallel dual processes, the software test cases in the software test case set can be run in parallel on the chip design for verification without modifying the software test cases. This reduces the cost of cross-stage verification of software test cases and improves chip verification efficiency. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A flowchart of the software and hardware integration debugging method based on IPC provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides a hardware / software integration method based on IPC, such as... Figure 1 As shown, it includes:

[0017] Step S1: Obtain a set of N software test cases {A1, A2, ..., A...} that need to be run in parallel on the chip design under test. n ,...,A N}, A n This is the nth software test case, where n ranges from 1 to N. The chip under test is designed based on RTL code implementation.

[0018] It should be noted that a software test case set can specifically be a set of software test cases used for regression testing, or a collection of other software test cases that require parallel execution. RTL code can specifically be code generated using the Verilog or SystemVerilog languages.

[0019] Step S2, for each A n Assign the corresponding process group (B1) n B2 n B1 n For A n The corresponding first process, B2 n For A n The corresponding second process assigns a corresponding interaction identifier P to each process group based on the IPC protocol. n The IPC protocol is an inter-process communication protocol, which specifically refers to the protocol for data exchange and information transmission between different processes in a computer system.

[0020] It should be noted that each process group has a unique interaction identifier P. n Each process group uses its corresponding interaction identifier P. n Bind two processes, with the two processes linked based on P. n Implement IPC communication.

[0021] Step S3: Start all B1 in parallel n Each B1 n Start executing the corresponding A n Simultaneously, the chip's RTL code performs chip initialization operations, B1 n Based on the corresponding A n Generate A n The corresponding register configuration instruction triggers a wait state.

[0022] It should be noted that B1 n This corresponds to pure software operation, B2 n For interaction with the chip under test (DUT) design, it needs to be implemented in hardware. During system startup, the hardware typically needs to perform chip initialization before subsequent interaction can proceed. Chip initialization specifically includes hardware initialization, system power-on, and reset. Therefore, B1... n The execution speed must be greater than B2. n When each B1 n After startup, the corresponding A will begin execution. n B1 n Based on the corresponding A n Generate A n The corresponding register configuration instructions require register configuration to be implemented based on the design of the chip under test (DUT). This necessitates waiting for the DUT design to complete chip initialization; therefore, B1... n Entering a waiting state.

[0023] Step S4: After the chip initialization operation is completed, B1 n B2 n Based on the corresponding P n To perform inter-process communication, A n It runs on the chip design under test.

[0024] It should be noted that after the chip initialization operation is completed, B1 n B2 n It can generate a device carrying P n Inter-process communication is conducted through interactive information, thereby enabling software test case A to be transferred without altering the software test case. n It is run on the chip design under test for verification.

[0025] As one embodiment, step S3 includes:

[0026] Steps S31 and B1 n Analysis of the corresponding A n , obtain A n The corresponding operation parameters and operation logic.

[0027] It should be noted that the operation parameters can be the original operation parameters and the original operation logic corresponding to the test case. The operation parameters can also be the original operation parameters and the intermediate operation parameters obtained based on the original operation parameters, and the operation logic can be the original operation logic and the intermediate operation logic obtained based on the original operation logic.

[0028] Steps S32 and B1 n Obtain the memory information of the chip under test design, based on the memory information of the chip under test design as A. n The corresponding operation parameters are allocated memory addresses.

[0029] It should be noted that B1 n The driver module can allocate a corresponding memory address for each computational parameter based on the memory size required by the computational parameters and the current memory resources. The driver module can obtain all resource information of the current chip design under test, such as memory size, register type, engine resources, etc.

[0030] Steps S33 and B1 n Based on A n The corresponding operational parameters and A n The memory address allocated for the corresponding operation parameters generates A. n The corresponding register configuration instruction, namely A n The corresponding register configuration instruction includes A n The corresponding process group and its corresponding interaction identifier P n .

[0031] As one embodiment, step S4 includes:

[0032] Step S41: After the chip initialization operation is completed, B1 n A n The corresponding register configuration instruction is sent to B2 via the IPC interface. n .

[0033] It should be noted that after the chip design and initialization are completed, the chip can be accessed via B2. n With B1 n Interact with it.

[0034] Steps S42 and B2 n Based on A nThe corresponding register configuration instructions perform register configuration operations on the chip under test design.

[0035] It should be noted that B2 n B1 was received via the IPC interface. n Send A n The corresponding register configuration instruction. The original A n The corresponding register configuration instructions are generated based on the software language and cannot be directly executed on the chip under test design. Through language conversion, register configuration operations can be executed on the chip under test design.

[0036] Steps S43 and B1 n In A n After the corresponding register configuration instruction is executed, based on each A n The corresponding operation parameters and register configuration information generate A n The corresponding data transfer instructions are sent to B2 via the IPC interface. n A n The corresponding data transfer instructions include A n The corresponding process group and its corresponding interaction identifier P n .

[0037] It should be noted that after the registers are configured, each A needs to be... n The corresponding computational parameters are stored in the memory corresponding to the chip design under test, therefore it is necessary to base them on each A. n The corresponding operation parameters and register configuration information generate A n The corresponding data transfer instructions are sent to B2 via the IPC interface. n .

[0038] Steps S44 and B2 n Based on A n The corresponding data transfer instructions will be A in the design of the chip under test. n The corresponding computational parameters are stored in the memory corresponding to the design of the chip under test.

[0039] It should be noted that the original A n Corresponding data transfer instruction B2 n Based on software language generation, it cannot be directly executed on the chip under test design. Language conversion is used to enable the A... n The corresponding computational parameters are stored in the memory corresponding to the design of the chip under test.

[0040] Steps S45 and B1 n In A n After the corresponding data transfer instructions are executed, based on A n The corresponding operational logic generates An The corresponding doorbell command is sent to B2 via the IPC interface. n A n The corresponding doorbell commands include A n The corresponding process group and its corresponding interaction identifier P n .

[0041] Steps S46 and B2 n Based on A n The corresponding doorbell command and the A stored in the memory of the chip under test design n The corresponding operational parameters are executed in the chip design under test using A. n The corresponding operational logic generates A. n The results of the calculations performed on the chip design under test.

[0042] It should be noted that the original A n The corresponding doorbell commands are generated based on a software language and cannot be directly executed on the chip under test (DUT). Language conversion is used to enable execution of A commands on the DUT. n The corresponding operational logic.

[0043] As one embodiment, step S42 includes:

[0044] Steps S421 and B2 n Through the Direct Programming Interface (DPI), A n The corresponding register configuration instruction is converted to A n The corresponding SystemVerilog implementation of register configuration instructions.

[0045] DPI is a standard interface that allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages; therefore, it enables the conversion between software languages ​​and SystemVerilog, which will not be elaborated further here.

[0046] Steps S422 and B2 n Based on A n The corresponding SystemVerilog implementation of register configuration instructions performs register configuration operations on the chip under test design.

[0047] As one embodiment, step S44 includes:

[0048] Steps S441 and B2 n A through direct programming interface n The corresponding data transfer instructions are converted to A nThe corresponding SystemVerilog implementation of the data movement instructions.

[0049] Steps S442 and B2 n Based on A n The corresponding SystemVerilog implementation of data transfer instructions will be used in the design of the chip under test (DUT) to implement A. n The corresponding computational parameters are stored in the memory corresponding to the design of the chip under test.

[0050] As one embodiment, step S46 includes:

[0051] Steps S461 and B2 n A through direct programming interface n The corresponding doorbell command is converted into a SystemVerilog implementation of A. n The corresponding doorbell command.

[0052] Steps S462 and B2 n Based on A n The corresponding SystemVerilog implementation of the doorbell instruction and the A stored in the memory of the chip under test design. n The corresponding operational parameters are executed in the chip design under test using A. n The corresponding operational logic generates A. n The results of the calculations performed on the chip design under test.

[0053] It should be noted that the direct programming interface can convert instructions implemented in software languages ​​into SystemVerilog instructions that can be executed on the chip under test (DUT) design. Conversely, if the DUT design needs to generate instructions that are returned to B1... n The instructions, since the instructions of the chip under test are based on hardware language, also need to be converted into software language instructions through a direct programming interface before being passed to B1. n Software languages ​​can specifically include C, C++, etc.

[0054] B1 n Judge B2 n There are at least two ways to determine whether the corresponding operation has been completed:

[0055] Implementation Method 1

[0056] B1 n By obtaining B2 n The sent completion command determines whether the corresponding operation is completed. The completion command includes A. n The corresponding process group and its corresponding interaction identifier P nThe completion instructions are chip initialization completion instructions, register configuration completion instructions, and data transfer completion instructions. That is, B2. n After the operation is completed, a corresponding operation completion instruction is generated, which is then converted into a software language implementation instruction via a direct programming interface, and finally fed back to B1 via an IPC interface. n B1 n After receiving the completion instruction, determine B2. n The corresponding operation is complete, B1 n Continue with the subsequent instruction generation operation.

[0057] Implementation Method 2

[0058] Set the number of requests that can be sent in the IPC interface to 1, B1 n After the instructions are generated, they are stored in the IPC interface. When B2 n After retrieving the currently stored instructions from the IPC interface, B2 n Send the next instruction to the IPC interface.

[0059] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0060] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0061] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0062] This invention, based on dual-process communication, enables the verification of the chip design under test by directly running software test cases on the RTL code implementation. Furthermore, through multiple sets of parallel dual processes, the software test cases in the software test case set can be run in parallel on the chip design under test for verification without modifying the software test cases. This reduces the cost of cross-stage verification of software test cases and improves chip verification efficiency.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A hardware / software integration debugging method based on IPC, characterized in that, include: Step S1: Obtain a set of N software test cases {A1, A2, ..., A...} that need to be run in parallel on the chip design under test. n ,...,A N }, A n This is the nth software test case, where n ranges from 1 to N. The chip under test is designed based on RTL code implementation. Step S2, for each A n Assign the corresponding process group (B1) n B2 n ), B1 n For A n The corresponding first process, B2 n For A n The corresponding second process assigns a corresponding interaction identifier P to each process group based on the IPC protocol. n The IPC protocol is an inter-process communication protocol; Step S3: Start all B1 in parallel n Each B1 n Start executing the corresponding A n Simultaneously, the chip's RTL code performs chip initialization operations, B1 n Based on the corresponding A n Generate A n The corresponding register configuration instruction will trigger a wait state. Step S4: After the chip initialization operation is completed, B1 n B2 n Based on the corresponding P n To perform inter-process communication, A n Running on the chip design under test; Among them, B1 n A n The corresponding register configuration instructions, data transfer instructions, and doorbell instructions are sent to B2 via the IPC interface. n B2 n A through direct programming interface n The corresponding register configuration instructions, data transfer instructions, and doorbell instructions are converted to A. n The corresponding SystemVerilog implementations include register configuration instructions, data transfer instructions, and doorbell instructions.

2. The method according to claim 1, characterized in that, Step S3 includes: Steps S31 and B1 n Analysis of the corresponding A n , obtain A n The corresponding operation parameters and operation logic; Steps S32 and B1 n Obtain the memory information of the chip under test design, based on the memory information of the chip under test design as A. n The corresponding operation parameters are allocated memory addresses; Steps S33 and B1 n Based on A n The corresponding operational parameters and A n The memory address allocated for the corresponding operation parameters generates A. n The corresponding register configuration instruction, namely A n The corresponding register configuration instruction includes A n The corresponding process group and its corresponding interaction identifier P n .

3. The method according to claim 2, characterized in that, Step S4 includes: Step S41: After the chip initialization operation is completed, B1 n A n The corresponding register configuration instruction is sent to B2 via the IPC interface. n ; Steps S42 and B2 n Based on A n The corresponding register configuration instructions execute register configuration operations on the chip under test design; Steps S43 and B1 n In A n After the corresponding register configuration instruction is executed, based on each A n The corresponding operation parameters and register configuration information generate A n The corresponding data transfer instructions are sent to B2 via the IPC interface. n A n The corresponding data transfer instructions include A n The corresponding process group and its corresponding interaction identifier P n ; Steps S44 and B2 n Based on A n The corresponding data transfer instructions will be A in the design of the chip under test. n The corresponding computational parameters are stored in the memory corresponding to the design of the chip under test; Steps S45 and B1 n In A n After the corresponding data transfer instructions are executed, based on A n The corresponding operational logic generates A n The corresponding doorbell command is sent to B2 via the IPC interface. n A n The corresponding doorbell commands include A n The corresponding process group and its corresponding interaction identifier P n ; Steps S46 and B2 n Based on A n The corresponding doorbell command and the A stored in the memory of the chip under test design n The corresponding operational parameters are executed in the chip design under test using A. n The corresponding operational logic generates A. n The results of the calculations performed on the chip design under test.

4. The method according to claim 3, characterized in that, Step S42 includes: Steps S421 and B2 n A through direct programming interface n The corresponding register configuration instruction is converted to A n The corresponding SystemVerilog implementation of register configuration instructions; Steps S422 and B2 n Based on A n The corresponding SystemVerilog implementation of register configuration instructions performs register configuration operations on the chip under test design.

5. The method according to claim 3, characterized in that, Step S44 includes: Steps S441 and B2 n A through direct programming interface n The corresponding data transfer instructions are converted to A n The corresponding SystemVerilog implementation of the data transfer instructions; Steps S442 and B2 n Based on A n The corresponding SystemVerilog implementation of data transfer instructions will be used in the design of the chip under test (DUT) to implement A. n The corresponding computational parameters are stored in the memory corresponding to the design of the chip under test.

6. The method according to claim 3, characterized in that, Step S46 includes: Steps S461 and B2 n A through direct programming interface n The corresponding doorbell command is converted into a SystemVerilog implementation of A. n Corresponding doorbell commands; Steps S462 and B2 n Based on A n The corresponding SystemVerilog implementation of the doorbell instruction and the A stored in the memory of the chip under test design. n The corresponding operational parameters are executed in the chip design under test using A. n The corresponding operational logic generates A. n The results of the calculations performed on the chip design under test.

7. The method according to claim 3, characterized in that, B1 n By obtaining B2 n The sent completion command determines whether the corresponding operation has been completed. The completion command includes A. n The corresponding process group and its corresponding interaction identifier P n The completion instructions are: chip initialization operation completion instruction, register configuration completion instruction, and data transfer completion instruction.

8. The method according to claim 3, characterized in that, Set the number of requests that can be sent in the IPC interface to 1, B1 n After the instructions are generated, they are stored in the IPC interface. When B2 n After retrieving the currently stored instructions from the IPC interface, B2 n Send the next instruction to the IPC interface.

9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being configured to perform the method of any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-8.

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