Interrupt device and interrupt reporting method

Abstract

The invention provides an interrupt device and an interrupt reporting method. The device comprises a timer, an expiration register, at least one storage unit and an interrupt adjustment mechanism timing logic unit, the at least one storage unit is used for storing expiration trigger values and scanning timing values of all interrupt timing trigger events bound to an interrupt vector; the interrupt regulation mechanism timing logic unit is used for traversing and scanning the at least one storage unit once after the timing of the timer meets a scanning period, and adding 1 to the corresponding scanning timing value when the expiration trigger value of the interrupt timing trigger event is scanned to be greater than 0, so as to obtain the interrupt regulation mechanism timing logic unit. If the scanning timing value is equal to the expiration trigger value, setting a value in an expiration register corresponding to an interrupt timing trigger event as a first set value, so as to report an interrupt vector corresponding to the interrupt timing trigger event after the interrupt event arrives; the first set value indicates that the interrupt timing trigger event has expired.

Description

Technical Field

[0001] This application belongs to the field of network communication technologies, and particularly relates to an interrupt device and an interrupt reporting method. Background Art

[0002] A high-speed network card realizes data reception and transmission by reporting interrupts to a host. In the MSI-X (Message Signaled Interrupts eXtended, an interrupt mechanism in the PCI specification) in the MSI-X capability structure of the PCI configuration space, the number can reach thousands, and interrupts are triggered to the host in a serial manner of interrupt vectors. Summary of the Invention

[0003] The purpose of this application is to provide an interrupt device and an interrupt reporting method, aiming to solve the technical problems of an overly large register bit width of the expiration trigger value causing an overly large adapter area and relatively high requirements for middle and back-end timing convergence and layout routing.

[0004] According to the first aspect of this application, an interrupt device is provided, including: a timer, an expiration register, at least one storage unit, and an interrupt adjustment mechanism timing logic unit;

[0005] The at least one storage unit is used to store the expiration trigger values and scan timing values of all interrupt timing trigger events bound to the interrupt vector;

[0006] The interrupt adjustment mechanism timing logic unit is configured to traverse and scan the at least one storage unit once every time the timing of the timer satisfies a scan period, and when the expiration trigger value of the interrupt timing trigger event scanned is greater than 0, increment the corresponding scan timing value, and if the scan timing value is equal to the expiration trigger value, set the value in the expiration register corresponding to the interrupt timing trigger event to a first set value, so that after an interrupt event arrives, report the interrupt vector corresponding to the interrupt timing trigger event; the first set value indicates that the interrupt timing trigger event has expired.

[0007] In an optional implementation, after the interrupt adjustment mechanism timing logic unit sets the value in the expiration register to the first set value, it clears the corresponding scan timing value to 0.

[0008] In an alternative embodiment, when the interrupt adjustment mechanism timing logic unit performs subsequent traversal scans, if the value of the expiration register corresponding to the interrupt timing trigger event is the first set value and the corresponding scan timing value is 0, the scan timing value is not incremented. If the value of the expiration register corresponding to the interrupt timing trigger event changes to the second set value, the scan timing value continues to be incremented; the second set value indicates that the interrupt timing trigger event has not expired.

[0009] In an alternative embodiment, all of the interrupt timing trigger events share one timer; the bit width of the timer is greater than the maximum bit width among the scan timers of all of the interrupt timing trigger events.

[0010] In an alternative embodiment, the interrupt device further includes: an interrupt vector register, a mapping register, an interrupt source recording logic unit register, and an interrupt vector logic unit;

[0011] The interrupt vector register is used to store the interrupt enable signal of each interrupt vector;

[0012] The mapping register is used to store the interrupt vector number bound to each interrupt event and the index number of the interrupt timing trigger event;

[0013] After receiving an interrupt event, query the interrupt vector number bound to the interrupt event and the index number of the interrupt timing trigger event from the mapping register, and record the interrupt vector number and the index number of the interrupt timing trigger event in the interrupt source recording logic unit register;

[0014] The interrupt vector logic unit is used to report the interrupt vector corresponding to the interrupt timing trigger event to the host when the value of the expiration register of the interrupt timing trigger event is the first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the interrupt source recording logic unit register records the index number of the interrupt timing trigger event and the corresponding interrupt vector number.

[0015] In an alternative embodiment, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the interrupt adjustment mechanism timing logic unit sets the values in the expiration registers of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0016] According to a second aspect of the present application, there is provided an interrupt reporting method, including:

[0017] After it is detected that the timing of the timer of the interrupt device reaches one scan cycle, trigger the interrupt adjustment mechanism of the interrupt device, and the timing logic unit scans at least one storage unit of the interrupt device; the at least one storage unit stores the expiration trigger values of all interrupt timing trigger events bound to the interrupt vector and the scan timing values;

[0018] If the expiration trigger value of one of the interrupt timing trigger events is greater than 0 during the scan, increment the corresponding scan timing value by 1;

[0019] If the scan timing value is equal to the expiration trigger value, set the value in the expiration register corresponding to the interrupt timing trigger event to a first set value, so that after the interrupt event arrives, report the interrupt vector corresponding to the interrupt timing trigger event; the first set value indicates that the interrupt timing trigger event has expired.

[0020] In an alternative embodiment, after setting the value in the expiration register corresponding to the interrupt timing trigger event to the first set value, the method further includes:

[0021] The interrupt adjustment mechanism timing logic unit clears the scan timing value corresponding to the interrupt timing trigger event to 0.

[0022] In an alternative embodiment, in the next scan cycle, the method further includes:

[0023] If the value in the expiration register corresponding to the interrupt timing trigger event is the first set value and the corresponding scan timing value is 0, the interrupt adjustment mechanism timing logic unit does not increment the scan timing value. If the value in the expiration register corresponding to the interrupt timing trigger event becomes a second set value, continue to increment the scan timing value; the second set value indicates that the interrupt timing trigger event has not expired.

[0024] In an alternative embodiment, all the interrupt timing trigger events share the timer; the bit width of the timer is greater than the maximum bit width among the scan timers of all the interrupt timing trigger events.

[0025] In an alternative embodiment, the method further includes:

[0026] After receiving an interrupt event, query the interrupt vector number and the index number of the interrupt timing trigger event bound to the interrupt event from the mapping register of the interrupt device, and record the interrupt vector number and the index number of the interrupt timing trigger event in the interrupt source record logic unit register of the interrupt device;

[0027] When the interrupt vector logic unit of the interrupt device detects that the value of the expiration register of the interrupt timing trigger event is the first set value, and the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the interrupt source recording logic unit register records the index number of the interrupt timing trigger event and the corresponding interrupt vector number, the interrupt vector corresponding to the interrupt timing trigger event is reported to the host.

[0028] In an alternative embodiment, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the method further includes:

[0029] The interrupt adjustment mechanism timing logic unit sets the values in the expiration registers of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0030] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0031] As the demand for the number of ITRs or the number of interrupt vectors of high-speed network cards increases, the number of expiration trigger values of ITRs also increases accordingly. If registers are used to store the ITR expiration trigger values, assuming there are 2k interrupt vectors and 3 ITRs sharing the same interrupt vector, and all ITRs share a 16-bit timer, then the total bit width of the ITR trigger values is nearly 10k for 2k×3×16. As the demand for the number of ITRs for the same interrupt vector increases, the total bit width of the ITR trigger values will far exceed 10k. The huge register bit width will pose a great challenge to the adapter area. Using the present application can greatly reduce the adapter area; in addition, using the method of the present application can reduce the chip occupied resources and power consumption, which can be observed through the number of instances after synthesis, and is beneficial to the timing convergence and wiring of the middle and back ends.

[0032] Other features and advantages of the present application will be described in the following specification, and will be partially obvious from the specification, or will be understood by implementing the present application. The objectives and other advantages of the present application can be realized and obtained through the structures and processes pointed out in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 It is a structural block diagram of an interrupt device according to an exemplary embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of a storage unit storing data according to an exemplary embodiment of the present application.

[0036] Figure 3A It is a schematic diagram of the scanning effect of a storage unit according to an exemplary embodiment of the present application.

[0037] Figure 3B It is a schematic diagram of the scanning state of a storage unit according to an exemplary embodiment of the present application.

[0038] Figure 4 It is a schematic diagram of the system structure for an interrupt vector to report to a host according to an exemplary embodiment of the present application.

[0039] Figure 5 It is a schematic diagram of the process of an interrupt reporting method according to an exemplary embodiment of the present application. Detailed implementation manners

[0040] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0041] In a high-speed network card, multiple ITRs (Interrupt throttling) share the same interrupt vector. All ITRs will be timed separately, and each ITR corresponds to a separate ITR expiration trigger value, and parallel timing is implemented by storing in registers.

[0042] The timing of all ITRs (assuming a total of N) sharing the same interrupt vector is implemented by sharing a single timer (with a bit width of M). The expiration trigger value for each ITR is: expiration trigger value = current timer value + (ITR interval × time granularity). ITR interval × time granularity is the timing time of the ITR. Therefore, the total bit width of the registers for the expiration trigger values of all ITRs is N × M. When the value of the timer is equal to the ITR expiration trigger value, the ITR expires.

[0043] The following problems exist in the above related technologies:

[0044] As the demand for the number of ITRs or the number of interrupt vectors in high-speed network cards increases, the number of expiration trigger values of ITRs also increases. If registers are used to store ITR expiration trigger values, for example: if there are 2k interrupt vectors and 3 ITRs share the same interrupt vector, then the common timer for all ITRs is 16 bits. So the total bit width of ITR expiration trigger values is 2k × 3 × 16, approaching 10k in size. As the demand for the number of ITRs sharing the same interrupt vector increases, the total bit width of ITR expiration trigger values will exceed 10k. The huge register bit width of expiration trigger values will pose a great challenge to the adapter area. At the same time, the sharp increase in the number of ITRs, bringing huge bit width of ITR expiration trigger value registers, will also pose a great challenge to the timing convergence and layout routing of the middle and back ends.

[0045] Therefore, this application proposes a solution to store ITR-related information using RAM. In this solution, each ITR no longer depends on the ITR expiration trigger value and the value of the current timer to determine whether the ITR has expired. The RAM is scanned and read once every tus. When the scanned timing value interval cnt of the ITR read during the scan is the expiration trigger value ITR interval, it means that the ITR has expired. At this time, the hardware clears the interval cnt of this ITR to 0 and sets the expiration flag ITR_time_out in the ITR expiration register to 1. During subsequent scan reads, when the interval cnt of this ITR is read as 0, if ITR_time_out is 1, it means that the ITR is currently in the expired state waiting for an interrupt event, and no increment operation is performed on the interval cnt of this ITR. If ITR_time_out is 0, it means that the interrupt has been reported and re-timing is required, and the increment operation on the interval cnt of this ITR starts again.

[0046] Since all ITRs share a single timer and the bit width of the timer depends on the maximum ITR interval value corresponding to all ITRs, the value of the timer must be greater than the maximum ITR interval value × time granularity. Then the bit width of the timer must be greater than the maximum bit width of the ITR interval cnt value. Suppose the total storage bit width of the ITR (N) interval cnt values of all interrupt vectors is W, and the bit width of the timer for timing N ITR interval values is M. Then the total storage bit width of the ITR interval cnt value and the ITR interval value in the related art is W + N × M. After replacing the register with RAM in this application, the actual bit width is: 2W. Since 2W << W + N × M, this application significantly and effectively reduces the adapter area.

[0047] As Figure 1As shown, the present application exemplarily proposes an interrupt device, including: a timer, an expiration register, at least one storage unit, and an interrupt adjustment mechanism timing logic unit;

[0048] The at least one storage unit is used to store the expiration trigger values and scan timing values of all interrupt timing trigger events bound to the interrupt vector;

[0049] The interrupt adjustment mechanism timing logic unit is used to traverse and scan the at least one storage unit once every time the timer's timing meets a scan period, and when the expiration trigger value of the interrupt timing trigger event scanned is greater than 0, increment the corresponding scan timing value by 1, and if the scan timing value is equal to the expiration trigger value, set the value in the expiration register corresponding to the interrupt timing trigger event to a first set value, so that after the interrupt event arrives, report the interrupt vector corresponding to the interrupt timing trigger event; the first set value indicates that the interrupt timing trigger event has expired.

[0050] Exemplarily, all interrupt timing trigger events (for ease of understanding, described as ITR in the present application) of the interrupt device share a timer, and each interrupt timing trigger event corresponds to an expiration register for storing the value ITR_time_out indicating whether the interrupt timing trigger event has expired. When the ITR_time_out is a first set value such as 1, it indicates that the ITR has expired, and when the ITR_time_out is a second set value such as 0, it indicates that the ITR has not expired.

[0051] Exemplarily, one interrupt vector can be bound to one or more interrupt timing trigger events, and each interrupt timing trigger event corresponds to an expiration trigger value ITR interval and a scan timing value ITR interval cnt. A storage unit RAM can store the expiration trigger values ITR interval and scan timing values ITR interval cnt of all interrupt timing trigger events bound to one interrupt vector.

[0052] Exemplarily, every tus (i.e., a scan cycle, also referred to as a time granularity) the timer counts, the timing logic unit of the interrupt adjustment mechanism scans and reads the storage unit once. After the next scan cycle arrives, the timing logic unit of the interrupt adjustment mechanism continues with the next scan read operation. During a scan read operation, if the expiration trigger value of the interrupt timing trigger event scanned is greater than 0, the scan timing value of the interrupt timing trigger event (the initial value of the scan timing value is 0) is incremented by 1. After the increment, if the scan timing value is equal to the expiration trigger value, it indicates that the interrupt timing trigger event has expired. At this time, the value in the expiration register corresponding to the interrupt timing trigger event can be set to a first set value, such as 1. In this way, when the corresponding hardware detects that the value bit in the expiration register is the first set value, it can determine that the corresponding interrupt timing trigger event has expired, and thus can determine whether to report the interrupt vector corresponding to the interrupt timing trigger event by determining whether the corresponding interrupt event has arrived, etc.

[0053] In some alternative embodiments, after the timing logic unit of the interrupt adjustment mechanism sets the value in the expiration register to the first set value, it clears the corresponding scan timing value to 0.

[0054] Exemplarily, after the value in the expiration register is set to the first set value, it indicates that the interrupt timing trigger event has expired, and then the timing can start anew. Therefore, the scan timing value can be cleared to 0.

[0055] In some alternative embodiments, during subsequent traversal scans, if the value in the expiration register corresponding to the interrupt timing trigger event is the first set value and the corresponding scan timing value is 0, the scan timing value is not incremented. If the value in the expiration register corresponding to the interrupt timing trigger event changes to a second set value, the scan timing value continues to be incremented; the second set value indicates that the interrupt timing trigger event has not expired.

[0056] Exemplarily, after each scan cycle arrives, the timing logic unit of the interrupt adjustment mechanism scans and reads the storage unit once. During the scan read process, if the value in the expiration register of a certain interrupt timing trigger event is set to the first set value and the scan timing value is cleared to 0, it indicates that the interrupt timing trigger event has expired and is in a state of waiting for the corresponding interrupt event to arrive. At this time, the timing can be stopped, so the scan timing value is not incremented. If the value in the expiration register corresponding to the interrupt timing trigger event changes back from the first set value to the second set value, it means that the interrupt event corresponding to the interrupt timing trigger event has arrived and has been reported. At this time, the timing can start anew, so the scan timing value can start to be incremented.

[0057] In some alternative embodiments, all the interrupt timing trigger events share a single timer; the bit width of the timer is greater than the maximum bit width among the scan timers of all the interrupt timing trigger events.

[0058] As described above, only one timer can be set in the present application for timing the scan cycle, and there is no need to set a timer separately for each interrupt timing trigger event.

[0059] Taking the process of reporting an interrupt to the host by the interrupt vector as an example, the embodiments of the present application will be described below.

[0060] As Figure 2 shown, exemplarily, itr0 to itrN-1 are N interrupt timing trigger events ITRs bound to an interrupt vector, intrl cnt and intrl are the scan timing values ITRinterval cnt and the expiration trigger value ITR interval corresponding to each interrupt timing trigger event ITR, respectively.

[0061] Exemplarily, Figure 2 the data stored in each RAM storage unit shown contains all ITRinterval values (expiration trigger values) sharing the interrupt vector and the scan timing value intervalcnt corresponding to each ITR, and the bit width of the intervalcnt value of each ITR is the same as that of the interval value.

[0062] As Figure 3A shown, exemplarily, the ordinate is the timing value of the timer shared by all ITRs. This timer increments by 1 every 1 us and performs a read / write scan on all ITR RAMs within every tus range. All RAM addresses correspond to the interrupt vector numbers. If there are too many interrupt vector numbers, it may not be possible to traverse and scan-read / write the entire RAM within the time granularity of tus. Therefore, it is necessary to split the RAM depth, that is, split it into multiple RAMs, so that each RAM can be parallel-read / write scanned once within tus. Since each ITR interval value stored in the RAM needs to be opened for software read / write access, in addition to the above traversal scan read / write, the RAM also involves software read / write access. As Figure 3B shown, exemplarily, the traversal scan read operation of the RAM and the software read / write access operation can be completed in an interleaved manner within the tus time. The specific number of interleaved beats can be set according to actual needs, and the present application does not limit this. As long as it is ensured that the RAM is traversed, scanned, read, and written within tus.

[0063] The time granularity tus serves as the scanning period for reading the RAM in a scanning manner. It performs an alternate-shot parallel traversal scan read on all the split RAMs. When the ITR interval stored at a certain address is read during the scan and is greater than 0, the corresponding ITR interval cnt is incremented by 1 and then rewritten to the same address in the RAM. The adjacent shots of the traversal scan read serve as the ITR interval clock signal for software reading and writing access to the RAM. When the software initiates a read request, only the value of the ITR interval is returned to the software. When the software initiates a write access, the hardware writes the value of the ITR interval carried by the write access to the specified data bit field of the RAM. Each ITR no longer depends on the expiration trigger value of the ITR and the current timer value to determine whether the ITR has expired. The RAM is traversed and scanned once every tus. When the ITR interval cnt value of the ITR read during the scan is equal to the ITR interval, it represents that the ITR has expired. The timing logic unit of the interrupt adjustment mechanism clears the ITR interval cnt to 0 and sets the value ITR_time_out stored in the ITR expiration register to 1. During subsequent scan reads, when the interval cnt of the ITR is read as 0, if ITR_time_out is 1, the increment operation is not performed, indicating that the ITR is currently in the expired state waiting for an interrupt event. If ITR_time_out is 0, the increment operation continues, indicating that the interrupt vector has been reported and re-timing is required.

[0064] All ITRs share a single timer. The bit width of the timer depends on the maximum ITR interval value. Therefore, the value of the timer must be greater than the maximum ITR interval value × the time granularity. Then the bit width of the timer must be greater than the ITR with the maximum bit width. Suppose the total storage bit width of the ITR (N) interval cnt values of all interrupt vectors is W, and the bit width of the timer used to time the N ITR interval values is M. Then in the related art, the total storage bit width of the ITR interval cnt value and the ITR interval value is W + N×M. However, in this application, after replacing the register with a RAM, the actual bit width is: 2W. Since 2W << W + N×M, this application significantly and effectively reduces the adapter area.

[0065] In some alternative embodiments, the interrupt device further includes: an interrupt vector register, a mapping register, an interrupt source recording logic unit register, and an interrupt vector logic unit;

[0066] The interrupt vector register is used to store the interrupt enable signal of each interrupt vector;

[0067] The mapping register is used to store the interrupt vector number bound to each interrupt event and the index number of the interrupt timing trigger event;

[0068] After receiving an interrupt event, query the interrupt vector number bound to the interrupt event and the index number of the interrupt timing trigger event from the mapping register, and record the interrupt vector number and the index number of the interrupt timing trigger event in the interrupt source record logic unit register;

[0069] The interrupt vector logic unit is used to report the interrupt vector corresponding to the interrupt timing trigger event to the host when the value of the expiration register of the interrupt timing trigger event is the first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register.

[0070] Exemplarily, Figure 4 The figure shows an example structure in which the interrupt vector of the interrupt device reports an interrupt request to the host. 101 is the interrupt vector register, which is used to receive and store the interrupt vector enable signal configured by software. Only when the interrupt vector enable signal is 1 can the condition for reporting the interrupt request be met. Each interrupt vector corresponds to an interrupt vector register. 102 is the interrupt adjustment mechanism timing logic unit, and its implementation function is shown in Figure 2 , Figure 3A , Figure 3B as shown.

[0071] 103 is the mapping register, which is used to store the interrupt vector number msix ind and the ITR index identifier ITR indx bound to each interrupt event. After the interrupt event occurs, the mapping register will first query the content of the mapping register pre-bound to the interrupt event to determine the interrupt vector number msix ind and the ITR index identifier indx bound to the interrupt event.

[0072] Exemplarily, 104 is the interrupt source recording logic unit register of the interrupt vector, which is used to store the interrupt vector number msix indx and the ITR index identifier indx bound to the received interrupt event. The bit width of each interrupt vector is consistent with the number of ITRs bound to the interrupt vector, that is, eicr[N-1:0]. After receiving an interrupt event, the interrupt device reads the mapping register 103 bound to the interrupt event to obtain the ITR indx and msix indx bound to the interrupt event. If there are M interrupt vectors in total, and each interrupt vector corresponds to N ITRs, then the M interrupt vectors are represented as eicr[M-1:0][N-1:0]. If the ITR indx is 1 and the interrupt vector number msix indx is 0, then the interrupt vector eicr[M-1:0][N-1:0]UI corresponds to N’h1. 106 is the interrupt vector logic unit. After each interrupt vector meets the following three conditions, it will send the interrupt vector to the host to report the corresponding interrupt request:

[0073] 1) The interrupt enable signal of the interrupt vector register 101 of the software interrupt vector is 1;

[0074] 2) The value of the expiration register of the ITR bound to the interrupt vector is the first set value, such as 1;

[0075] 3) The interrupt event bound to the interrupt vector is recorded in the interrupt source recording logic unit register, and the ITR indx bound to the interrupt event is 1.

[0076] When the above three conditions are met, the interrupt vector logic unit 105 sends the interrupt vector to the host. After sending, the interrupt adjustment mechanism timing logic unit clears the ITR_time_out of all ITRs corresponding to the interrupt vector, that is, sets the ITR_time_out corresponding to the interrupt vector to the second set value, such as 0.

[0077] Therefore, in some embodiments, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the interrupt adjustment mechanism timing logic unit sets the values in the expiration registers of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0078] Exemplarily, after the value in the expiration register returns to the second set value, the interrupt adjustment mechanism timing logic unit can continue to increment the scan timing value corresponding to the interrupt timing trigger event by 1 in subsequent scans.

[0079] The above-mentioned interrupt device proposed by this application has at least the following advantages:

[0080] As the demand for the number of ITRs or the number of interrupt vectors in high-speed network cards increases, the number of expiration trigger values of ITRs also increases. If registers are used to store the ITR expiration trigger values, assuming there are 2k interrupt vectors and 3 ITRs share the same interrupt vector, and all ITRs share a 16-bit timer, then the total bit width of the ITR trigger values is nearly 10k for 2k×3×16. As the demand for the number of ITRs with the same interrupt vector increases, the total bit width of the ITR trigger values will far exceed 10k. The huge register bit width will pose a great challenge to the adapter area. Using the present application can greatly reduce the adapter area; in addition, the method of the present application can reduce the chip occupied resources and power consumption, which can be observed through the number of instances after synthesis, and is beneficial to the timing convergence and routing in the middle and back ends.

[0081] Correspondingly, as Figure 5 shown, the present application exemplarily further provides an interrupt reporting method, including:

[0082] In step S501, after detecting that the timing of the timer of the interrupt device reaches a scan cycle, trigger the interrupt adjustment mechanism timing logic unit of the interrupt device to scan at least one storage unit of the interrupt device; the at least one storage unit stores the expiration trigger values and scan timing values of all interrupt timing trigger events bound to the interrupt vector;

[0083] In step S502, if the expiration trigger value of one of the interrupt timing trigger events is scanned to be greater than 0, increment the corresponding scan timing value by 1;

[0084] In step S503, if the scan timing value is equal to the expiration trigger value, set the value in the expiration register corresponding to the interrupt timing trigger event to a first set value, so that after the interrupt event arrives, report the interrupt vector corresponding to the interrupt timing trigger event; the first set value indicates that the interrupt timing trigger event has expired.

[0085] In some optional embodiments, after setting the value in the expiration register corresponding to the interrupt timing trigger event to the first set value, the method further includes:

[0086] The interrupt adjustment mechanism timing logic unit clears the scan timing value corresponding to the interrupt timing trigger event to 0.

[0087] In some optional embodiments, in the next scan cycle, the method further includes:

[0088] If the value of the expiration register corresponding to the interrupt timing trigger event is the first set value and the corresponding scan timing value is 0, the timing logic unit of the interrupt adjustment mechanism does not increment the scan timing value. If the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value, the scan timing value continues to be incremented; the second set value indicates that the interrupt timing trigger event has not expired.

[0089] In some alternative embodiments, all interrupt timing trigger events share a timer; the bit width of the timer is greater than the maximum bit width in the scan timers of all interrupt timing trigger events.

[0090] In some alternative embodiments, the method further includes:

[0091] After receiving an interrupt event, query the interrupt vector number bound to the interrupt event and the index number of the interrupt timing trigger event from the mapping register of the interrupt device, and record the interrupt vector number and the index number of the interrupt timing trigger event in the register of the interrupt source recording logic unit of the interrupt device;

[0092] When the interrupt vector logic unit of the interrupt device detects that the value of the expiration register of the interrupt timing trigger event is the first set value, and the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the register of the interrupt source recording logic unit records the index number of the interrupt timing trigger event and the corresponding interrupt vector number, report the interrupt vector corresponding to the interrupt timing trigger event to the host.

[0093] In some alternative embodiments, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the method further includes:

[0094] The timing logic unit of the interrupt adjustment mechanism sets the values in the expiration registers of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0095] The above method can be implemented on the interrupt device provided in the above embodiments. For the specific implementation method, reference can be made to the description of the interrupt device in the above embodiments, which will not be elaborated here.

[0096] It can be understood that the circuit structures, names, and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the usage needs, and should not limit the concept of the present application to the specific details of the above examples.

[0097] Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An interruption device, characterized in that: include: a timer, an expiration register, at least one storage unit, and an interrupt regulation mechanism timing logic unit; The at least one storage unit is used to store the expiration trigger value and the scan timing value of all interrupt timing trigger events bound to the interrupt vector; The interrupt regulation mechanism timing logic unit is used to traverse and scan the at least one storage unit every time the timing of the timer satisfies a scanning cycle, and when the expiration trigger value of the interrupt timing trigger event is scanned to be greater than 0, the corresponding scanning timing value is increased by 1, and if the scanning timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set to a first set value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported; the first set value indicates that the interrupt timing trigger event has expired.

2. The interruption device according to claim 1, characterized in that: The interrupt regulation mechanism timing logic unit clears the corresponding scan timing value to 0 after setting the value in the expiration register to the first set value.

3. The interruption device according to claim 1, characterized in that: When the interrupt regulation mechanism timing logic unit performs subsequent traversal scanning, if the value of the expiration register corresponding to the interrupt timing trigger event is the first set value and the corresponding scan timing value is 0, the scan timing value is not added by 1; if the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value, the scan timing value continues to be added by 1; the second set value indicates that the interrupt timing trigger event has not expired.

4. The interruption device according to claim 1, characterized in that: All the interrupt timing triggering events share one timer; the bit width of the timer is greater than the maximum bit width of the scanning timers of all the interrupt timing triggering events.

5. The interruption device according to any one of claims 1 to 4, characterized in that: The interrupt device further comprises: an interrupt vector register, a mapping register, an interrupt source recording logic unit register and an interrupt vector logic unit; The interrupt vector register is used to store an interrupt enable signal of each interrupt vector; The mapping register is used to store the interrupt vector number bound to each interrupt event and the index number of the interrupt timing trigger event; After receiving an interrupt event, query the interrupt vector number bound to the interrupt event and the index number of the interrupt timing trigger event from the mapping register, and record the interrupt vector number and the index number of the interrupt timing trigger event in the interrupt source recording logic unit register; The interrupt vector logic unit is used to report the interrupt vector corresponding to the interrupt timing trigger event to the host when the value of the expiration register of the interrupt timing trigger event is a first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the register of the interrupt source recording logic unit.

6. The interruption device according to claim 5, characterized in that: After reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the interrupt regulation mechanism timing logic unit sets the value in the expiration register of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

7. A method for reporting an interruption, characterized in that: include: After detecting that the timing of the timer of the interrupt device reaches a scanning cycle, triggering the interrupt adjustment mechanism timing logic unit of the interrupt device to scan at least one storage unit of the interrupt device; the at least one storage unit stores the expiration trigger value and the scan timing value of all interrupt timing trigger events bound to the interrupt vector; If the expiration trigger value of one of the interrupt timing trigger events is greater than 0, the corresponding scanning timing value is increased by 1; If the scan timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set to a first set value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported; the first set value indicates that the interrupt timing trigger event has expired.

8. The interruption reporting method according to claim 7, characterized in that: After setting the value in the expiration register corresponding to the interrupt timing trigger event to a first set value, the method further includes: The interrupt regulation mechanism timing logic unit clears the scan timing value corresponding to the interrupt timing triggering event to 0.

9. The interruption reporting method according to claim 7, characterized in that: In the next scanning cycle, the method further includes: If the value of the expiration register corresponding to the interrupt timing trigger event is the first set value, and the corresponding scan timing value is 0, the interrupt adjustment mechanism timing logic unit does not add 1 to the scan timing value; if the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value, the scan timing value continues to be added by 1; the second set value indicates that the interrupt timing trigger event has not expired.

10. The interruption reporting method according to claim 7, characterized in that: All the interrupt timing triggering events share the timer: the bit width of the timer is greater than the maximum bit width of the scanning timers of all the interrupt timing triggering events.

11. The interruption reporting method according to any one of claims 7 to 10, characterized in that: The method further comprises: After receiving an interrupt event, query the interrupt vector number bound to the interrupt event and the index number of the interrupt timing trigger event from the mapping register of the interrupt device, and record the interrupt vector number and the index number of the interrupt timing trigger event in the interrupt source recording logic unit register of the interrupt device; When the interrupt vector logic unit of the interrupt device detects that the value of the expiration register of the interrupt timing trigger event is a first set value, and the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the register of the interrupt source recording logic unit, the interrupt vector corresponding to the interrupt timing trigger event is reported to the host.

12. The interruption reporting method according to claim 11, characterized in that: After reporting the interrupt vector corresponding to the interrupt timing triggering event to the host, the method further includes: The interrupt regulation mechanism timing logic unit sets the value in the expiration register of all interrupt timing triggering events corresponding to the interrupt vector to a second set value.

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