Multi-chip integration system, chip and data processing system

Abstract

The invention discloses a multi-core-particle integration system, a chip and a data processing system, and the system comprises a plurality of computing power core particles, each computing power core particle is used for carrying out data calculation based on a corresponding preset calculation path; the management core particle is respectively connected with the plurality of computing power core particles through a plurality of di2die interfaces, the di2die interfaces are in one-to-one correspondence with the computing power core particles, and the di2die interfaces are used for receiving external input data and sending the external input data to at least one computing power core particle, so that the external input data are processed through the computing power core particles to obtain target output data, and the target output data are sent to the management core particle. And in the data processing process, performing data forwarding among the plurality of computing power core particles, so that each computing power core particle performs data calculation according to the corresponding preset calculation path. Therefore, according to the system, the management core particle and the multiple computing power core particles are connected through the di2die interface, so that the multi-computing power core particle integrated system is constructed, higher computing power is provided, and the requirement of a large computing power application scene is met.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a multi-die integrated system, a chip, and a data processing system. Background Art

[0002] With the rise of technologies such as artificial intelligence and cloud computing, the explosive growth of data volume, and the increasing demand for computing power, more computing resources are required to process more data and perform more operations. Further, hardware processors with larger scale and higher performance are needed to adapt to various rapidly developing and diverse application scenarios. However, current hardware processors cannot meet this rapidly growing demand in terms of performance and flexibility. Summary of the Invention

[0003] This application aims to at least partly solve one of the technical problems in the related art. To this end, the first object of this application is to propose a multi-die integrated system that connects a management die and multiple computing dies through die-to-die interfaces to construct a multi-computing die integrated system, thereby providing higher computing power to meet the requirements of large computing power application scenarios.

[0004] The second object of this application is to propose a chip.

[0005] The third object of this application is to propose a data processing system.

[0006] To achieve the above object, an embodiment of the first aspect of this application proposes a multi-die integrated system, which includes: multiple computing dies, each computing die is used to perform data calculation based on a corresponding pre-designed calculation path; a management die, the management die is respectively connected to the multiple computing dies through multiple die-to-die interfaces, and the die-to-die interfaces are in one-to-one correspondence with each computing die, and are used to receive external input data, and send the external input data to at least one computing die, so that the computing die processes the external input data to obtain target output data, and during the data processing process, forward data between the multiple computing dies, so that each computing die performs data calculation according to the corresponding pre-designed calculation path.

[0007] In the multi-die integrated system according to an embodiment of the present application, each computing die is used to perform data calculation based on a corresponding pre-designed computing path. The management die is respectively connected to multiple computing dies through a plurality of die-to-die interfaces, and the die-to-die interfaces correspond to each computing die one by one. The management die is used to receive external input data and send the external input data to at least one computing die, so that the computing die processes the external input data to obtain target output data, and during the data processing process, forward data between multiple computing dies, so that each computing die performs data calculation according to the corresponding pre-designed computing path. Thus, the system connects the management die and multiple computing dies through the die-to-die interface to construct a multi-computing die integrated system, thereby providing higher computing power to meet the requirements of large computing power application scenarios.

[0008] In addition, the multi-die integrated system according to the above embodiment of the present application may further have the following additional technical features:

[0009] According to an embodiment of the present application, the management die is further used to determine target configuration information based on the target computing requirement, and configure parameters for each computing die based on the target configuration information, so as to construct the corresponding pre-designed computing path for each computing die.

[0010] According to an embodiment of the present application, the die-to-die interface includes: a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) port and an RGMII (Reduced Gigabit Media Independent Interface, an interface standard for connecting the Ethernet MAC layer and the PHY layer) port, which are used for data transmission between the management die and the computing die; an I2C (Inter-Integrated Circuit, a two-wire serial bus for connecting a microcontroller and its peripheral devices) port and a GPIO (General-Purpose Input / Output, a digital circuit port whose input and output states can be controlled by software) port, which are used for communication connection between the management die and the computing die.

[0011] According to an embodiment of the present application, the management die sends a control signal and a register configuration signal to the computing die through the I2C port.

[0012] According to an embodiment of the present application, the management die performs two-way communication with the computing die through the GPIO port, and the management die sends an interrupt signal to the computing die through the GPIO port.

[0013] According to an embodiment of the present application, multiple computing dies and a management die are connected through a silicon interposer.

[0014] According to an embodiment of the present application, the management die is arranged in the middle of the silicon interposer, and multiple computing dies are arranged at both ends of the management die along a first direction and are arranged in sequence along a second direction on the same side, where the second direction is perpendicular to the first direction.

[0015] According to an embodiment of the present application, the multi-die integrated system further includes a memory, and the memory is connected to the management die.

[0016] To achieve the above object, an embodiment of the second aspect of the present application provides a chip including the above multi-die integrated system.

[0017] Based on the above multi-die integrated system, the chip according to the embodiment of the present application can provide higher computing power to meet the requirements of large computing power application scenarios.

[0018] To achieve the above object, an embodiment of the third aspect of the present application provides a data processing system including the above multi-die integrated system or the above chip.

[0019] Based on the above multi-die integrated system or the above chip, the data processing system according to the embodiment of the present application can improve the data processing speed to meet the requirements of large computing power application scenarios.

[0020] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the connection of the multi-die integrated system according to an embodiment of the present application;

[0022] Figure 2 Schematic diagram of the connection of the multi-die integrated system according to a specific embodiment of the present application.

[0023] Figure 3 Schematic diagram of the die-to-die interface according to an embodiment of the present application;

[0024] Figure 4 Schematic diagram of the layout of the multi-die integrated system according to an embodiment of the present application;

[0025] Figure 5 Schematic diagram of the connection of the multi-die integrated system according to another embodiment of the present application;

[0026] Figure 6 Schematic block diagram of the chip according to an embodiment of the present application;

[0027] Figure 7 A block diagram of a data processing system according to an embodiment of the present application;

[0028] Figure 8 A block diagram of a data processing system according to another embodiment of the present application. Detailed implementation manners

[0029] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation to the present application.

[0030] Multi-die integrated systems, chips, and data processing systems proposed in embodiments of the present application will be described below with reference to the accompanying drawings.

[0031] In the intelligent era, the amount of data has grown explosively, making the computing power of current chips seriously insufficient. The bottleneck of chip computing power stems from many new problems brought about when the size of silicon-based devices in the post-Moore era is reduced to near the physical limit. In order to pursue high computing power, it is necessary to increase the computing power by manufacturing large chips. However, large chips necessarily mean a decrease in yield and a significant increase in cost. Also, due to the limitation of Amdahl's law, the theoretical computing power growth rate of a single chip is less than the chip scale growth rate.

[0032] Currently, fields such as artificial intelligence and autonomous driving have a strong demand for high computing power and require more hardware resources to process more data and operations. However, the current hardware processors cannot adapt to this rapidly growing demand in terms of performance and flexibility. At the same time, due to the manufacturing process of a single large chip approaching the physical limit, it is difficult to continue to miniaturize the transistor plane, and the computing power of a single chip is difficult to further improve. In addition, for data bandwidth, the existing board-level array method cannot meet the high-speed data communication requirements of high-computing-power chips, and it is impossible to expand the cluster computing power through the array method.

[0033] To solve at least one of the above technical problems, the present application proposes a multi-die integrated system. In the multi-die integrated system, a management die is respectively connected to a plurality of computing dies through a plurality of die-to-die interfaces, and the die-to-die interfaces correspond to each computing die one by one. Each computing die performs data calculation based on a corresponding pre-designed calculation path. When the management die receives external input data, the management die sends the external input data to at least one computing die to process the external input data through the computing die to obtain target output data, and during the data processing process, data is forwarded between the plurality of computing dies so that each computing die performs data calculation according to the corresponding pre-designed calculation path. Thus, the system connects the management die and the plurality of computing dies through die-to-die interfaces to construct a multi-computing-die integrated system, thereby providing higher computing power to meet the requirements of large-computing-power application scenarios.

[0034] The following will Figures 1-5 describe the multi-die integrated system of the present application in detail with reference to the accompanying

[0035] As Figure 1 shown, the multi-die integrated system of an embodiment of the present application may include: a plurality of computing dies 10 and a management die 20. The management die 20 is respectively connected to the plurality of computing dies 10 through a plurality of die-to-die interfaces, and the die-to-die interfaces correspond to each computing die 10 one by one.

[0036] Among them, each computing die 10 is used to perform data calculation based on a corresponding pre-designed calculation path. The management die 20 is used to receive external input data and send the external input data to at least one computing die 10 to process the external input data through the computing die 10 to obtain target output data, and during the data processing process, data is forwarded between the plurality of computing dies 10 so that each computing die 10 performs data calculation according to the corresponding pre-designed calculation path.

[0037] Specifically, taking the autonomous driving scenario as an example, it is necessary to deploy neural network algorithms to detect and identify image and video data. For example, the recognition of vision technology in the field of autonomous driving mainly includes the following core scenarios: the recognition of radar cloud maps, the recognition of obstacles during driving, the recognition of driving areas, the recognition of traffic signs, and the recognition of optical flow. Therefore, there is a large computing power demand.

[0038] In the related art, autonomous driving technology mainly uses various deep neural networks as the technical support for environmental perception and decision-making functions. The chips that implement the autonomous driving function actually deploy a large number of neural network accelerators. In addition to meeting the system computing power requirements, it is also necessary to complete the overall control and intelligent scheduling of artificial intelligence algorithms to process the information fusion between different sensors. Therefore, an operating system for running task scheduling is required.

[0039] The multi-die integrated system of the embodiments of the present application includes a management die 20 and multiple computing dies 10. Each computing die 10 is connected to the management die 20 through a die-to-die (die refers to a die, and die-to-die refers to inter-die interconnection) interface for high-bandwidth data transmission and basic management scheduling. The pre-designed computing path is used to characterize the achievable computing process of the computing die 10, such as the neural network algorithm that the computing die 10 can implement.

[0040] Among them, the computing die 10 focuses on high-density high-computing power calculations. Each computing die 10 supports end-to-end high-performance computing of neural network algorithms and supports concurrent execution of multiple neural network algorithms to achieve collaborative computing of a series of neural network processing tasks in complex application scenarios, providing a complete computing platform for intelligent applications such as autonomous driving and natural language processing. Since the computing die 10 focuses on high-density computing power calculations, it has strong superiority in terms of computing speed and power consumption.

[0041] The management die 20 is mainly used to provide overall control and intelligent scheduling of algorithms for the computing die 10, including operating systems for running task scheduling, managing and scheduling the computing die 10, and being responsible for data transmission between dies. Taking the multi-die integrated system applied to image data processing as an example, the management die 20 is also used to receive image data from multiple camera channels, preprocess the received image data, and then send the preprocessed image data to the computing die 10 for calculation. In addition, it is also used to process the processing results, that is, the target output data, obtained by the computing die 10 based on artificial intelligence algorithms, and forward the processed target output data to external devices such as user terminals and cloud servers for display or further processing of the target output data through the external devices.

[0042] Taking the multi-die integrated system applied to image data processing, the structure is as Figure 1 shown, taking four computing dies 10 and one management die 20 as an example. Each die is connected through a die-to-die interface, and data transmission and scheduling management between dies are realized through the die-to-die interface. The computing die 10 is used to process data based on neural network algorithms. During the working process, the management die 20 receives image data from the camera module, preprocesses the image data required by the neural network algorithm, and then transmits the image data to the computing die 10 through the die-to-die interface. Through the cooperative application of multiple computing dies 10 during the calculation process, the neural network algorithm is accelerated, and the calculation results are returned to the management die 20. After the management die 20 post-processes the returned image data calculation results, the final algorithm results are obtained.

[0043] For example, assume that the four computing die 10 are die A, die B, die C, and die D respectively. Die A is configured with a pre-designed computing path A, die B is configured with a pre-designed computing path B, die C is configured with a pre-designed computing path C, and die D is configured with a pre-designed computing path D. Based on the computing requirements, the computing die 10 determines the processing process of the image data. Assume that the processing process of the image data is to first process the image data based on the pre-designed computing path A and the pre-designed computing path B respectively to obtain data A and data B, then the pre-designed computing path C processes data A and data B to obtain data C, and the pre-designed computing path D processes data C to obtain the target output data. Then, during the computing process, the management die 10 first sends the processed image data to die A and die B respectively, then forwards the data A and data B fed back by die A and die B to die C, and then forwards the data C calculated by die C to die D. The data calculated by die D is used as the target output data to complete the processing of the image data.

[0044] This embodiment constructs a multi-die integrated system based on the management die 20 and multiple computing die 10. Through the scheduling and management of the management die 20, the requirements of high computing power and flexibility can be taken into account simultaneously.

[0045] In an embodiment of the present application, the management die 20 is further configured to determine target configuration information based on the target computing requirements, and perform parameter configuration on each computing die 10 based on the target configuration information to construct the pre-designed computing path corresponding to each computing die.

[0046] Specifically, the management die 20 can perform computing task division on the target computing requirements based on the received target computing requirements and the feature information of each computing die 10 to generate the target configuration information corresponding to each computing die 10. The target configuration information may include the computing order, computing tasks, computing parameter coefficients, etc. of each computing die 10. Among them, the feature information of each computing die 10 may include the computing power of each computing die 10 to achieve the optimal computing task allocation. The parameters of the computing die 10 may include parameter information for computing, processing logic, etc.

[0047] That is to say, the management die 20 can perform parameter configuration on each computing die 10 according to the target computing requirements determined by the application scenario to construct the corresponding pre-designed computing path, meet the target computing requirements, thereby improving the application flexibility of the multi-die integrated system to adapt to various rapidly developing and diverse application scenarios.

[0048] Such as Figure 2 and Figure 3As shown, in an embodiment of the present application, the die-to-die interface includes: a PCIe port and an RGMII port, which are used to manage data transmission between die 20 and computing die 10; an I2C port and a GPIO port, which are used to manage the communication connection between die 20 and computing die 10.

[0049] Specifically, a system solution integrating a single management die 20 and multiple computing dies 10 is as Figure 2 shown. The die-to-die interface solution of the multi-die integrated system includes a PCIe port, an RGMII port, an I2C port, and a GPIO port. Among them, the PCIe port and the RGMII port are used to connect to a high-bandwidth data transmission bus, and the I2C port and the GPIO port are used to connect to the die control bus.

[0050] Furthermore, the PCIe port serves as the main data transmission port of the die-to-die interface and is used for high-bandwidth data transmission between dies. The management die 20 is in the RC mode (Root Complex mode, the master mode in the PCIe system), and the computing die 10 is in the EP mode (Endpoint mode, the terminal device mode in the PCIe system). The RGMII port serves as the auxiliary data transmission port of the die-to-die interface and is used for relatively high-bandwidth data transmission between dies. The I2C port and the GPIO port serve as the control interfaces of the die-to-die interface and are used for communication between dies, such as the communication transmission of control signals, terminal signals, configuration signals, etc.

[0051] In this multi-die integrated system, high-bandwidth data transmission between the management die 20 and the computing die 10 is the guarantee for the efficient execution of artificial intelligence algorithms. Considering that PCIe is a widely used high-speed serial expansion bus, which uses serial transmission and has a single-channel data transmission speed of up to multiple GT / s, it can be used as a high-speed data transmission interface between multi-dies; while RGMII, as an interface standard for the Ethernet physical layer, can provide a transmission bandwidth of 1 Gbps with 8 signal lines and does not require an additional PHY (Physical Layer), so it can be used as a data transmission interface for multi-die integration.

[0052] This embodiment uses PCIe / RGMII / I2C / GPIO as a group of die-to-die interfaces for management control and data transmission between dies to meet the high-bandwidth data transmission requirements. At the same time, because each port in the die-to-die interface is relatively mature, it can stably, efficiently, and conveniently integrate multiple functional chips into one, maximizing the reuse rate of hardware IP (Intellectual Property) and reducing the cost of repeated development.

[0053] In one embodiment of the present application, the management die 20 sends control signals and register configuration signals to the computing die 10 through the I2C port.

[0054] In one embodiment of the present application, the management die 20 performs bidirectional communication with the computing die 10 through the GPIO port, and the management die 20 sends interrupt signals to the computing die 10 through the GPIO port.

[0055] That is to say, the I2C port serves as the die-to-die control interface for control and register configuration between dies, with the advantages of low overhead and simple operation. The GPIO port is the die-to-die control interface for basic input / output communication, and can directly send signals and interrupts to each die. In addition, before the initialization of the PCIe and RGMII ports is completed and when transmitting data, relevant information of the die can be read through the control interface to configure the relevant registers of the die.

[0056] Thus, this embodiment proposes a die-to-die interface solution for the multi-die integrated system, forming a die-to-die interface standard for the die integrated interconnection interface for efficient data transmission and control between dies. Among them, PCIe and RGMII in the die-to-die interface are used for high-bandwidth data transmission bus connection ports, and I2C and GPIO are used for die control bus connection ports.

[0057] As Figure 4 shown, in one embodiment of the present application, multiple computing dies 10 and the management die 20 are connected through the silicon interposer 40.

[0058] Specifically, for data bandwidth, the existing board-level array method cannot meet the high-speed data communication requirements of high-computing power chips, and the cluster computing power cannot be expanded through the array method. To solve this technical problem, the present application integrates the computing die 10 and the management die 20 together onto the silicon interposer 40 through 2.5D packaging technology, shortening the distance in the physical space to achieve an increase in the transmission data bandwidth. The multi-die integrated system connects various different dies through the silicon interposer 40, and finally packages the silicon interposer 40 into a complete chip through an organic substrate.

[0059] In this embodiment, the silicon interposer 40 provides high-density, high-bandwidth, and high-reliability interconnection for the dies, constructing the complete functions of a large chip. On the one hand, the manufacturing cost is reduced by the mixed application of advanced nodes and mature nodes, and on the other hand, the development speed of application-specific chips for actual applications is also improved, thus meeting the requirements of high-computing power chips.

[0060] In one embodiment of the present application, the management die 20 is arranged in the middle of the silicon interposer, and a plurality of computing dies 10 are arranged at both ends of the management die 20 along a first direction, and the plurality of computing dies 10 on the same side are arranged in sequence along a second direction, wherein the second direction is perpendicular to the first direction.

[0061] That is to say, the management die 20 is located in the middle of the silicon interposer to run the operating system of the entire chip and provide scheduling and management for the plurality of computing dies 10. The plurality of computing dies 10 are placed on the upper and lower sides of the silicon interposer to execute artificial intelligence algorithms and provide high-density large computing power. Through this layout method, the distance between the computing die 10 and the management die 20 is physically shortened, and the transmission data bandwidth is increased.

[0062] Combined with Figure 5 As shown, in one embodiment of the present application, the multi-die integrated system further includes a memory 30, and the memory 30 is connected to the management die 20.

[0063] Specifically, the memory 30 is used for data storage, such as storing target configuration information corresponding to target computing requirements, intermediate data obtained by calculation, system configuration data, characteristic information of each die, etc. DRAM (Dynamic Random Access Memory) can be used as the memory 30. Combined with the attached Figure 4 As shown, integrating the memory 30 on the silicon interposer 40 reduces data access latency, can improve the system operating frequency to a certain extent, and brings a comprehensive improvement in computing performance.

[0064] Exemplarily, the computing die 10, the management die 20, and the memory 30 are integrated onto the silicon interposer together through 2.5D packaging technology, shortening the distance between the computing die 10, the management die 20, and the memory 30 in physical space, and increasing the transmission data bandwidth.

[0065] In addition, the multi-die integrated system connects various different dies through the silicon interposer 40, and finally packages the silicon interposer 40 through an organic substrate into a complete chip, providing the necessary high-speed, high-bandwidth, and high-reliability interconnection capabilities for the computing chip, and realizing the construction of a large-scale integrated circuit system with multi-functional integration.

[0066] As a specific embodiment of the present application, the multi-die integrated system is as Figure 4As shown, heterogeneous integration of multiple chips with different materials, functions, and process nodes is achieved to obtain improvements in system-level integration and performance. The silicon interposer 40 provides high-density, high-bandwidth, and high-reliability interconnections for the chiplets, constructing the complete functions of the large chip. On the one hand, the manufacturing cost is reduced through the hybrid application of advanced nodes and mature nodes. On the other hand, the development speed of application-specific chips for actual applications is also increased, thus meeting the requirements of high-computing-power chips.

[0067] In addition, the ports in the die-to-die interface of this multi-chiplet integration system are interfaces commonly used in the industry, and there is no need to design dedicated circuits specifically for die-to-die interconnection. At the same time, because each port of the die-to-die interface is relatively mature, multiple functional chips can be stably, efficiently, and conveniently integrated into one, maximizing the reuse rate of hardware IP and reducing the cost of repeated development.

[0068] In the post-Moore era, when it is difficult to continue improving the performance of a single chip through advanced processes for high-computing-power chips, the overall performance at the system level is improved through flexible multi-chiplet integration design. On the other hand, it can provide higher communication bandwidth between processors and accelerators, and between processors and memories, significantly reducing the access overhead of data between different processors and memories, and thus alleviating the problems of memory wall, power wall, and I / O wall brought by the von Neumann architecture bottleneck.

[0069] In summary, for the multi-chiplet integration system according to the embodiments of the present application, each computing power chiplet is used to perform data calculation based on the corresponding pre-designed computing path. The management chiplet is respectively connected to multiple computing power chiplets through multiple die-to-die interfaces, and the die-to-die interface corresponds to each computing power chiplet one by one. The management chiplet is used to receive external input data and send the external input data to at least one computing power chiplet, so as to perform data processing on the external input data through the computing power chiplet to obtain target output data, and during the data processing process, forward data between multiple computing power chiplets, so that each computing power chiplet performs data calculation according to the corresponding pre-designed computing path. Thus, this system connects the management chiplet and multiple computing power chiplets through the die-to-die interface to construct a multi-computing power chiplet integration system, thereby providing higher computing power and meeting the requirements of large-computing-power application scenarios.

[0070] Corresponding to the above embodiments, the present application also proposes a chip.

[0071] As Figure 6 shown, the chip 200 according to the embodiments of the present application includes the above multi-chiplet integration system 100.

[0072] Based on the above multi-chiplet integration system, the chip according to the embodiments of the present application can provide higher computing power and meet the requirements of large-computing-power application scenarios.

[0073] Corresponding to the above embodiments, the present application also proposes a data processing system.

[0074] As Figure 7 shown, the data processing system 1000 of the embodiments of the present application includes the above multi-die integrated system 100, or as Figure 8 shown, the data processing system 1000 of the embodiments of the present application includes the above chip 200.

[0075] According to the data processing system of the embodiments of the present application, based on the above multi-die integrated system or the above chip, the data processing speed is improved to meet the requirements of large computing power application scenarios.

[0076] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0077] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0078] In the present application, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0079] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A multi-chip integrated system, characterized in that: The system comprises: A plurality of computing power core particles, each of which is used to perform data calculation based on a corresponding preset computing path; A management chip, wherein the management chip is connected to multiple computing chiplets through multiple die2die interfaces, and the die2die interfaces correspond to each of the computing chiplets one by one, and are used to receive external input data and send the external input data to at least one of the computing chiplets, so that the external input data can be processed by the computing chiplets to obtain target output data, and during the data processing, data is forwarded between the multiple computing chiplets, so that each of the computing chiplets can perform data calculation according to the corresponding preset calculation path.

2. The multi-chip integrated system according to claim 1, characterized in that: The management core is also used to determine target configuration information based on target computing requirements, and to perform parameter configuration on each of the computing power cores based on the target configuration information, so as to construct the preset computing path corresponding to each of the computing power cores.

3. The multi-chip integrated system according to claim 1, characterized in that: The die2die interface includes: PCIe port and RGMII port, used for data transmission between the management core particle and the computing power core particle; The I2C port and the GPIO port are used for the communication connection between the management core particle and the computing power core particle.

4. The multi-chip integrated system according to claim 3, characterized in that: The management core particle sends a control signal and a register configuration signal to the computing power core particle through the I2C port.

5. The multi-chip integrated system according to claim 3, characterized in that: The management core particle performs bidirectional communication with the computing power core particle through the GPIO port, and the management core particle sends an interrupt signal to the computing power core particle through the GPIO port.

6. The multi-chip integrated system according to claim 1, characterized in that: The multiple computing power cores and the management core are connected via a silicon adapter board.

7. The multi-chip integrated system according to claim 6, characterized in that: The management chip is arranged in the middle of the silicon adapter board, the multiple computing power chips are arranged at both ends of the management chip along a first direction, and the multiple computing power chips located on the same side are arranged in sequence along a second direction, wherein the second direction is perpendicular to the first direction.

8. The multi-chip integrated system according to any one of claims 1 to 7, characterized in that: The system further comprises a memory connected to the management core particle.

9. A chip, characterized in that: Comprising the multi-core integrated system according to any one of claims 1-8.

10. A data processing system, characterized in that: It comprises the multi-chip integrated system according to any one of claims 1 to 8, or the chip according to claim 9.

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