Abnormal display processing method after LVDS signal interruption and liquid crystal display device
By adjusting the pulse timing of the first clock signal and the second clock signal in the liquid crystal display device, the gate drive signal is set to a low level when the LVDS signal is interrupted, and the data writing is completed after the signal returns to normal, thus solving the display abnormality problem and achieving data integrity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TRULY (RENSHOU) HIGH-END DISPLAY TECH LTD
- Filing Date
- 2025-03-14
- Publication Date
- 2026-07-28
AI Technical Summary
In existing liquid crystal display devices, after the LVDS signal is interrupted, the gate drive signal is pulled low, causing data to be written incorrectly and resulting in display abnormalities.
By adjusting the pulse timing of the first clock signal and the second clock signal, the gate drive signal is set to a low level when the LVDS signal is interrupted, and data is written to the row pixels in the unscanned area after the signal returns to normal, thus avoiding pixel leakage.
The problem of incorrect data writing caused by LVDS signal interruption has been resolved, avoiding display abnormalities and ensuring data integrity.
Smart Images
Figure CN120071849B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LVDS signal interruption display anomaly technology for liquid crystal displays, and particularly to an abnormal display processing method and liquid crystal display device after LVDS signal interruption. Background Technology
[0002] Display devices are frequently affected by static electricity or the surrounding environment, causing interruptions in the data signals transmitted from the host to the display driver IC. For example, during data transmission from the host to the display driver IC via the LVDS (Low Voltage Differential Signaling) interface, interference from static electricity or surrounding signals can occur, leading to data interruptions on the LVDS transmission signal lines. In this case, the display driver IC cannot receive the correct signal. The current method is to ground all gate drive signals output by the GIP (Gate Input Processor), i.e., the Gate output is low. When the data transmission is normal, the display is re-scanned, i.e., the drive is re-scanned from the top to the bottom of the display. However, because some voltages within the GIP cannot be fully released, the P-point voltage of the gate output corresponding to the LVDS transmission signal line interruption cannot be pulled low. When the display is re-scanned from top to bottom, since the CK signal is connected to the current corresponding GIP circuit, the current GIP circuit also outputs a high level. At this time, data signals that do not belong to this area (data that should belong to the top area of the display) are written into this area, resulting in incorrect data writing and causing the display to display incorrect data. In addition, since GIPs are cascaded, the Gate signal output by this error will continue to be output, meaning that incorrect charging will continue to charge the wrong data, at which point the display will show abnormalities. Summary of the Invention
[0003] In existing display devices, after the LVDS transmission signal is interrupted, the gate drive signal is pulled low. Under normal circumstances, the scanning is restarted from top to bottom, which leads to incorrect data writing and display abnormalities.
[0004] To address the aforementioned issues, a method for handling abnormal display after LVDS signal interruption and a liquid crystal display device are proposed. By adjusting the pulse timing of the first clock signal and the second clock signal, when an LVDS signal interruption occurs, the gate drive signal is set to a low level to prevent pixel leakage. After the LVDS signal returns to normal, data writing continues to the row pixels of the remaining area of the current frame. This avoids writing pixel data from the already scanned area of the current frame into the row pixels of the current frame that have not yet been scanned, thus solving the problem of abnormal display caused by incorrect data writing when the LVDS signal occurs in existing display devices.
[0005] Firstly, a method for handling abnormal display after LVDS signal interruption includes:
[0006] Step 100: After the LVDS transmission signal is interrupted, pull down the gate drive signal output by the gate drive unit of all rows to maintain the pixel voltage of the area that has been scanned in the current frame.
[0007] Step 200: After the LVDS transmission signal returns to normal, use the first clock signal and the second clock signal to continue writing data to the row pixels of the remaining unscanned area of the current frame until all row pixels have been written.
[0008] The pulse timing of the first clock signal is opposite to that of the second clock signal.
[0009] In conjunction with the anomaly display processing method described in the first aspect of the present invention, in a first possible embodiment, the anomaly display processing method further includes:
[0010] Step 300: After writing data to the row pixels in the remaining unscanned area, start scanning the next frame using the start signal:
[0011] Set the start signal high to begin the drive scan for the next frame.
[0012] In conjunction with the first possible embodiment of the first aspect of the present invention, in the second possible embodiment, step 200 includes:
[0013] Step 210: Obtain the pulse level of the first clock signal in the area that has been scanned in the current frame;
[0014] Step 220: If the last pulse level of the first clock signal in the scanned area of the current frame is a high-level pulse, then the first pulse level of the remaining unscanned area of the current frame is output as a low-level pulse.
[0015] Step 230: Continue to output pulse levels continuously until all row pixel data of the remaining unscanned area of the current frame has been written.
[0016] In conjunction with the second possible implementation of the first aspect of the present invention, in a third possible implementation, step 200 further includes:
[0017] Step 240: Obtain the pulse level of the second clock signal in the area that has been scanned in the current frame;
[0018] Step 250: If the last pulse level of the second clock signal in the scanned area of the current frame is a low level pulse, then the first pulse level of the remaining unscanned area of the current frame is output as a high level.
[0019] Step 260: Continue to output pulse levels continuously until all row pixel data of the remaining unscanned area of the current frame has been written.
[0020] In conjunction with the third possible implementation of the first aspect of the present invention, in the fourth possible implementation, step 100 includes:
[0021] Step 110: In the area where the current frame has been scanned, set the reset signal to low level.
[0022] In conjunction with the fourth possible implementation of the first aspect of the present invention, in the fifth possible implementation, step 200 further includes:
[0023] Step 270: After the data of the last row of pixels in the remaining unscanned area of the current frame is written, set the reset signal to high level to end the current frame drive scan.
[0024] In a second aspect, a liquid crystal display device employs the abnormal display processing method described in the first aspect, comprising:
[0025] First timing control unit;
[0026] Second timing control unit;
[0027] Control unit;
[0028] The control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit;
[0029] The first timing control unit is used to output a first driving timing according to the control signal of the control unit, and is used to pull down the gate driving signal output by the gate driving unit of all rows after the LVDS transmission signal is interrupted, so as to maintain the pixel voltage of the area that has been scanned in the current frame.
[0030] The second timing control unit is used to output a first pulse timing sequence and a second pulse timing sequence to the first clock signal line and the second clock signal line respectively according to the control signal of the control unit. After the LVDS transmission signal returns to normal, it continues to write data to the row pixels of the remaining unscanned area of the current frame until all row pixels are written.
[0031] The timing of the first pulse is the opposite of that of the second pulse.
[0032] In conjunction with the liquid crystal display device described in the second aspect of the present invention, in a first possible embodiment, the liquid crystal display device further includes:
[0033] Third timing control unit;
[0034] The third timing control unit is electrically connected to the control unit and is used to output the second driving timing to the start signal line after the data writing of the row pixels in the remaining unscanned area is completed, so as to start the scanning of the next frame:
[0035] Set the start signal high to begin the drive scan for the next frame.
[0036] In conjunction with the first possible embodiment of the second aspect of the present invention, in the second possible embodiment, the timing of the first pulse is as follows:
[0037] If the last pulse of the first clock signal in the scanned area of the current frame is a high-level pulse, then the first pulse of the remaining unscanned area of the current frame will be output as a low-level pulse, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.
[0038] In conjunction with the second possible implementation of the first aspect of the present invention, in the third possible implementation, the second pulse timing is as follows:
[0039] If the second clock signal is a low-level pulse in the last pulse of the scanned area of the current frame, then the first pulse of the remaining unscanned area of the current frame will be output as a high-level pulse, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.
[0040] The present invention provides an abnormal display processing method and liquid crystal display device. By adjusting the pulse timing of the first clock signal and the second clock signal, when an LVDS signal interruption occurs, the gate drive signal is set to a low level to prevent pixel leakage. After the LVDS signal returns to normal, data writing continues to the row pixels of the remaining area of the current frame. This avoids writing pixel data of the area that has been scanned in the current frame into the row pixels that have not been scanned in the current frame, thus solving the problem of display abnormalities caused by incorrect data writing when the LVDS signal occurs in existing display devices. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a schematic diagram of a liquid crystal display device in the prior art;
[0043] Figure 2 This is a schematic diagram of the gate driving circuit of a liquid crystal display device in an existing technical solution;
[0044] Figure 3 This is a timing diagram of the gate driving circuit of a liquid crystal display device in the prior art.
[0045] Figure 4 This is a timing diagram of the driver for handling abnormalities in a liquid crystal display device in an existing technical solution;
[0046] Figure 5 This is a timing diagram of the abnormal handling process of the liquid crystal display device in this application;
[0047] Figure 6 This is a schematic flowchart of a specific embodiment of an abnormal display processing method after LVDS signal interruption in this application;
[0048] Figure 7 yes Figure 6 A schematic diagram of a specific embodiment of step 200 in the process;
[0049] Figure 8 yes Figure 7 A flowchart of a specific embodiment following step 230;
[0050] Figure 9 This is a schematic diagram of a module structure of a liquid crystal display device according to this application. Detailed Implementation
[0051] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0054] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0056] In existing display devices, after an LVDS transmission signal interruption, the gate drive signal is pulled low. Normally, the scanning process restarts from top to bottom, leading to incorrect data writing and display abnormalities. For example... Figures 1-4 , Figure 1 This is a schematic diagram of a liquid crystal display device in the prior art. Figure 2 This is a schematic diagram of the gate driving circuit of a liquid crystal display device in an existing technical solution. Figure 3 This is a timing diagram of the gate driving circuit in a liquid crystal display device in an existing technical solution. Figure 4 This is a timing diagram of the abnormal handling process in a liquid crystal display device using existing technology. Existing technology pulls all Gate drive signals output by the Gate Injection Circuit (GIP) to a low level, i.e., the VGL potential, to ensure that the pixel voltage of the current frame does not leak. After the data is normalized, scanning begins again from the first line to the last line. At this point, due to leakage at point P, the data to be written is incorrectly charged, causing the display to malfunction. Furthermore, because the current frame of data is not completely written, the display may exhibit a split-screen phenomenon.
[0057] To address the above problems, a method for handling abnormal displays after LVDS signal interruption and a liquid crystal display device are proposed.
[0058] Firstly, a method for handling abnormal display after LVDS signal interruption, such as... Figure 6 , Figure 6 This is a schematic flowchart of a specific embodiment of an abnormal display processing method after LVDS signal interruption in this application, including:
[0059] Step 100: After the LVDS transmission signal is interrupted, pull the gate drive signal output by the gate drive unit of all rows low to maintain the pixel voltage of the scanned area of the current frame. Step 200: After the LVDS transmission signal returns to normal, use the first clock signal (CK1) and the second clock signal (CK2) to continue writing data to the row pixels of the remaining unscanned area of the current frame until all row pixels are written. The pulse timing of the first clock signal (CK1) and the second clock signal (CK2) is opposite. By adjusting the pulse timing of the first clock signal (CK1) and the second clock signal (CK2), the gate drive signal is set to a low level when the LVDS signal is interrupted to prevent pixel leakage. After the LVDS signal returns to normal, data writing continues to be performed on the row pixels of the remaining area of the current frame. This avoids writing pixel data of the scanned area of the current frame to the row pixels of the unscanned area of the current frame, thus solving the problem of data miswriting and display abnormalities caused by LVDS signal errors in existing display devices.
[0060] In a preferred embodiment, the anomaly display processing method further includes:
[0061] Step 300: After writing data to the row pixels in the remaining unscanned area, the start signal (STV) is used to initiate the next frame scan. The start signal (STV) is set to a high level to initiate the drive scan of the next frame. After the current frame scan is completed, the start signal (STV) outputs a high level to initiate the drive scan of the next frame.
[0062] In a preferred embodiment, such as Figure 7 , Figure 7 yes Figure 6 A schematic flowchart of a specific embodiment of step 200 is shown below; step 200 includes step 210, obtaining the pulse level of the first clock signal (CK1) in the scanned area of the current frame; step 220, if the last pulse level of the first clock signal (CK1) in the scanned area of the current frame is a high-level pulse, then outputting the first pulse level of the remaining unscanned area of the current frame as a low-level pulse; step 230, continuing to continuously output pulse levels until all row pixel data of the remaining unscanned area of the current frame is written, such as... Figure 5 , Figure 5 This is a timing diagram of the abnormal handling process of the liquid crystal display device in this application.
[0063] In a preferred embodiment, such as Figure 8 , Figure 8 yes Figure 7A flowchart of a specific embodiment following step 230 is shown; step 200 further includes: step 240, obtaining the pulse level of the second clock signal (CK2) in the scanned area of the current frame; step 250, if the last pulse level of the second clock signal (CK2) in the scanned area of the current frame is a low-level pulse, then outputting the first pulse level of the remaining unscanned area of the current frame as a high-level pulse; step 260, continuing to output pulse levels continuously until all row pixel data of the remaining unscanned area of the current frame is written, such as... Figure 5 .
[0064] exist Figure 5 When an LVDS transmission signal interruption occurs, the start signal (STV), reset signal (RST), first clock signal (CK1), and second clock signal (CK2) are all at low level. When the LVDS transmission signal returns to normal, the scanning of the remaining lines continues using the first clock signal (CK1) and the second clock signal (CK2).
[0065] In a preferred embodiment, step 100 includes: step 110, setting the reset signal (RST) to a low level in the area where the current frame has been scanned.
[0066] In a preferred embodiment, step 200 further includes step 270: after the data of the last row of pixels in the remaining unscanned area of the current frame has been written, the reset signal (RST) is set to a high level to end the current frame drive scan.
[0067] After the data is normal, the first n-1 will still set the reset signal (RST) to low level and continue scanning the remaining lines of the current frame. After the remaining lines are scanned, the reset signal (RST) will be set to high level to end the current frame drive scan.
[0068] Secondly, a liquid crystal display device, such as Figure 9 , Figure 9This is a schematic diagram of a module structure of a liquid crystal display device according to the present application. It employs the abnormal display processing method of the first aspect, including a first timing control unit, a second timing control unit, and a control unit. The control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit. The first timing control unit outputs a first driving timing sequence according to the control signal of the control unit, and pulls down the gate driving signals output by the gate driving units of all rows after the LVDS transmission signal is interrupted, so as to maintain the pixel voltage of the scanned area of the current frame. The second timing control unit outputs a first pulse timing sequence and a second pulse timing sequence to the first clock signal (CK1) line and the second clock signal (CK2) line respectively according to the control signal of the control unit, and continues to write data to the row pixels of the remaining unscanned area of the current frame after the LVDS transmission signal returns to normal, until all row pixels are written.
[0069] The timing of the first pulse is the opposite of that of the second pulse.
[0070] Specifically, the liquid crystal display device also includes a third timing control unit; the third timing control unit is electrically connected to the control unit and is used to output a second driving timing to the start signal (STV) line after the data writing of the row pixels in the remaining unscanned area is completed, so as to start the next frame scanning: set the start signal (STV) to a high level to start the driving scan of the next frame.
[0071] Specifically, the timing of the first pulse is as follows: if the last pulse level of the first clock signal (CK1) in the scanned area of the current frame is a high level pulse, then the first pulse level of the remaining unscanned area of the current frame will be output as a low level, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.
[0072] Specifically, the timing of the second pulse is as follows: if the last pulse level of the second clock signal (CK2) in the scanned area of the current frame is a low level pulse, then the first pulse level of the remaining unscanned area of the current frame will be output as a high level, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.
[0073] An abnormal display processing method and liquid crystal display device according to the present invention adjusts the pulse timing of the first clock signal (CK1) and the second clock signal (CK2). When an LVDS signal interruption occurs, the gate drive signal is set to a low level to prevent pixel leakage. After the LVDS signal returns to normal, data writing continues to the row pixels of the remaining area of the current frame. This avoids writing pixel data of the area that has been scanned in the current frame to the row pixels that have not been scanned in the current frame, thus solving the problem of display abnormalities caused by incorrect data writing when the LVDS signal occurs in existing display devices.
[0074] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for displaying an exception after an LVDS signal interruption, characterized in that, The process includes: Step 100: After the LVDS transmission signal is interrupted, pull down the gate drive signals output by the gate drive units of all rows to maintain the pixel voltage of the scanned area of the current frame; Step 200: After the LVDS transmission signal returns to normal, during the remaining time period of the current frame, use the first clock signal CK1 and the second clock signal CK2 of the gate drive circuit to continue writing data to the row pixels of the remaining unscanned area of the current frame until the remaining row pixels are written; wherein, the pulse timing of the first clock signal CK1 and the second clock signal CK2 are opposite; the first clock signal CK1 is CK1 used by the pull-up circuit, and the second clock signal CK2 is CK2 used by the pull-down circuit; Step 300: After writing data to the row pixels in the remaining unscanned area, start scanning the next frame using the start signal: Set the start signal high to begin the drive scan for the next frame.
2. The LVDS signal interruption abnormal display processing method according to claim 1, characterized in that, Step 200 includes: Step 210: Obtain the pulse level of the first clock signal in the area that has been scanned in the current frame; Step 220: If the last pulse level of the first clock signal in the scanned area of the current frame is a high-level pulse, then the first pulse level of the remaining unscanned area of the current frame will be output as a low-level pulse. Step 230: Continue to output pulse levels continuously until all row pixel data of the remaining unscanned area of the current frame has been written.
3. The LVDS signal interruption abnormal display processing method according to claim 2, characterized by, Step 200 further includes: Step 240: Obtain the pulse level of the second clock signal in the area that has been scanned in the current frame; Step 250: If the last pulse level of the second clock signal in the scanned area of the current frame is a low level pulse, then the first pulse level of the remaining unscanned area of the current frame will be output as a high level. Step 260: Continue to output pulse levels continuously until all row pixel data of the remaining unscanned area of the current frame has been written.
4. The LVDS signal interruption abnormal display processing method according to claim 3, characterized in that, Step 100 includes: Step 110: In the area where the current frame has been scanned, set the reset signal to low level.
5. The LVDS signal interruption abnormal display processing method according to claim 4, characterized in that, Step 200 further includes: Step 270: After the data of the last row of pixels in the remaining unscanned area of the current frame is written, set the reset signal to high level to end the current frame drive scan.
6. A liquid crystal display device employing the abnormal display processing method after the LVDS signal interruption according to any one of claims 1 to 5, characterized by include: First timing control unit; Second timing control unit; Control unit; The control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit; The first timing control unit is used to output a first driving timing according to the control signal of the control unit, and is used to pull down the gate driving signal output by the gate driving unit of all rows after the LVDS transmission signal is interrupted, so as to maintain the pixel voltage of the area that has been scanned in the current frame. The second timing control unit is used to output the first pulse timing and the second pulse timing to the first clock signal line and the second clock signal line respectively according to the control signal of the control unit. After the LVDS transmission signal returns to normal, it continues to write data to the row pixels of the remaining unscanned area of the current frame until all row pixels are written. The timing of the first pulse is the opposite of that of the second pulse.
7. The liquid crystal display device according to claim 6, wherein The liquid crystal display device further includes: Third timing control unit; The third timing control unit is electrically connected to the control unit and is used to output the second driving timing to the start signal line after the data writing of the row pixels in the remaining unscanned area is completed, so as to start the scanning of the next frame: Set the start signal high to begin the drive scan for the next frame.
8. The liquid crystal display device according to claim 7, wherein The timing sequence of the first pulse is as follows: If the last pulse of the first clock signal in the scanned area of the current frame is a high-level pulse, then the first pulse of the remaining unscanned area of the current frame will be output as a low-level pulse, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.
9. The liquid crystal display device according to claim 8, wherein The timing sequence of the second pulse is as follows: If the second clock signal is a low-level pulse in the last pulse of the scanned area of the current frame, then the first pulse of the remaining unscanned area of the current frame will be output as a high-level pulse, and the pulse level will continue to be output continuously until all row pixel data of the remaining unscanned area of the current frame is written.