A phase modulating pull-up circuit

Abstract

The application relates to a same-phase modulation pull-up circuit, belonging to the technical field of liquid crystal panel driving circuit, and comprising a pull-up unit and a same-phase modulation unit; wherein the pull-up unit is composed of two double-gate control thin film transistors, and the same-phase modulation unit is composed of two inverters. The application can simultaneously solve the problems of insufficient Q point charging or weak potential holding capacity caused by positive and negative shifts of threshold voltage of an oxide GOA, realize the stability and uniformity of GOA driving of a liquid crystal display, and improve the reliability and quality of the liquid crystal display product.

Description

Technical Field

[0001] This invention belongs to the field of liquid crystal panel manufacturing technology. Specifically, this invention relates to an in-phase modulation pull-up circuit. Background Technology

[0002] GOA stands for Gate Driven on Array, meaning gate drive integration on the array substrate, enabling progressive scan driving of the LCD panel. In traditional active matrix LCDs, the row scan signal is implemented by an external integrated circuit (G-COF). GOA driving, however, uses a process similar to that of thin-film transistors (TFTs) to fabricate the row scan drive circuit, requiring only a few control signals from the external circuit, thus achieving progressive scan driving. Therefore, GOA driving saves on the integrated circuits related to scan driving, reducing the manufacturing cost of the LCD. As the driving principle of the LCD panel shows, the row scan drive circuit essentially functions as a shift register. Under the control signals of the external circuit, it generates shift pulse signals. These shift pulse signals drive the pixels of the current row to turn on the TFTs and also serve as the start signal for the next row (the first row is triggered by the frame start signal STV) and the end signal for the previous row.

[0003] GOA driving design reduces the manufacturing cost of LCD panels. Oxide thin-film transistors (OSTs), due to their high mobility, have become an important part of next-generation display technology. However, due to the threshold voltage offset characteristics of OSTs, issues such as uniformity and stability arise, causing positive / negative shifts in the device's threshold voltage. Figure 3 As shown, the shift of curve 2 towards curve 1 can easily lead to leakage problems, such as causing leakage in the pull-up unit of the GOA, resulting in insufficient Q-point potential holding. Conversely, the shift of curve 2 towards curve 3 can easily lead to charging problems, such as insufficient charging in the pull-up unit circuit of the GOA. It is difficult to effectively solve the above-mentioned problems of insufficient charging or weak potential holding capability simultaneously from the perspective of process or circuit design alone. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes an in-phase modulation pull-up circuit to solve the problem of insufficient Q-point charging or weak potential retention caused by the positive and negative offset of the threshold voltage on the oxide GOA.

[0005] This invention provides a non-inverting modulation pull-up circuit, comprising:

[0006] Pull-up unit and in-phase modulation unit;

[0007] The pull-up unit is composed of a dual-gate controlled thin-film transistor T1 and a dual-gate controlled thin-film transistor T2, and includes:

[0008] The drain of the dual-gate controlled thin-film transistor T1 is connected to the source of the dual-gate controlled thin-film transistor T2;

[0009] The source of the dual-gate controlled thin-film transistor T1 is used as the Q-point terminal of the external GOA circuit;

[0010] The drain of the dual-gate controlled thin-film transistor T2 is used for the high-level VGH terminal of the external GOA circuit;

[0011] The top gate electrode of the dual-gate control thin-film transistor T1 and the dual-gate control thin-film transistor T2 are connected to each other and are used to connect to the output electrode of the in-phase modulation unit.

[0012] The bottom gate electrode of the dual-gate control thin-film transistor T1 is connected to the bottom gate electrode of the dual-gate control thin-film transistor T2, and is used to connect the input electrode of the in-phase modulation unit and the STN terminal of the external GOA circuit.

[0013] The in-phase modulation unit is composed of inverter A and inverter B; wherein...

[0014] The high-level electrode of inverter A is connected to the high-level electrode of inverter B, which is used to connect the high-level V of the external GOA circuit. GH end;

[0015] The low-level electrode of inverter A is connected to the low-level electrode of inverter B, which is used to connect the low-level V of the external GOA circuit. SSQ end;

[0016] The input electrode of inverter A serves as the input electrode of the in-phase modulation unit and is used to connect to the STN terminal of the external GOA circuit.

[0017] The output electrode of inverter A is connected to the input electrode of inverter B;

[0018] The output electrode of inverter B serves as the output electrode of the in-phase modulation unit, and is connected to the top gate electrode of dual-gate controlled thin-film transistor T1 and dual-gate controlled thin-film transistor T2.

[0019] Furthermore, the inverter A is composed of transistor T3 and transistor T4, wherein:

[0020] The drain and gate of transistor T3 are connected, serving as the high-level electrode of inverter A for connecting the high-level V of the external GOA circuit. GH end;

[0021] The source of transistor T4 is used to connect the low-level V of the external GOA circuit. SSQ end.

[0022] Furthermore, the gate of the transistor T4 serves as the input electrode of the inverter A, and is used to connect the STN terminal of the external GOA circuit.

[0023] Furthermore, the drain of transistor T4 is connected to the source of transistor T3, and is connected to the input electrode of inverter B as the output electrode of inverter A.

[0024] Furthermore, the inverter B is composed of transistor T5 and transistor T6, wherein:

[0025] The drain and gate of transistor T5 are connected, serving as the high-level electrode of inverter B for connecting the high-level V of the external GOA circuit. GH end;

[0026] The source of transistor T6 is used to connect the low-level V of the external GOA circuit. SSQ end.

[0027] Furthermore, the gate of the transistor T6 serves as the input electrode of the inverter B and is connected to the output electrode of the inverter A.

[0028] Furthermore, the drain of transistor T6 is connected to the source of transistor T5 to serve as the output electrode of inverter B.

[0029] Furthermore, the equipotential points with the same function inside the in-phase modulation pull-up circuit are internally electrically connected and have a unified connection port to the external circuit.

[0030] The advantages of this invention compared to the prior art are:

[0031] This invention can simultaneously solve the problems of insufficient Q-point charging or weak potential retention caused by the positive and negative offset of the threshold voltage on the oxide GOA, thereby achieving stability and uniformity of GOA driving in liquid crystal displays and improving the reliability and quality of liquid crystal display products. Attached Figure Description

[0032] Figure 1 This is a diagram of an in-phase modulation pull-up circuit provided in an embodiment of the present invention.

[0033] Figure 2 This is a connection diagram of an in-phase modulation pull-up circuit applied in a GOA circuit according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the uniformity curve offset of a conventional high-migration oxide transistor provided in an embodiment of the present invention.

[0035] Figure 4 This is the modulation effect characteristic curve of the pull-up unit provided in the embodiment of the present invention.

[0036] Figure 5 This is the modulation effect characteristic curve of the in-phase modulation unit provided in the embodiment of the present invention.

[0037] Figure 6 This is a waveform and timing diagram of a non-inverting modulation pull-up circuit in operation, provided by an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0039] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0040] Method Implementation Examples

[0041] This invention primarily addresses the stability issue of GOA driving in liquid crystal displays by providing an in-phase modulation pull-up circuit, as shown in the attached diagram. Figure 1 As shown, it specifically includes:

[0042] Pull-up unit and in-phase modulation unit;

[0043] The pull-up unit is composed of dual-gate control thin-film transistors T1 and T2, and includes:

[0044] The drain of the dual-gate controlled thin-film transistor T1 is connected to the source of the dual-gate controlled thin-film transistor T2;

[0045] The source of the dual-gate controlled thin-film transistor T1 is used as the Q-point terminal of the external GOA circuit;

[0046] The drain of the dual-gate controlled thin-film transistor T2 is used to connect the high-level V of the external GOA circuit. GH end;

[0047] The top gate electrodes of the dual-gate control thin-film transistors T1 and T2 are connected to the output electrode of the in-phase modulation unit, i.e., point T in the figure.

[0048] The bottom gate electrodes of the dual-gate control thin-film transistors T1 and T2 are connected to each other and are used to connect to the input electrode of the in-phase modulation unit and the STN terminal of the external GOA circuit.

[0049] The in-phase modulation unit is composed of inverter A and inverter B; wherein...

[0050] The high-level electrode of inverter A is connected to the high-level electrode of inverter B, which is used to connect the high-level V of the external GOA circuit. GH end;

[0051] The low-level electrode of inverter A is connected to the low-level electrode of inverter B, which is used to connect the low-level V of the external GOA circuit. SSQ end;

[0052] The input electrode of inverter A serves as the input electrode of the in-phase modulation unit and is used to connect to the STN terminal of the external GOA circuit.

[0053] The output electrode of inverter A is connected to the input electrode of inverter B;

[0054] The output electrode of inverter B serves as the output electrode of the in-phase modulation unit and is connected to the top gate electrode of dual-gate control thin-film transistors T1 and T2.

[0055] Furthermore, the inverter A is composed of transistor T3 and transistor T4, wherein:

[0056] The drain and gate of transistor T3 are connected, serving as the high-level electrode of inverter A for connecting the high-level V of the external GOA circuit. GH end;

[0057] The source of transistor T4 is used to connect the low-level V of the external GOA circuit. SSQ end;

[0058] The gate of transistor T4 serves as the input electrode of inverter A, used to connect the STN terminal of the external GOA circuit.

[0059] The drain of transistor T4 is connected to the source of transistor T3, and serves as the output electrode of inverter A, which is connected to the input electrode of inverter B.

[0060] Furthermore, the inverter B is composed of transistor T5 and transistor T6, wherein:

[0061] The drain and gate of transistor T5 are connected, serving as the high-level electrode of inverter B for connecting the high-level V of the external GOA circuit. GH end;

[0062] The source of transistor T6 is used to connect the low-level V of the external GOA circuit. SSQ end;

[0063] The gate of transistor T6 serves as the input electrode of inverter B and is connected to the output electrode of inverter A.

[0064] The drain of transistor T6 is connected to the source of transistor T5 to serve as the output electrode of inverter B.

[0065] Preferably, in the above circuit structure, the terminals of equipotential points with the same function are internally electrically connected and have a unified connection port to the external circuit. For example, the source of transistor T4 is connected to the source of transistor T6, and the gate of transistor T4 is connected to the bottom gate electrode of T1 and T2.

[0066] For example, the in-phase modulation pull-up circuit described in this invention is set in the GOA circuit, such as... Figure 2 As shown.

[0067] Figure 2 Within the dashed block diagram, the existing pull-up unit only has T11, which only has on and off functions and cannot perform in-phase modulation of the threshold voltage.

[0068] Figure 2 The in-phase modulation pull-up circuit consists of T11, T12, T81, T82, T83, and T84. Among them, the pull-up units are T11 and T12, both of which are dual-gate transistors with dual-gate modulation capability. Transistors T11 and T12 are mainly used for charging the Q-point of the GOA circuit.

[0069] The threshold voltage of the pull-up unit of this invention is controllable and modulated. The dual-gate modulation effect curve of the pull-up unit of this invention is shown below. Figure 4 As shown: at high level V GH Under modulation, the threshold voltage at the Q-point of the pull-up unit becomes negatively biased, as shown in V. GH Modulation curve; at low level V SSQ Under modulation, the threshold voltage at the Q-point of the pull-up unit becomes positively biased, as shown in V. SSQ Modulation curve. The middle curve is the initial, unmodulated curve.

[0070] Figure 2 The in-phase modulation units are T81, T82, T83, and T84. The high-level signal of this unit is connected to V. GH Low level connected to V SSQ Its typical input / output characteristics are as follows: Figure 5 As shown: When the input is a positive voltage, such as V... STNH Its output is V GH When the input voltage is negative, such as V... STNL Its output is V SSQ .

[0071] Specific work process:

[0072] 1. During the charging phase at point Q, the STN terminal of the GOA circuit outputs a high potential (V). STNHTransistors T11 and T12 are turned on. Because the input is at a high potential, point T of the circuit will output V. GH (like Figure 5 As shown). The high potential at point T will negatively modulate the threshold voltage of T11 and T12 (e.g. Figure 4 (As shown). This increases the on-state current of transistors T11 and T12, thereby increasing the transistor's charging capability.

[0073] 2. After charging at point Q is complete, the STN outputs a low potential (V). STNL Transistors T11 and T12 are turned off. Because the input is at a low potential, point T of the module will output V. SSQ (like Figure 5 As shown). The low potential at point T will positively modulate the threshold voltage of T11 and T12 (e.g.). Figure 4 (As shown). This improves the leakage current problem of transistors T11 and T12.

[0074] The waveforms and timing diagrams during specific operation are as follows: Figure 6 As shown, Figure 6 The waveform contains STN, T, and Q signals, by Figure 6 It is evident that the in-phase modulation pull-up circuit with the in-phase modulation structure has better pull-up capability and the ability to prevent leakage current at the Q point potential.

[0075] The STN signal of the GOA circuit is a periodic square wave signal used to turn transistors T11 and T12 on or off within a specified operating range.

[0076] The function of the T signal is to output a square wave signal in the same direction as the STN signal to modulate the threshold voltages of transistors T11 and T12. When STN is high, the T signal outputs V. GH This is done by negatively adjusting the threshold voltages of transistors T11 and T12, thereby increasing the on-state current when transistors T11 and T12 are turned on, so as to charge the Q point to the appropriate voltage as quickly as possible. When STN is low, the T signal outputs V. GL This allows for positive regulation of the threshold voltages of transistors T11 and T12, thereby reducing the leakage current when transistors T11 and T12 are off. This ensures that the Q-point voltage remains stable.

[0077] The Q signal of the GOA circuit is a static operating point of the circuit, used to charge and release the corresponding voltage within a specified operating cycle to turn on or off transistors T21 and T22, thereby realizing the step-by-step output of the horizontal scanning square wave signal G(N) and the next stage STN signal.

[0078] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A non-inverting modulation pull-up circuit, characterized in that, include: Pull-up unit and in-phase modulation unit; The pull-up unit is composed of a dual-gate controlled thin-film transistor T1 and a dual-gate controlled thin-film transistor T2, and includes: The drain of the dual-gate controlled thin-film transistor T1 is connected to the source of the dual-gate controlled thin-film transistor T2; The source of the dual-gate controlled thin-film transistor T1 is used as the Q-point terminal of the external GOA circuit; The drain of the dual-gate controlled thin-film transistor T2 is used for the high-level VGH terminal of the external GOA circuit; The top gate electrode of the dual-gate control thin-film transistor T1 and the dual-gate control thin-film transistor T2 are connected to each other and are used to connect to the output electrode of the in-phase modulation unit. The bottom gate electrode of the dual-gate control thin-film transistor T1 is connected to the bottom gate electrode of the dual-gate control thin-film transistor T2, and is used to connect the input electrode of the in-phase modulation unit and the STN terminal of the external GOA circuit. The in-phase modulation unit is composed of inverter A and inverter B; wherein... The high-level electrode of inverter A is connected to the high-level electrode of inverter B, which is used to connect the high-level V of the external GOA circuit. GH end; The low-level electrode of inverter A is connected to the low-level electrode of inverter B, which is used to connect the low-level V of the external GOA circuit. SSQ end; The input electrode of inverter A serves as the input electrode of the in-phase modulation unit and is used to connect to the STN terminal of the external GOA circuit. The output electrode of inverter A is connected to the input electrode of inverter B; The output electrode of inverter B serves as the output electrode of the in-phase modulation unit and is connected to the top gate electrode of dual-gate controlled thin-film transistor T1 and dual-gate controlled thin-film transistor T2. The inverter A is composed of transistor T3 and transistor T4, wherein: The drain and gate of transistor T3 are connected, serving as the high-level electrode of inverter A for connecting the high-level V of the external GOA circuit. GH end; The source of transistor T4 is used to connect the low-level V of the external GOA circuit. SSQ end; The gate of transistor T4 serves as the input electrode of inverter A, and is used to connect the STN terminal of the external GOA circuit. The drain of transistor T4 is connected to the source of transistor T3, and is connected to the output electrode of inverter A and the input electrode of inverter B. The inverter B is composed of transistor T5 and transistor T6, wherein: The drain and gate of transistor T5 are connected, serving as the high-level electrode of inverter B for connecting the high-level V of the external GOA circuit. GH end; The source of transistor T6 is used to connect the low-level V of the external GOA circuit. SSQ end; The gate of transistor T6 serves as the input electrode of inverter B and is connected to the output electrode of inverter A. The drain of transistor T6 is connected to the source of transistor T5, serving as the output electrode of inverter B.

2. The in-phase modulation pull-up circuit according to claim 1, characterized in that: The equipotential points with the same function inside the in-phase modulation pull-up circuit are internally electrically connected and have a unified connection port to the external circuit.

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