Method for testing Ethernet PHY (Physical Layer) chip

Abstract

The invention relates to a method for testing an Ethernet PHY (Physical Layer) chip, belongs to the technical field of Ethernet transceiver testing, and solves the problem that the writing difficulty of testing PATTERN of the existing method for testing the Ethernet PHY chip is relatively high. An Ethernet PHY chip test method comprises the following steps: an ATE test board controls a pin of a to-be-tested PHY chip to be connected with the ATE test board, test data of parameter test are sent to the to-be-tested PHY chip, and parameter test is carried out on the to-be-tested PHY chip; the ATE testboard controls a pin of the PHY chip to be tested to be connected with the FPGA and sends test data of the function test of the Ethernet protocol to the FPGA, the FPGA controls the test data to communicate between the PHY chip to be tested and the PHY chip to be tested, and the function test of the Ethernet protocol is carried out on the PHY chip to be tested.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet transceiver testing, and in particular to a testing method for an Ethernet PHY chip. Background Art

[0002] First, the Ethernet communication protocol is introduced as follows. The Ethernet PHY chip supports Gigabit Media Independent Interface (GMII), Reduced GMII (RGMII), Serial Gigabit Media Independent Interface (SGMII), Ten-bit Interface (TBI), and Reduced TBI (RTBI) for direct connection to the MAC / switch interface. The Ethernet protocol frame between the MAC and the PHY is shown in Table 1 below, including seven parts: preamble, start frame delimiter, destination address, source address, length, data and payload, and CRC check.

[0003] Table 1 Thumbnail of Ethernet MAC layer protocol frame

[0004]

[0005] During the testing process of the Ethernet PHY chip, since the data length and the specific content of the data will change, each time it changes, it is necessary to recalculate the cyclic redundancy check code. The cyclic redundancy check code can be calculated by writing script software and written back to the test PATTERN of the test system according to different protocol formats in sequence. Thus, the capacity of the entire Ethernet protocol is large, and the computational amount of the cyclic redundancy check code is very large, resulting in a great difficulty in writing the test PATTERN. Even if 1 bit is incorrect, it will cause communication failure between the MAC and the PHY chip, and manually calculating using the algorithm causes great trouble for subsequent debugging. Summary of the Invention

[0006] In view of the above analysis, the embodiments of the present invention aim to provide a testing method for an Ethernet PHY chip to solve the problem of the great difficulty in writing the test PATTERN of the existing testing method for Ethernet PHY chips.

[0007] The present invention discloses a testing method for an Ethernet PHY chip, and the testing method includes:

[0008] The ATE test bench controls the pins of the PHY chip under test to be connected to the ATE test bench, sends test data for parameter testing to the PHY chip under test, and performs parameter testing on the PHY chip under test;

[0009] The ATE test bench controls the pins of the PHY chip under test to be connected to the FPGA, sends test data for the functional test of the Ethernet protocol to the FPGA, and the FPGA controls the communication of the test data between the PHY chip under test and the countermeasure PHY chip to perform the functional test of the Ethernet protocol on the PHY chip under test.

[0010] Based on the above solution, the present invention has also made the following improvements:

[0011] Furthermore, the ATE test bench stores the test data and test instructions for each parameter test of the PHY chip under test; the ATE test bench performs parameter tests on the PHY chip under test and executes:

[0012] The ATE test bench controls the connection mode between the ATE test bench and the pins of the PHY chip under test according to the test instructions of the current parameter test;

[0013] The ATE test bench sends the test data for the corresponding parameter test to the PHY chip under test and samples back the test observation signals of the corresponding parameter test fed back by the PHY chip under test;

[0014] The ATE test bench determines whether the corresponding parameter test passes based on the test observation signals of the corresponding parameter test.

[0015] Furthermore, during the process of the ATE test bench performing parameter tests on the PHY chip under test:

[0016] The ATE test bench configures and reads out the registers of the PHY chip under test through the MDIO pins, and configures the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode;

[0017] Send the test data for the corresponding parameter test to the PHY chip under test through the TX pin of the ATE test bench, and sample back the test observation signals of the corresponding parameter test fed back by the PHY chip under test using the RX of the ATE test bench for reception;

[0018] Among them, the test data and test observation signals of the parameter test are both data frames in the GMII format.

[0019] Furthermore, the ATE test bench also stores the test data and test instructions for each functional test of the Ethernet protocol of the PHY chip under test; the ATE test bench performs the functional test of the Ethernet protocol on the PHY chip under test and executes:

[0020] The ATE test bench controls the PHY chip under test to power on;

[0021] The FPGA loads the corresponding Ethernet protocol controller IP core according to the test instructions of the current functional test of the Ethernet protocol, and controls the connection mode between the FPGA and the pins of the PHY chip under test;

[0022] After the handshake between the PHY chip under test and the countermeasure PHY chip is successful, the FPGA uses the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and controls the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip under test and the countermeasure PHY chip;

[0023] The FPGA parses the second data frame returned by the PHY chip under test and the countermeasure PHY chip to obtain the test observation signal of the corresponding Ethernet protocol;

[0024] Based on the test observation signal of the corresponding Ethernet protocol, the ATE test bench determines whether the function test of the corresponding Ethernet protocol passes.

[0025] Further, after the handshake between the PHY chip under test and the countermeasure PHY chip is successful, execute:

[0026] The FPGA configures the CONFIG and HWCFG MODE of the PHY chip under test and the countermeasure PHY chip through the IO pins;

[0027] The FPGA sends a reset signal to the PHY chip under test and the countermeasure PHY chip. The PHY chip under test and the countermeasure PHY chip start to reset and respectively collect their own hardware configuration information, and then perform a handshake and auto-negotiation, waiting for the handshake between the PHY chip under test and the countermeasure PHY chip to be successful.

[0028] Further, after the handshake between the PHY chip under test and the countermeasure PHY chip is successful, the ATE test bench sends test data to the IO port of the FPGA through the test PATTERN, and the received FIFO of the FPGA receives the test data of the corresponding Ethernet protocol from the ATE test bench; so that the FPGA uses the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol in the received FIFO into the first data frame of the corresponding Ethernet protocol.

[0029] Further, in the FPGA, the first data frame of the Ethernet protocol is obtained by performing the following operations:

[0030] Based on the loaded controller IP core of the Ethernet protocol, the FPGA generates two identical MAC controllers of the corresponding Ethernet protocol; one MAC controller is responsible for communicating with the PHY chip under test, and the other MAC controller is responsible for communicating with the countermeasure PHY chip;

[0031] The two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert it into the first data frame of the corresponding Ethernet protocol; and send the first data frame of the corresponding Ethernet protocol to the PHY chip under test or the countermeasure PHY chip connected by communication.

[0032] Further, the PHY chip under test and the countermeasure PHY chip obtain a second data frame by performing the following operations:

[0033] After the PHY chip under test and the countermeasure PHY chip respectively pass the verification of the received first data frame, they send the first data frame to each other using a preset data transmission rate;

[0034] After both parties receive the first data frame and pass the verification, they convert the first data frame into a data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame;

[0035] The FPGA parses the second data frame and stores the data after parsing the second data frame as a test observation signal of the corresponding Ethernet protocol in the transmit FIFO of the FPGA.

[0036] Further, the ATE test bench determines whether the function test of the Ethernet protocol passes by performing the following operations:

[0037] The ATE test bench sends a read valid signal and a read clock to the FPGA to read the test observation signal in the transmit FIFO of the FPGA;

[0038] The ATE test bench compares the test data of the corresponding Ethernet protocol with the test observation signal. If they are consistent, the function test of the corresponding Ethernet protocol passes; otherwise, the function test of the corresponding Ethernet protocol fails.

[0039] Further, each function test selects one Ethernet protocol from GMII\MII\RGMII\TBI\RTBI\SGMII and one data transmission rate from 10 / 100 / 1000BASE T to cooperate for data transmission.

[0040] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0041] The test method for an Ethernet PHY chip provided by the present invention can realize a comprehensive test covering function test and parameter test of the Ethernet PHY chip, and well solves the problem of the large difficulty in writing the test PATTERN of the existing test method for an Ethernet PHY chip.

[0042] The test method for the Ethernet PHY chip provided by the present invention controls the decoder through the ATE test bench to load the IP cores of different Ethernet protocols into the FPGA time-divisionally, and adds the transmission of Ethernet data frames during the test process in cooperation with the PHY chip under test. Finally, a one-key test for the entire process controlled by the ATE is realized. After receiving the data sent by the ATE, the FPGA can automatically generate Ethernet data frames, calculate the cyclic redundancy check code automatically after modifying the data, without parsing the Ethernet protocol, avoiding writing complex protocols back to the test PATTERN by hand, and facilitating the debugging of the test development process. In addition, the PHY chip under test is directly controlled through the ATE test bench, and complex Ethernet data frames are parsed to implement the coverage test of the DC parameters of the PHY chip under test.

[0043] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combined solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can be made obvious from the description, or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the description and the drawings. Description of the Drawings

[0044] The drawings are only for the purpose of showing specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;

[0045] Figure 1 is a flowchart of the test method for the Ethernet PHY chip;

[0046] Figure 2 is a schematic structural diagram of the test system for the Ethernet PHY chip;

[0047] Figure 3 is a schematic structural diagram of the MAC layer communication path in the test system for the Ethernet PHY chip;

[0048] Figure 4 is a schematic structural diagram of the PHY communication path in the test system for the Ethernet PHY chip;

[0049] Figure 5 is a block diagram of the logic resources of the test board in the test system for the Ethernet PHY chip;

[0050] Figure 6 is a schematic diagram of the connection method of the GMII interfaces of the PHY chip under test and the reference PHY chip to the communication pins of the MAC layer of the FPGA;

[0051] Figure 7 is a schematic internal logic diagram of the core FPGA GMII IP core;

[0052] Figure 8 Schematic diagram of the connection method of the MII interfaces of the PHY chip to be tested and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA

[0053] Figure 9 Internal logic schematic diagram of the core FPGA MII IP core

[0054] Figure 10 Schematic diagram of the connection method of the RGMII interfaces of the PHY chip to be tested and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA

[0055] Figure 11 Internal logic schematic diagram of the core FPGA RGMII IP core

[0056] Figure 12 Schematic diagram of the connection method of the TBI interfaces of the PHY chip to be tested and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA

[0057] Figure 13 Internal logic schematic diagram of the core FPGA TBI IP core

[0058] Figure 14 Schematic diagram of the connection method of the RTBI interfaces of the PHY chip to be tested and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA

[0059] Figure 15 Internal logic schematic diagram of the core FPGA RTBI IP core

[0060] Figure 16 Schematic diagram of the connection method of the SGMII interfaces of the PHY chip to be tested and the countermeasure PHY chip and the connection to the MAC layer of the FPGA

[0061] Figure 17 Internal logic schematic diagram of the core FPGA SGMII IP core

[0062] Figure 18 Internal logic schematic diagram of the core FPGA GMII (TO FIBER) IP core Specific implementation manners

[0063] The following will specifically describe the preferred embodiments of the present invention in conjunction with the accompanying drawings. Among them, the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0064] In order to avoid repeatedly parsing complex communication protocols during the test development process, this embodiment provides the following test method for an Ethernet PHY chip to solve the above problems existing in the test process of the Ethernet PHY chip.

[0065] A test method for an Ethernet PHY chip, the flowchart is as Figure 1 shown, and the test method includes:

[0066] Step S1: The ATE test bench controls the pins of the PHY chip under test to be connected to the ATE test bench, sends test data for parameter testing to the PHY chip under test, and performs parameter testing on the PHY chip under test;

[0067] Step S2: The ATE test bench controls the pins of the PHY chip under test to be connected to the FPGA, sends test data for functional testing of the Ethernet protocol to the FPGA, and the FPGA controls the test data to communicate between the PHY chip under test and the countermeasure PHY chip, and performs functional testing of the Ethernet protocol on the PHY chip under test.

[0068] The ATE test bench stores the test data and test instructions for each parameter test of the PHY chip under test; in step S1, the ATE test bench performs parameter testing on the PHY chip under test and executes:

[0069] Step S11: The ATE test bench controls the connection mode between the ATE test bench and the pins of the PHY chip under test according to the test instructions of the current parameter test;

[0070] Step S12: The ATE test bench sends test data for the corresponding parameter test to the PHY chip under test and samples back the test observation signals of the corresponding parameter test fed back by the PHY chip under test;

[0071] Step S13: The ATE test bench determines whether the corresponding parameter test passes based on the test observation signals of the corresponding parameter test.

[0072] During the process of the ATE test bench performing parameter testing on the PHY chip under test, the ATE test bench configures and reads out the registers of the PHY chip under test through the MDIO pin, and configures the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode. The ATE test bench sends test data for the corresponding parameter test to the PHY chip under test through the TX pin of the ATE test bench, and uses the receiving RX of the ATE test bench to sample back the test observation signals of the corresponding parameter test fed back by the PHY chip under test. In this embodiment, both the test data and the test observation signals of the parameter test are data frames in the GMII format.

[0073] The ATE test bench also stores the test data and test instructions for each functional test of the Ethernet protocol of the PHY chip under test.

[0074] In step S2, the ATE test bench performs a functional test of the Ethernet protocol on the PHY chip under test, and executes:

[0075] Step S21: The ATE test bench controls the PHY chip under test to power on.

[0076] Step S22: The FPGA loads the corresponding Ethernet protocol controller IP core according to the test instructions of the current Ethernet protocol functional test, and controls the pin connection mode between the FPGA and the PHY chip under test.

[0077] After the handshake between the PHY chip under test and the countermeasure PHY chip is successful, the FPGA uses the corresponding Ethernet protocol controller IP core to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and controls the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip under test and the countermeasure PHY chip.

[0078] In step S23, the following operations are specifically executed:

[0079] Step S231: The FPGA configures the CONFIG and HWCFG MODE of the PHY chip under test and the countermeasure PHY chip through the IO pins.

[0080] Step S232: The FPGA sends a reset signal to the PHY chip under test and the countermeasure PHY chip. The PHY chip under test and the countermeasure PHY chip start to reset and respectively collect their own hardware configuration information, and then perform a handshake and auto-negotiation, waiting for the handshake between the PHY chip under test and the countermeasure PHY chip to be successful.

[0081] After the handshake between the PHY chip under test and the countermeasure PHY chip is successful, the ATE test bench sends test data to the IO port of the FPGA through the test PATTERN, and the received FIFO of the FPGA receives the test data of the corresponding Ethernet protocol from the ATE test bench; so that the FPGA uses the corresponding Ethernet protocol controller IP core to convert the test data of the corresponding Ethernet protocol in the received FIFO into the first data frame of the corresponding Ethernet protocol.

[0082] Specifically, in the FPGA, the first data frame of the Ethernet protocol is obtained by performing the following operations:

[0083] The FPGA generates two identical MAC controllers of the corresponding Ethernet protocol based on the loaded Ethernet protocol controller IP core; one MAC controller is responsible for communicating with the PHY chip under test, and the other MAC controller is responsible for communicating with the countermeasure PHY chip;

[0084] Two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert it into the first data frame of the corresponding Ethernet protocol, and send the first data frame of the corresponding Ethernet protocol to the PHY chip under test or the peer PHY chip connected by communication.

[0085] Step S24: The FPGA parses the second data frames returned by the PHY chip under test and the peer PHY chip to obtain the test observation signals of the corresponding Ethernet protocol.

[0086] The specific execution of step S24 is as follows:

[0087] Step S241: After the PHY chip under test and the peer PHY chip respectively pass the verification of the received first data frame, they send the first data frame to each other at a preset data transmission rate.

[0088] Step S242: After both parties receive the first data frame and pass the verification, they convert the first data frame into a data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame.

[0089] Step S243: The FPGA parses the second data frame and stores the data after parsing the second data frame as the test observation signal of the corresponding Ethernet protocol in the transmit FIFO of the FPGA.

[0090] Step S25: The ATE test bench determines whether the function test of the corresponding Ethernet protocol passes based on the test observation signal of the corresponding Ethernet protocol.

[0091] Specifically, step S25 is executed as follows:

[0092] Step S251: The ATE test bench sends a read valid signal and a read clock to the FPGA to read the test observation signal in the transmit FIFO of the FPGA.

[0093] Step S252: The ATE test bench compares the test data of the corresponding Ethernet protocol with the test observation signal. If they are consistent, the function test of the corresponding Ethernet protocol passes; otherwise, the function test of the corresponding Ethernet protocol fails.

[0094] Preferably, each function test selects one Ethernet protocol from GMII\MII\RGMII\TBI\RTBI\SGMII and one data transmission rate from 10 / 100 / 1000BASE T to cooperate for data transmission.

[0095] The test method in this embodiment is coordinated with the test system. Next, the test system is introduced as follows, and then the specific content of each function test and parameter test is described in detail.

[0096] In this embodiment, the schematic structural diagram of the test system for the Ethernet PHY chip is as follows Figure 2 shown. The test system includes: an ATE test bench, an FPGA, and a PHY chip for cross-testing. Among them, the ATE test bench is used to store the test data and test instructions for the functional test of each Ethernet protocol of the PHY chip to be tested; the FPGA is used to load the controller IP core of the corresponding Ethernet protocol based on the test instructions of the corresponding Ethernet protocol when performing the functional test of each Ethernet protocol of the PHY chip to be tested; and use the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and control the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip to be tested and the PHY chip for cross-testing; it also parses the second data frame returned by the PHY chip to be tested and the PHY chip for cross-testing to the FPGA to obtain the test observation signal of the corresponding Ethernet protocol; the ATE test bench also determines whether the functional test of the corresponding Ethernet protocol passes based on the test observation signal of the corresponding Ethernet protocol.

[0097] Preferably, the test system further includes a control decoder and a configuration memory corresponding to each Ethernet protocol. Among them, the control decoder is used to receive the test instructions of the Ethernet protocol sent by the ATE test bench to generate the control instructions for the configuration memory corresponding to the corresponding Ethernet protocol; the configuration memory selects the controller IP core of the corresponding Ethernet protocol based on the control instructions for the FPGA to load.

[0098] Preferably, the test system further includes a relay control module; the controller IP core of the Ethernet protocol includes the control logic of the corresponding Ethernet protocol, and the control logic includes the pin connection method between the FPGA and the PHY chip to be tested; at this time, the relay control module is used to control the switching of the pin connection or disconnection between the PHY chip to be tested and the FPGA according to the controller IP core of the corresponding Ethernet protocol when performing the functional test of each Ethernet protocol of the PHY chip to be tested.

[0099] In addition, the test system further includes a system clock and a power conversion chip. Among them, the system clock is used to provide clock signals for the FPGA, the PHY chip to be tested, and the PHY chip for cross-testing. The power conversion chip is used to supply power to the test system. In the test system for the Ethernet PHY chip provided in this embodiment, the FPGA, the PHY chip for cross-testing, the control decoder, the configuration memory, the relay control module, the system clock, and the power conversion chip are all arranged on the test board.

[0100] Next, the overall technical concept of the test system for the Ethernet PHY chip provided in this embodiment will be described as follows: All devices on the test board are directly powered by the ATE test bench or powered by the ATE through a power conversion chip. To establish a LINK relationship with the PHY chip under test for normal data transmission, in the test system provided in this embodiment, additional content for cooperative testing of the PHY chip under test is added. The FPGA is responsible for receiving test data from the ATE test bench, converting the test data into the first data frame of the corresponding Ethernet protocol, and performing protocol transceiver between the MAC controller, the PHY chip under test, and the PHY chip under test. The test process needs to cover various Ethernet protocol formats such as GMII, MII, RGMII, TBI, RTBI, and SGMII. Each Ethernet protocol format requires a different controller IP core for scheduling and control. Therefore, in the test system provided in this embodiment, a control decoder is added, and different control instructions select different configuration memories for the FPGA to load the controller IP cores of different protocols. During the functional test of the Ethernet protocol, the communication pins of the PHY chip under test are connected to the IO pins of the FPGA and the PHY chip under test through a relay control module, and the ATE test bench does not directly participate in the communication. In addition, the test system may further include a JTAG interface, which is used to load the controller IP cores of different Ethernet protocols into the FPGA during the debugging process. The relay control module is also used to control the switching of the connection or disconnection between the pins of the PHY chip under test and the digital channels of the ATE test bench. During the parameter test, the connection relationship between the FPGA and the PHY chip under test is released, and the PHY chip under test is directly connected to the ATE to implement input / output parameter testing. By switching the pin connection method of the PHY chip under test through the relay control module, the parameter coverage testing of the PHY chip under test is realized. That is, the parameter test of the PHY chip under test is directly controlled by the ATE test bench: the ATE test bench directly sends the test data for the corresponding parameter test to the PHY chip under test and samples back the test observation signals fed back by the PHY chip under test for the corresponding parameter test; the ATE test bench determines whether the corresponding parameter test passes based on the test observation signals of the corresponding parameter test. It should be emphasized that before the parameter test, the ATE test bench configures the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode to sample back the test observation signals fed back by the PHY chip under test.

[0101] Specifically, the design scheme on the test board in the test system can also be disassembled into Figure 3 and Figure 4 shown in two parts. Among them, Figure 3 represents the structural schematic diagram of the MAC layer communication path in the test system of the Ethernet PHY chip, Figure 4The schematic diagram of the structure of the PHY communication path in the test system of the Ethernet PHY chip. The above two figures are actually integrated on a test board. Because the MAC layer and the PHY communication path are different, two figures are used to distinguish them. PHY belongs to the physical layer; MAC belongs to the data link layer and is mainly responsible for controlling and connecting the physical medium of the physical layer. The logical resource block diagram of the test board in the test system of the Ethernet PHY chip is as follows Figure 5 As shown in the figure, in order to complete the joint functional test of multiple Ethernet protocols and DC parameter test of the PHY chip to be tested, the test board includes a test adapter (for carrying the PHY chip to be tested), the PHY chip to be tested, FPGA, power conversion chip, system clock, relay control module, configuration memory, JTAG interface, optical fiber interface and manual reset. The main components in the test system are introduced in detail below.

[0102] (1) Power supply

[0103] All devices on the test board need working voltages of 1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, etc. to work normally. In order to facilitate debugging and subsequent normalized management and use, this embodiment makes a power conversion chip that can realize voltage conversion from 5V to all the above voltages. The 5V power input comes from the 5V DC source and external port of the ATE test bench respectively: during offline debugging, the 5V power supply is connected by an external voltage regulator to power all devices on the test board, and the test board can be debugged and worked offline without the ATE test bench; during the debugging of the ATE test bench, the physical connection between the PHY chip to be tested and the power conversion chip is manually disconnected, and the digital channel of the ATE test bench is used to power the AVDD, CVDD and DVDD of the PHY chip to be tested, so as to facilitate the measurement of the power consumption of the PHY chip to be tested during the test, and other devices on the test board are still powered by the power conversion chip.

[0104] (2) System clock

[0105] In this embodiment, the system clock is an Ethernet clock generator. For example, the Ethernet clock generator uses AD9571. In the specific implementation process, a 25M active crystal oscillator is selected as the clock reference as the clock input of AD9571, and the working reference clocks of the FPGA, the PHY chip to be tested, and the PHY chip to be tested are all generated by AD9571.

[0106] Exemplarily, the 125M and 100M clock references generated by the AD9571 are output to a clock buffer (such as the LMK1D1024). The FPGA controls the 2-to-1 selection of the clock reference to use 100M or 125M, and finally outputs it as a clock synchronization signal to the GTX module of the FPGA, the PHY chip under test, and the SGMII interface of the countermeasure PHY chip.

[0107] (3) FPGA (including configuration memory and control part)

[0108] The FPGA is the core device for implementing the test function in this embodiment. The communication protocols of the PHY chip under test and the countermeasure PHY chip are both configured by the FPGA. The FPGA packs the test data sent by the ATE test bench into data frames corresponding to the Ethernet protocol through the built-in MAC controller, and sends the data frames of the Ethernet protocol (i.e., the "first data frames") to the PHY chip under test and the countermeasure PHY chip through the MAC layer. Subsequently, it receives the data frames (i.e., the "second data frames") sent by the PHY chip under test and the countermeasure PHY chip in full duplex, unpacks the data frames (i.e., the "second data frames"), and sends the parsed data (test observation signals) back to the ATE through the IO interface for comparison.

[0109] During the test process, multiple Ethernet protocol formats are involved, and the FPGA needs to load the controller IP cores of different Ethernet protocols multiple times in a time-sharing manner to implement MAC controllers of different protocols. Set the configuration pins M[2:0] of the FPGA to 001, and the configuration method is the main MASTER SPI. Exemplarily, in this embodiment, 8 configuration memories are set to store the controller IP cores of different Ethernet protocols respectively. The 8 configuration memories are selected by the control decoder. The ATE test bench controls the 3-way chip select signals A0, A1, and A2 of the control decoder to determine which configuration memory the FPGA starts from. After the FPGA is powered on, it automatically loads the corresponding Ethernet protocol controller IP core from the selected configuration memory. The IO ports of the FPGA are respectively connected to the PHY chip under test and the countermeasure PHY chip under test, mainly including all data ports for data transfer between the MAC layer and the PHY. In the specific implementation process, the control core preferably uses a high-performance FPGA with a GTX high-speed SEEDS interface, and the actual FPGA model selected is XC7K325T-FFG900I.

[0110] (4) PHY chip under test and countermeasure PHY chip (including relay control part)

[0111] The actual package sizes of the reference PHY chip and the PHY chip under test are the same. During the test process, the reference PHY chip is directly soldered onto the test board. To enable the testing of different PHY chips under test, the PHY chip under test is fixed to the test board in a screwing manner through a test adapter.

[0112] The communication pins of the MAC layer of the reference PHY chip are directly connected to the FPGA. The reference PHY chip is directly powered by a power conversion chip. The communication ports MDI[3:0] of the reference PHY chip and the PHY chip under test are connected after signal conditioning through a high-speed Ethernet transformer.

[0113] The communication pins of the MAC layer of the PHY chip under test are not directly connected to the FPGA, nor are the power pins directly connected to the digital channels of the ATE test bench or the power conversion chip. The pins of the PHY chip under test are controlled by a relay control module. According to the current test item (functional test or parameter test), the communication pins are selected to be connected to the FPGA or the digital channels of the ATE test bench. The power pins are connected manually and are powered by the power conversion chip during off-line debugging. The ATE test bench also stores the test instructions for each parameter test of the PHY chip under test. The test instructions for the parameter test are used to configure the connection mode between the ATE test bench and the pins of the PHY chip under test for each parameter test. The relay control module is used to control the switching of the connection or disconnection of the pins between the PHY chip under test and the ATE test bench according to the test instructions for the parameter test when performing the parameter test of the PHY chip under test. Specifically, when the ATE test bench performs the parameter test, it is powered by the ATE test bench and the power consumption current is tested in real time. A relay control module is selected to switch the pins of the PHY chip under test to control the switching of the connection or disconnection of the pins between the PHY chip under test and the ATE test bench. On the one hand, it is convenient to test the pin connection of the PHY chip under test. On the other hand, to parse the communication protocol, the PHY chip under test can directly communicate with the ATE test bench to perform the input and output level tests.

[0114] (5) Hardware configuration part

[0115] The PHY chip under test and the reference PHY chip allow the working mode to be set through the Config[6:0] pins, including physical address, PHY operation mode, auto-negotiation, and MID crossover configuration. All these can be achieved through hardware configuration, thus avoiding direct access to internal registers. The registers for hardware configuration can be modified and overwritten through MDIO.

[0116] Table 2 LED corresponding hardware control codes

[0117] Pin Bit[2:0] VDDO 111 LED_LINK10 110 LED_LINIK100 101 LED_LINK1000 100 LED_DUPLEX 011 LED_RX 010 LED_TX 001 VSS 000

[0118] Registers corresponding to the CONFIG signal in Table 3

[0119] Pin Bit[2] Bit[1] Bit[0] CONFIG0 <![CDATA[PHYADR[2] 1 > PHYADR[1]1 <![CDATA[PHYADR[0] 1 > CONFIG1 ENA_PAUSE <![CDATA[PHYADR[4] 1 > <![CDATA[PHYADR[3] 1 > CONFIG2 ANEG[3] ANEG[2] ANEG[1] CONFIG3 ANEG[0] ENA_XC DIS_125 CONFIG4 HWCFG_MoDE[2] HWCFG_MODE[1] HWCFG_MODE[0] CONFIG5 DIS_FC DIS_SLEEP HWCFG_MODE[3] CONFIG6 SEL_TWSI INT_POL 75 / 50OHM

[0120] The PHY chip under test maps the common mode registers to Config[6:0] (Table 3), and at the same time assigns values to the LED hardware control codes (Table 2). Table 4 shows the register configuration information corresponding to different working modes. As can be seen from Table 3, the hardware configuration of the registers in Table 4 can be completed through CONFIG4 and CONFIG5. The test process in this embodiment mainly involves the HWCFG MODE[3:0] bits of the registers.

[0121] Table 4 Register settings corresponding to different working modes

[0122]

[0123] During the test process, CONFIG4 and CONFIG5 are respectively connected to the control decoder, and three inputs of the controller decoder are controlled through the IO pins of the FPGA to ensure that CONFIG is connected to one of the LEDs, thus completing the assignment of the LED hardware control code in Table 2 to CONFIG, and thus realizing the assignment of the HWCFG MODE[3:0] of the registers, and realizing the hardware setting of the working modes of the PHY chip under test and the PHY chip under test.

[0124] In addition to the above-discussed content, the test board also includes a fiber optic interface, which is mainly used for data transmission in fiber optic communication (FIBER itself is optical communication, and SGMII and FIBER share a high-speed differential interface, so time division multiplexing needs to be carried out through a relay control module); a JTAG interface, which is used for real-time configuration of the FPGA during the debugging process and for solidifying the configuration memory at the FPGA end. After the debugging is completed, this interface is not used during the actual test process. The test system can also include a manual reset port, which is used for resetting the FPGA during the debugging process. There are also other buffers, which are used for signal isolation and buffering, and will not be elaborated here.

[0125] For the entire data transmission process of the PHY chip under test, a complete communication link between the MAC and the PHY, as well as a complete LINK relationship between the PHY chip under test and the countermeasure PHY chip, are required. A functional test will select one of SGMII / GMII / MII / RGMII / TBI / RTBI and one of 10 / 100 / 1000BASE T to cooperate for data transmission. During the actual test process, the COPPER side communicates at the highest test rate allowed by the protocol. Seven MAC layer IP cores (i.e., "controller IP cores") are required for test scheduling and transmission, and the specific control port configurations are as shown in Table 5 below:

[0126] Table 5 Correspondence between control terminals and MAC layer IP cores

[0127] Serial number Control terminal (A[2:0]) MAC layer protocol 1 000 GMII TO COPPER(1000BASET) 2 001 MII TO COPPER(10BASET) 3 010 RGMII TO COPPER(1000BASET) 4 011 TBI TO COPPER(1000BASET) 5 100 RTBI TO COPPER(1000BASET) 6 101 SGMII TO COPPER(1000BASET) 7 110 FIBER TO COPPER(1000BASET)

[0128] 1. GMII TO COPPER protocol transmission

[0129] (1) Protocol overview

[0130] GMII (Gigabit Media Independant Interface), a gigabit MII interface. GMII uses 8-bit interface data, has a working frequency of 125MHZ, and a data transmission speed of up to 1000Mbps. It is also compatible with the 10 / 100Mbps working mode specified by MII. The GMII interface data structure conforms to the IEEE Ethernet standard. The schematic diagram of the connection method between the GMII interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 6 shown.

[0131] (2) Test implementation

[0132] Install the test board on the ATE test bench, turn on the power-on button of the power conversion chip, and power on all other devices on the test board except the PHY chip under test through the power conversion chip. Start the test. The digital channel of the ATE test bench provides the voltage required for the normal operation of the PHY chip under test, and the PHY chip under test is powered on. Use the test vector to set the configuration pins A[2:0] of the control decoder to 000 according to Table 4. The FPGA loads the GMII controller IP core from the 0th configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the countermeasure PHY chip through the IO pins. Set HWCFG MODE[3:0] to 1111, and then send a reset signal. The PHY chip under test and the countermeasure PHY chip start to reset and respectively collect their own hardware configuration information, and then perform handshaking and auto-negotiation. It should be noted that the hardware configuration information of the PHY chip under test and the countermeasure PHY chip is kept consistent to ensure mutual communication.

[0133] From the start of the test until the handshake is successful, the ATE test bench keeps waiting through the test pattern. A fixed waiting time is obtained through multiple tests, and this time needs to ensure the successful handshake between the PHY chip under test and the countermeasure PHY chip. After the waiting ends, the ATE test bench sends test data to specific IO ports of the FPGA (ports written and agreed inside the FPGA for observing the FPGA output) through the test pattern. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in GMII format and sends this first data frame to the PHY chip under test and the countermeasure PHY chip respectively. After receiving the first data frame in GMII format, after verifying the integrity of the first data frame, the PHY chip under test and the countermeasure PHY chip send the first data frame to each other through the MDI[3:0] interface at the data transfer rate of 1000BASE T. After receiving the first data frame, both sides verify whether the first data frame is intact, and then convert the first data frame into a data frame in GMII format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in GMII format sent by the PHY chip under test and the countermeasure PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the GMII protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the parsed data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0134] (3) Programming idea of the controller IP core

[0135] The GMII controller IP core mainly includes five parts: the receive FIFO, the transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, and the control logic (placed inside the controller IP core). Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the GMII-1000BASE T method, send a reset signal, and control the acquisition of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read the test data into and store it in the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers pack the test data and finally form data frames in GMII format for the PHY chip under test and the countermeasure PHY chip. The data frames in GMII format are sent through the physical interfaces of the MAC and PHY. Figure 7Internal logic schematic diagram of the core FPGA GMII IP core.

[0136] The PHY chip under test and the countermeasure PHY chip simultaneously receive data frames in GMII format from the MAC layer and perform full-duplex communication at a data transmission rate of 1000BASE-T. Two MAC controllers respectively receive the data frames in GMII format from the PHY chip under test and the countermeasure PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO of the FPGA. The transmit FIFO drives the data back to the ATE test bench under the ATE read signal for comparison. The actually received data should be exactly the same as the transmitted data. If the comparison is successful, it proves that the GMII-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0137] 2. MII TO COPPER protocol transmission

[0138] (1) Protocol brief

[0139] MII, namely Media Independent Interface, is also called Media Access Control (MAC) and Physical Layer (PHY) Interface. It is an Ethernet industry standard defined by IEEE-802.3. It includes a 4-bit data interface and a management interface between the MAC and the PHY. The data interface is used for two independent channels for the transmitter and the receiver respectively. Each channel has its own data, clock, and control signals. MII transmits data bidirectionally in 4-bit nibble mode, with a clock rate of 25 MHz and a working speed of up to 100 Mb / s. When the clock rate is 2.5 MHz, the corresponding speed is 10 Mb / s. Although the MII interface is flexible, due to the limitation of the transceiver rate, it has been gradually replaced by GMII. The schematic diagram of the connection method between the MII interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 8 shown. Compared with GMII, the MII interface only reduces the data bits from 8 bits to 4 bits, and other control bits and working modes remain unchanged.

[0140] (2) Test implementation

[0141] Start the test. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 001 according to Table 4 using the test vector. The FPGA loads the MII controller IP core from the first configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Set HWCFG MODE[3:0] to 1111, i.e., the GMII-COPPER mode. Then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshaking and auto-negotiation. Assign the register with address 4 the value 0041 to configure the data transfer rate to 10M and convert the GMII protocol to the MII protocol; assign the register with address 0 the value 8000, and the PHY chip under test and the paired PHY chip start a soft reset and perform handshaking and auto-negotiation again.

[0142] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that the PHY chip under test and the paired PHY chip complete a successful handshake; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in MII format and sends this first data frame to the PHY chip under test and the paired PHY chip respectively; after the PHY chip under test and the paired PHY chip receive the first data frame in MII format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at a data transfer rate of 10BASE T; after both parties receive the first data frame, they verify whether the first data frame is intact, then convert the first data frame into a data frame in MII format and send it as the second data frame to the FPGA; the FPGA receives the second data frames in MII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data; and stores the parsed data as the test observation signal of the MII protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0143] (3) Programming idea of the controller IP core

[0144] The MII controller IP core mainly consists of six parts: a receive FIFO, a transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, control logic, and MDIO read / write. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the GMII-10BASE-T method, send a reset signal, control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset, and ensure the effectiveness of the hardware configuration; configure the memories of the PHY chip under test and the countermeasure PHY chip through the MDIO interface, modify the GMII format to the MII format, and at the same time start a soft reset and perform a PHY chip handshake again. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock; after the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the MII data frames of the PHY chip under test and the countermeasure PHY chip. The MII data frames are sent through the physical interfaces of the MAC and PHY. Figure 9 It is the internal logic schematic diagram of the core FPGA MII IP core.

[0145] The PHY chip under test and the countermeasure PHY chip simultaneously receive the MII format data frames at the MAC layer and perform full-duplex communication at the data transfer rate of 10BASE-T; the two MAC controllers respectively receive the MII format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO of the FPGA. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal; the actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the MII-10BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0146] 3. Transmission of the RGMII TO COPPER protocol

[0147] (1) Protocol brief description

[0148] RGMII (Reduced Gigabit Media Independant Interface), a reduced GMII interface. Compared with GMII, RGMII has the following characteristics: the transmit / receive data lines are reduced from 8 to 4, TX_ER and TX_EN are multiplexed and transmitted through TX_CTL, RX_ER and RX_EN are multiplexed and transmitted through RX_CTL. Although the RGMII signal lines are halved, the TXC / RXC clock is still 125MHZ. To achieve a transmission rate of 1000Mbit, the TXD / RXD signal lines transmit / receive TXD[3:0] / RXD[3:0] in the GMII interface at the rising edge of the clock and transmit / receive TXD[7:4] / RXD[7:4] at the falling edge of the clock. The schematic diagram of the connection method between the RGMII interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 10 shown. Compared with GMII, RGMII simplifies both the control signal and the data bit width. To ensure the data transmission rate, the DDR method is used for data transmission to achieve the same data transmission rate as GMII.

[0149] (2) Test implementation

[0150] Start the test. The digital channel of the ATE test bench provides the voltage required for the normal operation of the PHY chip under test, and the PHY chip under test is powered on. Use the test vector to set the configuration pins A[2:0] of the control decoder to 010 according to Table 4, and the FPGA loads the RGMII controller IP core from the second configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the countermeasure PHY chip through the IO pins. Specifically: assign the control code 011 of the LED_DUPLEX signal to CONFIG4 of the PHY chip under test and the countermeasure PHY chip through the control decoder TMUX1308; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5 of the PHY chip under test and the countermeasure PHY chip; through the above hardware configuration, the register HWCFGMODE[3:0] is set to 1011, corresponding to the RGMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the countermeasure PHY chip start to reset and collect the hardware configuration information, and then perform handshaking and auto-negotiation.

[0151] From the start of the test until the handshake is successful, the ATE keeps waiting through the test pattern. Through multiple tests, a fixed waiting time is obtained, which needs to ensure the successful handshake between the PHY chip under test and the countermeasure PHY chip. After the waiting ends, the ATE sends test data to specific IO ports of the FPGA through the test pattern. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in RGMII format and sends this first data frame to the PHY chip under test and the countermeasure PHY chip respectively. After receiving the first data frame in RGMII format, and after verifying the integrity of the first data frame, the PHY chip under test and the countermeasure PHY chip send the first data frame to each other through the MDI[3:0] interface at the data transfer rate of 1000BASE T. After receiving the first data frame, both sides verify whether the first data frame is intact, and then convert the first data frame into a data frame in RGMII format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in RGMII format sent by the PHY chip under test and the countermeasure PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the RGMII protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0152] (3) Programming idea of the controller IP core

[0153] The RGMII controller IP core mainly includes five parts: receive FIFO, transmit FIFO, MAC controller of the PHY chip under test, MAC controller of the countermeasure PHY chip, and control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate in the RGMII-1000BASE T mode, send a reset signal, and control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read the test data into and store it in the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers pack the test data and finally form the RGMII data frames of the PHY chip under test and the countermeasure PHY chip, and the data frames are sent through the physical interfaces of the MAC and PHY. Figure 11 Schematic diagram of the internal logic of the core FPGA RGMII IP core.

[0154] The PHY chip under test and the paired PHY chip simultaneously receive data frames in RGMII format from the MAC layer and conduct full-duplex communication at a data transfer rate of 1000BASE-T. Two MAC controllers respectively receive the data frames in RGMII format from the PHY chip under test and the paired PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO. The transmit FIFO drives the data back to the ATE test bench under the ATE read signal for comparison. The actually received data should be exactly the same as the transmitted data. If the comparison is successful, it proves that the RGMII-1000BASE-T links of the PHY chip under test and the paired PHY chip are intact and meet the requirements of the data manual.

[0155] 4. Transmission of TBI TO COPPER Protocol

[0156] (1) Protocol Overview

[0157] TBI (Ten Bit Interface): The interface data bit width is increased from 8 bits of the GMII interface to 10 bits. In fact, the TBI interface and the GMII interface are not very different. The extra 2 bits of data are mainly because: under the TBI interface, the MAC chip performs an 8B - 10B transformation before sending the data to the PHY chip. Due to the increase in the data bit width, the data transfer rate increases from 1000 Mbps of the GMII interface to 1.25 Gbps. The TBI interfaces of most chips are compatible with the GMII interface. When used as a TBI interface, CRS and COL are generally not used. The schematic diagram of the connection method between the TBI interfaces of the PHY chip under test and the paired PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 12 shown.

[0158] (2) Test Implementation

[0159] Start the test. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 011 according to Table 4 using the test vector. The FPGA loads the TBI controller IP core from the 3rd configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 101 of the LED_LINK100 signal to CONFIG4; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 1101, corresponding to the TBI TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshaking and auto-negotiation.

[0160] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that the PHY chip under test and the paired PHY chip have a successful handshake; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in TBI format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively; after the PHY chip under test and the paired PHY chip receive the first data frame in TBI format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at the data transfer rate of 1000BASE T; after both parties receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in TBI format and send it to the FPGA as the second data frame; the FPGA receives the second data frames in TBI format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data; and stores the parsed data as the test observation signal of the TBI protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronous signal of the ATE test bench.

[0161] (3) Programming idea of the controller IP core

[0162] The controller IP core of TBI mainly includes five parts: a receive FIFO, a transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, and control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the TBI-1000BASE T mode, send a reset signal, and control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the TBI data frames of the PHY chip under test and the countermeasure PHY chip. The TBI data frames are sent through the physical interfaces of the MAC and PHY. Figure 13 It is the internal logic schematic diagram of the core FPGA TBI IP core.

[0163] The PHY chip under test and the countermeasure PHY chip simultaneously receive the TBI format data frames at the MAC layer and perform full-duplex communication at the data transfer rate of 1000BASE-T. The two MAC controllers respectively receive the TBI format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the TBI-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0164] 5. RTBI TO COPPER Protocol Transmission

[0165] (1) Protocol Summary

[0166] RTBI (Reduced Ten Bit Interface), that is, a simplified TBI interface, with an interface data width of 5 bits and a clock frequency of 125 MHZ. Sampling is performed twice at the rising and falling edges of the clock. Finally, the data transfer rate is the same as that of TBI, but the interface is further simplified. The schematic diagram of the connection method between the RTBI interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 14 shown.

[0167] (2) Test Implementation

[0168] Start the test. The digital channels of the ATE test bench provide the voltages required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 100 according to Table 4 using the test vector. The FPGA loads the controller IP core of RTBI from the 4th configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG4; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 1001, corresponding to the RTBI TO COPPER communication protocol mode in Table 4. Then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshake and auto-negotiation.

[0169] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that the PHY chip under test and the paired PHY chip handshake successfully. After the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in RTBI format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively. After the PHY chip under test and the paired PHY chip receive the first data frame in RTBI format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at the data transfer rate of 1000BASE T. After both parties receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in RTBI format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in RTBI format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the RTBI protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0170] (3) Programming idea of the controller IP core

[0171] The controller IP core of RTBI mainly includes five parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the countermeasure PHY chip, and control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the RTBI-1000BASE T method, send a reset signal, control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset, and ensure the effectiveness of the hardware configuration; the receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data in the receive FIFO under the drive of the write clock; after the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the RTBI data frames of the PHY chip under test and the countermeasure PHY chip. The RTBI data frames are sent through the physical interfaces of the MAC and PHY. Figure 15 Schematic diagram of the internal logic of the core FPGA RTBI IP core.

[0172] The PHY chip under test and the countermeasure PHY chip simultaneously receive the RTBI format data frames at the MAC layer and perform full-duplex communication at a data transfer rate of 1000BASE-T; the two MAC controllers respectively receive the RTBI format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal; the actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the RTBI-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0173] 6. SGMII TO COPPER Protocol Transmission

[0174] (1) Protocol Overview

[0175] SGMII, that is, Serial GMII, performs data transceiver through the high-speed serial interfaces of the FPGA and the PHY. There is a pair of differential signal lines for each of the transceiver, with a clock frequency of 625MHZ and sampling at both the rising edge and the falling edge of the clock signal. The schematic diagram of the connection method between the SGMII interfaces of the PHY chip under test and the countermeasure PHY chip and the MAC layer of the FPGA is as Figure 16 shown. SGMII simplifies the communication hardware through a high data rate.

[0176] (2) Test Implementation

[0177] Start the test. The digital channels of the ATE test bench provide the voltages required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 101 according to Table 4 using the test vector. The FPGA loads the SGMII controller IP core from the 5th configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 000 of the VSS signal to CONFIG4; through another TMUX1308, assign the control code 000 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 0000, corresponding to the SGMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshake and auto-negotiation.

[0178] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure the successful handshake of the PHY chip under test and the paired PHY chip; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in SGMII format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively through the high-speed serial interface; after the PHY chip under test and the paired PHY chip receive the first data frame in SGMII format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at the data transfer rate of 1000BASE T; after both parties receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in SGMII format and send it to the FPGA as the second data frame through the high-speed serial transceiver interface; the FPGA receives the data frames in SGMII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frame to obtain the parsed data; and stores the parsed data as the test observation signal of the SGMII protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0179] (3) Programming idea of the controller IP core

[0180] The SGMII controller IP core mainly consists of five parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the countermeasure PHY chip, and control logic. The control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the SGMII-1000BASE T mode, send a reset signal, and control the acquisition of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can recognize the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form SGMII format data frames for the PHY chip under test and the countermeasure PHY chip. The data frames are sent through the physical interfaces of the MAC and PHY. Figure 17 It is the internal logic schematic diagram of the core FPGA SGMII IP core.

[0181] The PHY chip under test and the countermeasure PHY chip simultaneously receive SGMII format data frames at the MAC layer and perform full-duplex communication at a data transfer rate of 1000BASE-T. The two MAC controllers respectively receive the SGMII format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the SGMII-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0182] 7. GMII TO FIBER Protocol Transmission

[0183] (1) Protocol Overview

[0184] For both GMII TO FIBER and GMII TO COPPER communication methods, the communication protocol between the FPGA and the PHY is GMII. The communication protocols between the two PHY chips are different. FIBER is fiber communication through a high-speed serial interface, and COPPER is twisted-pair communication. The FIBER transmission medium and ports are shared with the SGMII interface, namely three pairs of high-speed differential signals: SIN, SOUT, and CLK. When communicating using the SGMII protocol, the three pairs of differential signals are connected to the FPGA. When using GMII TO FIBER for data transmission, the three pairs of differential signals are used for data transmission between the two PHYs.

[0185] (2) Test implementation

[0186] Start the test. Switch the high-speed relay, and interconnect the three pairs of high-speed differential signals of the two PHY chips. The digital channels of the ATE test bench provide the voltage required for the normal operation of the PHY chip under test, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 110 according to Table 4 using the test vector. The FPGA loads the GMII TO COPPER controller IP core from the 6th configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 111 of the VDDO signal to CONFIG4; through another TMUX1308, assign the control code 000 of the VSS signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 0111, corresponding to the GMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect the hardware configuration information, and then perform handshaking and auto-negotiation.

[0187] From the start of the test to the success of the handshake, the ATE has been waiting through the test PATTERN, and a fixed waiting time is obtained through multiple tests. This time needs to ensure the success of the handshake between the PHY chip under test and the paired PHY chip; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in GMII format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively; after the PHY chip under test and the paired PHY chip receive the first data frame in GMII format and verify that the first data frame is intact, they send the first data frame to the other party through the high-speed serial interface; after both parties receive the first data frame, verify whether the first data frame is intact, and then convert the first data frame into a data frame in GMII format and send it to the FPGA as the second data frame; the FPGA receives the second data frames in GMII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data; and stores the parsed data as the test observation signal of the GMII protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronous signal of the ATE test bench.

[0188] (3) Programming idea of the controller IP core

[0189] The GMII controller IP core mainly consists of five parts: the receive FIFO, the transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, and the control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate in the GMII-1000BASE X (FIBER) mode, send a reset signal, and control the acquisition of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can recognize the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the GMII data frames of the PHY chip under test and the countermeasure PHY chip. The data frames are sent through the physical interfaces of the MAC and PHY. Figure 18 Internal logic schematic diagram of the core FPGA GMII (TO FIBER) IP core.

[0190] The PHY chip under test and the countermeasure PHY chip simultaneously receive the GMII format data frames at the MAC layer and perform full-duplex communication through the data transmission rate of the FIBER. The two MAC controllers respectively receive the GMII format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transmit the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the transmitted data. If the comparison is successful, it proves that the GMII-1000BASE-X link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0191] 8. Testing of DC parameters

[0192] According to the chip data manual, the DC parameters mainly include the testing of the power consumption current and the input and output levels. During the parameter testing process, the AVDD, DVDD, and VDDO of the PHY chip under test are directly powered by the digital channels of the ATE test bench, and the power consumption currents of the three power supply terminals of the PHY chip under test can be read during the data transmission process.

[0193] During the functional testing process, data communication is carried out between the FPGA and the PHY chip under test. There is no direct connection relationship between the pins of the PHY chip under test and the digital channels of the ATE test bench. The input and output levels of pins such as TX, RX, and MIDO cannot be tested, and the integrity of the chip pin connections cannot be tested either.

[0194] During the parameter testing process, first use the ATE control relay control module to switch, and switch all the pins of the PHY chip under test to the ATE test bench. Test the integrity of the pin connections of the PHY chip under test. Use the ATE test bench to configure and read the registers of the PHY chip under test through the MDIO pins, configure the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode, parse the GMII Ethernet data frame, send the GMII data frame to the PHY chip under test through the TX pins, use the receiving RX of the ATE test bench to receive the sent GMII data frame, and compare it with the sent data frame. Through the above methods, use the SEARCH test method of modifying the dynamic load multiple times to comprehensively evaluate the input level threshold and the load-bearing capacity of the output level of the PHY chip under test.

[0195] In this embodiment, in order to meet the requirements of technical indicators and cover as many protocol data transmission methods of the PHY chip under test as possible, the research group separately developed 7 functional controller IP cores, namely GMII TO COPPER, MII TO COPPER, RGMII TO COPPER, TBI TO COPPER, RTBI TO COPPER, SGMII TO COPPER, and GMII TO FIBER, to meet the test requirements of different protocols. During the test, use the ATE test bench to control the 3-8 decoder to load the IP cores of different Ethernet protocols time-sharing, and increase the transmission of Ethernet data frames during the test process in cooperation with the PHY chip under test, and finally realize the one-key test of the entire ATE control process. Realize the coverage test of 7 protocols, namely SGMII, GMII, MII, RGMII, TBI, and RTBI, between MAC and PHY. At the same time, traverse protocol formats such as 10BASE T, 100BASE T, 1000BASE T, and 1000BASE X. Among them, the data transmission rate of the SGMII protocol communication method reaches the maximum data transmission rate of the chip, 1250MBPS, meeting the test requirements. During the functional test process, the FPGA is the test core. Develop multiple controller IP cores and use multiple configuration memories to achieve multiple repeated loadings during the test process, enabling the test of multiple protocol formats to be realized through one-key testing; the FPGA generates the MAC controller core. After the FPGA receives the data sent by the ATE, it can automatically generate an Ethernet data frame, calculate the cyclic redundancy check code automatically after modifying the data, and does not need to parse the Ethernet protocol, avoiding writing the complex protocol back to the test PATTERN by hand and facilitating the debugging of the test development process. In addition, switch the pin connection method of the PHY chip under test through the relay control module, and parse the complex Ethernet data frame to realize the coverage test of the DC parameters of the PHY chip under test.

[0196] Those skilled in the art can understand that all or part of the processes of implementing the methods of the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.

[0197] As described above, only the preferred specific embodiments of the present invention are given, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A test method for an Ethernet PHY chip, characterized in that, the test method includes: The ATE test bench controls the pins of the PHY chip under test to be connected to the ATE test bench, sends test data for parameter testing to the PHY chip under test, and performs parameter testing on the PHY chip under test; The ATE test bench controls the pins of the PHY chip under test to be connected to the FPGA, sends test data for functional testing of the Ethernet protocol to the FPGA, and the FPGA controls the test data to communicate between the PHY chip under test and the countermeasure PHY chip, and performs functional testing of the Ethernet protocol on the PHY chip under test.

2. The test method for an Ethernet PHY chip according to claim 1, characterized in that, The ATE test bench stores the test data and test instructions for each parameter test of the PHY chip under test; the ATE test bench performs parameter testing on the PHY chip under test and executes: The ATE test bench controls the connection method between the ATE test bench and the pins of the PHY chip under test according to the test instructions of the current parameter test; The ATE test bench sends test data for the corresponding parameter test to the PHY chip under test and samples back the test observation signals of the corresponding parameter test fed back by the PHY chip under test; The ATE test bench determines whether the corresponding parameter test passes based on the test observation signals of the corresponding parameter test.

3. The test method for an Ethernet PHY chip according to claim 2, characterized in that, During the process of the ATE test bench performing parameter testing on the PHY chip under test: The ATE test bench configures and reads the registers of the PHY chip under test through the MDIO pin, and configures the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode; Sends test data for the corresponding parameter test to the PHY chip under test through the TX pin of the ATE test bench, and uses the receiving RX of the ATE test bench to sample back the test observation signals of the corresponding parameter test fed back by the PHY chip under test; Among them, the test data and test observation signals of the parameter test are both data frames in the GMII format.

4. The test method for an Ethernet PHY chip according to claim 3, characterized in that, The ATE test bench also stores the test data and test instructions for each functional test of the Ethernet protocol of the PHY chip under test; the ATE test bench performs functional testing of the Ethernet protocol on the PHY chip under test and executes: The ATE test bench controls the PHY chip under test to be powered on; The FPGA loads the controller IP core of the corresponding Ethernet protocol according to the test instructions of the current functional test of the Ethernet protocol, and controls the connection method between the FPGA and the pins of the PHY chip under test; After the PHY chip under test and the countermeasure PHY chip complete the handshake successfully, the FPGA uses the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and controls the first data frame of the corresponding Ethernet protocol to communicate between the PHY chip under test and the countermeasure PHY chip; The FPGA parses the second data frames returned by the PHY chip under test and the countermeasure PHY chip to obtain the test observation signals of the corresponding Ethernet protocol. The ATE test bench determines whether the functional test of the corresponding Ethernet protocol passes based on the test observation signals of the corresponding Ethernet protocol.

5. The test method for an Ethernet PHY chip according to claim 4, wherein, when the PHY chip under test and the countermeasure PHY chip succeed in handshaking, execute: The FPGA configures the CONFIG and HWCFG MODE of the PHY chip under test and the countermeasure PHY chip through the IO pins; The FPGA sends a reset signal to the PHY chip under test and the countermeasure PHY chip. The PHY chip under test and the countermeasure PHY chip start to reset and respectively collect their own hardware configuration information, and then perform handshaking and auto-negotiation, waiting for the PHY chip under test and the countermeasure PHY chip to succeed in handshaking.

6. The test method for an Ethernet PHY chip according to claim 5, wherein, after the PHY chip under test and the countermeasure PHY chip succeed in handshaking, the ATE test bench sends test data to the IO port of the FPGA through the test PATTERN, and the received FIFO of the FPGA receives the test data of the corresponding Ethernet protocol from the ATE test bench; so that the FPGA uses the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol in the received FIFO into the first data frame of the corresponding Ethernet protocol.

7. The test method for an Ethernet PHY chip according to claim 6, wherein, in the FPGA, the first data frame of the Ethernet protocol is obtained by performing the following operations: The FPGA generates two identical MAC controllers of the corresponding Ethernet protocol based on the loaded controller IP core of the Ethernet protocol; one MAC controller is responsible for communicating with the PHY chip under test, and the other MAC controller is responsible for communicating with the countermeasure PHY chip; The two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert them into the first data frame of the corresponding Ethernet protocol; and send the first data frame of the corresponding Ethernet protocol to the PHY chip under test or the countermeasure PHY chip connected for communication.

8. The test method for an Ethernet PHY chip according to claim 7, wherein, the PHY chip under test and the countermeasure PHY chip obtain the second data frame by performing the following operations: After the PHY chip under test and the countermeasure PHY chip respectively pass the verification of the received first data frame, they send the first data frame to the other party at the preset data transmission rate; After both parties receive the first data frame and pass the verification, they convert the first data frame into the data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame; The FPGA parses the second data frame and stores the data after parsing the second data frame as the test observation signal of the corresponding Ethernet protocol in the transmit FIFO of the FPGA.

9. The test method for an Ethernet PHY chip according to claim 8, wherein, the ATE test bench determines whether the functional test of the Ethernet protocol passes by performing the following operations: The ATE test bench sends a read valid signal and a read clock to the FPGA, and reads the test observation signals in the transmit FIFO of the FPGA; The ATE test bench compares the test data of the corresponding Ethernet protocol with the test observation signals. If they are consistent, the functional test of the corresponding Ethernet protocol passes; otherwise, the functional test of the corresponding Ethernet protocol fails.

10. The test method for an Ethernet PHY chip according to claim 9, characterized in that, Each functional test selects one Ethernet protocol from GMII\MII\RGMII\TBI\RTBI\SGMII and one data transmission rate from 10 / 100 / 1000BASE T to cooperate for data transmission.

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