Message processing method and device, chip and storage medium

Abstract

The invention discloses a message processing method and device, a chip and a storage medium, and the method comprises the steps: determining a first processing core for processing a message when a to-be-sent message is detected; when it is determined that the first processing core for processing the message is an A core, the to-be-sent message is sent to a first transceiver in a first transceiving group through the A core; when the to-be-sent message is determined to be not the message required by the upper target application based on the identifier of the to-be-sent message, controlling the first transceiver to perform self-transmitting and self-receiving operation on the to-be-sent message through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the to-be-sent message to be inward transmission; sending the message to be sent after the transmission direction is adjusted to an internal routing device through the first transceiver; and sending the message to be sent to a bus through the routing equipment. By adopting the scheme provided by the invention, the load capacity of the M cores is reduced, and inter-core load balancing is realized.

Description

Technical Field

[0001] This application relates to the technical field of message processing, and particularly to a message processing method, device, chip and storage medium. Background Art

[0002] With the continuous improvement of vehicle intelligence, the requirements for the real-time performance and reliability of vehicle electronic systems are getting higher and higher. For this reason, multi-core heterogeneous chips with both A cores (Application Cores) and M cores (Microcontroller Cores) are widely used. Among them, A cores are responsible for processing complex calculations and running application programs, such as for human-computer interaction, network communication, etc.; M cores are used for real-time tasks, low-power requirements and applications with high real-time requirements. Since the multi-core architecture can allocate different tasks to different cores, the processing speed and efficiency of tasks can be improved.

[0003] The load is the number of tasks that do not get an execution opportunity within a period of time. For a multi-core heterogeneous chip with both A cores and M cores, since the sending and receiving of all CAN channel messages are on the M core, the A core cannot independently perform the sending and receiving operations of CAN messages, resulting in a high load on the M core and unbalanced load between cores.

[0004] Therefore, how to provide a message processing method to reduce the load on the M core and achieve balanced load between cores. Summary of the Invention

[0005] This application provides a message processing method, device, chip and storage medium to reduce the load on the M core and achieve balanced load between cores.

[0006] This application provides a message processing method for a multi-core heterogeneous chip, including:

[0007] When a message to be sent is detected, determine a first processing core of the chip that processes the message to be sent, where the first processing core includes at least an A core or includes an M core;

[0008] When it is determined that the first processing core for processing the message to be sent is an A core, send the message to be sent to a first transceiver in a first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus;

[0009] When it is determined based on the identifier of the message to be sent that the message to be sent is not a message required by the upper-layer target application, control the first transceiver to perform a self-sending and self-receiving operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to be inward transmission;

[0010] Send the message to be sent after adjusting the transmission direction to the internal routing device through the first transceiver;

[0011] Send the message to be sent to the bus through the routing device.

[0012] The beneficial effects of this application are as follows: When a message to be sent is detected, determine the first processing core of the chip that processes the message to be sent, and the first processing core includes at least an A core or an M core; when it is determined that the first processing core for processing the message to be sent is an A core, send the message to be sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus; when it is determined based on the identifier of the message to be sent that the message to be sent is not the message required by the upper-layer target application, control the first transceiver to perform a self-transmitting and self-receiving operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to be inward transmission; send the message to be sent after adjusting the transmission direction to the internal routing device through the first transceiver; send the message to be sent to the bus through the routing device. Since the first transceiver is set with a loopback configuration, the loopback configuration allows the first transceiver to perform a self-transmitting and self-receiving operation on the message. When the message to be sent is self-transmitted, the transmission direction of the message to be sent is outward transmission. When the message to be sent is self-received, the transmission direction of the message is adjusted to be inward transmission. Therefore, the loopback configuration can perform self-transmitting and self-receiving on the message sent by the A core, adjust the transmission direction of the message from outward transmission to inward transmission, so that the first transceiver sends the message to the internal routing device, and then enables the routing device to send the message to the bus, enabling the A core to have the function of sending the message to the bus, so as to reduce the load of the M core and achieve inter-core load balancing.

[0013] In one embodiment, the method further includes:

[0014] When the second transceiver in the second transceiver group receives the message sent by the bus, determine the second processing core that processes the message to be sent;

[0015] When it is determined that the second processing core for processing the message to be sent is an A core, put the message to be processed into a pre-set container;

[0016] Send an interrupt signal to the A core to notify the A core that there is a message to be processed in the pre-set container.

[0017] In one embodiment, the determining the second processing core that processes the message to be processed includes:

[0018] Obtain the identifier of the message to be processed;

[0019] Query the correspondence table according to the identifier of the message to be processed to determine the second processing core for processing the message to be processed, where the correspondence table includes the correspondence between the identifier of the message and the processing core.

[0020] In one embodiment, the method further includes:

[0021] When the identifier of the message to be processed is not stored in the correspondence table, obtain the real-time requirement level of the message to be processed;

[0022] When the real-time requirement level of the message to be processed is greater than the preset level, determine that the second processing core for processing the message to be sent is the M core.

[0023] In one embodiment, the method further includes:

[0024] When the real-time requirement level of the message to be processed is less than the preset level, determine the processing core with the lowest load among all processing cores as the second processing core for processing the message to be processed.

[0025] In one embodiment, the step of sending the message to be sent to the bus by the routing device includes:

[0026] Forward the message to be sent to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus.

[0027] In one embodiment, the method further includes:

[0028] When the message to be sent is a message required by the upper-layer target application, control the first transceiver to send the message to be sent to the interface for communicating with the upper-layer target application, so that the upper-layer target application can obtain the message to be sent through the interface.

[0029] The present application also provides a message processing device for a multi-core heterogeneous chip, including:

[0030] A first determination module, configured to determine the first processing core of the chip for processing the message to be sent when detecting the message to be sent, where the first processing core at least includes the A core or includes the M core;

[0031] A first sending module, configured to, when the first processing core for processing the message to be sent is determined to be the A core, send the message to be sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus;

[0032] An adjustment module, configured to, when it is determined based on the identifier of the message to be sent that the message to be sent is not the message required by the upper-layer target application, control the first transceiver to perform a self-transmission and self-reception operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to be inward transmission;

[0033] A second sending module, configured to send the message to be sent after adjusting the transmission direction to an internal routing device through the first transceiver;

[0034] A third sending module, configured to send the message to be sent to the bus through the routing device.

[0035] In one embodiment, the device further includes:

[0036] A second determination module, configured to determine a second processing core for processing the message to be sent when a second transceiver in the second transceiver group receives a message sent by the bus;

[0037] A putting module, configured to put the message to be processed into a preset container when it is determined that the second processing core for processing the message to be sent is the A core;

[0038] A fourth sending module, configured to send an interrupt signal to the A core to notify the A core that there is a message to be processed in the preset container.

[0039] In one embodiment, the first determination module or the second determination module includes:

[0040] A first obtaining sub-module, configured to obtain the identifier of the message to be processed;

[0041] A first determination sub-module, configured to query a correspondence table according to the identifier of the message to be processed to determine a second processing core for processing the message to be processed, where the correspondence table includes the correspondence between the identifier of the message and the processing core.

[0042] In one embodiment, the first determination module or the second determination module further includes:

[0043] A second obtaining sub-module, configured to obtain the real-time requirement level of the message to be processed when the identifier of the message to be processed is not stored in the correspondence table;

[0044] A second determination sub-module, configured to determine that the second processing core for processing the message to be sent is the M core when the real-time requirement level of the message to be processed is greater than a preset level.

[0045] In one embodiment, the second determination sub-module is further configured to:

[0046] When the real-time requirement level of the message to be processed is lower than the preset level, determine the processing core with the lowest load among the processing cores as the second processing core for processing the message to be processed.

[0047] In one embodiment, the third sending module is further configured to:

[0048] Forward the message to be sent to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus.

[0049] In one embodiment, the device further includes:

[0050] A control module, configured to control the first transceiver to send the message to be sent to the interface for communicating with the upper-layer target application when the message to be sent is the message required by the upper-layer target application, so that the upper-layer target application can obtain the message to be sent through the interface.

[0051] This application also provides a message processing chip, including:

[0052] At least one processor; and,

[0053] A memory communicatively connected to the at least one processor; wherein,

[0054] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement the message processing method described in any of the above embodiments.

[0055] This application also provides a computer-readable storage medium. When the instructions in the storage medium are executed by the processor corresponding to the message processing chip, the message processing chip can implement the message processing method described in any of the above embodiments.

[0056] Other features and advantages of this application will be described in the following specification, and, in part, will become apparent from the specification, or will be understood by implementing this application. The objectives and other advantages of this application can be achieved and obtained through the structures specifically pointed out in the written specification, claims, and drawings.

[0057] The following further describes the technical solutions of this application in detail through the drawings and embodiments. Description of the Drawings

[0058] The drawings are used to provide a further understanding of this application, and constitute a part of the specification. Together with the embodiments of this application, they are used to explain this application, and do not constitute a limitation to this application. In the drawings:

[0059] Figure 1It is a flowchart of a message processing method in an embodiment of the present application;

[0060] Figure 2 It is a schematic diagram of the internal communication structure of a multi-core heterogeneous chip in the related art;

[0061] Figure 3 It is a schematic diagram of the internal communication structure of a multi-core heterogeneous chip in an embodiment of the present application;

[0062] Figure 4 It is a flowchart of the A core sending a message in an embodiment of the present application;

[0063] Figure 5 It is a flowchart of the A core receiving a message in an embodiment of the present application

[0064] Figure 6 It is a block diagram of a message processing device in an embodiment of the present application;

[0065] Figure 7 It is a schematic diagram of the hardware structure of a message processing chip in an embodiment of the present application. Detailed implementation manners

[0066] The following describes the preferred embodiments of the present application with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0067] Figure 1 It is a flowchart of a message processing method in an embodiment of the present application. As Figure 1 shown, the method can be implemented as the following steps S101 - S105:

[0068] In step S101, when a message to be sent is detected, determine the first processing core of the chip that processes the message to be sent. The first processing core includes at least the A core or includes the M core;

[0069] In step S102, when it is determined that the first processing core for processing the message to be sent is the A core, send the message to be sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus;

[0070] In step S103, when it is determined based on the identifier of the message to be sent that the message to be sent is not a message required by the upper-layer target application, control the first transceiver to perform a self-transmission and self-reception operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to be inward;

[0071] In step S104, send the message to be sent after adjusting the transmission direction to the internal routing device through the first transceiver;

[0072] In step S105, the message to be sent is sent to the bus through the routing device.

[0073] In the related art, the A core is a general-purpose processing core mainly used for executing general computing tasks. The A core generally adopts a relatively high clock frequency and a large cache to provide strong single-thread processing performance. It is suitable for running operating systems, applications, and most common computing tasks. The M core is a core for processing additional tasks, generally adopting a relatively low clock frequency and a small cache to provide low power consumption and high real-time performance. It is suitable for processing sensor data, executing real-time control algorithms, and other tasks with high requirements for low power consumption and real-time performance. In the related art, the M core communicates with the bus, while the A core does not communicate with the bus. Figure 2 It is a schematic diagram of the internal communication structure of a multi-core heterogeneous chip in the related art. Through Figure 2 It can be seen that in the related art, the CAN channels capable of communicating with the bus are the transceiver group composed of 8 transceivers CAN0 - CAN7, while the transceiver group composed of 8 transceivers CAN8 - CAN15 is in an idle state and does not communicate with the bus. When the M core communicates with the bus, it is achieved by accessing the transceiver group composed of 8 transceivers CAN0 - CAN7. Since the A core has high processing performance, its processing ability is higher than that of the M core. Therefore, usually, after the A core efficiently processes the assigned tasks, it is in an idle state for a large part of the time, while the M core is in a busy state for most of the time. If the number of received and sent messages is large, the load on the M core is too high, and it may not be able to ensure the immediacy of message processing. Therefore, how to utilize the remaining computing power of the A core to balance the load of the M core is the problem to be solved in this application.

[0074] In this application, when a message to be sent is detected, the first processing core of the chip for processing the message to be sent is determined, and the first processing core includes at least the A core or includes the M core;

[0075] Specifically, in this application, the identifier of the message to be processed can be obtained, and the corresponding relationship table is queried according to the identifier of the message to be processed to determine the second processing core for processing the message to be processed, where the corresponding relationship table includes the corresponding relationship between the identifier of the message and the processing core.

[0076] For example, the identifier of the message and the corresponding relationship table can be preset. For example, the identifier can be the message identifier appended according to the message sending and receiving order, and the message identifier is 1 - 999. In the corresponding relationship table, 1 - 499 corresponds to the M core, and 500 - 999 corresponds to the A core. Or the odd identifiers can be corresponding to the M core, and the even identifiers to the A core. Therefore, the processing core for processing the message can be determined according to the identifier. Of course, this is just an example. Since the message itself also has an identifier, which can usually be used to represent the message type, the corresponding relationship table can also store the corresponding relationship between the identifier of the message itself for representing the message type and the processing core, so as to allocate the message to the platform suitable for processing the message.

[0077] When the identifier of the message to be processed is not stored in the corresponding relationship table, obtain the real-time requirement level of the message to be processed; when the real-time requirement level of the message to be processed is greater than the preset level, determine that the second processing core for processing the message to be sent is the M core. When the real-time requirement level of the message to be processed is less than the preset level, determine the processing core with the smallest load among all processing cores as the second processing core for processing the message to be processed. Since the M core is mainly used to process messages, and the A core is used to assist in processing messages, and there may be many other tasks with higher priorities than messages in the A core. Therefore, when the real-time requirement of the message is high, it is processed by the M core to avoid the situation that the A core is processing other tasks and cannot process the message in time. If the real-time requirement of the message is low, consider the load of the processing core and allocate the message to the processing core with the smallest load.

[0078] When it is determined that the second processing core for processing the message to be sent is the A core, the message to be sent is sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus; specifically, Figure 3 This is the schematic diagram of the internal communication structure of the multi-core heterogeneous chip in this application. As Figure 3 shown, the first transceiver group can be a transceiver group composed of 8 transceivers CAN8 - CAN15. Figure 3 In this case, taking CAN9 as the first transceiver as an example, it can be understood that in this application, any one or more of the 8 transceivers CAN8 - CAN15 can be set in a loopback manner, so that it has the function of the first transceiver.

[0079] When it is determined based on the identifier of the message to be sent that the message to be sent is not the message required by the upper-layer target application, control the first transceiver to perform a self-sending and self-receiving operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to the inward transmission.

[0080] Send the message to be sent after adjusting the transmission direction to the internal routing device through the first transceiver;

[0081] Send the message to be sent to the bus through the routing device. Specifically, forward the message to be sent to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus. In this application, Figure 3 Any one of the 8 transceivers CAN0 - CAN7 shown has the function of the second transceiver.

[0082] Figure 4 The process of sending a message for the A core is as Figure 4 shown. When the message to be sent is a message required by the upper-layer target application, control the first transceiver to send the message to the interface communicating with the upper-layer target application, so that the upper-layer target application can obtain the message to be sent through the interface. For example, for a light-off operation, this message can achieve the function if it is sent to the bus through the second transceiver in the second transceiver group; however, if the upper-layer application also needs to achieve this function through certain means, the bottom layer needs to provide an interface (such as a socket interface) for communication with the upper-layer application. When it is found that the message to be sent is a message required by the upper-layer target application, control the first transceiver to send the message to the interface communicating with the upper-layer target application, so that the upper-layer target application can obtain the message to be sent through the interface.

[0083] If the second transceiver in the second transceiver group receives a message, it can also determine the second processing core for processing the message to be sent in the same way as the previous method; when it is determined that the second processing core for processing the message to be sent is the A core, put the message to be processed into a pre-set container; send an interrupt signal to the A core to notify the A core that there is a message to be processed in the pre-set container. It can be understood that if it is a message that needs to be processed by the M core, an interrupt signal is sent to the M core to notify the M core that there is a message to be processed in the pre-set container. If it is a message that does not need to be specifically specified which processing core processes it, interrupt signals are sent to both the M core and the A core respectively. The message identifier is stored in the interrupt signal. When the M core or the A core receives the interrupt signal, it can obtain the message corresponding to the identifier from the pre-set container based on the message identifier.

[0084] Secondly, in this application, the A core and the M core share the second transceiver group, and the sleep and wake-up of the A core are controlled by the M core, which can avoid the A core using some transceivers in the second transceiver group alone, thus avoiding competition between the A core and the M core. As Figure 5As shown, after the bus sends a message to the chip, the message enters the Low Latency Communication Engine (LLCE) from the second transceiver. At this time, the chip determines whether the function of the A core to receive messages is enabled. Specifically, when the M core controls the A core to sleep, the function of the A core to receive messages is turned off, and when the M core controls the A core to wake up, the function of the A core to receive messages is turned on. Of course, it can be understood that the M core controlling the sleep and wake-up of the A core refers to the M core controlling the opening and closing of the function of the A core to receive messages, and does not limit the opening and closing of the function of the A core to process other tasks.

[0085] The beneficial effect of this application is as follows: when a message to be sent is detected, determine the first processing core of the chip that processes the message to be sent, and the first processing core at least includes the A core or includes the M core; when it is determined that the first processing core that processes the message to be sent is the A core, send the message to be sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus; when it is determined based on the identifier of the message to be sent that the message to be sent is not the message required by the upper-layer target application, control the first transceiver to perform a self-transmitting and self-receiving operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to be inward transmission; send the message to be sent after adjusting the transmission direction to the internal routing device through the first transceiver; send the message to be sent to the bus through the routing device. Since the first transceiver is provided with a loopback configuration, the loopback configuration allows the first transceiver to perform a self-transmitting and self-receiving operation on the message. When the message to be sent is self-transmitted, the transmission direction of the message to be sent is outward transmission. When the message to be sent is self-received, the transmission direction of the message is adjusted to be inward transmission. Therefore, the message sent by the A core can be self-transmitted and self-received through the loopback configuration, and the transmission direction of the message is adjusted from outward transmission to inward transmission, so that the first transceiver sends the message to the internal routing device, and then enables the routing device to send the message to the bus, enabling the A core to have the function of sending the message to the bus, so as to reduce the load of the M core and achieve inter-core load balancing.

[0086] In one embodiment, the method further includes the following steps A1 - A3:

[0087] In step A1, when the second transceiver in the second transceiver group receives a message sent by the bus, determine the second processing core that processes the message to be sent;

[0088] In step A2, when it is determined that the second processing core that processes the message to be sent is the A core, put the message to be processed into a pre-set container;

[0089] In step A3, an interrupt signal is sent to the A core to notify the A core that there is a message to be processed in the preset container.

[0090] In one embodiment, determining the second processing core for processing the message to be sent in the above step S101 includes the following steps B1 - B5:

[0091] In step B1, obtain the identifier of the message to be processed;

[0092] In step B2, query the correspondence table according to the identifier of the message to be processed to determine the second processing core for processing the message to be processed, where the correspondence table includes the correspondence between the identifier of the message and the processing core;

[0093] In step B3, when the identifier of the message to be processed is not stored in the correspondence table, obtain the real - time requirement level of the message to be processed;

[0094] In step B4, when the real - time requirement level of the message to be processed is greater than the preset level, determine that the second processing core for processing the message to be sent is the M core;

[0095] In step B5, when the real - time requirement level of the message to be processed is less than the preset level, determine that the processing core with the smallest load among all processing cores is the second processing core for processing the message to be processed.

[0096] It can be understood that when determining the first processing core for processing the message, the above - mentioned capture A1 - A3 can also be used for determination.

[0097] In one embodiment, the above step S105 includes the following steps:

[0098] Forward the message to be sent to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus.

[0099] In one embodiment, the method can also be implemented as the following steps:

[0100] When the message to be sent is a message required by the upper - layer target application, control the first transceiver to send the message to the interface for communicating with the upper - layer target application, so that the upper - layer target application can obtain the message to be sent through the interface.

[0101] Figure 6 It is a block diagram of a message processing device for a multi - core heterogeneous chip according to the present application, such as Figure 6 As shown, the device includes:

[0102] The first determination module 61 is configured to determine a first processing core of a chip for processing the to-be-sent message when detecting the to-be-sent message, where the first processing core at least includes an A core or includes an M core;

[0103] The first sending module 62 is configured to, when determining that the first processing core for processing the to-be-sent message is an A core, send the to-be-sent message to a first transceiver in a first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus;

[0104] The adjustment module 63 is configured to, when determining that the to-be-sent message is not a message required by an upper-layer target application based on the identifier of the to-be-sent message, control the first transceiver to perform a self-sending and self-receiving operation on the to-be-sent message through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the to-be-sent message to an inward transmission;

[0105] The second sending module 64 is configured to send the to-be-sent message with the adjusted transmission direction to an internal routing device through the first transceiver;

[0106] The third sending module 65 is configured to send the to-be-sent message to the bus through the routing device.

[0107] In one embodiment, the device further includes:

[0108] The second determination module is configured to determine a second processing core for processing the to-be-sent message when a second transceiver in a second transceiver group receives a message sent by the bus;

[0109] The putting module is configured to, when determining that the second processing core for processing the to-be-sent message is an A core, put the to-be-processed message into a preset container;

[0110] The fourth sending module is configured to send an interrupt signal to the A core to notify the A core that there is a to-be-processed message in the preset container.

[0111] In one embodiment, the first determination module or the second determination module includes:

[0112] The first obtaining sub-module is configured to obtain an identifier of the to-be-processed message;

[0113] The first determination sub-module is configured to query a correspondence table according to the identifier of the to-be-processed message to determine a second processing core for processing the to-be-processed message, where the correspondence table includes the correspondence between the identifier of the message and the processing core.

[0114] In one embodiment, the first determination module or the second determination module further includes:

[0115] A second acquisition sub-module, configured to obtain the real-time requirement level of the message to be processed when the identifier of the message to be processed is not stored in the corresponding relationship table;

[0116] A second determination sub-module, configured to determine that the second processing core for processing the message to be sent is the M core when the real-time requirement level of the message to be processed is greater than a preset level.

[0117] In one embodiment, the second determination sub-module is further configured to:

[0118] When the real-time requirement level of the message to be processed is less than the preset level, determine the processing core with the smallest load among all processing cores as the second processing core for processing the message to be processed.

[0119] In one embodiment, the third sending module is further configured to:

[0120] Forward the message to be sent to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus.

[0121] In one embodiment, the device further includes:

[0122] A control module, configured to control the first transceiver to send the message to be sent to an interface for communicating with the upper-layer target application when the message to be sent is a message required by the upper-layer target application, so that the upper-layer target application can obtain the message to be sent through the interface.

[0123] Figure 7 This is a schematic diagram of the hardware structure of a message processing chip in an embodiment of the present application. As Figure 7 shown, the message processing chip includes:

[0124] At least one processor 720; and,

[0125] A memory 704 communicatively connected to the at least one processor 720; wherein,

[0126] The memory 704 stores instructions executable by the at least one processor 720, and the instructions are executed by the at least one processor 720 to implement the message processing method described in any of the above embodiments.

[0127] Referring to Figure 7 , the message processing chip 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0128] The processing component 702 generally controls the overall operation of the packet processing chip 700. The processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the above - mentioned method. In addition, the processing component 702 may include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0129] The memory 704 is configured to store various types of data to support the operation of the packet processing chip 700. Examples of such data include instructions for any application or method operating on the packet processing chip 700, such as text, pictures, videos, etc. The memory 704 can be implemented by any type of volatile or non - volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read - only memory (EEPROM), erasable programmable read - only memory (EPROM), programmable read - only memory (PROM), read - only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0130] The power supply component 706 provides power to various components of the packet processing chip 700. The power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the packet processing chip 700.

[0131] The multimedia component 708 includes a screen that provides an output interface between the packet processing chip 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 708 may also include a front - facing camera and / or a rear - facing camera. When the packet processing chip 700 is in an operating mode, such as a shooting mode or a video mode, the front - facing camera and / or the rear - facing camera can receive external multimedia data. Each of the front - facing camera and the rear - facing camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0132] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), which is configured to receive external audio signals when the message processing chip 700 is in an operating mode, such as an alarm mode, a recording mode, a voice recognition mode, and a voice output mode. The received audio signals can be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 further includes a speaker for outputting audio signals.

[0133] The I / O interface 712 provides an interface between the processing component 702 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a start button, and a lock button.

[0134] The sensor component 714 includes one or more sensors for providing a status assessment of various aspects of the message processing chip 700. For example, the sensor component 714 can include a sound sensor. Additionally, the sensor component 714 can detect the on / off state of the message processing chip 700, the relative positioning of components, such as the display and keypad of the message processing chip 700. The sensor component 714 can also detect the operating state of the message processing chip 700 or a component of the message processing chip 700, such as the operating state of an air distribution plate, a structural state, the operating state of a discharge scraper, etc., the orientation or acceleration / deceleration of the message processing chip 700, and the temperature change of the message processing chip 700. The sensor component 714 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 714 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 714 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, a material accumulation thickness sensor, or a temperature sensor.

[0135] The communication component 716 is configured to enable the message processing chip 700 to provide communication capabilities with other devices and a cloud platform in a wired or wireless manner. The message processing chip 700 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0136] In an exemplary embodiment, the packet processing chip 700 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, and is used to execute the packet processing method described in any of the above embodiments.

[0137] The present application also provides a computer-readable storage medium. When the instructions in the storage medium are executed by the processor corresponding to the packet processing chip, the packet processing chip can implement the packet processing method described in any of the above embodiments.

[0138] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0139] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the specified functions in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0140] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the specified functions in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Therefore, the instructions executed on the computer or other programmable device provide for implementing the process inFigure 1 one process or multiple processes and / or boxes Figure 1 steps of the functions specified in one box or multiple boxes.

[0142] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A message processing method for a multi-core heterogeneous chip, Characterized in that, It includes: When a message to be sent is detected, determine a first processing core of the chip that processes the message to be sent, where the first processing core at least includes an A core or includes an M core; When it is determined that the first processing core for processing the message to be sent is an A core, send the message to be sent to the first transceiver in the first transceiver group through the A core, where there is no message interaction between the first transceiver group and the bus; When it is determined based on the identifier of the message to be sent that the message to be sent is not a message required by the upper-layer target application, control the first transceiver to perform a self-transmission and self-reception operation on the message to be sent through the loopback configuration of the first transceiver, so as to adjust the transmission direction of the message to be sent to an inward transmission; Send the message to be sent after adjusting the transmission direction to an internal routing device through the first transceiver; Send the message to be sent to the bus through the routing device.

2. The method according to claim 1, Characterized in that, The method further includes: When the second transceiver in the second transceiver group receives the message to be processed sent by the bus, determine a second processing core for processing the message to be processed, where there is message interaction between the second transceiver group and the bus; When it is determined that the second processing core for processing the message to be processed is an A core, put the message to be processed into a preset container; Send an interrupt signal to the A core to notify the A core that there is a message to be processed in the preset container.

3. The method according to claim 2, Characterized in that, Determining the second processing core for processing the message to be processed includes: Obtain the identifier of the message to be processed; Query a correspondence table according to the identifier of the message to be processed to determine the second processing core for processing the message to be processed, where the correspondence table includes the correspondence between the identifier of the message and the processing core.

4. The method according to claim 3, Characterized in that, The method further includes: When the identifier of the message to be processed is not stored in the correspondence table, obtain the real-time requirement level of the message to be processed; When the real-time requirement level of the message to be processed is greater than a preset level, determine that the second processing core for processing the message to be processed is an M core; When the real-time requirement level of the message to be processed is less than the preset level, determine that the processing core with the smallest load in the chip is the second processing core for processing the message to be processed.

5. The method according to claim 4, Characterized in that, Determining that the processing core with the smallest load in the chip is the second processing core for processing the message to be processed includes: When it is determined that the processing core with the smallest load in the chip is an A core, determine that the A core is the second processing core for processing the message to be processed; When it is determined that the processing core with the smallest load in the chip is an M core, determine that the M core is the second processing core for processing the message to be processed.

6. The method according to claim 1, Characterized in that, The sending the message to be sent to the bus through the routing device includes: Forward the to-be-sent message to the second transceiver in the second transceiver group through the routing device, so that the second transceiver sends the message to the bus.

7. The method according to claim 1, wherein, the method further includes: When it is determined based on the message identifier that the to-be-sent message is a message required by the upper-layer target application, control the first transceiver to send the to-be-sent message to the interface for communicating with the upper-layer target application, so that the upper-layer target application can obtain the to-be-sent message through the interface.

8. A message processing device for a multi-core heterogeneous chip, wherein, it includes: A first determination module, configured to determine the first processing core of the chip for processing the to-be-sent message when detecting the to-be-sent message, and the first processing core at least includes an A core or includes an M core; A first sending module, configured to send the to-be-sent message to the first transceiver in the first transceiver group through the A core when it is determined that the first processing core for processing the to-be-sent message is an A core, wherein there is no message interaction between the first transceiver group and the bus; An adjustment module, configured to control the first transceiver to perform a self-transmission and self-reception operation on the to-be-sent message through the loopback configuration of the first transceiver when it is determined based on the identifier of the to-be-sent message that the to-be-sent message is not a message required by the upper-layer target application, so as to adjust the transmission direction of the to-be-sent message to be inward transmission; A second sending module, configured to send the to-be-sent message after adjusting the transmission direction to an internal routing device through the first transceiver; A third sending module, configured to send the to-be-sent message to the bus through the routing device.

9. A message processing chip, wherein, it includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement the message processing method according to any one of claims 1-7.

10. A computer-readable storage medium, wherein, When the instructions in the storage medium are executed by the processor corresponding to the message processing chip, the message processing chip can implement the message processing method according to any one of claims 1-7.

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