DMA sending starting control method and device based on time triggering

Abstract

The invention discloses a DMA sending start control method and device based on time triggering, and the method comprises the steps: S01, obtaining a static scheduling time table of time-sensitive traffic, calculating an offset moment, generating a TX ring scheduling time table, and configuring the TX ring scheduling time table to a DMA sending start control module; step S02, running a DMA sending start control module, polling a TX ring scheduling timetable, judging whether non-time sensitive stream information in a current TX descriptor ring needs to be cleared or not during polling each time, mounting a corresponding offset address and a message length to the TX descriptor ring when judging that time sensitive stream mounting offset is reached, and sending a signal to a DMA controller; and S03, the DMA controller starts DMA read processing according to the received signal, and sends the time sensitive message in the deterministic sending buffer area to the network. The method has the advantages of being simple in implementation method, low in cost, high in efficiency, high in flexibility and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of Time Sensitive Networking (TSN), and particularly to a time-triggered DMA transmission start control method and device. Background Art

[0002] There are a large number of "sensing-computing-execution" control loops in distributed real-time systems such as industrial control systems, automotive electronic systems, and aerospace systems that have strict requirements for end-to-end real-time performance. The control loop consists of sensors, computing nodes, actuators, as well as sensing data streams and control data streams. The sensor generates a sensing data stream and sends it to the computing node through the network. The computing node runs a computing task, which uses the sensing data stream to calculate the control data stream and sends the control data stream to the actuator through the network. The actuator performs corresponding actions according to the control data stream to complete the "sensing-computing-execution" control loop. Since the control loop has high real-time requirements, the involved sensing data stream and control data stream are also time-sensitive streams or time-critical streams. Time-sensitive streams have extremely strict requirements for end-to-end real-time performance. For example, in an autonomous driving system, it is required that the end-to-end delay of the time-sensitive stream is between 100 microseconds and 250 microseconds, and the end-to-end jitter is below dozens of microseconds. Time-sensitive streams have end-to-end determinism. Especially in a distributed system, it is a system-level attribute that requires the joint guarantee of determinism on the end system and determinism in the network.

[0003] Time Sensitive Networking (TSN) can provide deterministic services for Ethernet, ensuring the transmission determinism of time-sensitive traffic in the network. It introduces functions such as time synchronization, deterministic packet forwarding, frame replication and redundancy elimination technology, and resource reservation on the basis of standard Ethernet. TSN upgrades Ethernet from an event-triggered type to a time-triggered type by adding a time reference to the standard Ethernet, enables each node in the network to have a common time reference through time synchronization technology, and divides the global time into equal-length time slots.

[0004] In the prior art, the DMA (Direct Memory Access) engine in TSN (Time-Sensitive Networking) adopts an "event-triggered" working mode, that is, the skb (Socket Buffer) associated with the packet is mounted on the descriptor, and the DMA engine reads the packet from the memory are all event-triggered, resulting in the packet sending not being able to be carried out according to the planned time. As a result, the network card needs to additionally implement the injection control of time-sensitive packets, and an additional buffer is required to store the time-sensitive packets that arrive in advance but cannot be scheduled for sending. Moreover, during the operation of the current TSN's DMA engine, it is impossible to distinguish between time-sensitive packets and non-time-sensitive packets, and the number of descriptors in the TX descriptor ring is limited. The time for the hardware to write back the descriptors is also affected by the number of packets processed in each round and there is uncertainty, resulting in the processing of time-sensitive packets being extremely vulnerable to the impact of sudden non-time-sensitive packets. Based on the above event-triggered characteristics and the mixed processing of non-time-sensitive packets, the determinacy of time-sensitive packets is reduced, making the DMA transmission engine on the end-system network card actually not have the ability to transmit deterministic packets. Summary of the Invention

[0005] The technical problem to be solved by the present invention lies in: aiming at the technical problems existing in the prior art, the present invention provides a time-triggered DMA transmission start control method and device with simple implementation method, low cost, high efficiency and strong flexibility.

[0006] To solve the above technical problems, the technical solution proposed by the present invention is: A time-triggered DMA transmission start control method, the steps include: Step S01. Obtain the static scheduling time table of time-sensitive traffic, calculate the mounting offset time and the ring clearing offset time according to the triggering time of the time-sensitive packets in the obtained static scheduling time table, generate a TX ring scheduling time table and configure it into the DMA transmission start control module. The mounting offset time is the offset of the time-sensitive packet information mounting time within the scheduling period, and the ring clearing offset time is the offset of clearing the non-time-sensitive packet information in the TX descriptor ring within the scheduling period; Step S02. Run the DMA transmission start control module, poll the TX ring scheduling time table, and each time when polling, judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the offset time in the TX ring scheduling time table. When it is judged that the mounting offset time of the time-sensitive flow is reached, after mounting the offset address and packet length corresponding to the time-sensitive packet information on the TX descriptor ring, send a doorbell signal to the DMA transmission start register of the DMA controller; Step S03. The DMA controller starts the DMA read process according to the received doorbell signal, and sends the time-sensitive packets in the deterministic transmission buffer to the network.

[0007] Further, the fields in the TX ring scheduling time table further include an operation, an offset address, and a packet length. The operation is the operation that the DMA transmission start control module needs to execute at the operation offset time, including clearing the descriptor information of non-time-sensitive packets, mounting the time-sensitive packet information to the TX transmission descriptor ring, and sending a doorbell signal to notify the hardware to perform DMA read processing; the offset address is the offset address of the time-sensitive packet in the deterministic transmission buffer, and the time-sensitive flow is stored in a continuous memory area; the packet length is the length of the time-sensitive packet.

[0008] Further, in step S01, the TX ring scheduling time table is generated by using a preset scheduling algorithm. The input parameters of the preset scheduling algorithm include the static scheduling time table of time-sensitive traffic, the DMA channel bandwidth, the processing time of the network card, the time consumed for clearing the descriptor information of other non-time-sensitive flows on the TX ring, the time consumed for mounting the descriptor information of the current time-sensitive flow, and the time consumed for refreshing the tail pointer. The content of the table entries in the static scheduling time table includes any one or more of the source end, the destination end, the period, the packet length, and the deadline. The output parameters of the preset scheduling algorithm include an array of transmission buffer offset amounts of critical flows for marking the positions of critical flows in the transmission buffer and a scheduling time table. The scheduling time table includes any one or more fields such as the scheduling time of the operation, the specific operation type, the buffer offset amount for mounting the time-sensitive traffic, and the packet length of each time-sensitive traffic.

[0009] Further, step S01 includes: Step S101. Initialize the transmission buffer offset amount array and the TX ring scheduling time table according to the size of the static scheduling time table; Step S102. Poll the static scheduling time table, and calculate the storage offset address and the delayed mounting time of the time-sensitive packet in the deterministic buffer item by item according to the information of each time-sensitive packet; Step S103. Determine the mounting offset time of the time-sensitive packet according to the transmission time in the static scheduling time table and the delayed mounting time, and store them into a temporary array in sequence; Step S104. Calculate the TX descriptor ring clear time according to the temporary array, and generate a schedule entry for the TX ring schedule table. The clear time of the TX descriptor ring is calculated based on the current time-sensitive flow information mounting time and the clear ring time consumption. The clear time corresponding to the current time-sensitive traffic, the mounting offset time, the corresponding operations, the offset address, and the message length are added as a schedule entry to the TX ring schedule table. The clear ring time consumption is the time required to clear all non-time-sensitive message information on the ring before mounting the time-sensitive message information. Step S105. Output the complete TX ring schedule table for use by the DMA transmission start control module.

[0010] Furthermore, the delayed mounting time includes the descriptor dma processing time t_dma_desc, the data dma processing time t_dma_data, the time consumption t_mount for mounting the current time-sensitive flow descriptor information, the time consumption t_tail for refreshing the tail pointer, and the processing time t_nic of the network card.

[0011] Furthermore, in step S103, the mounting offset time of the time-sensitive message is corrected by calculating the time consumption from the mounting of the time-sensitive message to the descriptor to the actual transmission of the message by the network card.

[0012] Furthermore, the TX ring schedule table also includes a pointer for polling each item in the TX ring schedule table; the DMA transmission start control module performs corresponding operations by comparing the current global time with the table entry pointed to by the pointer of the TX ring schedule table, that is, determines whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is determined that the time-sensitive flow mounting offset is satisfied, mounts the offset address and message length corresponding to the time-sensitive flow information to the TX descriptor ring and sends a doorbell signal to the DMA transmission start register of the DMA controller.

[0013] Furthermore, step S02 includes: Step S201. After the DMA transmission start control module starts running, continuously obtain the global time and compare it with the current table entry pointer offset time of the TX ring schedule table; Step S202. Determine whether the current time is the TX ring schedule table offset time. If so, jump to step S203; otherwise, jump to step S205; Step S203. Determine whether the offset time corresponding to the current time is the time-sensitive message mounting offset. If so, determine that the time-sensitive message mounting offset time has been reached and jump to step S204; otherwise, determine that the clear ring offset time has been reached and jump to step S206; Step S204. Write the storage offset address and the message length of the current time-sensitive message into the descriptor ring, and then transfer to Step S207; Step S205. Determine whether the number of messages on the current ring has reached the threshold or whether the timer has expired. If so, transfer to Step S207; otherwise, return to Step S201; Step S206. Directly clear the descriptor information of the non-critical messages in the TX transmission descriptor ring, that is, release the correspondence between the descriptor and the corresponding non-critical message, and set the message value on the ring to 0, then transfer to Step S208; Step S207. Send a doorbell signal to the DMA send start register of the DMA controller; Step S208. Move the table entry pointer to the next entry in the TX ring scheduling time table, jump to Step S201, and continue to wait for triggering.

[0014] A time-triggered DMA send start control device includes a processor and a memory. The memory is used to store a computer program, and the processor is used to execute the computer program to perform the above method.

[0015] A computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the above method.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. By introducing a time scale on the basis of a standard DMA engine, the present invention uses the TX ring scheduling time table to control the time when time-sensitive message information is mounted on the TX descriptor ring, and further controls the time when the DMA engine reads time-sensitive messages in memory, enabling the "event-triggered" standard DMA engine to have the characteristics of "time-triggered". By planning the sending offset time of time-sensitive messages and controlling the sending of messages according to time, the consumption of hardware storage resources can be reduced. At the same time, in cooperation with a deterministic sending buffer, the polling DMA send start control module is used instead of the interrupt method to send the doorbell signal, so that the sending of messages is only related to the time when the descriptor is mounted, which can improve the certainty of the message sending time, effectively reduce the jitter of the network card sending time-sensitive flows, improve the delay certainty of message sending, and thus improve the end-to-end certainty of time-sensitive flows.

[0017] 2. By correcting the offset time of mounting time-sensitive message information and message sending, the present invention enables the underlying hardware not to allocate too much storage space to accommodate time-sensitive messages that arrive too early, which can save the storage resources of the underlying hardware and is especially suitable for the application of on-chip embedded end systems.

[0018] 3. The present invention realizes the deterministic scheduling of time-sensitive traffic in mixed traffic through software, which can also improve the implementation flexibility, reduce the hardware design cost, simplify the hardware design, and has better portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the principle of the time-triggered DMA transmission start control method based on this embodiment.

[0020] Figure 2 It is a schematic diagram of the implementation process of the time-triggered DMA transmission start control method based on this embodiment.

[0021] Figure 3 It is a schematic diagram of the configuration of the TX ring scheduling time table obtained in the specific application embodiment of the present invention.

[0022] Figure 4 It is a flowchart of the implementation of the time-triggered DMA transmission start control based on this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0024] For ease of understanding, the relevant technical background related to the present invention will be introduced first by way of example.

[0025] On the end system in the TSN network, the message needs to pass through the application, Socket API, protocol stack, network card driver, DMA engine, and network card switch in sequence from the application task to the physical link. Among them, the application copies the constructed message Msg for sending to the kernel space through system calls such as sendto(), constructs an skb according to the content of Msg and performs an enqueue operation; in the protocol stack, the skb will be processed by the transport layer and network layer, such as filling in the header field operation; then it enters the traffic control subsystem. If there is no queue rule restricting the message sending, the message will be immediately mounted to the send (TX) descriptor ring in the driver; if there is a restriction, a suitable queue will be selected for enqueue processing, and it will be decided when to issue it to the driver according to the queue rule and queue quota; the driver maintains the mapping relationship between the TX descriptor ring address and the DMA address, and the network card reads the skb mounted by the descriptor through DMA, finds the message at the memory location pointed to by the skb, DMA it to the message buffer of the network card, and finally the network card will send the message to the network. Among them, the DMA engine is an important link to ensure the determinacy of the end system. The DMA engine uses DMA technology to write the message in the memory to the network card. DMA is a data transfer method in which the I / O device directly exchanges data with the memory without the intervention of the CPU.

[0026] In the prior art, the standard DMA engine and the network card driver exchange data through a descriptor mechanism and an interrupt mechanism. The specific process is as follows: 1. First, the network card driver initializes a descriptor ring in memory. The descriptor ring is a key data structure for the DMA engine and the network card driver to exchange packets, and is organized into a circular structure by individual descriptors. A descriptor includes a pointer to the packet buffer, that is, the physical address of the packet buffer. A descriptor can be regarded as a summary of the packet buffer, and the packet buffer is the area where the packet is actually stored. The specific data structure of the descriptor is related to the network card, but its key fields are roughly the same, including the address of the packet buffer, the packet length, and the status bit. The status bit is used to indicate whether there is a packet in the packet buffer pointed to by this descriptor.

[0027] 2. The skb representing the packet reaches the network card driver after being processed by the protocol stack, the neighbor subsystem, and the network device subsystem. In the driver function, an element is taken from the send descriptor ring, and the skb is attached to the element, and a memory mapping is constructed for the data corresponding to the skb to allow the device to read data from the RAM through DMA. It is necessary to traverse all the fragments of the packet, generate a valid mapping for each fragment of the skb, and update the head pointer of the descriptor ring. The head pointer is the pointer pointing to the next available send descriptor.

[0028] 3. When the send queue is paused from sending by the driver or the protocol stack, or the number of written descriptors reaches a preset threshold, that is, the flag indicating that there is no more data to send is set, the driver will write the current descriptor position into the hardware tail pointer register to notify the hardware for processing. That is, the DMA engine obtains the number and position of the descriptors of the currently written packets. The DMA processes the descriptors by polling, retrieves the packets from the memory and writes them into the buffer of the network card. After the hardware sends each packet, it will write back the flag bit to the descriptor so that the driver can recycle the send descriptor in the subsequent interrupt processing.

[0029] The working process of the above standard DMA engine belongs to the "event-triggered" type. Among them, the occurrence of attaching the skb associated with the packet to the descriptor and the occurrence of the DMA engine reading the packet from the memory are both event-triggered, resulting in the packet sending not being able to be carried out according to the planned time. As a result, the network card needs to additionally implement the injection control of time-sensitive packets, and an additional buffer is required to store time-sensitive packets that arrive in advance but cannot be scheduled for sending. Moreover, since the above standard DMA engine cannot distinguish between time-sensitive packets and non-time-sensitive packets during the working process, it leads to the problem of mixed processing of non-time-sensitive packets. The processing of time-sensitive packets is extremely vulnerable to the impact of sudden non-time-sensitive packets, thus reducing the determinism of time-sensitive packets and making the standard DMA send engine on the end-system network card not have the ability to transmit deterministic packets.

[0030] In view of the above problems existing in the prior art, the present invention provides a time-triggered DMA transmission start control method and device with simple implementation method, low cost, high efficiency and strong flexibility. By introducing a time scale on the basis of a standard DMA engine and using a TX ring scheduling time table to control the time when time-sensitive packet information is mounted on the TX descriptor ring, and further controlling the time when the DMA engine reads the time-sensitive packets in the memory, the "event-triggered" standard DMA engine has the characteristics of "time-triggered". By planning the transmission offset time of time-sensitive packets and controlling the packets to be sent according to time, the consumption of hardware storage resources can be reduced. At the same time, in cooperation with a deterministic transmission buffer, a polling DMA transmission start control module is used instead of an interrupt to send a doorbell signal, so that the transmission of packets is only related to the time when the descriptors are mounted, which can improve the certainty of the packet transmission time, effectively reduce the jitter of the network card when sending time-sensitive flows, improve the delay certainty of packet transmission, and thus improve the end-to-end certainty of time-sensitive flows.

[0031] The present invention will be further described below in conjunction with specific embodiments.

[0032] As Figure 1 shown, the principle of the time-triggered DMA transmission start control method in this embodiment is to generate and configure a TX ring scheduling time table for the DMA transmission start control module. The DMA transmission start control module obtains the global time and then compares it with the offset time of the TX ring scheduling time table entry. When the ring clearing offset is satisfied, the information of non-time-sensitive flows on the TX descriptor ring is cleared to prepare for the mounting of time-sensitive flows; when the time-sensitive flow mounting offset is satisfied, the corresponding offset address and packet length are mounted on the TX descriptor ring and a doorbell signal is sent to notify the hardware to perform DMA read processing.

[0033] As Figure 2 shown, the steps of the time-triggered DMA transmission start control method in this embodiment include: Step S01. Obtain the static scheduling time table of time-sensitive traffic, calculate the mounting offset time and the ring clearing offset time according to the triggering time of the time-sensitive packets in the obtained static scheduling time table, generate a TX ring scheduling time table and configure it into the DMA transmission start control module. The mounting offset time is the offset of the time when the time-sensitive packet information is mounted within the scheduling period, and the ring clearing offset time is the offset of clearing the non-time-sensitive packet information on the TX descriptor ring within the scheduling period; Step S02. Run the DMA transmission start control module, poll the TX ring scheduling time table, and each time when polling, determine whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the ring clearing offset time in the TX ring scheduling time table, and when it is judged that the mounting offset time of the time-sensitive packet information is reached, mount the offset address and packet length corresponding to the time-sensitive packet information onto the TX descriptor ring, and send a doorbell signal to the DMA transmission start register of the DMA controller; Step S03. The DMA controller starts the DMA read process according to the received doorbell signal, and sends the time-sensitive packets in the deterministic transmission buffer to the network.

[0034] Since the time-sensitive flow is periodic and static, a time-sensitive flow can be described by a five-tuple of source, destination, period, packet length, and deadline. Therefore, each time-sensitive traffic can be pre-planned to obtain a static scheduling time table that can be known in advance for the traffic planning and scheduling of TSN. In this embodiment, first, according to the static scheduling time table of the time-sensitive traffic known a priori, combined with the DMA transmission time consumption of the system, etc., a TX ring scheduling time table is generated. Then, the DMA transmission start control module is run, and by polling the TX ring scheduling time table, it is decided when to clear the non-time-sensitive flow information in the current TX descriptor ring, or when to mount the time-sensitive flow information onto the TX descriptor ring, and a doorbell signal is sent to the DMA transmission start register of the underlying hardware. The DMA controller starts the DMA read according to the doorbell signal, and sends the time-sensitive packets in the deterministic transmission buffer to the network on time. In the above manner, by using the TX ring scheduling time table to control the time when the time-sensitive packet information is mounted onto the TX descriptor ring, and thus control the time when the DMA engine reads the time-sensitive packets in the memory, the "event-triggered" standard DMA engine can have the characteristics of "time-triggered". By controlling the mounting timing of the time-sensitive packet information and the timing when the packet is submitted to the underlying hardware, the transmission of the time-sensitive traffic conforms to the network scheduling plan, and the "last mile" problem of the time-delay determinism of the time-sensitive flow on the sending side can be solved. At the same time, using the polling DMA transmission start control module instead of the interrupt method to send the doorbell signal makes the packet transmission only related to the time when the descriptor is mounted, and has nothing to do with other factors such as the number, length of non-time-sensitive packets, and the processing queue of the protocol stack, making the packet transmission time more deterministic. Therefore, the jitter of the network card sending the time-sensitive flow can be reduced, the time-delay determinism of the packet transmission can be improved, and the end-to-end determinism of the time-sensitive flow can be improved.

[0035] In this embodiment, each field in the TX ring scheduling time table includes an offset time, an operation, an offset address, and a message length. The offset time is the mounting offset time and the ring clearing offset time. Among them, the mounting offset time is the offset of the time-sensitive message information mounting time within the scheduling period, and the ring clearing offset time is the offset of the TX descriptor ring clearing non-time-sensitive message information within the scheduling period; the operation is the operation that the DMA transmission start control module needs to execute when reaching the operation offset time, including clearing the descriptor information of the non-time-sensitive message, mounting the time-sensitive message information to the TX transmission descriptor ring, and sending a doorbell signal to notify the hardware to perform DMA read processing; the offset address is the offset address of the time-sensitive message in the deterministic transmission buffer, and the time-sensitive stream is stored in a continuous memory area; the message length is the length of the time-sensitive message. Specifically, the specific definitions of each field in the TX ring scheduling time table are as follows: (1) Offset time: The offset time represents the offset of the time-sensitive message information mounting time within the scheduling period, that is, the mounting offset time. Adding this offset time to the start time of the scheduling period gives the mounting time of the corresponding information of this stream; or it is the offset of the TX descriptor ring clearing non-time-sensitive message information within the scheduling period, that is, the ring clearing offset time. Adding this offset time to the start time of the scheduling period gives the clearing time of the non-time-sensitive message information in the TX descriptor ring. The entries in the static scheduling time table are sorted in ascending order of the offset time. The mounting offset time and the ring clearing offset time of the time-sensitive message information can also be configured to be sorted in ascending order.

[0036] (2) Operation: It represents the operation that the DMA transmission start control module will execute when reaching the operation offset time, including clearing the descriptor information of the non-time-sensitive message, or mounting the time-sensitive message information to the TX transmission descriptor ring and sending a doorbell signal to notify the hardware to perform DMA read processing.

[0037] (3) Offset address: It represents the offset address of the time-sensitive message in the deterministic transmission buffer.

[0038] In this embodiment, a continuous memory area is pre-allocated for all time-sensitive streams for storage. Each stream corresponds to a priori known static scheduling time table and has its own specific offset address. In this way, after the DMA engine receives the doorbell signal sent by the transmission start control module, it can obtain the correct time-sensitive message at the specified offset address.

[0039] (4) Message length: It represents the length of the time-sensitive message.

[0040] In this embodiment, step S01 uses a preset scheduling algorithm to generate a TX ring scheduling schedule according to the static scheduling schedule of the priori known time-sensitive flow and the deterministic transmission buffer address, and configures it into the DMA transmission start control module. The specific steps are as follows: Step S101. Initialize the transmission buffer offset array and the TX ring scheduling schedule according to the size of the static scheduling schedule; Step S102. Poll the static scheduling schedule, and calculate the storage offset address and the delayed mounting time of the time-sensitive message in the deterministic buffer item by item according to the information of each time-sensitive message; Step S103. Determine the mounting offset time of the time-sensitive message according to the transmission time and the delayed mounting time in the static scheduling schedule, and store it in the temporary array in sequence; Step S104. Calculate the TX descriptor ring clearing time according to the temporary array, and generate a schedule entry for the TX ring scheduling schedule. Among them, calculate the clearing time of the TX descriptor ring according to the mounting time of the current time-sensitive flow information and the clearing time consumption. Add the clearing time corresponding to the current time-sensitive traffic, the mounting offset time, the corresponding operation, the offset address, and the message length as a schedule entry to the TX ring scheduling schedule. The clearing time consumption is the time required to clear all non-time-sensitive message information on the ring before the time-sensitive message information is mounted; Step S105. Output the complete TX ring scheduling schedule for use by the DMA transmission start control module.

[0041] In the above step S103, by calculating the time consumption from the time when the time-sensitive message is mounted to the descriptor to the time when the network card actually sends the message, the mounting offset time of the time-sensitive message is corrected. The time-sensitive flow information needs to be mounted on the TX descriptor ring at a specified time.

[0042] Since an application may generate time-sensitive packets prematurely, if the information of a time-sensitive packet is mounted as soon as it is generated, it may fail to send due to insufficient descriptor quantity or the packet may be discarded due to insufficient hardware storage resources. In this embodiment, by correcting the offset time of mounting the information of the time-sensitive packet and sending the packet, when the application generates a time-sensitive packet, the time-sensitive packet will be directly stored in a pre-applied deterministic transmission buffer first. The DMA transmission start control module polls the TX ring scheduling time table, and when the offset time for mounting the time-sensitive packet is met, it mounts its information, i.e., the offset address and the packet length, onto the TX descriptor ring, and immediately sends a doorbell signal to the DMA transmission start register of the underlying hardware to notify the hardware network card to process the descriptor and send the time-sensitive packet. Since the underlying hardware does not need to allocate excessive storage space to accommodate prematurely arriving time-sensitive packets, it can effectively save the storage resources of the underlying hardware and simplify the design of the underlying hardware, which is especially suitable for applications in on-chip embedded end systems.

[0043] In step S01 of this embodiment, when generating the TX ring scheduling time table by adopting a preset scheduling algorithm, the input parameters of the preset scheduling algorithm include the static scheduling time table of time-sensitive traffic, the DMA channel bandwidth, the processing time of the network card, the time consumed to clear the descriptor information of other non-time-sensitive flows on the TX ring, the time consumed to mount the descriptor information of the current time-sensitive flow, and the time consumed to refresh the tail pointer. The content of the table entries of the static scheduling time table includes any one or more of the source end, the destination end, the period, the packet length, and the deadline. The output parameters of the preset scheduling algorithm include an array of transmission buffer offset amounts of critical flows for marking the positions of critical flows in the transmission buffer and a scheduling time table. The scheduling time table includes any one or more fields of the scheduling time of the operation, the specific operation type, the buffer offset amount for mounting time-sensitive traffic, and the packet length of each time-sensitive traffic.

[0044] Specifically, the input parameters required by the scheduling algorithm include: critical_flow_schedule: The static scheduling time table of time-sensitive traffic that is known a priori, and the content of the table entries includes a five-tuple of the source end, the destination end, the period, the packet length, and the deadline; dma_bandwidth: The DMA channel bandwidth; t_nic: The processing time of the network card, such as queuing time, etc.; t_clear: The time consumed to clear the descriptor information of other non-time-sensitive flows on the TX ring.

[0045] t_mount: The time consumed to mount the descriptor information of the current time-sensitive flow.

[0046] t_tail: The time taken to refresh the tail pointer, i.e., the time taken by hardware through MMIO.

[0047] The above t_clear, t_mount, and t_tail can all obtain empirical values based on experiments.

[0048] The output parameters of the scheduling algorithm include: buffer_offset_array: An array of send buffer offsets for critical flows, used to mark the positions of critical flows in the send buffer, and can be used as an intermediate output parameter for schedule_table. Among them, each offset of buffer_offset_array can be determined by the packet size of each time-sensitive flow in critical_flow_schedule.

[0049] schedule_table: The scheduling time table. It includes the following fields: the scheduling time offset_time of the operation, the specific operation type operation (clear_ring or mount_critical_flow), the buffer offset offset_arr for mounting the time-sensitive traffic (this value is NULL during the clear_ring operation), and the packet length pkt_len of each time-sensitive traffic.

[0050] In a specific application embodiment, the scheduling algorithm can be configured as the following steps: (1) Initialize the send buffer offset array and the TX ring scheduling time table according to the size of the input static scheduling time table.

[0051] (2) Poll the static scheduling time table and calculate the storage offset address of the send buffer offset array (buffer_offset_array) and the delayed mounting time of the time-sensitive packets item by item. For each time-sensitive packet, i.e., the critical flow, calculate its storage offset address in the deterministic buffer according to the packet size; calculate the delay time (latency_offset) according to the packet size, DMA bandwidth, network card processing rate, etc.

[0052] Specifically, the delayed mounting time includes the descriptor dma processing time t_dma_desc, the data dma processing time t_dma_data, the time taken to mount the descriptor information of the current time-sensitive flow t_mount, the time taken to refresh the tail pointer t_tail, and the processing time of the network card t_nic. For example, the descriptor dma processing time: t_dma_desc = descriptor_size / dma_bandwidth; Data DMA processing time: t_dma_data = packet_size / dma_bandwidth; Latency time latency_offset = t_mount + t_tail + t_dma_desc + t_dma_data + t_nic.

[0053] (3) Determine the mounting offset time of the time-sensitive packet according to the sending time and latency_offset in the static scheduling time table, and store them in the temporary array in sequence. Among them, the mounting time = the sending time of the time-sensitive flow - latency_offset.

[0054] (4) Calculate the ring clearing time of the TX descriptor ring according to the temporary array, and generate a scheduling table entry. When calculating a ring clearing time, add the ring clearing and mounting offset times corresponding to the time-sensitive traffic, their corresponding operations, offset addresses, and packet lengths to the scheduling table. Among them, the ring clearing time = the mounting time of the current time-sensitive flow information - the ring clearing time consumption.

[0055] Before mounting the time-sensitive packet information, it is necessary to clear all non-time-sensitive packet information on the ring first, to prevent a large number of unprocessed non-time-sensitive packets from occupying the limited descriptors, and to prevent the time-sensitive packets from missing the processing time due to processing too many non-time-sensitive packets.

[0056] (5) Return the scheduling table. Output the complete TX ring scheduling time table shcedule_table for the DMA sending start control module to use.

[0057] In a specific application embodiment, the TX ring scheduling time table generated by calling the above scheduling algorithm is configured as Figure 3 shown.

[0058] In this embodiment, the ring scheduling time table is a circular structure generated according to the static scheduling time table for controlling the mounting of time-sensitive traffic information to the TX descriptor ring or clearing the TX descriptor ring information. The TX ring scheduling time table also includes a pointer for polling each item in the TX ring scheduling time table; the DMA sending start control module compares the current global time with the item pointed to by the pointer of the TX ring scheduling time table to perform corresponding operations, that is, to judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is judged that the mounting offset of the time-sensitive flow is satisfied, execute the operation of mounting the offset address and packet length corresponding to the time-sensitive flow information to the TX descriptor ring, and send a doorbell signal to the DMA sending start register of the DMA controller.

[0059] Step S1 generates a TX ring scheduling schedule based on the static scheduling schedule of the time-sensitive flow known a priori and the deterministic sending buffer address, and configures it to the DMA sending start control module; then step S02 implements the DMA sending start control based on time triggering. Figure 4 As shown, in this embodiment, the detailed steps of step S02 include: Step S201. After the DMA transmission start control module starts running, it continuously obtains the global time and compares it with the current entry pointer offset time of the TX ring scheduling time table; Step S202. Determine whether the current time is the offset time of the TX ring scheduling schedule. If yes, jump to step S203; otherwise, jump to step S205; Step S203. Determine whether the offset time corresponding to the current time is the time-sensitive message mounting offset. If so, determine that the time-sensitive message mounting offset time has been reached, and jump to step S204. Otherwise, determine that the ring clearing offset time has been reached and jump to step S206. Step S204. Write the storage offset address and message length of the current time-sensitive message into the descriptor ring, and proceed to step S207; Step S205. Determine whether the number of messages on the current ring has reached a threshold or whether the timer has expired. If so, proceed to step S207, otherwise return to step S201; Step S206. directly send the descriptor information of the non-critical message of the descriptor ring to TX to perform a clearing operation, that is, cancel the corresponding relationship between the descriptor and the corresponding non-critical message, and set the message value on the ring to 0, and then go to step S208; Step S207: Send a doorbell signal to the DMA send start register of the DMA controller to notify the hardware that it can send a data packet; Step S208: Move the entry pointer to the next entry in the TX ring scheduling schedule, jump to step S201, and continue to wait for triggering.

[0060] The threshold and timer used in the above step S205 can be customized by the user according to the scheduling of time-sensitive messages. For example, each time a message is mounted, the counter is increased by 1. When the hardware processes the message, the number is reduced by the corresponding number. When the ring clearing operation is performed, the counter is set to 0; the timer increases with the system clock and is cleared after expiration. When the threshold is met or the timer expires, jump to step S207 and then jump to step S201, otherwise jump directly to step S207.

[0061] The present invention introduces a time scale on the basis of a standard DMA engine, uses a TX ring scheduling time table to control the time when time-sensitive packet information is mounted on the TX descriptor ring, and further controls the time when the DMA engine reads the time-sensitive packets in the memory, so that the "event-triggered" standard DMA engine has the characteristics of "time-triggered". By controlling the mounting time of the time-sensitive packet information, the time when the packet is submitted to the underlying hardware is controlled, so that the transmission of time-sensitive traffic conforms to the network scheduling plan, and the "last mile" problem of the time delay determinism of time-sensitive flows on the sending side can be solved; at the same time, the present invention corrects the offset time of the mounting of the time-sensitive packet information and the packet sending, so that the underlying hardware does not need to allocate too much storage space to accommodate the time-sensitive packets that arrive too early, which can save the storage resources of the underlying hardware and simplify the design of the underlying hardware. The present invention realizes the deterministic scheduling of time-sensitive traffic in mixed traffic through software, and can also improve the implementation flexibility, reduce the hardware design cost, thus simplifying the hardware design and having better portability.

[0062] This embodiment further provides a DMA transmission start control device based on time-triggering, including a processor and a memory. The memory is used to store a computer program, and the processor is used to execute the computer program to execute the method as described above.

[0063] It can be understood that the method in this embodiment can be executed by a single device, such as a computer or a server, etc., or can also be applied to a distributed scenario where multiple devices cooperate with each other to complete. In the case of a distributed scenario, one device among multiple devices can only execute one or more steps in the method in this embodiment, and multiple devices interact with each other to complete the above method. The processor can be implemented in ways such as a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc., and is used to execute relevant programs to implement the method in this embodiment. The memory can be implemented in forms such as a read-only memory ROM, a random access memory RAM, a static storage device, and a dynamic storage device. The memory can store an operating system and other application programs. When implementing the method in this embodiment through software or firmware, the relevant program codes are stored in the memory and are called and executed by the processor.

[0064] This embodiment further provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method as described above is implemented.

[0065] Those skilled in the art should understand that the above embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks

[0066] The above are only the preferred embodiments of the present invention and do not impose any formal limitations on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. A DMA transmission start control method based on time triggering, characterized in that the steps include: Step S01. Obtain a static scheduling schedule for time-sensitive traffic, calculate a mount offset time and a ring clearing offset time according to the trigger time of the time-sensitive message in the obtained static scheduling schedule, generate a TX ring scheduling schedule and configure it to the DMA transmission start control module, the mount offset time is the offset of the mount time of the time-sensitive message information within the scheduling period, and the ring clearing offset time is the offset of the TX descriptor ring clearing non-time-sensitive message information within the scheduling period; Step S02. Run the DMA transmission start control module, poll the TX ring scheduling schedule, and judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the ring clearing offset time in the TX ring scheduling schedule each time polling, and when it is judged that the mounting offset time of the time-sensitive message information has arrived, mount the offset address and message length corresponding to the time-sensitive message information on the TX descriptor ring, and send a doorbell signal to the DMA transmission start register of the DMA controller; Step S03: The DMA controller starts DMA read processing according to the received doorbell signal, and sends the time-sensitive message in the deterministic send buffer to the network.

2. The time-triggered DMA transmission start control method according to claim 1, characterized in that: The fields in the TX ring scheduling schedule also include operations, offset addresses and message lengths. The operations are the operations that the DMA send startup control module needs to perform when the operation offset time is reached, including clearing the descriptor information of non-time-sensitive messages, mounting the time-sensitive message information to the TX send descriptor ring and sending a doorbell signal to notify the hardware to perform DMA read processing; the offset address is the offset address of the time-sensitive message in the deterministic send buffer, and the time-sensitive stream is stored in a continuous memory area; the message length is the length of the time-sensitive message.

3. The time-triggered DMA transmission start control method according to claim 1, characterized in that: In the step S01, the TX ring scheduling schedule is generated by adopting a preset scheduling algorithm, the input parameters of the preset scheduling algorithm include a static scheduling schedule for time-sensitive traffic, DMA channel bandwidth, network card processing time, time to clear descriptor information of other non-time-sensitive flows on the TX ring, time to mount the current time-sensitive flow descriptor information, and time to refresh the tail pointer, the table content of the static scheduling schedule includes any one or more of the source end, destination end, cycle, message length, and deadline, the output parameters of the preset scheduling algorithm include a send buffer offset array of the key flow for marking the position of the key flow in the send buffer and the scheduling schedule, the scheduling schedule includes the scheduling time of the operation, the specific operation type, the buffer offset for mounting the time-sensitive traffic, and any one or more fields in the message length of each time-sensitive traffic.

4. The time-triggered DMA transmission start control method according to claim 1, characterized in that: Step S01 includes: Step S101. Initialize the transmit buffer offset array and the TX ring scheduling schedule according to the size of the static scheduling schedule; Step S102: poll the static scheduling schedule, and calculate the storage offset address and delayed mounting time of the time-sensitive message in the deterministic buffer item by item according to the information of each time-sensitive message; Step S103. According to the sending time in the static scheduling schedule and the delayed mounting time, the mounting offset time of the time-sensitive message is determined and stored in a temporary array in sequence; Step S104. Calculate the ring clearing offset time according to the temporary array, generate a scheduling table entry of the TX ring scheduling timetable, wherein the ring clearing offset time is calculated according to the current time-sensitive message information mounting time and the ring clearing time consumption, and add the ring clearing offset time and mounting offset time corresponding to the current time-sensitive traffic and the corresponding operation, offset address, and message length as a scheduling table entry to the TX ring scheduling timetable, wherein the ring clearing time consumption is the time required to clear all non-time-sensitive message information on the ring before the time-sensitive message information is mounted; Step S105: Output a complete TX ring scheduling schedule to provide it to the DMA transmission start control module for use.

5. The time-triggered DMA transmission start control method according to claim 4, characterized in that: The delayed mount time includes the descriptor DMA processing time t_dma_desc, the data DMA processing time t_dma_data, the time t_mount for mounting the current time-sensitive stream descriptor information, the time t_tail for refreshing the tail pointer, and the time t_nic for processing the network card.

6. The time-triggered DMA transmission start control method according to claim 4, characterized in that: In step S103, the mounting offset time of the time-sensitive message is corrected by calculating the time taken for the time-sensitive message to be mounted on the descriptor and actually sent out by the network card.

7. The time-triggered DMA transmission start control method according to any one of claims 1 to 6, characterized in that: The TX ring scheduling schedule also includes a pointer for polling each item in the TX ring scheduling schedule; the DMA send start control module obtains the current global time and compares it with the table item pointed to by the pointer of the TX ring scheduling schedule to perform corresponding operations, that is, it determines whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is determined that the mounting offset time of the time-sensitive message has arrived, it executes the mounting of the offset address and message length corresponding to the time-sensitive message information on the TX descriptor ring, and sends a doorbell signal to the DMA send start register of the DMA controller.

8. The time-triggered DMA transmission start control method according to any one of claims 1 to 6, characterized in that: Step S02 includes: Step S201. After the DMA transmission start control module starts running, it continuously obtains the global time and compares it with the current entry pointer offset time of the TX ring scheduling time table; Step S202. Determine whether the current time is the offset time of the TX ring scheduling schedule. If yes, jump to step S203; otherwise, jump to step S205; Step S203. Determine whether the offset time corresponding to the current time is the time-sensitive message mounting offset. If so, determine that the time-sensitive message mounting offset time has been reached, and jump to step S204. Otherwise, determine that the ring clearing offset time has been reached and jump to step S206. Step S204. Write the storage offset address and message length of the current time-sensitive message into the descriptor ring, and proceed to step S207; Step S205. Determine whether the number of messages on the current ring has reached a threshold or whether the timer has expired. If so, proceed to step S207, otherwise return to step S201; Step S206. directly send the descriptor information of the non-critical message of the descriptor ring to TX to perform a clearing operation, that is, cancel the corresponding relationship between the descriptor and the corresponding non-critical message, and set the message value on the ring to 0, and then go to step S208; Step S207: Send a doorbell signal to the DMA send start register of the DMA controller; Step S208: Move the entry pointer to the next entry in the TX ring scheduling schedule, jump to step S201, and continue to wait for triggering.

9. A time-triggered DMA transmission start control device, comprising a processor and a memory, wherein the memory is used to store a computer program, characterized in that: The processor is configured to execute the computer program to perform the method according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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