MAC (Media Access Control)-based CPU (Central Processing Unit) inter-core session synchronization method and device and electronic equipment

Abstract

The invention relates to an MAC (Media Access Control)-based CPU (Central Processing Unit) inter-core session synchronization method and device. According to the method, the CPU core ID is embedded in the MAC address, so that the service message and the session synchronization message can be ensured to be processed on the same CPU core of different DPVS nodes, and an efficient and consistent message processing mechanism is realized. According to the method, the RSS and FDIR functions of the network card are utilized, and the message is directly distributed to the specified CPU core by configuring the proper rule, so that the processing performance of the characteristic message and the system efficiency are remarkably improved. Besides, the session synchronization messages are directly processed among the CPU cores of the DPVS nodes, centralized distribution is not needed, the real-time performance of session synchronization is effectively improved, and the performance bottleneck of single-core centralized distribution is eliminated. The method is suitable for a distributed network processing system, and the overall performance and reliability of the system can be remarkably improved.

Description

Technical Field

[0001] This application belongs to the technical field of session synchronization, and particularly relates to a method, device, computer-readable storage medium, and electronic device for CPU core-to-core session synchronization based on MAC. Background Art

[0002] In the existing DPVS (DPDK-based Virtual Server) session synchronization solution, since the session data structure of DPVS is Per-CPU-based (i.e., sessions are distributed on each CPU core), the session synchronization between nodes essentially synchronizes the session information on each CPU core of one DPVS node to the corresponding CPU cores of other DPVS nodes.

[0003] The currently adopted single-core centralized synchronization method, as Figure 1 shown, is that the session packets synchronized from other nodes are received by CPU0 core on the current node, then hash calculation is performed according to the five-tuple information of the packets, and then the packets are distributed to each service CPU core. During implementation, an independent thread is usually created for the session synchronization function. For example, when DPVS starts, in addition to the main service thread, send (Pub) and receive (Sub) threads for session synchronization are also created.

[0004] The above solution has the following defects: (1) CPU resource waste: Each DPVS node needs to specially allocate a CPU0 core for receiving and distributing session packets, and this core cannot be used to process service packets. This design causes valuable CPU resources to be occupied, reducing the overall utilization rate of the system.

[0005] (2) Performance bottleneck: As the number of sessions to be synchronized on each DPVS node increases, CPU0 core will become the performance bottleneck of session synchronization, specifically manifested as: The session synchronization latency increases, resulting in a decrease in session synchronization efficiency.

[0006] In high-load situations, session synchronization failures may occur, further affecting the stability and reliability of the system. Summary of the Invention

[0007] To address the above problems, this application proposes a new method for CPU core-to-core session synchronization based on MAC.

[0008] The overall design architecture of this method is as Figure 2As shown in the figure, in the DPVS1 node, the relevant information of the session on CPU1 of the DPVS1 node is embedded in the destination MAC address of the sent session synchronization packet. When the session synchronization packet arrives at the DPVS2 node, through the flow direction (FDIR) rule of the network card, the packet is allocated to CPU1 of the DPVS2 node for processing. At the same time, the session information is also created and maintained in the data structure related to CPU1 of the DPVS2 node.

[0009] The present method mainly realizes the following functions: (1) Packet distribution based on network card hardware functions By utilizing the receive-side scaling (RSS) and flow direction (FDIR) functions of the network card, packet distribution is realized at the hardware level. Combining with the network card characteristics, appropriate RSS and FDIR rules are issued to directly distribute packets with specific characteristics to the specified CPU core for processing.

[0010] (2) Constructing a special MAC address To ensure that service packets and session synchronization packets can be processed on the same CPU core of different DPVS nodes, the same RSS hash algorithm is used on the network cards of all DPVS nodes. When the service packets are encapsulated and transferred between the DPVS cluster and the RS, a MAC address containing the CPU core ID is constructed and used as the source MAC address of the service packet. When the service packet returns from the RS, the destination MAC carried is the source MAC of the original packet. When the service packet enters a certain DPVS node, the network card will directly send the packet to the specified CPU core for processing according to the pre-issued FDIR rule.

[0011] To ensure that session synchronization packets can be processed on the same CPU core of different DPVS nodes, a MAC address containing the CPU core ID is constructed and used as the destination MAC address of the session synchronization packet. When the session packet enters a certain DPVS node, the network card will directly send the packet to the specified CPU core for processing according to the pre-issued FDIR rule.

[0012] (3) Improving session synchronization performance The session synchronization packets are directly processed between the CPU cores of each DPVS node without centralized distribution through other cores. This processing method significantly improves the real-time performance of session synchronization and effectively eliminates the performance bottleneck problem caused by centralized distribution of a single core.

[0013] To achieve the above object, the present application provides the following technical solutions: The first aspect of the present application provides a method for session synchronization between CPU cores based on MAC, and the method includes: Use the RSS (Receive Side Scaling) function of the network card to distribute service packets to a specified queue of the network card, and the specified queue is bound to a specified core of the CPU; Use the FDIR (Flow Direction) function of the network card. By configuring FDIR rules, distribute packets to a specified packet receiving queue of the network card according to the destination MAC address of the packets; Embed a specific MAC address representing the CPU core ID where the session is located in the session synchronization packet, so that the session synchronization packet can be distributed to the same CPU core of the target node for processing; On the target node, distribute the received session synchronization packet to the CPU core corresponding to the CPU core ID for processing according to the FDIR rule, and create and maintain session information on this CPU core.

[0014] Further, in the method of this application, the last byte of the specific MAC address represents the CPU core ID where the session is located.

[0015] Further, in the method of this application, the FDIR rule distributes packets to the corresponding network card packet receiving queue according to the value of the last byte of the destination MAC address.

[0016] Further, in the method of this application, the service packets and session synchronization packets are processed on the same CPU core of different DPVS nodes to ensure the consistency and continuity of session information.

[0017] Further, in the method of this application, when a certain node in the DPVS cluster fails, the service packets are switched to other nodes for processing, and there will be no situation of session loss.

[0018] Further, in the method of this application, when the service packet is sent to the RS (Real Server), its source MAC address is modified to a specific MAC address containing the CPU core ID.

[0019] Further, in the method of this application, the service packet returned by the RS is distributed to the specified CPU core of the target node for processing according to the destination MAC address, and backhaul session information is created on this CPU core.

[0020] Further, in the method of this application, the last byte of the destination MAC address of the session synchronization packet and the backhaul session synchronization packet both represents the CPU core ID where the session is located.

[0021] The second aspect of this application provides a MAC-based inter-CPU-core session synchronization device, and the device includes: A network card, which is used to distribute service packets to a specified queue through the RSS function, and the specified queue is bound to a specified core of the CPU; Configuration module, used to configure FDIR rules on the network card, and the FDIR rules distribute packets to the specified packet receiving queue according to the destination MAC address of the packets; Packet processing module, used to embed a specific MAC address representing the CPU core ID where the session is located in the session synchronization packet, and distribute the received session synchronization packet to the same CPU core of the target node for processing according to the FDIR rules; Session management module, used to create and maintain session information on the CPU core of the target node.

[0022] When the device runs, it implements the steps of the foregoing MAC-based inter-CPU-core session synchronization method.

[0023] The third aspect of this application provides an electronic device, including: a memory and a processor; Memory: used to store computer programs; Processor: used to execute the computer program to implement the steps of the foregoing MAC-based inter-CPU-core session synchronization method.

[0024] The fourth aspect of this application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the foregoing MAC-based inter-CPU-core session synchronization method.

[0025] In summary, the MAC-based inter-CPU-core session synchronization method proposed in this application has the following advantages: (1) MAC address design based on CPU core ID By embedding the CPU core ID in the MAC address, it is ensured that service packets and session synchronization packets can be processed on the same CPU core of different DPVS nodes, thereby realizing an efficient and consistent packet processing mechanism.

[0026] (2) Optimize packet distribution by using network card hardware functions By configuring appropriate RSS (Receive Side Scaling) and FDIR (Flow Directed Information Retrieval) rules, the hardware characteristics of the network card are used to achieve efficient distribution of characteristic packets. This mechanism significantly improves the processing performance of characteristic packets and optimizes the overall system efficiency.

[0027] (3) Improve session synchronization performance Session synchronization packets are directly processed between the CPU cores of each DPVS node without centralized distribution through other cores. This processing method significantly improves the real-time performance of session synchronization and effectively eliminates the performance bottleneck problem caused by centralized distribution of a single core.

[0028] Other features and advantages of the present application will be elaborated in detail in the subsequent specification, or can be understood by implementing the relevant technical solutions of the present application. The objectives and other advantages of the present application can be achieved by the technical features and technical means clearly pointed out in the specification, claims, and drawings, and can be obtained through the implementation process of these technical contents. Description of the Drawings

[0029] In order to more clearly elaborate the technical solutions of the embodiments of the present application, the drawings involved in the description of the embodiments will be briefly introduced below. It should be noted that the drawings only show some embodiments of the present application. For those skilled in the art, without creative labor, other related drawings can be deduced based on these drawings.

[0030] Figure 1 It is a schematic diagram of the overall architecture of the existing single-core centralized synchronization method.

[0031] Figure 2 It is a schematic diagram of the overall design architecture of the method of the present application.

[0032] Figure 3 It is the overall implementation flowchart of the MAC-based CPU core-to-core session synchronization method of the present application.

[0033] Figure 4 It is the composition structure diagram of the MAC-based CPU core-to-core session synchronization device of the present application.

[0034] Figure 5 It is a schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed Embodiments

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be clear that the described embodiments are only some embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor shall fall within the protection scope of the present application.

[0036] In this document, the term "including" and any of its variants (such as "including", "included", etc.) are open-ended expressions and should be understood as "including but not limited to", that is, the listed content is not an exhaustive list and may also include other content not explicitly mentioned. The term "based on" should be understood as "at least partially based on", that is, the referred basis or condition may not be the only factor and may also involve other relevant factors. The term "an embodiment" should be understood as "at least one embodiment", that is, the described embodiment is not the only possible implementation and there may be other similar embodiments.

[0037] In this application, when the terms "a" and "multiple" are used to modify relevant elements or features, their expressions are illustrative rather than restrictive. Unless otherwise clearly stated in the context, "a" should be understood as "at least one", and "multiple" should be understood as "at least two". Those skilled in the art should make a reasonable interpretation of these terms according to the semantic and logical relationships in the context to ensure that they cover the possibility of "one or more".

[0038] Term Explanation: DPDK (Data Plane Development Kit): It is a data plane development toolset provided by Intel, designed specifically for Intel Architecture (IA) processors, and is used to achieve efficient packet processing in the user space. Different from the general-purpose goal of the Linux system, DPDK focuses on the high-performance processing of packets in network applications. DPDK applications run in the user space, receive and send packets through the data plane library it provides, and bypass the packet processing process of the Linux kernel protocol stack. From the perspective of the Linux kernel, DPDK applications are ordinary user-mode processes, and their compilation, linking, and loading methods are no different from ordinary programs. After a DPDK program starts, only one main thread is allowed to exist, and then multiple child threads can be created and bound to specified CPU cores to run.

[0039] FDIR (Intel Ethernet Flow Director): It is an Ethernet traffic steering technology proposed by Intel. This technology can perform precise matching based on the fields of packets and allocate the matching packets to specific queues, thereby achieving efficient traffic classification and processing.

[0040] RSS (Receive Side Scaling): A network card driver technology used to efficiently distribute received packets to multiple CPU cores in a multi-processor system. The network card parses the received packets, extracts five-tuple information such as IP address, protocol, and port, and calculates a hash value through a configured hash function. The lower bits (the specific number of bits depends on the network card design) of this hash value are used as the index of the redirection table (RETA), and the packets are distributed to the corresponding CPU cores according to the values in the RETA. Based on the RSS technology, a program can implement the distribution of data streams among multiple CPU cores through hardware and achieve load balancing through dynamic adjustment of the RETA.

[0041] CPU MAC: A special MAC address constructed based on the core ID of the CPU that processes service packets or session synchronization packets. It is used to identify the identity of a specific CPU core in network communication.

[0042] DPVS (DPDK-based Virtual Server): A high-performance layer-4 load balancer based on DPDK, whose name comes from the combination of DPDK and Linux Virtual Server (LVS). The clustering solution of DPVS is achieved through routing, and the internal BGP protocol is used to publish the forward VTEP (Virtual Extensible LAN Tunnel Endpoint) address routing of DPVS nodes. However, the final traffic distribution depends on the ECMP (Equal-Cost Multi-Path) function of the switch. The disadvantage of ECMP implementation is that when a DPVS node fails, the traffic originally belonging to that node will be forwarded to other nodes in the cluster. If session synchronization is not performed within the cluster, the packets of this connection will be discarded, resulting in a timeout at the service layer. This phenomenon has a particularly significant impact on long-connection services. To ensure that when a node in the DPVS cluster fails, other nodes can continue to process the established TCP connections, it is necessary to implement cross-machine storage of session information. In this way, when the traffic is redirected to other DPVS nodes, the packets can still be correctly forwarded.

[0043] Figure 3 The overall implementation process of the MAC-based CPU core-to-core session synchronization method provided by this application is shown below, including the following steps: S1. Use the RSS (Receive Side Scaling) function of the network card to distribute service packets to the specified queue of the network card, and the specified queue is bound to the specified core of the CPU; S2. Use the FDIR (Flow Direction) function of the network card, and by configuring FDIR rules, distribute the packets to the specified packet reception queue of the network card according to the destination MAC address of the packets; S3. Embed a specific MAC address representing the CPU core ID where the session is located in the session synchronization message, so that the session synchronization message can be distributed to the same CPU core on the target node for processing; S4. On the target node, distribute the received session synchronization message to the CPU core corresponding to the CPU core ID according to the FDIR rule, and create and maintain session information on this CPU core.

[0044] To more clearly elaborate on the technical solution of this application, the following will be further described through embodiments in specific scenarios.

[0045] The method of this embodiment realizes the processing of service messages and session synchronization messages on the same CPU core of different DPVS nodes by using the RSS (Receive Side Scaling) and FDIR (Flow Direction) functions of the network card, and combining the MAC address embedded with the special CPU core ID as the FDIR matching rule. The following is a specific example of the processing flow: 1. Enter the processing flow of service messages and corresponding session synchronization messages in the DPVS cluster When a service message arrives at the network card of a DPVS node, the network card distributes the message to the 3rd queue of the network card through the RSS feature. This queue is bound to the 3rd core of the CPU. Therefore, this service message is processed on CPU3, and the generated session information is also stored on CPU3 (the session data structure is independent for each CPU core).

[0046] When synchronizing this session to other DPVS nodes, the destination MAC address of the constructed session synchronization message is 11:22:33:44:55:03, where the last byte 03 of the MAC address represents the CPU core ID where the session is located.

[0047] The FDIR rule pre-configured on the network card distributes the message to the corresponding network card packet reception queue according to the value of the last byte of the destination MAC address. For example, when a session synchronization message with the destination MAC address 11:22:33:44:55:03 arrives at the network card, the message will be distributed to the 3rd packet reception queue of the network card. This queue is bound to the 3rd core of the CPU. Therefore, this session synchronization message is processed on CPU3, and session information is also created on CPU3.

[0048] Through the session synchronization mechanism of service messages, subsequent service messages of the same flow entering the DPVS cluster will be processed on CPU3 regardless of which DPVS node they are assigned to, and the session information related to this message will always be retained on CPU3. When a node in the DPVS cluster fails, the service messages of this flow are switched to other nodes for processing, and there will be no session loss.

[0049] 2. The service packets returned by RS enter the DPVS cluster and the corresponding session synchronization packet processing process When the service packet is sent to RS (Real Server) after being processed on CPU3 of a certain node in the DPVS cluster, the source MAC address of the packet is modified to aa:bb:cc:dd:ee:03. The destination MAC address of the packet returned by RS is aa:bb:cc:dd:ee:03. According to the pre-configured FDIR rule on the network card, this rule matches the destination MAC address, and the packet is distributed to the corresponding network card receive packet queue according to the value of the last byte of the destination MAC address. Therefore, the service packet with the destination MAC address of aa:bb:cc:dd:ee:03 is distributed to the 3rd receive packet queue of the network card, and this queue is bound to the 3rd core of the CPU. Therefore, this service packet is processed on CPU3, and the return session information is also created on CPU3.

[0050] The destination MAC address of the constructed return session synchronization packet is 11:22:33:44:55:03, where the last byte 03 of the MAC address represents the CPU core ID where the session is located. According to the pre-configured FDIR rule on the network card, this rule matches the destination MAC address of the packet, and the packet is distributed to the corresponding network card receive packet queue according to the value of the last byte of the destination MAC address. For example, when the packet with the destination MAC address of 11:22:33:44:55:03 arrives at the network card, this packet will be distributed to the 3rd receive packet queue, and this queue is bound to the 3rd core of the CPU. Therefore, this session synchronization packet is processed on CPU3, and the session information is also created on CPU3.

[0051] Through the session synchronization mechanism of the return packet, when the subsequent service packets returned by RS enter the DPVS cluster, no matter which DPVS node they are assigned to, they will be processed on CPU3, and the session information related to this packet is always retained on CPU3. When a certain node in the DPVS cluster fails, the service packets returned by RS are switched to other nodes for processing, and there will be no session loss.

[0052] Figure 4 The following shows a MAC-based inter-CPU core session synchronization device proposed in this application. The device includes: A network card, which is used to distribute service packets to a specified queue through the RSS function, and the specified queue is bound to a specified core of the CPU; A configuration module, which is used to configure the FDIR rule on the network card, and the FDIR rule distributes the packet to the specified receive packet queue according to the destination MAC address of the packet; A message processing module is used to embed a specific MAC address representing the CPU core ID where the session is located in the session synchronization message, and distribute the received session synchronization message to the same CPU core of the target node for processing according to the FDIR rule; A session management module is used to create and maintain session information on the CPU core of the target node.

[0053] When the above device runs, it implements the steps of the MAC-based inter-CPU-core session synchronization method disclosed in this application.

[0054] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementations of the devices, methods, and computer program products according to various embodiments of this application, including the architecture, functions, and operations. In these figures, each block may represent a module, a program segment, or a part of the code, which contains one or more executable instructions for implementing the specified logical function. It should be noted that each block in the block diagram and / or flowchart, as well as combinations of these blocks, can be implemented by a dedicated hardware-based system to perform the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0055] As Figure 5 shown, an embodiment of this application also discloses an electronic device, including: a processor 310, a communication interface 320, a memory 330 for storing computer programs executable by the processor, and a communication bus 340. Among them, the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 runs the executable computer program to implement the steps of the above MAC-based inter-CPU-core session synchronization method.

[0056] It can be understood that in addition to including a memory and a processor, this electronic device may also include an input device (such as a keyboard), an output device (such as a display), and other communication modules. These input devices, output devices, and other communication modules communicate with the processor through the I / O interface (i.e., the input / output interface).

[0057] The operations of this application can be implemented by writing computer program code using one or more programming languages or combinations thereof. The programming languages include but are not limited to the following types: Object-oriented programming languages, such as Java, Smalltalk, C++, etc.; Conventional procedural programming languages, such as the "C" language or similar programming languages.

[0058] The execution modes of the program code include but are not limited to: Executing entirely on the user's computer; Part is executed on the user's computer and part is executed on a remote computer; Executed as an independent software package; Fully executed on a remote computer or server.

[0059] In scenarios involving a remote computer, the remote computer can be connected to the user's computer through any type of network connection, including but not limited to a local area network (LAN) or a wide area network (WAN). In addition, the remote computer can also be connected to an external computer through an Internet service provider, such as by using the Internet for the connection.

[0060] Furthermore, the present application also discloses a computer-readable storage medium, which, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute each step of the MAC-based CPU core-to-core session synchronization method disclosed in the present application.

[0061] In the context of the present application, a computer-readable storage medium refers to a tangible medium that can store computer program code and related data. Specific examples include but are not limited to the following: (1) Portable computer disk: A removable magnetic storage medium such as a floppy disk.

[0062] (2) Hard disk: Fixed storage devices including mechanical hard disks and solid-state drives.

[0063] (3) Random access memory (RAM): A volatile storage medium for temporarily storing data and program code.

[0064] (4) Read-only memory (ROM): A non-volatile storage medium for storing fixed programs and data.

[0065] (5) Erasable programmable read-only memory (EPROM) or flash memory: A non-volatile storage medium that supports multiple erasures and programming.

[0066] (6) Fiber optic storage device: A storage medium based on fiber optic technology.

[0067] (7) Portable compact disc read-only memory (CD-ROM): A read-only medium for storing data in the form of an optical disc.

[0068] (8) Optical storage device: Storage media based on optical principles such as DVDs and Blu-ray discs.

[0069] (9) Magnetic storage device: Storage media based on magnetic principles such as magnetic tapes and disks.

[0070] Any suitable combination of the above: for example, multiple storage media are used in combination to meet different storage requirements.

[0071] These computer-readable storage media can be used to store the program code and related data described in this application to support the operation of the program and the persistent storage of data.

[0072] In particular, according to the embodiments of the present application, the processes described in the flowcharts can be implemented as computer software programs. For example, the embodiments of the present application relate to a computer program product that includes a computer program carried on a non-transitory computer-readable medium. The computer program contains program code for executing the MAC-based CPU inter-core session synchronization method disclosed in the present application. When the computer program is executed by a processing device, the above functions defined in the embodiments of the present application can be realized.

[0073] Although there are several specific implementation details in the above discussion, these details should not be construed as limitations on the scope of the present application. The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features. At the same time, the present application should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept.

[0074] Those skilled in the art should also understand that they can modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements on some of the technical features without departing from the spirit and scope of the technical solutions of the embodiments of the present application. These modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the core spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A MAC-based CPU inter-core session synchronization method, characterized in that: The method comprises the following steps: The RSS function of the network card is used to distribute the service message to the designated queue of the network card, and the designated queue is bound to the designated core of the CPU; Use the FDIR function of the network card and configure FDIR rules to distribute packets to the specified packet receiving queue of the network card according to the destination MAC address of the packet; A specific MAC address representing the CPU core ID of the session is embedded in the session synchronization message, so that the session synchronization message can be distributed to the same CPU core of the target node for processing; On the target node, the received session synchronization message is distributed to the CPU core corresponding to the CPU core ID for processing according to the FDIR rule, and the session information is created and maintained on the CPU core.

2. The method according to claim 1, characterized in that The last byte of the specific MAC address indicates the CPU core ID where the session is located.

3. The method according to claim 1, characterized in that The FDIR rule distributes the message to the corresponding network card packet receiving queue according to the last byte value of the destination MAC address.

4. The method according to claim 1, characterized in that: The service messages and session synchronization messages are processed on the same CPU core of different DPVS nodes to ensure the consistency and continuity of session information.

5. The method according to claim 1, characterized in that When a node in the DPVS cluster fails, service packets are switched to other nodes for processing, and session loss does not occur.

6. The method according to claim 1, characterized in that When the service message is sent to the RS, its source MAC address is modified to a specific MAC address containing the CPU core ID.

7. The method according to claim 6, characterized in that The service message returned by the RS is distributed to the designated CPU core of the target node for processing according to the destination MAC address, and the return session information is created on the CPU core.

8. The method according to claim 1, characterized in that The last byte of the destination MAC address of the session synchronization message and the return session synchronization message both indicates the CPU core ID where the session is located.

9. A MAC-based CPU inter-core session synchronization device, characterized in that: The device comprises: The network card is used to distribute the service messages to a designated queue through the RSS function, and the designated queue is bound to the designated core of the CPU; A configuration module, used for configuring FDIR rules on the network card, wherein the FDIR rules distribute the message to a designated packet receiving queue according to the destination MAC address of the message; A message processing module is used to embed a specific MAC address representing the CPU core ID of the session in the session synchronization message, and distribute the received session synchronization message to the same CPU core of the target node for processing according to the FDIR rule; The session management module is used to create and maintain session information on the CPU core of the target node.

10. An electronic device, characterized in that: include: Memory and processor; Memory: used to store computer programs; Processor: used to execute the computer program to implement the steps of the MAC-based CPU core inter-session synchronization method as described in any one of claims 1-8.

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