Data frame coding method, decoding method and device based on SPI communication protocol
By determining the frame header based on the mode control word and address bit in the SPI communication protocol, and determining the data bits in combination with the bit width and functional item requirements of the register, the problems of low data transmission efficiency and poor compatibility in the prior art are solved, and efficient and flexible data transmission is achieved.
Patent Information
- Application Number
- CN202510102953.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-30
AI Technical Summary
When facing different number and bit width registers, the data frame encoding method of the existing SPI communication protocol has low data transmission efficiency and poor compatibility, making it difficult to compatible with the communication requirements of short bit width registers.
By determining the frame header based on the mode control word and address bit, determining the data bits based on the bit width and functional item requirements of the register, then building data frames suitable for different registers to realize efficient data transmission based on the SPI communication protocol.
It improves data transmission efficiency, especially when transmitting long-bit wide registers, ensuring efficient data transmission, and is compatible with short-bit wide registers, improving communication flexibility.
Smart Images
Figure CN120075304A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor chip communication technologies, and in particular, to a data frame encoding method, a decoding method, and a device based on the SPI communication protocol. Background Art
[0002] In the communication control of semiconductor chips, the SPI protocol is usually used to control the reading and writing of control words in the internal register module of the chip.
[0003] For different chip sizes and the scale of control requirements in the same chip, different numbers and different bit widths of registers are used to write and read control words. For example, in the control of a mixed-signal integrated circuit chip, short-bit-width registers can be used for the individual control of small modules; while for those involving the whole and more control words, long-bit-width registers can be used; in addition, the control requirements of other digital functions of the chip also need to be compatible.
[0004] The existing frame format encoding is not comprehensive enough in terms of compatibility with the reading and writing of registers with different numbers and different bit widths, and different function controls. When facing a large number of registers with different lengths, a longer address bit will lead to a reduction in data transmission efficiency when using short-bit-width registers.
[0005] Based on this, a SPI communication data frame encoding method is needed to improve data transmission efficiency and ensure the compatibility of different registers and digital functions.
[0006] Therefore, in the existing process of data frame encoding and then data transmission based on the SPI communication protocol, there are problems of low data transmission efficiency and poor compatibility of registers and digital functions. Summary of the Invention
[0007] The present disclosure provides a data frame encoding method, a decoding method, a device, a device, and a storage medium based on the SPI communication protocol.
[0008] According to a first aspect of the present disclosure, there is provided a data frame encoding method based on the SPI communication protocol, the method comprising:
[0009] Determining a frame header based on a mode control word and an address bit, wherein the mode control word is used to determine different modes, and the address bit is used for register addressing;
[0010] Determining data bits based on the bit width of the register and the requirements of function items;
[0011] Determining a data frame according to the frame header and the data bits for data transmission based on the SPI communication protocol.
[0012] In some implementation manners of the first aspect, the method further comprises:
[0013] Configure the bit widths and address bits of different registers for reading and writing different-bit-width registers based on the determined data frame.
[0014] In some implementations of the first aspect, the method further includes:
[0015] When the mode control word is configured as the first type, the determined data frame supports writing to type-A registers;
[0016] When the mode control word is configured as the second type, the determined data frame supports writing to type-B registers;
[0017] When the mode control word is configured as the third type, the determined data frame supports writing to type-C registers;
[0018] When the mode control word is configured as the fourth type, the determined data frame supports writing to type-D registers;
[0019] When the mode control word is configured as the fifth type, the determined data frame supports reading from type-A registers;
[0020] When the mode control word is configured as the sixth type, the determined data frame supports reading from type-B registers;
[0021] When the mode control word is configured as the seventh type, the determined data frame supports reading from type-C registers;
[0022] When the mode control word is configured as the eighth type, the determined data frame supports reading from type-D registers.
[0023] In some implementations of the first aspect, the mode control word includes 3-bit data; the address bits include 5-bit data.
[0024] According to a second aspect of the present disclosure, there is provided a method for decoding a data frame based on the SPI communication protocol, the method including:
[0025] Receive a data frame determined based on a frame header and data bits according to the SPI communication protocol;
[0026] Parse the frame header in the data frame to obtain a mode control word and address bits;
[0027] Parse the data bits to obtain the bit width of the register and the functional item requirements;
[0028] Determine the corresponding working mode based on the mode control word and perform register addressing based on the address bits.
[0029] In some implementations of the second aspect, the received data frame is determined based on the bit widths and address bits of different registers for reading and writing different-bit-width registers.
[0030] According to a third aspect of the present disclosure, there is provided a data frame decoding device based on the SPI communication protocol, the device comprising:
[0031] a receiving module, configured to receive a data frame determined based on a frame header and data bits according to the SPI communication protocol;
[0032] a parsing module, configured to parse the frame header in the data frame to obtain a mode control word and an address bit;
[0033] the parsing module is further configured to parse the data bits to obtain the bit width of the register and the functional item requirements;
[0034] a processing module, configured to determine a corresponding working mode based on the mode control word and perform register addressing based on the address bit.
[0035] According to a fourth aspect of the present disclosure, there is provided an electronic device, the electronic device comprising: a memory and a processor, a computer program is stored on the memory, and when the processor executes the program, the above method is implemented.
[0036] According to a fifth aspect of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above method is implemented.
[0037] In the present disclosure, the frame header is determined based on the mode control word and the address bit, wherein the mode control word is used to determine different modes, and the address bit is used for register addressing; the data bits are determined based on the bit width of the register and the functional item requirements; the data frame is determined according to the frame header and the data bits for data transmission based on the SPI communication protocol. The present disclosure configures the bit widths and address bits of different registers to realize the reading and writing of registers with different bit widths based on the determined data frame, which can not only ensure high data transmission efficiency when transmitting long-bit-width registers, but also be compatible with short-bit-width registers to ensure communication flexibility.
[0038] It should be understood that the content described in the summary of the invention section is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In combination with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the embodiments of the present disclosure will become more obvious. The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:
[0040] Figure 1 shows a schematic flowchart of a data frame encoding method based on the SPI communication protocol according to an embodiment of the present disclosure;
[0041] Figure 2 Shows a read-write timing diagram according to an embodiment of the present disclosure;
[0042] Figure 3 Shows a schematic diagram of read-write in a different mode according to an embodiment of the present disclosure;
[0043] Figure 4 Shows a timing diagram of writing to a register of type A according to an embodiment of the present disclosure;
[0044] Figure 5 Shows a timing diagram of writing to a register of type B according to an embodiment of the present disclosure;
[0045] Figure 6 Shows a timing diagram of writing to a register of type C according to an embodiment of the present disclosure;
[0046] Figure 7 Shows a timing diagram of writing to a register of type D according to an embodiment of the present disclosure;
[0047] Figure 8 Shows a timing diagram of reading from a register of type A according to an embodiment of the present disclosure;
[0048] Figure 9 Shows a timing diagram of reading from a register of type B according to an embodiment of the present disclosure;
[0049] Figure 10 Shows a timing diagram of reading from a register of type C according to an embodiment of the present disclosure;
[0050] Figure 11 Shows a timing diagram of reading from a register of type D according to an embodiment of the present disclosure;
[0051] Figure 12 Shows a schematic flowchart of a data frame decoding method based on the SPI communication protocol according to an embodiment of the present disclosure;
[0052] Figure 13 Shows a block diagram of a data frame encoding device based on the SPI communication protocol according to an embodiment of the present disclosure;
[0053] Figure 14 Shows a block diagram of a data frame decoding device based on the SPI communication protocol according to an embodiment of the present disclosure;
[0054] Figure 15 Shows a block diagram of an exemplary electronic device capable of implementing the embodiments of the present disclosure. Detailed implementation manners
[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.
[0056] In addition, the term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.
[0057] In the present disclosure, to solve the above technical problems, the frame header is determined based on the mode control word and the address bit. Among them, the mode control word is used to determine different modes, and the address bit is used for register addressing; the data bit is determined based on the bit width of the register and the functional item requirements; the data frame is determined according to the frame header and the data bit to perform data transmission based on the SPI communication protocol. The present disclosure can configure the bit widths and address bits of different registers to realize the reading and writing of registers with different bit widths based on the determined data frame, which can not only ensure high data transmission efficiency when transmitting long-bit-width registers, but also be compatible with short-bit-width registers to ensure communication flexibility.
[0058] Figure 1 The flowchart of a data frame encoding method based on the SPI communication protocol provided by an embodiment of the present disclosure is shown, as Figure 1 shown, the data frame encoding method 100 based on the SPI communication protocol may include:
[0059] S101, determining a frame header based on a mode control word and an address bit, where the mode control word is used to determine different modes, and the address bit is used for register addressing.
[0060] Figure 2 The read / write timing diagram provided by an embodiment of the present disclosure is shown. It should be further noted that, in combination with Figure 2 shown, the SPI communication adopted by the present disclosure uses a four-wire structure, and the port signals include a clock signal (CLK), a chip select signal (CSB), a host transmit slave receive (PDI), and a slave transmit host receive (PDO). When the CSB signal is at a low level, data exchange is performed between the master device and the slave device. The master device performs data acquisition and data transmission at the falling edge of the clock, and the slave device performs data acquisition and data transmission at the rising edge of the clock.
[0061] S102, determining a data bit based on the bit width of the register and the functional item requirements.
[0062] In order to be able to read and write registers with different bit widths, in some embodiments, the bit widths and address bits of different registers can be configured to be used for reading and writing registers with different bit widths based on a determined data frame.
[0063] Specifically, data is transmitted in the form of a data frame, which can be divided into two parts: a frame header and data bits. For the convenience of single-chip microcomputer communication, in a specific example, the frame header can be set to 8 bits (bits 0 to 7), and the data bits can be flexibly selected according to the bit width of the register and the requirements of the function items. Among them, bits 0, 1, and 2 can be mode control words, which can support 2^3 = 8 different modes.
[0064] Figure 3 is a schematic diagram of reading and writing in different modes provided by an embodiment of the present disclosure. As Figure 3 shown, in order to implement the reading and writing functions of multiple modes, in some embodiments, when the mode control word is configured as the first type (000), the determined data frame supports writing to type A registers;
[0065] when the mode control word is configured as the second type (001), the determined data frame supports writing to type B registers;
[0066] when the mode control word is configured as the third type (010), the determined data frame supports writing to type C registers;
[0067] when the mode control word is configured as the fourth type (011), the determined data frame supports writing to type D registers;
[0068] when the mode control word is configured as the fifth type (100), the determined data frame supports reading from type A registers;
[0069] when the mode control word is configured as the sixth type (101), the determined data frame supports reading from type B registers;
[0070] when the mode control word is configured as the seventh type (110), the determined data frame supports reading from type C registers;
[0071] when the mode control word is configured as the eighth type (111), the determined data frame supports reading from type D registers.
[0072] Figure 4 is a timing diagram of writing to type A registers provided by an embodiment of the present disclosure. As Figure 4As shown, when the mode control word is configured as the first type (000), that is, the mode control word is configured as 000, it supports writing to type A registers. The maximum number of supported registers is 32. It is agreed that 0x00 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0073] Figure 5 is a timing diagram of writing to type B registers provided by an embodiment of the present disclosure, as Figure 5 As shown, when the mode control word is configured as the second type (001), that is, the mode control word is configured as 001, it supports writing to type B registers. The maximum number of supported registers is 32. It is agreed that 0x20 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0074] Figure 6 is a timing diagram of writing to type C registers provided by an embodiment of the present disclosure, as Figure 6 As shown, when the mode control word is configured as the third type (010), that is, the mode control word is configured as 010, it supports writing to type C registers. The maximum number of supported registers is 32. It is agreed that 0x40 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0075] Figure 7 is a timing diagram of writing to type D registers provided by an embodiment of the present disclosure, as Figure 7 As shown, when the mode control word is configured as the fourth type (011), that is, the mode control word is configured as 011, it supports writing to type D registers. The maximum number of supported registers is 32. It is agreed that 0x60 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0076] Figure 8 is a timing diagram of reading type A registers provided by an embodiment of the present disclosure, as Figure 8 As shown, when the mode control word is configured as the fifth type (100), that is, the mode control word is configured as 100, it supports reading type A registers. The maximum number of supported registers is 32. It is agreed that 0x00 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0077] Figure 9 is a timing diagram of reading type B registers provided by an embodiment of the present disclosure, as Figure 9As shown, when the mode control word is configured as the sixth type (101), that is, the mode control word is configured as 101, it supports reading of type B registers. The maximum number of supported registers is 32. It is agreed that 0x20 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0078] Figure 10 is a timing diagram of reading type C registers provided by an embodiment of the present disclosure. As Figure 10 shown, when the mode control word is configured as the seventh type (110), that is, the mode control word is configured as 110, it supports reading of type C registers. The maximum number of supported registers is 32. It is agreed that 0x40 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0079] Figure 11 is a timing diagram of reading type D registers provided by an embodiment of the present disclosure. As Figure 11 shown, when the mode control word is configured as the eighth type (111), that is, the mode control word is configured as 111, it supports reading of type D registers. The maximum number of supported registers is 32. It is agreed that 0x60 is the initial address, and the 3rd to 7th bits are the register offset address bits. The data bit X is agreed in advance in the communication protocol.
[0080] That is to say, the 3rd to 7th bits can be used as address bits to achieve register addressing. There is no requirement for the length of the data bit. The register length and address are agreed in the protocol, so that the read and write functions of registers with different bit widths can be realized. It can not only ensure high data transmission efficiency when transmitting long-bit-width registers, but also be compatible with short-bit-width registers to ensure communication flexibility.
[0081] In the above embodiment, in order to be compatible with more types of registers, the above mode control word can include 3-bit data and can also be adjusted according to actual situations; the address bit can include 5-bit data and can also be adjusted according to actual situations, which is not limited here.
[0082] S103. Determine the data frame based on the frame header and data bit to perform data transmission based on the SPI communication protocol.
[0083] In the process of S101 - S103, by configuring the bit widths and address bits of different registers, the reading and writing of registers with different bit widths are realized based on the determined data frame. It can not only ensure high data transmission efficiency when transmitting long-bit-width registers, but also be compatible with short-bit-width registers to ensure communication flexibility.
[0084] Figure 12 shows a schematic flowchart of a data frame decoding method based on the SPI communication protocol provided by an embodiment of the present disclosure. AsFigure 12 As shown in Figure 12 , the data frame decoding method 1200 based on the SPI communication protocol may include:
[0085] S1201, receiving a data frame determined based on a frame header and data bits according to the SPI communication protocol;
[0086] S1202, parsing the frame header in the data frame to obtain a mode control word and address bits;
[0087] S1203, parsing the data bits to obtain the bit width of the register and the functional item requirements;
[0088] S1204, determining the corresponding working mode based on the mode control word and performing register addressing based on the address bits.
[0089] In some embodiments, the received data frame is determined based on the bit widths and address bits of different registers for reading and writing registers with different bit widths.
[0090] In the process of S1201 - S1204, the received data frame is implemented by configuring the bit widths and address bits of different registers, and thus the reading and writing of registers with different bit widths can be achieved based on the determined data frame. This can not only ensure high data transmission efficiency when transmitting long-bit-width registers but also be compatible with short-bit-width registers to ensure communication flexibility.
[0091] The above is the introduction of the method embodiments. The following further illustrates the solution of the present disclosure through device embodiments.
[0092] Figure 13 Shows a block diagram of a data frame encoding device based on the SPI communication protocol according to an embodiment of the present disclosure.
[0093] As Figure 13 shown in Figure 13 , the data frame encoding device 1300 based on the SPI communication protocol may include:
[0094] A frame header determination module 1301, configured to determine a frame header based on a mode control word and address bits, where the mode control word is used to determine different modes and the address bits are used for register addressing;
[0095] A data bit determination module 1302, configured to determine data bits based on the bit width of the register and the functional item requirements;
[0096] A data frame determination module 1303, configured to determine a data frame according to the frame header and the data bits for data transmission based on the SPI communication protocol.
[0097] In some embodiments, the data bit determination module 1302 may also be used to configure the bit widths and address bits of different registers for reading and writing registers with different bit widths based on the determined data frame.
[0098] In some embodiments, when the mode control word is configured as the first type, the determined data frame supports writing to type A registers;
[0099] When the mode control word is configured as the second type, the determined data frame supports writing to type B registers;
[0100] When the mode control word is configured as the third type, the determined data frame supports writing to type C registers;
[0101] When the mode control word is configured as the fourth type, the determined data frame supports writing to type D registers;
[0102] When the mode control word is configured as the fifth type, the determined data frame supports reading from type A registers;
[0103] When the mode control word is configured as the sixth type, the determined data frame supports reading from type B registers;
[0104] When the mode control word is configured as the seventh type, the determined data frame supports reading from type C registers;
[0105] When the mode control word is configured as the eighth type, the determined data frame supports reading from type D registers.
[0106] In some embodiments, the mode control word may include 3-bit data, and the address bits may include 5-bit data.
[0107] Figure 14 A block diagram of a data frame decoding device based on the SPI communication protocol according to an embodiment of the present disclosure is shown.
[0108] As Figure 14 shown, the data frame decoding device 1400 based on the SPI communication protocol may include:
[0109] A receiving module 1401, configured to receive a data frame determined based on a frame header and data bits according to the SPI communication protocol;
[0110] A parsing module 1402, configured to parse the frame header in the data frame to obtain a mode control word and address bits;
[0111] The parsing module 1402 is further configured to parse the data bits to obtain the bit width of the register and the functional item requirements;
[0112] A processing module 1403 is configured to determine a corresponding working mode based on the pattern control word and perform register addressing based on address bits.
[0113] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present disclosure is not limited by the described action sequence, because according to the present disclosure, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present disclosure.
[0114] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the described modules can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.
[0115] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.
[0116] Figure 15 A block diagram of an exemplary electronic device capable of implementing the embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0117] The device 1500 includes a computing unit 1501, which can execute various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1502 or a computer program loaded from a storage unit 1508 into a random access memory (RAM) 1503. In the RAM 1503, various programs and data required for the operation of the device 1500 can also be stored. The computing unit 1501, the ROM 1502, and the RAM 1503 are connected to each other through a bus 1504. An input / output (I / O) interface 1505 is also connected to the bus 1504.
[0118] Multiple components in device 1500 are connected to I / O interface 1505, including: an input unit 1506, such as a keyboard, a mouse, etc.; an output unit 1507, such as various types of displays, speakers, etc.; a storage unit 1508, such as a disk, an optical disc, etc.; and a communication unit 1509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1509 allows device 1500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.
[0119] The computing unit 1501 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1501 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1501 executes the various methods and processes described above, such as method 100 or method 1200. For example, in some embodiments, method 100 or method 1200 can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 1508. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 1500 via the ROM 1502 and / or the communication unit 1509. When the computer program is loaded into the RAM 1503 and executed by the computing unit 1501, one or more steps of method 100 described above, or one or more steps of method 1200 described above, can be executed.
[0120] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), application-specific standard products (ASSP), systems-on-chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special or general programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.
[0121] The program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.
[0122] In the context of the present disclosure, a machine-readable medium may be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0123] In order to provide interaction with a user, the systems and techniques described herein may be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0124] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.
[0125] A computer system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, a server of a distributed system, or a server incorporating blockchain.
[0126] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this disclosure can be achieved, and this is not limited herein.
[0127] The above specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.
Claims
1. A data frame encoding method based on SPI communication protocol, characterized in that: The method comprises: Determine the frame header based on a mode control word and an address bit, wherein the mode control word is used to determine different modes and the address bit is used for register addressing; Determine the data bits based on the bit width of the register and the functional requirements; A data frame is determined according to the frame header and the data bits to perform data transmission based on the SPI communication protocol.
2. The method according to claim 1, characterized in that The method further comprises: The bit widths and address bits of different registers are configured to implement reading and writing of registers with different bit widths based on a determined data frame.
3. The method according to claim 1, characterized in that The method further comprises: When the mode control word is configured as the first type, the determined data frame supports writing to the A type register; When the mode control word is configured as the second type, the determined data frame supports B-type register writing; When the mode control word is configured as the third type, the determined data frame supports C type register writing; When the mode control word is configured as the fourth type, the determined data frame supports D type register writing; When the mode control word is configured as the fifth type, the determined data frame supports A type register reading; When the mode control word is configured as the sixth type, the determined data frame supports B-type register reading; When the mode control word is configured as the seventh type, the determined data frame supports C type register reading; When the mode control word is configured as the eighth type, the determined data frame supports D type register reading.
4. The method according to claim 1, characterized in that: The mode control word includes 3 bits of data; The address bits include 5 bits of data.
5. A data frame decoding method based on SPI communication protocol, characterized in that: The method comprises: Receive a data frame determined based on a frame header and data bits according to an SPI communication protocol; Parsing the frame header in the data frame to obtain a mode control word and an address bit; Parsing the data bits to obtain the bit width and function item requirements of the register; The corresponding working mode is determined based on the mode control word, and register addressing is performed based on the address bit.
6. The method according to claim 5, characterized in that The received data frame is determined based on the bit width and address bits of different registers for reading and writing registers of different bit widths.
7. A data frame encoding device based on SPI communication protocol, characterized in that: The device comprises: A frame header determination module, used for determining the frame header based on a mode control word and an address bit, wherein the mode control word is used for determining different modes, and the address bit is used for register addressing; A data bit determination module, used to determine the data bit based on the bit width of the register and the functional item requirements; The data frame determination module is used to determine the data frame according to the frame header and the data bit to perform data transmission based on the SPI communication protocol.
8. A data frame decoding device based on SPI communication protocol, characterized in that: The device comprises: A receiving module, used for receiving a data frame determined based on a frame header and data bits according to an SPI communication protocol; A parsing module, used for parsing the frame header in the data frame to obtain a mode control word and an address bit; The parsing module is further used to parse the data bits to obtain the bit width and function item requirements of the register; The processing module is used to determine the corresponding working mode based on the mode control word and perform register addressing based on the address bit.
9. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; It is characterized in that the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.