Data cache control method and system, electronic equipment and storage medium

Abstract

The invention discloses a data caching control method and system, electronic equipment and a storage medium, and relates to the field of data processing. The invention provides a system capable of being used for TDI data superposition, and the method comprises the steps: employing a ratio of a pixel line interval to pixels in an image sensor and a light source number to calculate a numerical value, and taking the numerical value as a total stage number of a cache region in a data cache module; and overlapping the row pixel data generated in the image sensor with the data in the last-stage cache region in the data cache module, inputting the overlapped data into the next data cache module, and enabling the data in the cache region to flow downwards stage by stage. Therefore, based on the hardware structure, for one frame of image data generated after each exposure, TDI superposition of row pixel data in the image sensor can be realized only according to a fixed process of data writing and caching, and a spatial position corresponding to a cache region does not need to be calculated, so that the image data superposition efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of data processing, and particularly relates to a data cache control method, system, electronic device, and storage medium. Background Art

[0002] In the field of machine vision, with the continuous improvement of the requirements for detection accuracy and detection efficiency, multi-line TDI cameras are increasingly widely used. Compared with ordinary linear array cameras with only one row of pixels, the typical feature of multi-line TDI cameras is that there are multiple rows of photosensitive pixels inside their TDI sensors (i.e., the image sensors in this application). For example, currently, multi-line TDI cameras with 2 rows or 4 rows of pixels are already relatively common, and there are even more multi-line TDI cameras with 12 rows or even 16 rows of photosensitive pixels.

[0003] Compared with multi-line TDI cameras with a higher number of rows (such as 256 rows), the feature of low-order pixel row multi-line TDI cameras is that their image sensors usually do not have the TDI stacking function. After all the image data corresponding to the pixels of all rows are read out from the TDI sensor, the TDI data stacking needs to be completed in the backend processor, which poses a high requirement for the cache space of the backend processor.

[0004] In order to reduce the cache space of the backend processor, the Chinese patent "CN118784994A A TDI Data Cache Method, System, Electronic Device, and Storage Medium" proposes a solution. During the TDI data stacking process, by repeatedly using the same buffer and adopting the method of reading, stacking, and rewriting the data to be stacked simultaneously, compared with the traditional multi-line cache parallel stacking method, the RAM cache resources can be reduced by more than half.

[0005] However, in the above TDI data cache solution, during each stacking process, it is necessary to calculate the cache address of each row of data according to factors such as the reading cycle, the total number of sensor rows, and the total number of light sources. When the number of sensor lines and the number of light source partitions increase, the calculation process of the cache address will become complex, and the consumption of logical resources will also increase significantly. Therefore, on the basis of reducing the TDI cache space, there is still room for improvement in the TDI data stacking efficiency. Summary of the Invention

[0006] A data cache control method, system, electronic device, and storage medium proposed in this application are used to further improve the TDI data stacking efficiency on the basis of reducing the TDI data cache space.

[0007] To achieve the above object, the present application proposes the following technical solutions: In the first aspect of the present application, a data cache control system is provided, including: N FIFO buffers connected in series, corresponding one by one to the pixel rows in the image sensor, for receiving and buffering the row pixel data sequentially output by the image sensor to output the data of N pixel rows simultaneously; wherein, the pixel rows in the image sensor are sorted according to the sequence of photographing the same area to be measured under the same light source; N represents the total number of pixel rows, and N≥2; N-1 adders, corresponding one by one to the pixel rows in the image sensor except the first row. Each adder is used for receiving the data of the corresponding pixel row output by the FIFO buffer and adding it to the data in the last buffer area of the data buffer module corresponding to the previous pixel row, and inputting the added data into the data buffer module corresponding to the next pixel row or using it as the data after addition; N-1 data buffer modules, corresponding one by one to the pixel rows in the image sensor except the last row, all including M buffer areas, for receiving the data of the first row of pixels or the added data, and sequentially moving the data in each buffer area to the next buffer area; wherein, M = A×B, A represents the integer obtained by rounding up the ratio of the pixel row interval to the pixel in the image sensor plus one, and B represents the number of light sources.

[0008] Optionally, in the N FIFO buffers connected in series, each FIFO buffer buffers the data of one row of pixels.

[0009] Optionally, the data buffer module is composed of one or more data buffer devices; Wherein, one data buffer device serves as one buffer area; or, the buffer space in one data buffer device is divided to form multiple buffer areas.

[0010] Optionally, each buffer area buffers the data of one row of pixels.

[0011] Optionally, the data buffer control system further includes: N data registers connected in parallel, replacing the N FIFO buffers connected in series, corresponding one by one to the pixel rows in the image sensor, for receiving and buffering the row pixel data sequentially output by the image sensor to output the data of N pixel rows simultaneously; wherein, one data register stores the data of one row of pixels.

[0012] In the second aspect of the present application, a data buffer control method is provided, which is applied to the system according to any one of the first aspect, and includes: Based on N FIFO buffers connected in series, receiving and buffering the row pixel data sequentially output by the image sensor, and sequentially moving the data of each row of pixels to the next FIFO buffer until the N FIFO buffers connected in series buffer the data of N pixel rows in total; wherein, N represents the total number of pixel rows, and N≥2; Input the data of N cached pixel rows into N - 1 adders and 1 data cache module simultaneously; for each adder, obtain the data in the last - level buffer area of the data cache module corresponding to the pixel row of the previous row of the data input into this adder, and superimpose it with the data in the same adder to obtain the superimposed data; wherein, the pixel rows in the image sensor are sorted according to the sequence of photographing the same area to be measured under the same light source; the adders correspond one - to - one with the pixel rows in the image sensor except the first row; the data cache module corresponds one - to - one with the pixel rows in the image sensor except the last row; the data of the first - row pixels in the image sensor is input into the first - level buffer area of the corresponding data cache module; Shift the data in each level of the buffer area in the data cache module to the next - level buffer area in sequence; Input the superimposed data into the first - level buffer area of the data cache module or use it as the data after completion of superimposition.

[0013] Optionally, if N parallel data registers replace N serial FIFO buffers in the system, before inputting the data of N cached pixel rows into N - 1 adders and 1 data cache module simultaneously, the method further includes: Based on N parallel data registers, receive and cache the row - pixel data sequentially output by the image sensor until the data of N row pixels is cached in N parallel data registers; wherein, the data registers correspond one - to - one with the pixel rows, and one data register caches the data of one row of pixels.

[0014] Optionally, each level of the buffer area caches the data of one row of pixels.

[0015] In the third aspect of the present application, an electronic device is provided, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus; The memory is used to store a computer program; The processor, when executing the program stored on the memory, implements the data cache control method described in any one of the second aspects.

[0016] In the fourth aspect of the present application, a computer - readable storage medium is provided. The computer - readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the data cache control method described in any one of the second aspects.

[0017] The beneficial effects of the present application are as follows: The present application provides a data cache control system, including: N FIFO buffers connected in series, corresponding one by one to the pixel rows in the image sensor, for receiving and buffering the row pixel data sequentially output by the image sensor to simultaneously output the data of N rows of pixels; wherein, the pixel rows in the image sensor are sorted according to the sequence of photographing the same area to be measured under the same light source; N represents the total number of pixel rows, and N≥2; N-1 adders, corresponding one by one to the pixel rows in the image sensor except the first row. Each adder is used to receive the data of the corresponding pixel row output by the FIFO buffer and add it to the data in the last buffer area of the data buffer module corresponding to the previous pixel row, and input the added data into the data buffer module corresponding to the next pixel row or use it as the completed added data; N-1 data buffer modules, corresponding one by one to the pixel rows in the image sensor except the last row, all including M buffer areas, for receiving the data of the first row of pixels or the added data, and sequentially moving the data in each buffer area to the next buffer area; wherein, M = A×B, A represents the integer obtained by rounding up the ratio of the pixel row interval to the pixel in the image sensor plus one, and B represents the number of light sources.

[0018] Based on the above processing, the present application provides a system hardware structure for TDI data addition, using the value calculated from the ratio of the pixel row interval to the pixel in the image sensor and the number of light sources as the total number of buffer areas in the data buffer module, adding the row pixel data generated in the image sensor to the data in the last buffer area of the data buffer module, and inputting the added data into the next data buffer module, and after adding each row of pixels, the data in the buffer area flows down step by step.

[0019] Thus, based on the hardware structure design provided by the above system, for each frame of image data generated after each exposure, only by following the fixed process of data writing and buffering, the TDI addition of the row pixel data in the image sensor can be realized, without calculating the corresponding spatial position of the buffer area, improving the efficiency of image data addition. Description of the Drawings

[0020] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and the schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings: Figure 1 is a structural diagram of a data buffer control system provided by the present application; Figure 2 is a structural diagram of another data buffer control system provided by the present application; Figure 3 is a structural diagram of another data buffer control system provided by the present application; Figure 4 It is a structural diagram of another data cache control system provided by this application; Figure 5 It is a structural diagram of an electronic device provided by this application. Detailed implementation manners

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some but not all of the embodiments of this application.

[0022] TDI (Time Delay Integration) technology can utilize the advantage of multiple rows of pixels in a line array sensor (i.e., the image sensor of this application). By matching the relationship between the object movement speed and the line frequency, the same position of the object to be measured can be imaged onto different rows of pixels of the line array sensor at different times. Further, by superimposing the imaging results of different rows of pixels, a higher image signal-to-noise ratio can be achieved.

[0023] In existing multi-line TDI sensors, usually after reading out the graphic data corresponding to all rows of pixels, the TDI data is superimposed in the backend processor, which requires a large amount of cache space. To reduce the cache space of the backend processor, Chinese Patent "CN118784994A A TDI Data Caching Method, System, Electronic Device, and Storage Medium" proposes a solution. During the TDI data superimposing process, by repeatedly using the same buffer and adopting the method of reading, superimposing, and rewriting the data to be superimposed on the fly, compared with the traditional multi-line cache parallel superimposing method, the RAM cache resources are reduced by more than half.

[0024] However, in the above TDI data caching solution, during each superimposing process, it is necessary to calculate the cache address of each row of pixel data (i.e., the data of one row of pixels in this application) according to factors such as the reading cycle, the total number of sensor rows, and the total number of light sources. When the number of sensor lines and the number of light source partitions increase, the calculation process of the cache address will become complex, and the corresponding consumption of logical resources will also increase significantly, reducing the superimposing efficiency of the image data generated by the TDI sensor.

[0025] To solve the above problems, this application proposes a data cache control system, including: N FIFO buffers connected in series, corresponding one-to-one with the pixel rows in the image sensor, are used to receive and buffer the row pixel data successively output by the image sensor, so as to output the pixel data of N rows simultaneously; wherein, the pixel rows in the image sensor are sorted according to the sequence of photographing the same area to be measured under the same light source; N represents the total number of pixel rows, and N≥2.

[0026] N-1 adders, corresponding one-to-one with the pixel rows in the image sensor except the first row, each adder is used to receive the data output by the FIFO buffer and corresponding to the pixel row, and add it to the data in the last buffer area of the data buffer module corresponding to the previous pixel row, and input the added data into the data buffer module corresponding to the next pixel row or use it as the row pixel data after addition.

[0027] N-1 data buffer modules, corresponding one-to-one with the pixel rows in the image sensor except the last row, all contain M buffer areas, are used to receive the data of the first row of pixels or the added data, and shift the data in each buffer area to the next buffer area in turn. Wherein, M = A×B, A represents the integer part of the ratio of the pixel row interval to the pixel in the image sensor plus one, and B represents the number of light sources.

[0028] Based on the above processing, the present application provides a system hardware structure for TDI data addition, using the value calculated from the ratio of the pixel row interval to the pixel in the image sensor and the number of light sources as the total number of buffer areas in the data buffer module, adding the row pixel data generated in the image sensor to the data in the last buffer area of the data buffer module, and inputting the added data into the next data buffer module, and after adding each row of pixels, the data in the buffer area flows down level by level.

[0029] Thus, based on the hardware structure design provided by the above system, for each frame of image data generated after each exposure, only by following the fixed process of data writing and buffering, the TDI addition of the row pixel data in the image sensor can be realized, without calculating the corresponding spatial position of the buffer area, improving the efficiency of image data addition.

[0030] In the technical solution provided by the present application, the total number of pixel rows in the image sensor is N, and the pixel rows are sorted according to the sequence of photographing the same area to be measured by different pixel rows, and are divided into the first row, the second row to the Nth row.

[0031] Among them, the pixel data generated by the first row of pixels is used as the first row pixel data in the present application; the pixel data generated by the Nth row of pixels is used as the last row pixel data in the present application.

[0032] A row pixel read cycle represents the time taken for an image sensor to output data for one row of pixels (or, to obtain data for one row of pixels within the image sensor). In the technical solution provided in this application, within one row pixel read cycle, the image sensor outputs data for one row of pixels.

[0033] After one exposure, pixel values are generated at each pixel point within the image sensor, forming one frame of image. The data cache control system provided in this application sequentially obtains data for one row of pixels from the above-mentioned one frame of image data within each row pixel read cycle. Sequentially obtaining means obtaining the data generated by one row of pixels in sequence based on the arrangement order of the pixel rows.

[0034] In some embodiments, the N serially-connected FIFO (First Input First Output) buffers provided in this application belong to a serially-connected row buffer FIFO queue to enable obtaining of multiple rows of pixel data at the same time. Among them, each FIFO buffer caches data for one row of pixels.

[0035] Considering that one frame of image generated by the image sensor after each exposure contains N rows of pixel data, the data cache control system provided in this application includes N serially-connected FIFO buffers to enable simultaneous reading of the subsequent N - 1 rows of pixel data in one frame of image. The corresponding reading process is as follows: As Figure 1 shown, within one row pixel read cycle, the image sensor outputs data for one row of pixels. At the same time, according to the order of the pixel rows, the image sensor sequentially outputs the data for the first row of pixels to the data for the Nth row of pixels.

[0036] When the data for the first row of pixels is input, FIFO buffer 1 performs writing and does not read out; the remaining FIFO buffers neither write nor read out; When the data for the second row of pixels is input, FIFO buffer 1 writes the data for the second row of pixels and synchronously reads out the data for the first row of pixels; FIFO buffer 2 writes the data for the first row of pixels and does not read out; the remaining FIFO buffers neither write nor read out; When the data for the third row of pixels is input, FIFO buffer 1 writes the data for the third row of pixels and synchronously reads out the data for the second row of pixels; FIFO buffer 2 writes the data for the second row of pixels and simultaneously reads out the data for the first row of pixels; FIFO buffer 3 writes the data for the first row of pixels and does not read out; the remaining FIFO buffers neither write nor read out; By analogy, when the pixel data of the Nth row is input, the FIFO buffer 1 writes the pixel data of the Nth row, and at the same time reads out the pixel data of the N-1th row to the FIFO buffer 1; the FIFO buffer 2 writes the pixel data of the N-1th row, and at the same time reads out the pixel data of the N-2th row to the FIFO buffer 3; similarly, the FIFO buffer N writes the pixel data of the first row and does not read out.

[0037] Then, the FIFO buffers 1 to N-1 input the pixel data of the last N-1 rows in the image sensor into N-1 adders at the same time.

[0038] The working process of the above N cascaded FIFO buffers can be understood as follows: After any exposure, for a frame of image generated by the image sensor, during the process of inputting this frame of image into the FIFO buffer, it is judged whether to read and write to the next-level FIFO buffer according to the empty signals inside all FIFO buffers. That is, the FIFO buffer without an empty signal reads out and writes to the next level, and the FIFO buffer with an empty signal does not read out. Among them, each FIFO buffer writes a row of pixel data, and after a complete image frame is input and read out to the adder at the same time, all FIFO buffers are cleared.

[0039] In one implementation, the adder represents an electronic device that can complete data superposition, and a look-up table can also be used instead.

[0040] In addition, in the image sensor, except for the pixels of the first row, the pixels of the remaining rows correspond to the adders one by one. That is, the corresponding adder is used to receive and superimpose the data generated by the corresponding pixel row.

[0041] Except for the adder of the Nth row, the output ends of the remaining adders are all connected to a data cache module. Among them, the connected data cache module is used to receive and cache the superimposed data.

[0042] It can be seen that in the image data superposition system provided in this application, there are N-1 data cache modules. For the image sensor, except for the pixels of the last row, the pixels of the remaining rows correspond to the data cache modules one by one. Specifically, the first-row data cache module is used to cache the data generated by the first-row pixels. At the same time, except for the first-row data cache module, the remaining data cache modules are used to cache the data after superimposing the data generated by the corresponding pixel rows. Specifically, the second-row data cache module is used to cache the data after superimposing the data generated by the second-row pixels and the data in the last-level cache area of the first-row data cache module; the third-row data cache module is used to cache the data after superimposing the data generated by the third-row pixels and the data in the last-level cache area of the second-row data cache module; by analogy, the (N-1)th-row data cache module is used to cache the data after superimposing the data generated by the (N-1)th-row pixels and the data in the last-level cache area of the (N-2)th-row data cache module.

[0043] For the data generated by the Nth row of pixels, after being superimposed with the data in the last buffer area of the (N - 1)th row data buffer module in the Nth row adder, it serves as the completed superimposed data and is directly input into the next processor.

[0044] Each data buffer module contains M levels of buffer areas. The first-level buffer area is used to store the image data generated by one row of pixels. The total number of levels M is obtained by multiplying the integer part of the ratio of the pixel row interval to the pixel in the TDI sensor by the number of light sources. Here, taking the integer part of the ratio means that when the ratio is an integer, the integer part is the value itself, and when the ratio is a non-integer, the ratio can be rounded up or down according to requirements.

[0045] The number of light sources can be used to represent the number of exposure times when the TDI sensor moves a single row of pixel distance. For example, in the single-light mode, the row frequency of the TDI sensor and the object movement speed ratio is 1:1; in the multi-light mode with multi-angle lighting, the number of light sources is B. At this time, the row frequency and the object movement speed ratio is B:1.

[0046] Therefore, the total number of levels M of the buffer areas in the data buffer module is obtained by multiplying the value A, which is the integer part of the ratio of the pixel row interval to the pixel in the image sensor plus one, by the number of light sources B. And after each row of pixel data is superimposed, in the data buffer module used to cache the superimposed data, the data in each level of the buffer area is transferred step by step downward. Thus, when the row pixel data output by the image sensor and the data in the intermediate buffer module belong to the row pixel data of the same area taken under the same light source, it conforms to the basic rules of row pixel data superposition in the TDI superposition field.

[0047] As Figure 1 shown, the image sensor reads out 1 row of pixel data at a time. In the data buffer control system provided by this application, it includes N FIFO buffers, N - 1 adders, and N - 1 data buffer modules. Among them, in this application, FIFO buffer 1 can be not set, and the function of simultaneously outputting N rows of pixel data is achieved by retaining N - 1 FIFO buffers.

[0048] The hardware connection structure of the system is as follows: The output end of the image sensor is connected to FIFO buffer 1, and the N FIFO buffers are connected in series with each other to form a row buffer FIFO queue. At the same time, from FIFO buffer 1 to FIFO buffer N - 1, each is connected to an adder, which is used to input the last N - 1 rows of pixel data in the image sensor into the N - 1 adders respectively after the N FIFO buffers complete the caching of N rows of pixel data.

[0049] The other input terminal of any adder is connected to the data buffer module corresponding to the previous pixel row, and the output terminal is connected to the data buffer module corresponding to the current pixel row. It should be noted that the output terminal of the adder corresponding to the Nth pixel row is directly connected to the next processor, and the data after internal superposition is used as the row pixel data after superposition and is input to the next processor. Among them, the previous pixel row refers to the pixel row immediately before the pixel row to which the row pixel data input to the adder belongs. The current pixel row refers to the pixel row to which the row pixel data input to the adder belongs.

[0050] In addition, except for the first row of pixels, the remaining row pixels correspond one-to-one with the adders; except for the last row of pixels, the remaining row pixels correspond one-to-one with the data buffer modules. The total number of buffer areas in each data buffer module is M.

[0051] The corresponding row pixel data superposition process is as follows: After one exposure, the image sensor generates an image frame containing N rows of pixels and sequentially outputs the row pixel data in the image frame in the order of row pixels. The N rows of pixel data output by the image sensor are sequentially stored in FIFO buffer N to FIFO buffer 1.

[0052] Then, the N FIFO buffers simultaneously input the N rows of pixel data generated by the image sensor to N - 1 adders and data buffer module 1. During the process of receiving the row pixel data, the adder simultaneously reads the data in the last-level buffer area in the data buffer module connected to the other input terminal, and then superimposes the row pixel data with the data in the last-level buffer area. Among them, the first row of pixel data is input to buffer area 1 in data buffer module 1 After the data in the adder is superimposed, it is input to the corresponding data buffer module. Among them, during the process of receiving the superimposed data by the data buffer module, the data in each level of buffer area inside is sequentially moved to the next-level buffer area. For example, after the second row of pixel data is superimposed, it is input to buffer area 1 of data buffer module 2, and after the (N - 1)th row of pixel data is superimposed, it is input to buffer area 1 of data buffer module (N - 1). It should be noted that after the Nth row of pixel data is superimposed, the superimposed data is used as the row pixel data after superposition and is directly output.

[0053] The following describes the specific superposition process of the foregoing data buffer control scheme in an application scenario where N = 4 and M = 2×2 = 4. For example, an image sensor with a total of 4 rows, a ratio of pixel row interval to pixel of 1, and 2 light sources (at this time, the ratio of line frequency to object movement speed is 2) meets the foregoing scenario. As Figure 2 shown, Figure 2 is a schematic structural diagram of another data buffer control system provided by the present application.

[0054] After each exposure, the image sensor generates data for 4 rows of pixels. During the data reading process, only the data of one row of pixels is read in each row pixel reading cycle, and the data is read in the order of L1, L2, L3, and L4. The data cache control system provided in this application includes 4 FIFO buffers, 3 adders, and 3 data cache modules. Each data cache module contains 4 buffer areas, namely buffer areas 10 to 13, buffer areas 20 to 23, and buffer areas 30 to 33.

[0055] Combined with the TDI superposition principle, it can be known that in this application scenario, the first row pixel data in the first exposure is superimposed with the second row pixel data in the fifth exposure. According to the foregoing solution content, each row of pixel data is input to the adder and superimposed with the data in the last-level buffer area in the corresponding data cache module of the previous pixel row. After the superposition, the data in the buffer area in the data cache module is transferred to the next buffer area.

[0056] Therefore, according to the structure setting and data transfer direction of this superposition system, it is possible to superimpose the data of the first pixel row in the first exposure with the data of the second pixel row in the fifth exposure, which conforms to the process of TDI superposition.

[0057] After the first exposure, the data generated by pixel row L1 is valid data L11. After 4 row pixel reading cycles, the row pixel data L11 is cached in FIFO buffer 4, the row pixel data L21 is cached in FIFO buffer 3, the row pixel data L31 is cached in FIFO buffer 2, and the row pixel data L41 is cached in FIFO buffer 1. Among them, the row pixel data L41 represents the row pixel data generated by pixel row L4 in the first exposure.

[0058] Then, the 4 FIFO buffers input the row pixel data L41, L31, and L21 to different adders, and the row pixel data L11 is input to buffer area 10. It should be noted that during the process of inputting the row pixel data L11 to buffer area 10, the data in each buffer area in data cache module 1 is gradually moved to the next buffer area. That is, the original data in buffer area 10 is moved to buffer area 11, the original data in buffer area 11 is moved to buffer area 12, the original data in buffer area 12 is moved to buffer area 13, and the original data in buffer area 13 is moved to the adder corresponding to the second row of pixels.

[0059] At the same time, each adder obtains the data in the last-level buffer area in the corresponding data cache module. Specifically, the row pixel data L41 is superimposed with the data in buffer area 33, the row pixel data L31 is superimposed with the data in buffer area 23, and the row pixel data L21 is superimposed with the data in buffer area 13.

[0060] After that, the superimposed data in the adder and the first-row pixel data in the FIFO buffer are respectively input into the first-level buffer of the corresponding data buffer module. Among them, after the last-row pixel data is superimposed, it serves as the superimposed row pixel data and is directly output.

[0061] Specifically, the row pixel data L11 is input into buffer 10, the row pixel data L21 and the data in buffer 13 are superimposed and then input into buffer 20, the row pixel data L31 and the data in buffer 23 are superimposed and then input into buffer 30, and the row pixel data L41 and the data in buffer 33 are superimposed and directly output. It should be noted that since, during the first exposure, except for the row pixel data L11, the rest of the row pixel data are invalid data, before L11 is superimposed, the obtained superimposed row pixel data are all discarded.

[0062] Similarly, based on the above processing, after the second exposure, the row pixel data L12 is located in buffer 10, and the row pixel L11 is located in buffer 11.

[0063] After the fourth exposure, the row pixel data L14 is located in buffer 10, the row pixel data L13 is located in buffer 11, the row pixel data L12 is located in buffer 12, and the row pixel data L11 is located in buffer 13.

[0064] After the fifth exposure, the row pixel data L25 is superimposed with the row pixel data L11 in buffer 13, and the superimposed data is input into buffer 20.

[0065] After that, after the 9th exposure, the data obtained by superimposing the row pixel data L25 and the row pixel data L11 has been transferred to buffer 23, and then it is superimposed with the row pixel data L39, and the superimposed data is input into buffer 30.

[0066] After the 13th exposure, the data obtained by superimposing the row pixel data L39, the row pixel data L25, and buffer 13 has been transferred to buffer 33, and then it is superimposed with the row pixel L413, and the superimposed data is used as the superimposed row pixel data and is directly input into the next processor.

[0067] In addition, the TDI superposition process corresponding to the rest of the row pixels (i.e., the data caching in this application) can be understood with reference to the above process.

[0068] In some embodiments, the data buffer module consists of one or more data buffers. For example, one buffer serves as the first-level buffer, that is, a data buffer module consists of M buffers. Among them, the first-level buffer corresponds to the number of one buffer.

[0069] Alternatively, the data cache module may consist of a data cache, such as a FIFO cache, and by dividing the cache space within a cache, M - level buffer areas are formed. Based on the above - mentioned processing, the utilization rate of the cache resources within the cache can be improved.

[0070] In one implementation, each level of buffer area caches the data of one row of pixels. Among them, the data of one row of pixels includes the data before superposition and the data after superposition.

[0071] In some embodiments, as Figure 3 shown, the data cache control system provided by the present application further includes: N parallel data registers, replacing the N serial FIFO caches, corresponding one - to - one with the pixel rows in the image sensor, for receiving and caching the row pixel data successively output by the image sensor, so as to output the data of the last N - 1 row pixels in the image sensor simultaneously; wherein, one data register stores the data of one row of pixels.

[0072] Compared with the N serial FIFO caches, in the system including N parallel data registers, each row of pixel data in the image sensor is directly input into the corresponding data register through a data selector (or multiplexer). Among them, the data registers correspond one - to - one with the pixel rows of the image sensor. Taking Figure 4 as an example, the first - row pixel data is directly input into the row buffer register (i.e., the data register of the present application) 1, the second - row pixel data is directly input into the row buffer register 2, the third - row pixel data is directly input into the row buffer register 3, and the fourth - row pixel data (i.e., the last - row pixel data) is directly input into the row buffer register 4.

[0073] After the N parallel data registers complete caching of the N - row pixel data, the subsequent data superposition process is consistent with the system including N parallel data registers described above.

[0074] Based on the same inventive concept, the present application also provides a data cache control method, which is applied to the aforementioned data cache control system, and the method includes the following steps: S1. Based on N serial FIFO caches, receive and cache the row pixel data successively output by the image sensor, and shift the data of each row of pixels into the next FIFO cache in sequence until the N serial FIFO caches cache the data of N rows of pixels in total. Wherein, N represents the total number of pixel rows, and N≥2.

[0075] S2. Simultaneously input the data of N rows of pixels that have been cached into N - 1 adders and 1 data cache module; for each adder, obtain the data in the last-level buffer of the data cache module corresponding to the pixels in the previous row of the data input to this adder, and superimpose it with the row pixel data in the same adder to obtain the superimposed data.

[0076] Among them, the pixel rows in the image sensor are sorted according to the order of photographing the same area to be measured under the same light source; the adders correspond one-to-one with the pixel rows in the image sensor except the first row; the data cache module corresponds one-to-one with the pixel rows in the image sensor except the last row; the pixel data in the first row of the image sensor is input to the first-level buffer of the corresponding data cache module.

[0077] S3. Sequentially move the data in each level of the buffer in the data cache module to the next level of the buffer.

[0078] S4. Input the superimposed data to the first-level buffer of the data cache module or use it as the data after superimposition is completed.

[0079] It should be noted that step S3 and step S4 in the above method can be processed synchronously.

[0080] For step S1, the pixel data of the first row (i.e., the pixel data of the first row) is input to the first-level buffer of the corresponding data cache module. For step S4, after the pixel data of the last row is superimposed, it is directly output as the data after superimposition is completed, and the pixel data of the remaining rows is input to the first-level data buffer of the corresponding data cache module after superimposition. Among them, each level of data buffer caches one row of pixel data, and this one row of pixel data includes the data of one row of pixels before and after superimposition.

[0081] The embodiment of the present application also provides an electronic device, as Figure 5 shown, including a processor 501, a communication interface 502, a memory 503, and a communication bus 504. Among them, the processor 501, the communication interface 502, and the memory 503 complete communication with each other through the communication bus 504, The memory 503 is used to store a computer program; The processor 501 is used to implement any of the above data cache control methods when executing the program stored on the memory 503.

[0082] The communication bus mentioned in the above-mentioned electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0083] The communication interface is used for communication between the above-mentioned electronic device and other devices.

[0084] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0085] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0086] In another embodiment provided by the present application, there is also provided a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above data cache control methods are implemented.

[0087] In another embodiment provided by the present application, there is also provided a computer program product containing instructions, which when running on a computer, causes the computer to execute the steps of any of the data cache control methods in the above embodiments.

[0088] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data cache control system, characterized in that: include: N FIFO buffers connected in series correspond to pixel rows in the image sensor one by one, and are used to receive and buffer row pixel data outputted successively by the image sensor, so as to output N rows of pixel data simultaneously; wherein the pixel rows in the image sensor are sorted according to the order in which the same area to be measured is photographed under the same light source; N represents the total number of pixel rows, and N≥2; N-1 adders, corresponding to the pixel rows except the first row in the image sensor, each adder is used to receive the data of the corresponding pixel row output by the FIFO buffer, and superimpose the data with the data of the last-level buffer area in the data buffer module corresponding to the previous pixel row, and input the superimposed data to the data buffer module corresponding to the next pixel row or as the superimposed data; N-1 data cache modules correspond one to one with pixel rows except the last row in the image sensor, and each module includes an M-level cache area for receiving the data of the first row of pixels or the superimposed data, and moving the data in each level of cache area into the next level of cache area in sequence; wherein, M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to an integer plus one, and B represents the number of light sources.

2. The system according to claim 1, characterized in that In the N serially connected FIFO buffers, each FIFO buffer buffers data of one row of pixels.

3. The system according to claim 1, characterized in that The data cache module is composed of one or more data cache devices; A data cache device is used as a first-level cache area; or, a cache space within a data cache device is divided to form a multi-level cache area.

4. The system according to claim 1, characterized in that Each level of buffer caches data for one row of pixels.

5. The system according to claim 1, characterized in that The data cache control system also includes: N parallel data registers replace the N serially connected FIFO buffers, correspond one to one with the pixel rows in the image sensor, and are used to receive and cache the row pixel data output successively by the image sensor to output the data of N rows of pixels simultaneously; wherein one data register stores the data of one row of pixels.

6. A data cache control method, characterized in that: Applied to the system according to any one of claims 1 to 5, the data cache control method comprises: Based on N serially connected FIFO buffers, receiving and buffering row pixel data outputted successively by the image sensor, and sequentially shifting the data of each row of pixels into the next FIFO buffer, until the N serially connected FIFO buffers buffer a total of N rows of pixel data; wherein N represents the total number of pixel rows, and N≥2; The data of cached N rows of pixels are simultaneously input into N-1 adders and 1 data cache module; for each adder, the data of the last-level cache area in the data cache module corresponding to the previous row of pixels of the data input into the adder is obtained, and the data is superimposed with the data in the same adder to obtain the superimposed data; wherein the pixel rows in the image sensor are sorted according to the order in which the same area to be measured is photographed under the same light source; the adders correspond one-to-one to the pixel rows in the image sensor except the first row; the data cache module corresponds one-to-one to the pixel rows in the image sensor except the last row; the data of the first row of pixels in the image sensor is input into the first-level cache area of ​​the corresponding data cache module; Move the data in each level of cache in the data cache module to the next level of cache in sequence; The superimposed data is input into the first level buffer area of ​​the data buffer module or used as the superimposed data.

7. The data cache control method according to claim 6, characterized in that: If the system is replaced by N parallel data registers instead of N serial FIFO buffers, before the cached N rows of pixel data are simultaneously input to N-1 adders and 1 data buffer module, the method further includes: Based on N parallel data registers, row pixel data outputted successively by the image sensor are received and cached until the N parallel data registers cache the data of N rows of pixels; wherein the data registers correspond to the pixel rows one by one, and one data register caches the data of one row of pixels.

8. The data cache control method according to claim 6, characterized in that: Each level of buffer caches the data of one row of pixels.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the data cache control method described in any one of claims 6 to 8 when executing a program stored in a memory.

10. A computer-readable storage medium, characterized in that: A computer program is stored in the computer-readable storage medium, and when the computer program is executed by the processor, the data cache control method described in any one of claims 6 to 8 is implemented.

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