Thin film transistor, manufacturing method thereof and display

Abstract

The invention provides a thin film transistor, a manufacturing method thereof and a display. Wherein the source and drain electrode layer of the thin film transistor is connected with the driving electrode layer through a connecting hole. In the manufacturing process of the thin film transistor, after a first insulating layer is manufactured, an organic flat layer and a common voltage layer can be manufactured on the first insulating layer, the projection of the organic flat layer on a driving electrode insulating layer is located outside a connecting hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connecting hole. Therefore, the common voltage layer covers the structure of the first insulating layer at the position of the connecting hole. Through the mode, the contact between the first insulating layer and the source and drain electrode layer at the connecting hole and external water vapor can be better isolated, the surface reduction of the source and drain electrode layer caused by entering of the water vapor is avoided, the failure of the thin film transistor can be well avoided, and the production yield of the thin film transistor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a manufacturing method thereof, and a display device. Background Art

[0002] Organic self-luminous display devices, such as organic light-emitting diode (OLED) displays, have desired characteristics such as self-luminance, wide viewing angles, fast response, small thickness, high contrast, etc. Therefore, OLED displays, as next-generation flat panel display devices, have been widely used in our display mobile phones, tablets, and even computer display panels.

[0003] Currently, the mainstream backplane technologies for OLEDs are LTPS (low temperature polycrystalline silicon), LTPO (low temperature polycrystalline silicon oxide), and Oxide (oxide) TFT (Thin Film Transistor) (Oxide TFT (Oxide Thin Film Transistor)). Among them, LTPS and LTPO are limited by problems such as cost and yield, and are mainly applied to high-resolution small-size panels, such as mobile phones and tablets. Oxide TFT has excellent performance. It not only has excellent hard parameters such as high mobility (>8 cm2 / (V·s)), low leakage current (<10-12 A), and low subthreshold swing (<0.3 V / dec), but also has characteristics such as high transmittance, low preparation process temperature, simpler manufacturing process than amorphous silicon, good uniformity, and high chemical stability. Therefore, Oxide TFT can be used for medium and large-size OLEDs. The structure of Oxide TFT is generally divided into BCE (back-channel-etched, back-channel etching type structure), ESL (etch-stop-layer, etch stop type structure), and Top Gate (top gate structure). Among them, the BCE structure has low cost, and its mobility, stability, etc. reach or exceed the performance of the ESL structure. At the same time, it can also reduce backlight occlusion and thus reduce power consumption. Therefore, it has become the mainstream TFT structure for Oxide product backplanes.

[0004] The trend of higher resolution and higher refresh rate in future products is becoming increasingly obvious, which requires better capacitance resistance delay (RC delay). Therefore, the Cu (copper) wiring process (the Cu wiring process is an important part of semiconductor manufacturing, mainly used to connect various components such as transistors on the wafer to realize the functions of the circuit) has become a necessity. In addition, in the pursuit of narrow borders, the Hole Size (the size of the connection hole) of the product is getting smaller and smaller. Under the current situation of PHT equipment (lithography equipment) and materials, the PR Taper (the angle of the photoresist) gradually increases as the Hole size becomes smaller. The larger the PR Taper, the more difficult it is to control the Taper (taper) of the dry etching on the driving electrode insulating layer at the connection hole position, that is, it leads to an increase in the difficulty of controlling the GI Taper (the taper of the driving electrode insulating layer at the connection hole position) after dry etching. Subsequently, the coverage of the source-drain electrode layer and the first insulating layer at the connection hole of the driving electrode insulating layer is not good (caused by high GI Taper and poor SIOx (oxide of silicon) coverage). The PFA Outgas (degassing phenomenon of the organic glue) and water vapor entry in the subsequent process result in the reduction of CuO on the surface of the source-drain electrode layer. The above reduction spreading to the device area can lead to the electrical failure of the transistor. Summary of the Invention

[0005] To overcome the problems existing in the related art, the present disclosure provides a thin film transistor, a manufacturing method thereof, and a display.

[0006] According to the first aspect of the embodiments of the present disclosure, a manufacturing method of a thin film transistor is provided. The thin film transistor includes a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer, and a second insulating layer arranged in sequence. The driving electrode insulating layer includes a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole. The manufacturing method includes:

[0007] After the first insulating layer is manufactured, an organic planarization layer and a common voltage layer are manufactured on the first insulating layer, and the projection of the organic planarization layer on the driving electrode insulating layer is located outside the connection hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connection hole to ensure that the common voltage layer covers the structure of the first insulating layer at the position where the connection hole is located;

[0008] After the organic planarization layer and the common voltage layer are manufactured, the second insulating layer is manufactured.

[0009] In an optional embodiment, the manufacturing method includes:

[0010] When fabricating the common voltage layer, a portion of the common voltage layer located above the connection hole is reserved, such that the common voltage layer includes a connected reinforcing portion and a recessed portion, and the distance between the edge of the common voltage layer and the edge of the connection hole is greater than or equal to a first set distance; wherein, the recessed portion is a portion located in the area of the connection hole and recessed towards the connection hole, and the reinforcing portion is a portion located outside the area of the connection hole.

[0011] In an alternative embodiment, the fabrication method includes:

[0012] During the mask design process of the common voltage layer, the first set distance is determined based on the overlay error of the common voltage layer, the overlay error of the driving electrode insulating layer, the critical dimension tolerance of the common voltage layer, and the critical dimension tolerance of the driving electrode insulating layer.

[0013] In an alternative embodiment, the fabrication method includes:

[0014] When fabricating the organic planarization layer, a portion of the organic planarization layer located directly above the connection hole is exposed, and the distance between a first edge of the organic planarization layer and a second edge of the connection hole is greater than or equal to a second set distance; wherein, the first edge is the edge of the organic planarization layer close to the connection hole, and the second edge is the edge of the connection hole close to the organic planarization layer.

[0015] In an alternative embodiment, the fabrication method includes:

[0016] During the mask design process of the organic planarization layer, the second set distance is determined based on the overlay error of the organic planarization layer, the overlay error of the driving electrode insulating layer, the critical dimension tolerance of the organic planarization layer, and the critical dimension tolerance of the driving electrode insulating layer.

[0017] According to a second aspect of the embodiments of the present disclosure, a thin film transistor is provided. The thin film transistor includes a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer, and a second insulating layer arranged in sequence. The driving electrode insulating layer includes a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole;

[0018] The thin film transistor further includes a common voltage layer and an organic planarization layer. Both the common voltage layer and the organic planarization layer are located between the first insulating layer and the second insulating layer. The projection of the organic planarization layer on the driving electrode insulating layer is located outside the connection hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connection hole to ensure that the common voltage layer covers the structure of the first insulating layer located within the connection hole.

[0019] In an optional embodiment, the source-drain electrode layer, the first insulating layer, the second insulating layer, and the common voltage layer are respectively recessed in the direction of the driving electrode layer at the position of the connection hole, wherein the common voltage layer includes a reinforcing portion and a recessed portion connected to each other, and the distance between the edge of the common voltage layer and the edge of the connection hole is greater than or equal to a first set distance;

[0020] Wherein, the recessed portion is the portion located in the area where the connection hole is located and recessed toward the connection hole, and the reinforcing portion is located in the portion outside the area where the connection hole is located.

[0021] In an optional embodiment, the distance between the first edge of the organic planarization layer and the second edge of the connection hole is greater than or equal to a second set distance; wherein, the first edge is the edge of the organic planarization layer close to the connection hole, and the second edge is the edge of the connection hole close to the organic planarization layer.

[0022] In an optional embodiment, the first edge of the organic planarization layer and the third edge of the common voltage layer are arranged at intervals;

[0023] Wherein, the first edge is the edge of the organic planarization layer close to the connection hole, and the third edge is the edge of the common voltage layer close to the organic planarization layer.

[0024] According to the third aspect of the embodiments of the present disclosure, a display is provided, the display includes pixel units and the thin-film transistor according to any one of the second aspect, and the thin-film transistor is electrically connected to the pixel units for driving the pixel units to emit light.

[0025] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects: In the present disclosure, the thin-film transistor includes a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer, and a second insulating layer arranged in sequence. The driving electrode insulating layer includes a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole. During the manufacturing process of the thin-film transistor, after the first insulating layer is manufactured, the organic planarization layer and the common voltage layer can be manufactured on the first insulating layer, and the projection of the organic planarization layer on the driving electrode insulating layer is located outside the connection hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connection hole, so as to ensure that the common voltage layer covers the structure of the first insulating layer at the position where the connection hole is located; then the second insulating layer is manufactured. By the above method, the contact between the first insulating layer and the source-drain electrode layer at the connection hole position and external water vapor can be better isolated, the water vapor is prevented from entering and causing the surface of the source-drain electrode layer to be reduced, the failure of the thin-film transistor can be well avoided, and the production yield of the thin-film transistor can be improved.

[0026] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0028] Figure 1 is a schematic structural diagram of a thin film transistor shown according to an exemplary embodiment.

[0029] Figure 2 is a schematic mask design diagram of a thin film transistor shown according to an exemplary embodiment.

[0030] Figure 3 is a comparative schematic diagram showing the reduction and non-reduction of copper oxide in the source-drain electrode layer shown according to an exemplary embodiment.

[0031] Description of Reference Numerals:

[0032] GT, driving electrode layer; GI, driving electrode insulating layer; SD, source-drain electrode layer; PAS1, first insulating layer; PAS2, second insulating layer; PFA, organic planarizing layer; C-ITO, common voltage layer; GI Hole, connection hole;

[0033] 100, first edge; 200, second edge; 300, third edge;

[0034] 10, thin film transistor; 20, pixel unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The following will describe the embodiments of the present application with reference to the drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for explaining the present application, rather than for limiting the protection scope of the present application.

[0036] It should be noted that the drawings provided in the following embodiments only schematically illustrate the basic concept of the present application. Therefore, only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, numbers, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0037] The embodiments of the present application will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for illustrating the present application, rather than limiting the protection scope of the present application.

[0038] An embodiment of the present disclosure provides a thin film transistor, a manufacturing method thereof, and a display. In this embodiment, the thin film transistor includes a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer, and a second insulating layer arranged in sequence. The driving electrode insulating layer includes a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole. During the manufacturing process of the thin film transistor, after the first insulating layer is manufactured, an organic planarization layer and a common voltage layer can be manufactured on the first insulating layer, and the projection of the organic planarization layer on the driving electrode insulating layer is located outside the connection hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connection hole, so as to ensure that the common voltage layer covers the structure of the first insulating layer at the position where the connection hole is located; then the second insulating layer is manufactured. By the above method, the contact between the first insulating layer and the source-drain electrode layer at the connection hole position and external water vapor can be better isolated, preventing water vapor from entering and causing the surface of the source-drain electrode layer to be reduced, which can well avoid the failure of the thin film transistor and improve the production yield of the thin film transistor.

[0039] Embodiment 1

[0040] Reference Figure 1 As shown, this embodiment provides a manufacturing method and a thin film transistor (TFT), which can be, for example, an oxide thin film transistor (Oxide TFT). This manufacturing method is applied to the thin film transistor. That is, this embodiment provides a manufacturing method of a thin film transistor and the thin film transistor. Among them, the thin film transistor may include a driving electrode layer GT, a driving electrode insulating layer GI, a source-drain electrode layer SD, a first insulating layer PAS1, and a second insulating layer PAS2 arranged in sequence. The driving electrode insulating layer GI includes a connection hole GI Hole, and the source-drain electrode layer SD is connected to the driving electrode layer GT through the connection hole GI Hole.

[0041] During the manufacturing process of the oxide thin film transistor, a substrate can be provided first, and then the substrate is cleaned to remove impurities on the substrate. Then, the above-mentioned driving electrode layer GT, driving electrode insulating layer GI, source-drain electrode layer SD, first insulating layer PAS1, and second insulating layer PAS2 are manufactured on the substrate. Among them,

[0042] After the first insulating layer PAS1 is fabricated, the source / drain electrode layer SD and the first insulating layer PAS1 are recessed in the direction of the driving electrode layer GT at the positions of the connection holes GIHole, that is, both the source / drain electrode layer SD and the first insulating layer PAS1 completely cover the connection holes GI Hole. Then, the organic planarization layer PFA and the common voltage layer C-ITO can be fabricated on the first insulating layer PAS1.

[0043] For example, the organic planarization layer PFA and the common voltage layer C-ITO can be fabricated by photolithography technology. The main components of the organic planarization layer PFA may include: methyl 3-methoxypropionate (MMP) with a content of 30 - 40%; 1-methoxy-2-propanol (MFG) with a content of 30 - 40%; acrylic resin with a content of 5 - 15%; diethylene glycol methyl ethyl ether (MEC) with a content of 5 - 15%; naphthoquinone diazine (NQD) ester with a content of 1 - 10%; epoxy monomer with a content of 0.1 - 3%; additives (specific types are set based on actual requirements) with a content of 0.1 - 3%; coupling agents (specific types are set based on actual requirements) with a content of 0.1 - 3%; and the content of 1,4-dioxane < 0.5%. Of course, the organic planarization layer PFA can also have other compositions, which are not limited herein. The main component of the common voltage layer C-ITO can be indium tin oxide (ITO). Indium tin oxide is a transparent conductive oxide (TCO). In thin film transistors (TFTs), as the common voltage layer C-ITO, ITO can effectively transmit the common voltage signal, and due to its transparency, it will not significantly block the optical display effect of devices such as displays. It can form good electrical contact with other transparent electrode materials (such as IGZO) to achieve stable voltage transmission and signal control.

[0044] Among them, when manufacturing the organic planarization layer PFA, the projection of the organic planarization layer PFA on the driving electrode insulating layer GI can be located outside the connection hole GI Hole. That is, it is necessary to stagger the organic planarization layer PFA from the connection hole GI Hole, that is, to set the organic planarization layer PFA in an area other than directly above the connection hole GI Hole. When manufacturing the common voltage layer C-ITO, the projection of the common voltage layer C-ITO on the driving electrode insulating layer GI can cover the connection hole GI Hole. That is, there is no need to stagger the common voltage layer C-ITO from the connection hole GI Hole. Instead, the common voltage layer C-ITO is set in the area directly above the connection hole GI Hole, and it is ensured that the common voltage layer C-ITO completely covers the connection hole GI Hole, so as to ensure that the common voltage layer C-ITO covers the structure of the first insulating layer PAS1 at the position where the connection hole GI Hole is located. After the organic planarization layer PFA and the common voltage layer C-ITO are manufactured, the manufacturing of the second insulating layer PAS2 and subsequent manufacturing processes can be carried out to obtain a finished thin film transistor.

[0045] Among them, in the thin film transistor, in addition to the above-mentioned layers, a pixel electrode layer can also be included, which can be connected to the source-drain electrode layer SD. The pixel electrode layer can serve as a source or drain electrode to transmit a driving signal to the organic light-emitting diode pixel, so that the pixel can accurately emit light or go out according to the change of the signal.

[0046] It should be noted that the source-drain electrode layer SD generally uses Cu_Ti&Cu_MoNb. Among them, Cu_Ti means that the bottom layer of the source-drain electrode layer SD is titanium (Ti) and the upper layer is copper (Cu); Cu_MoNb means that the bottom layer of the source-drain electrode layer SD is molybdenum niobium (MoNb) and the upper layer is copper (Cu). However, it should be noted that in the thin film transistor of this embodiment, the lower metal of the source-drain electrode layer SD is not limited to the above two. In addition, since the thin film transistor of this embodiment adopts a BCE structure (back-channel-etched, back-channel etching type structure), the metal oxide is not covered by PR (photoresist) during etching, resulting in a certain degree of Damage to the metal oxide by the etching solution of the source-drain electrode layer SD. Therefore, it is necessary to replenish oxygen to the metal oxide before the first insulating layer PAS1 is formed to repair the defects on the surface of the metal oxide. Therefore, the pretreatment before the formation of the first insulating layer PAS1 is carried out with N 2 O. While replenishing oxygen to the metal oxide, the copper on the surface of the source-drain electrode layer SD is also oxidized to generate CuO (copper oxide) & Cu 2 O (cuprous oxide).

[0047] However, the trend of high resolution and high refresh rate of future products is becoming more and more obvious, requiring better capacitance resistance delay (RCdelay), so copper wiring (Cu wiring process is an important link in semiconductor manufacturing, mainly used to connect various transistors and other components on the wafer to realize the function of the circuit) process becomes necessary, and the pursuit of narrow frame, the HoleSize (the size of the connection hole GI Hole) in the product is getting smaller and smaller, and in the current PHT equipment (photolithography equipment) and materials, PRTaper (angle of photoresist) gradually increases as the hole size becomes smaller, and the larger the PR Taper, the more difficult it is for dry etching to control the Taper (taper) of the driving electrode insulating layer GI at the connection hole GI Hole position, that is, the difficulty of controlling the GI Taper (taper of the driving electrode insulating layer GI at the connection hole GI Hole) after dry etching increases, and the subsequent source and drain electrode layer SD and the first insulating layer PAS1 on the driving electrode insulating layer GI The connection hole GI The hole coverage is poor, and the PFA Outgas (degassing of organic glue) and water vapor in the subsequent process enter and cause the copper oxide (such as CuO) on the surface of the source and drain electrode layer SD to be reduced. If the above reduction is extended to the device area with IGZO (Indium-Gallium-Zinc-Oxide) in the thin film transistor, it will cause the characteristics of the device to change, and then cause the electrical failure of the thin film transistor.

[0048] It should be noted that the greater the taper of the connection hole GI Hole, the weaker the coverage of the first insulating layer PAS1. As the size of the connection hole GI Hole becomes smaller and smaller, the taper of the connection hole GI Hole will become larger and larger, and the coverage of the first insulating layer PAS1 will become worse and worse, and PFA outgas and air vapor will more easily penetrate, causing the copper oxide of the source and drain electrode layer SD to be reduced and discolored. In this embodiment, adding a common electrode layer to the area where the connection hole GI Hole is located is equivalent to adding a layer of film to protect the connection hole GI Hole, and changing the boundary position of the organic flat layer PFA can well eliminate the influence of PFA outgas. With this setting, the margin (process margin) of the taper of the connection hole GI Hole can be increased, and there is no need to frequently debug the process of the photolithography process and dry etching to reduce the taper of the connection hole GI Hole as much as possible. That is, this embodiment can improve the process deviation tolerance.

[0049] In addition, in this embodiment, by making the projection of the organic planarization layer PFA on the driving electrode insulating layer located outside the connection hole GI Hole, and making the projection of the common voltage layer C-ITO on the driving electrode insulating layer GI cover the connection hole GI Hole, to ensure that the common voltage layer C-ITO covers the structure of the first insulating layer PAS1 at the position where the connection hole GI Hole is located, it is possible to better isolate the contact between the first insulating layer PAS1 and the source-drain electrode layer SD and the external water vapor at the position of the connection hole GI Hole, avoid the ingress of water vapor and cause the surface of the source-drain electrode layer SD to be reduced, and further better avoid damage to the device area in the thin film transistor, and can well avoid the failure of the thin film transistor, improve the production yield of the thin film transistor, better meet the requirements of high resolution and high refresh rate of the product, and at the same time adapt to the trend of narrow border design. It should be noted that in the actual production process, the materials, thicknesses, process parameters, etc. of each layer can be appropriately adjusted according to specific product requirements and process conditions to achieve the best performance and effects.

[0050] Embodiment 2

[0051] Reference Figure 1 And Figure 2 As shown, this embodiment provides a manufacturing method and a thin film transistor (Oxide TFT), and this manufacturing method is applied to the thin film transistor. That is, this embodiment provides a manufacturing method of a thin film transistor and a thin film transistor. This embodiment is further improved on the basis of the above Embodiment 1. In this embodiment, when manufacturing the common voltage layer C-ITO, the part of the common voltage layer C-ITO located above the connection hole GI Hole is retained, so that the common voltage layer C-ITO includes a connected reinforcing part and a recessed part, and the distance between the edge of the common voltage layer C-ITO and the edge of the connection hole GI Hole is greater than or equal to a first set distance. Among them, the recessed part is the part located in the area where the connection hole GI Hole is located and recessed toward the connection hole GI Hole, and the reinforcing part is located outside the area where the connection hole GI Hole is located.

[0052] It should be noted that in a thin-film transistor, the source-drain electrode layer SD and the first insulating layer PAS1 are recessed in the direction of the driving electrode layer GT at the position of the connection hole GI Hole. The common voltage layer C-ITO of this embodiment not only includes the recessed part in the area where the connection hole GI Hole is located, but also includes a reinforcing part outside the area where the connection hole GI Hole is located. The two are constructed as an integrally connected common voltage layer C-ITO, so as to better ensure that the common voltage layer C-ITO completely covers the connection hole GI Hole and the structures of the source-drain electrode layer and the first insulating layer PAS1 at the position of the connection hole GI Hole, so as to improve the isolation effect of the first insulating layer PAS1 and the source-drain electrode layer SD from external water vapor at the position of the connection hole GI Hole, better avoid water vapor from entering and causing the surface of the source-drain electrode layer SD to be reduced, and further better avoid damage to the device area in the thin-film transistor, and can well avoid the failure of the thin-film transistor and improve the production yield of the thin-film transistor.

[0053] Among them, in order to achieve the complete coverage of the connection hole GI Hole by the common voltage layer C-ITO, during the mask design process of the common voltage layer C-ITO, the first set distance can be determined based on the overlay error (C-ITO VL) of the common voltage layer C-ITO, the overlay error (GI VL, which is an important parameter describing the overlay accuracy between the current layer and the reference layer) of the driving electrode insulating layer GI, the critical dimension tolerance (C-ITO CD tolerance) of the common voltage layer C-ITO, and the critical dimension tolerance (GI CD tolerance) of the driving electrode insulating layer GI. In some embodiments, the first set distance can be

[0054]

[0055] Among them, CD tolerance refers to CD (critical dimension). If the pattern is a line, it refers to the width of the line. If it is a hole, it refers to the diameter of the hole. Tolerance refers to the tolerance. It is impossible for all points of the entire product to be the same size, some are large and some are small. Then CD tolerance refers to the difference from the central value. For example, if the designed size of the hole is 5 and the CD Tolerance is ±0.7, it means that the maximum value on the product is 5.7 and the minimum value is 4.3.

[0056] It should be noted that in addition to determining the first set distance in the above manner, it can also be determined by other methods, which are not limited herein.

[0057] In this embodiment, by setting the first set distance, it is possible to better ensure that there is a sufficient distance between the edge of the common voltage layer C-ITO and the edge of the connection hole GI Hole, so as to ensure that the reinforcing part has a sufficient size. Furthermore, it can be avoided that the common voltage layer C-ITO cannot completely cover the connection hole GI Hole due to manufacturing errors, and it is possible to better ensure the isolation effect of the first insulating layer PAS1 and the source-drain electrode layer SD from external moisture at the position of the connection hole GI Hole, better avoid moisture ingress and cause the surface of the source-drain electrode layer SD to be reduced, and further better avoid damage to the device area in the thin film transistor, and can well avoid the failure of the thin film transistor, improving the production yield of the thin film transistor.

[0058] Embodiment Three

[0059] Reference Figure 1 And Figure 2 As shown, this embodiment provides a manufacturing method and a thin film transistor (Oxide TFT), and this manufacturing method is applied to the thin film transistor. That is, this embodiment provides a manufacturing method of a thin film transistor and a thin film transistor. This embodiment is a further improvement based on the above Embodiment One. In this embodiment, when manufacturing the organic planarization layer PFA, the part of the organic planarization layer PFA directly above the connection hole GI Hole is exposed, and the distance between the first edge 100 of the organic planarization layer PFA and the second edge 200 of the connection hole GI Hole is greater than or equal to the second set distance; wherein, the first edge 100 is the edge of the organic planarization layer PFA close to the connection hole GI Hole, and the second edge 200 is the edge of the connection hole GI Hole close to the organic planarization layer PFA.

[0060] It should be noted that the part of the organic planarization layer PFA directly above the connection hole GI Hole will not be exposed, that is, the organic planarization layer PFA will also completely cover the area where the connection hole GI Hole is located. Therefore, due to PFA Outgas (the outgassing phenomenon of the organic glue) and moisture ingress, it is easy to cause the reduction of CuO on the surface of the source-drain electrode layer SD. After the above reduction spreads to the device area, it can cause the electrical failure of the TFT. In this embodiment, the part of the organic planarization layer PFA directly above the connection hole GI Hole is exposed, and the distance between the first edge 100 of the organic planarization layer PFA and the second edge 200 of the connection hole GI Hole is greater than or equal to the second set distance, so as to ensure that there is a sufficient distance between the organic planarization layer PFA and the area directly above the connection hole GI Hole, thereby better avoiding PFA Outgas (the outgassing phenomenon of the organic glue) and moisture from entering the source-drain electrode layer SD, and can well avoid the reduction of CuO on the surface of the source-drain electrode layer SD, thus avoiding the electrical failure of the TFT.

[0061] Among them, in order to ensure that there is a sufficient distance directly above the connection hole GI Hole and the organic planarization layer PFA, during the mask design process of the organic planarization layer PFA, the second set distance can be determined based on the overlay error of the organic planarization layer PFA (PFA VL), the overlay error of the driving electrode insulating layer GI (GI VL), the critical dimension tolerance of the organic planarization layer PFA (PFA CD tolerance), and the critical dimension tolerance of the driving electrode insulating layer GI (GI CD tolerance). In some embodiments, the first set distance can be

[0062]

[0063] It should be noted that in addition to determining the second set distance through the above method, it can also be determined through other methods, and no limitation is made thereto.

[0064] In this embodiment, by setting the second set distance, it can better ensure that there is a sufficient distance in the area directly above the organic planarization layer PFA and the connection hole GI Hole, so as to better avoid PFA Outgas (the outgassing phenomenon of the organic glue) and water vapor from entering the source-drain electrode layer SD, and can well avoid the reduction of CuO on the surface of the source-drain electrode layer SD, thereby avoiding the electrical failure of the TFT. In addition, since there is a sufficient distance in the area directly above the organic planarization layer PFA and the connection hole GI Hole, it can also better provide a sufficient area for the common voltage layer C-ITO to ensure that there is a sufficient distance between the edge of the common voltage layer C-ITO and the edge of the connection hole GI Hole, so as to ensure that the reinforcing part has a sufficient size, and further avoid the situation that the common voltage layer C-ITO cannot completely cover the connection hole GI Hole due to manufacturing errors, and can better ensure the isolation effect of the first insulating layer PAS1 and the source-drain electrode layer SD from external water vapor at the position of the connection hole GI Hole, better avoid the reduction of the surface of the source-drain electrode layer SD caused by the entry of water vapor, and further better avoid the damage of the device area in the thin film transistor, and can well avoid the failure of the thin film transistor, improving the production yield of the thin film transistor.

[0065] Embodiment 4

[0066] Reference Figure 1 and Figure 2 As shown, this embodiment provides a thin film transistor (Oxide TFT). This thin film transistor can be obtained by the manufacturing method of the above Embodiment 1. Among them, the common voltage layer C-ITO can be obtained by the manufacturing method of the above Embodiment 2, and the organic planarization layer PFA can be obtained by the manufacturing method of the above Embodiment 3.

[0067] That is to say, in this embodiment, when designing the Mask of the organic planarization layer PFA, the area of the organic planarization layer PFA directly above the via hole GI Hole is not retained, and according to the Overlay capability of the PHT device, a sufficient distance is retained between the first edge 100 of the organic planarization layer PFA and the second edge 200 of the via hole GI Hole. For example, the second set distance can be determined based on the overlay error of the organic planarization layer PFA, the overlay error of the driving electrode insulating layer GI, the critical dimension tolerance of the organic planarization layer PFA, and the critical dimension tolerance of the driving electrode insulating layer GI.

[0068] Among them, in the lithography process of the organic planarization layer PFA (including photoresist coating, exposure, and development), based on the above-mentioned second set distance, the organic planarization layer PFA above the via hole GI Hole is exposed, so that the distance between the first edge 100 of the finally formed organic planarization layer PFA and the second edge 200 of the via hole GI Hole is greater than or equal to the second set distance, thereby ensuring that there is a sufficient distance between the boundary of the organic planarization layer PFA and the via hole GI Hole, and further avoiding the boundary of the organic planarization layer PFA shifting above the via hole GI Hole due to the problem of PHT Overlay.

[0069] In this embodiment, when designing the Mask of the common voltage layer C-ITO, the area of the common voltage layer C-ITO directly above the via hole GI Hole is retained, and the first set distance can be determined based on the overlay error of the common voltage layer C-ITO, the overlay error of the driving electrode insulating layer GI, the critical dimension tolerance of the common voltage layer C-ITO, and the critical dimension tolerance of the driving electrode insulating layer GI. Among them, in the lithography process of the common voltage layer C-ITO, the part of the common voltage layer C-ITO above the via hole GI Hole is retained, and the common voltage layer C-ITO includes a connected reinforcing part and a recessed part, and the distance between the edge of the common voltage layer C-ITO and the edge of the via hole GI Hole is greater than or equal to the first set distance, so as to ensure that the final mask of the common voltage layer C-ITO completely covers the area where the via hole GI Hole is located, which can well strengthen the isolation of the source-drain electrode layer SD in the via hole GI Hole from external water vapor, avoid water vapor from entering and causing the CuO on the surface of the source-drain electrode layer SD to be reduced, and thus avoid the reduction of the device area of the transistor, thereby avoiding the electrical failure of the transistor.

[0070] In addition, in this embodiment, the first edge 100 of the organic planar layer PFA is spaced from the third edge 300 of the common voltage layer C-ITO. The first edge 100 is the edge of the organic planar layer PFA close to the connection hole GI Hole, and the third edge 300 is the edge of the common voltage layer C-ITO close to the organic planar layer PFA. By spacing the first edge 100 of the organic planar layer PFA and the third edge 300 of the common voltage layer C-ITO, PFA Outgas (degassing of organic glue) and water vapor can be better prevented from entering the source-drain electrode layer SD, and the reduction of CuO on the surface of the source-drain electrode layer SD can be well avoided, and the device area of ​​the transistor can be prevented from being reduced, thereby avoiding electrical failure of the transistor, and improving product reliability and yield.

[0071] It should be noted that the greater the taper of the connection hole GI Hole, the weaker the coverage of the first insulating layer PAS1. As the size of the connection hole GI Hole becomes smaller and smaller, the taper of the connection hole GI Hole will become larger and larger, and the coverage of the first insulating layer PAS1 will become worse and worse, and PFA outgas and air vapor will more easily penetrate, causing the copper oxide of the source and drain electrode layer SD to be reduced and discolored. In this embodiment, adding a common electrode layer to the area where the connection hole GI Hole is located is equivalent to adding a layer of film to protect the connection hole GI Hole, and changing the boundary position of the organic flat layer PFA can well eliminate the influence of PFA outgas. With this setting, the margin (process margin) of the taper of the connection hole GI Hole can be increased, and there is no need to frequently debug the process of the photolithography process and dry etching to reduce the taper of the connection hole GI Hole as much as possible. That is, this embodiment can improve the process deviation tolerance.

[0072] Embodiment 5

[0073] refer to Figure 1 and Figure 3 As shown, this embodiment provides a display, which may include a pixel unit 20 and the thin film transistor 10 in the above embodiment. The thin film transistor 10 is electrically connected to the pixel unit 20 and is used to drive the pixel unit 20 to emit light. For example, in an active matrix display, each pixel unit 20 (also referred to as a pixel point) has a corresponding thin film transistor 10, and the driving circuit composed of these thin film transistors 10 can quickly and accurately adjust the light emitting brightness of each pixel unit 20 according to the requirements of displaying images, thereby achieving high-quality image display.

[0074] In this embodiment, through the above-mentioned thin film transistor 10, it is possible to better avoid PFA Outgas (the degassing phenomenon of organic glue) and water vapor from entering the source-drain electrode layer SD, and it is possible to well avoid the reduction of CuO on the surface of the source-drain electrode layer SD. That is, it is possible to avoid the reduction of the device area of the transistor, thereby avoiding the electrical failure of the transistor, improving the product reliability and yield, and better meeting the requirements of high resolution and high refresh rate of the organic light-emitting diode display, while adapting to the trend of narrow bezel design. It should be noted that in the actual production process, the materials, thicknesses, process parameters, etc. of each layer can be appropriately adjusted according to specific product requirements and process conditions to achieve the best performance and effects.

[0075] Those skilled in the art should also be able to further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0076] It should be noted that the phrases such as "one embodiment", "embodiment", "exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not necessarily every embodiment includes such specific features, structures, or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. Moreover, when combining specific features, structures, or characteristics with an embodiment, it is within the knowledge scope of those skilled in the art to implement such features, structures, or characteristics in combination with other embodiments, whether explicitly or implicitly described.

[0077] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without more limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0078] The above embodiments are only preferred embodiments given to fully illustrate the present application, and the protection scope of the present application is not limited thereto. Any equivalent substitution or transformation made by those skilled in the art on the basis of the present application shall fall within the protection scope of the present application.

Claims

1. A method for manufacturing a thin film transistor, wherein the thin film transistor comprises a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer and a second insulating layer arranged in sequence, wherein the driving electrode insulating layer comprises a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole, wherein: The production method comprises: After the first insulating layer is manufactured, an organic flat layer and a common voltage layer are manufactured on the first insulating layer, and a projection of the organic flat layer on the driving electrode insulating layer is located outside the connecting hole, and a projection of the common voltage layer on the driving electrode insulating layer covers the connecting hole, so as to ensure that the common voltage layer covers the structure where the first insulating layer is located at the location of the connecting hole; After the organic planar layer and the common voltage layer are manufactured, the second insulating layer is manufactured.

2. The method for manufacturing a thin film transistor according to claim 1, characterized in that: The production method comprises: When manufacturing the common voltage layer, retain the portion of the common voltage layer located above the connection hole, so that the common voltage layer includes a connected reinforcement portion and a recessed portion, and the distance between the edge of the common voltage layer and the edge of the connection hole is greater than or equal to a first set distance; wherein the recessed portion is a portion located in the area where the connection hole is located and recessed toward the connection hole, and the reinforcement portion is a portion located outside the area where the connection hole is located.

3. The method for manufacturing a thin film transistor according to claim 2, characterized in that: The production method comprises: During the mask design process of the common voltage layer, the first set distance is determined based on the overlay error of the common voltage layer, the overlay error of the drive electrode insulating layer, the critical dimension tolerance of the common voltage layer and the critical dimension tolerance of the drive electrode insulating layer.

4. The method for manufacturing a thin film transistor according to any one of claims 1 to 3, characterized in that: The production method comprises: When manufacturing the organic planar layer, the portion of the organic planar layer directly above the connecting hole is exposed, and the distance between the first edge of the organic planar layer and the second edge of the connecting hole is greater than or equal to a second set distance; wherein the first edge is the edge of the organic planar layer close to the connecting hole, and the second edge is the edge of the connecting hole close to the organic planar layer.

5. The method for manufacturing a thin film transistor according to claim 4, characterized in that: The production method comprises: In the mask design process of the organic planar layer, the second set distance is determined based on the overlay error of the organic planar layer, the overlay error of the drive electrode insulating layer, the critical dimension tolerance of the organic planar layer and the critical dimension tolerance of the drive electrode insulating layer.

6. A thin film transistor, comprising a driving electrode layer, a driving electrode insulating layer, a source-drain electrode layer, a first insulating layer and a second insulating layer arranged in sequence, wherein the driving electrode insulating layer comprises a connection hole, and the source-drain electrode layer is connected to the driving electrode layer through the connection hole, characterized in that: The thin film transistor also includes a common voltage layer and an organic planar layer, both of which are located between the first insulating layer and the second insulating layer, the projection of the organic planar layer on the driving electrode insulating layer is located outside the connecting hole, and the projection of the common voltage layer on the driving electrode insulating layer covers the connecting hole to ensure that the common voltage layer covers the structure of the first insulating layer located in the connecting hole.

7. The thin film transistor according to claim 6, characterized in that: The source-drain electrode layer, the first insulating layer, the second insulating layer, and the common voltage layer are respectively recessed at the position of the connection hole toward the direction of the driving electrode layer, wherein the common voltage layer includes a connected reinforcement portion and a recessed portion, and the distance between the edge of the common voltage layer and the edge of the connection hole is greater than or equal to a first set distance; The recessed portion is located in the area where the connection hole is located and is recessed toward the connection hole, and the reinforcement portion is located outside the area where the connection hole is located.

8. The thin film transistor according to claim 6 or 7, characterized in that: The distance between the first edge of the organic planar layer and the second edge of the connection hole is greater than or equal to a second set distance; wherein the first edge is the edge of the organic planar layer close to the connection hole, and the second edge is the edge of the connection hole close to the organic planar layer.

9. The thin film transistor according to claim 8, characterized in that: The first edge of the organic planar layer is spaced apart from the third edge of the common voltage layer; The first edge is an edge of the organic planar layer close to the connection hole, and the third edge is an edge of the common voltage layer close to the organic planar layer.

10. A display, characterized in that: The display comprises a pixel unit and a thin film transistor as claimed in any one of claims 6 to 9, wherein the thin film transistor is electrically connected to the pixel unit and is used to drive the pixel unit to emit light.

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