Display device, method for manufacturing display device, and head mounted display

Abstract

The invention provides a display device, a method for manufacturing the display device, and a head-mounted display. The display device includes: a substrate; a plurality of conductive layers sequentially stacked on the substrate; a reflective electrode layer on the plurality of conductive layers; a pad conductive layer on the plurality of conductive layers; an insulating layer covering at least a portion of the pad conductive layer and the reflective electrode layer; a plurality of light emitting elements on the insulating layer, each of the plurality of light emitting elements including a first electrode, a light emitting stack, and a second electrode; the first packaging inorganic layer is located on the second electrode; the second packaging inorganic layer is located on the first packaging inorganic layer; and an inorganic layer on at least a portion of a sidewall of the insulating layer in the opening exposing the pad conductive layer.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device, a method of manufacturing a display device, and a head-mounted display including the display device. Background Art

[0002] A head-mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet to form a focused image at a short distance in front of the user's eyes. The head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0003] The head-mounted display magnifies an image displayed on a small display device by using a plurality of lenses and displays the magnified image. Therefore, the display device applied to the head-mounted display should provide a high-resolution image, for example, an image having a resolution of 3000 pixels per inch (PPI) or higher. To this end, an organic light-emitting diode on silicon (OLED) (OLEDoS) as a small high-resolution organic light-emitting display device can be used as the display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is disposed on a semiconductor wafer substrate including a complementary metal oxide semiconductor (CMOS). Summary of the Invention

[0004] Aspects and features of embodiments of the present disclosure provide a display device capable of providing a high-resolution image.

[0005] Aspects and features of embodiments of the present disclosure also provide a method of manufacturing a display device capable of providing a high-resolution image.

[0006] Aspects and features of embodiments of the present disclosure also provide a head-mounted display capable of providing a high-resolution image.

[0007] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, there is provided a display device including: a substrate; a plurality of conductive layers sequentially stacked on the substrate; a reflective electrode layer on the plurality of conductive layers; a pad conductive layer on the plurality of conductive layers; an insulating layer covering at least a part of the pad conductive layer and the reflective electrode layer; a plurality of light-emitting elements on the insulating layer, each of the plurality of light-emitting elements including a first electrode, a light-emitting stack, and a second electrode; a first encapsulation inorganic layer on the second electrode; a second encapsulation inorganic layer on the first encapsulation inorganic layer; and an inorganic layer on at least a part of a sidewall of the insulating layer in an opening exposing the pad conductive layer.

[0009] The inorganic layer may include the same material as the second encapsulation inorganic layer.

[0010] The second encapsulation inorganic layer and the inorganic layer may include at least one of titanium oxide (TiO x ), and aluminum oxide (AlO x ).

[0011] The inorganic layer may include a material different from that of the first encapsulation inorganic layer.

[0012] The first encapsulation inorganic layer may include at least one of silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ). The inorganic layer may include at least one of titanium oxide (TiO x ), and aluminum oxide (AlO x ).

[0013] The inorganic layer may be in contact with the pad conductive layer.

[0014] The inorganic layer may be separated from the pad conductive layer.

[0015] The inorganic layer may include a first sub-inorganic layer and a second sub-inorganic layer separated from each other on the sidewall of the insulating layer.

[0016] The size of the first sub-inorganic layer and the size of the second sub-inorganic layer may be different from each other.

[0017] At least one of the first sub-inorganic layer and the second sub-inorganic layer may be in contact with the pad conductive layer.

[0018] The thickness of the inorganic layer may be less than the thickness of the first encapsulation inorganic layer.

[0019] The thickness of the pad conductive layer may be greater than the thickness of the reflective electrode layer.

[0020] The pad conductive layer may be divided into a first sub-pad and a second sub-pad by the insulating layer. The area of the first sub-pad may be different from the area of the second sub-pad.

[0021] The pad conductive layer of the first sub-pad and the pad conductive layer of the second sub-pad may be physically connected to each other.

[0022] The pad conductive layer of the first sub-pad and the pad conductive layer of the second sub-pad may be separated from each other.

[0023] The pad conductive layer of the first sub-pad and the pad conductive layer of the second sub-pad may be electrically connected to at least one of a plurality of conductive layers.

[0024] The pad conductive layer may be divided into a first sub-pad, a second sub-pad, and a third sub-pad by the insulating layer.

[0025] The area of the first sub-pad may be different from the area of the second sub-pad, and the area of the first sub-pad may be different from the area of the third sub-pad.

[0026] The area of the second sub-pad may be the same as the area of the third sub-pad.

[0027] The pad conductive layer of the first sub-pad, the pad conductive layer of the second sub-pad, and the pad conductive layer of the third sub-pad may be separated from each other.

[0028] The pad conductive layer of the first sub-pad, the pad conductive layer of the second sub-pad, and the pad conductive layer of the third sub-pad may be electrically connected to at least one of a plurality of conductive layers.

[0029] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided. The method includes: sequentially forming a plurality of conductive layers on a substrate; forming a reflective electrode layer on the plurality of conductive layers; forming a pad conductive layer on the plurality of conductive layers; forming an insulating layer covering at least a portion of the pad conductive layer and the reflective electrode layer; forming a plurality of light-emitting elements on the insulating layer, each of the plurality of light-emitting elements including a first electrode, a light-emitting stack located on the first electrode, and a second electrode located on the light-emitting stack; forming a first encapsulation inorganic layer on the second electrode; forming a second encapsulation inorganic layer on the first encapsulation inorganic layer, the pad conductive layer being exposed by an opening of the insulating layer, and the insulating layer covering at least a portion of the pad conductive layer; forming a plurality of color filters on the second encapsulation inorganic layer; forming a first lens layer on the second encapsulation inorganic layer and the plurality of color filters located on the pad conductive layer, and forming a second lens pattern layer including a plurality of convex patterns on the first lens layer; etching the first lens layer and the second lens pattern layer to form a plurality of lenses; and etching the second encapsulation inorganic layer and the first lens layer located on the pad conductive layer.

[0030] Etching the second encapsulation inorganic layer and the first lens layer located on the pad conductive layer may include: forming a mask pattern on the plurality of lenses; and dry-etching the second encapsulation inorganic layer and the first lens layer that are not covered by the mask pattern using an etching gas.

[0031] The etching gas may be carbon tetrafluoride (CF 4 ), the etching gas may be carbon tetrafluoride (CF 4 ) and oxygen (O 2 ), and / or the etching gas may be carbon tetrafluoride (CF 4 ) and argon (Ar).

[0032] The thickness of the first lens layer may be greater than the thickness of the second lens pattern layer.

[0033] When etching the first lens layer and the second lens pattern layer to form a plurality of lenses, the thickness of the etched first lens layer by etching may be greater than the thickness of the second lens pattern layer.

[0034] According to one or more embodiments of the present disclosure, there is provided a head-mounted display, the head-mounted display including: at least one display device; a housing member configured to accommodate at least one display device; and an optical member configured to magnify a display image of at least one display device or change an optical path. The at least one display device includes: a substrate; a plurality of conductive layers sequentially stacked on the substrate; a reflective electrode layer located on the plurality of conductive layers; a pad conductive layer located on the plurality of conductive layers; an insulating layer covering at least a part of the pad conductive layer and the reflective electrode layer; a plurality of light-emitting elements located on the insulating layer, each of the plurality of light-emitting elements including a first electrode, a light-emitting stack, and a second electrode; a first encapsulation inorganic layer located on the second electrode; a second encapsulation inorganic layer located on the first encapsulation inorganic layer; and an inorganic layer located on at least a part of a sidewall of the insulating layer in an opening exposing the pad conductive layer.

[0035] According to the above and other embodiments of the present disclosure, the pad conductive layer may be formed to have a large thickness of about or greater, and thus, even when pressure is applied to the pad conductive layer by a jig or a probe during an inspection process, the pad conductive layer can be prevented from being damaged.

[0036] Furthermore, according to the above and other embodiments of the present disclosure, a second sub-pad used during an inspection process and a first sub-pad connected to a circuit board are physically separated, and thus, even if the pad conductive layer of the second sub-pad is damaged, the pad conductive layer of the first sub-pad can be stably connected to the circuit board.

[0037] Furthermore, according to the above and other embodiments of the present disclosure, the encapsulation inorganic layer is formed very thin by an atomic layer deposition method and removed by an etching gas moving in a vertical direction in a dry etching process, such that it takes a long time to remove the encapsulation inorganic layer on the sidewall of the insulating layer, but by removing the encapsulation inorganic layer on the pad conductive layer and allowing the encapsulation inorganic layer on the sidewall of the insulating layer to remain without being removed, the time required for the dry etching process can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the drawings, in which:

[0039] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments;

[0040] Figure 2 is a block diagram showing a display device according to one or more embodiments;

[0041] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments;

[0042] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments;

[0043] Figure 5 is a diagram showing Figure 4 a layout diagram of an example of the display area of;

[0044] Figure 6 is a diagram showing Figure 4 a layout diagram of an example of the display area of;

[0045] Figure 7 is a diagram showing a cross-sectional view of an example of a display panel taken along the line I1-I1' of Figure 5 ;

[0046] Figure 8 is a diagram showing Figure 4 a layout diagram of an example of a first pad of a first pad portion of;

[0047] Figure 9 is a diagram showing a cross-sectional view of an example of a display panel taken along the line I2-I2' of Figure 8 ;

[0048] Figure 10 is a diagram showing a cross-sectional view of an example of a display panel taken along the line I2-I2' of Figure 8 ;

[0049] Figure 11 is a diagram showing Figure 4 a layout diagram of an example of a first pad of a first pad portion of;

[0050] Figure 12 is a diagram showing a cross-sectional view of an example of a display panel taken along the line I3-I3' of Figure 11 ;

[0051] Figure 13 is a diagram showing Figure 4 a layout diagram of an example of a first pad of a first pad portion of;

[0052] Figure 14 is a diagram showing a cross-sectional view of an example of a display panel taken along the line I4-I4' of Figure 13 ;

[0053] Figure 15 is a flowchart showing a method for manufacturing a display device according to one or more embodiments;

[0054] Figures 16 to 27is a cross-sectional view showing a method for manufacturing a display device according to one or more embodiments;

[0055] Figure 28 is a perspective view showing a head-mounted display according to one or more embodiments;

[0056] Figure 29 is showing Figure 28 an exploded perspective view of an example of the head-mounted display; and

[0057] Figure 30 is a perspective view showing a head-mounted display according to one or more embodiments. Detailed Description

[0058] Aspects and features of embodiments of the present disclosure and methods of implementing them can be more easily understood through a detailed description with reference to the embodiments and the accompanying drawings. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0059] Unless otherwise stated, the same reference numerals, labels, or combinations thereof always denote the same elements in the drawings and the present disclosure, and thus, their descriptions will not be repeated. In addition, parts that are not relevant to the description of one or more embodiments may not be shown to make the description clear.

[0060] In the drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0061] Various embodiments are described herein with reference to cross-sectional views, which are schematic views of the embodiments and / or intermediate structures. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. In addition, for the purposes of describing embodiments according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Accordingly, the embodiments disclosed herein should not be construed as limited to the specifically shown shapes of the regions, but will include deviations in shape caused by, for example, manufacturing.

[0062] For example, an implantation region shown as rectangular may have rounded or curved features at its edges and / or a gradient in implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are in fact schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to be limiting. Additionally, as will be recognized by those skilled in the art, the described embodiments may be modified in various different ways, all of which do not depart from the scope of the present disclosure.

[0063] In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, it is evident that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0064] Spatial relative terms such as "under", "below", "beneath", "underneath", "above", and "on" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under", "below", or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this means that the first part is disposed at the upper or lower side of the second part and is not limited to the upper side of the second part based on the direction of gravity.

[0065] Furthermore, in the present disclosure, the phrase "in a plane" or "in a plan view" means observing the target part from the top, and the phrase "in a cross-section" means observing the cross-section formed by vertically cutting the target part from the side.

[0066] It should be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "coupled to" another element or layer, the element, layer, region or component can be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or can be indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be intervening elements, layers, regions or components. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component can be directly electrically connected to or electrically coupled to the other layer, region or component, or there can be intervening layers, regions or components. However, "directly connected / coupled" means that one component is directly connected or coupled to another component without an intervening component. At the same time, other expressions describing the relationship between components, such as "between", "immediately between", "adjacent to" and "directly adjacent to", can be similarly interpreted. Additionally, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0067] For the purposes of the present disclosure, when expressions such as "at least one of", "one of" and "selected from" are before or after a list of elements, they modify the entire list of elements and not the individual elements of the list. For example, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted to mean only X, only Y, only Z, any combination of two or more of X, Y and Z (such as by way of example XYZ, XY, XZ and YZ) or any variation thereof. Similarly, an expression such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" means any combination and all combinations of one or more of the associated listed items. For example, an expression such as "A and / or B" can include A, B, or A and B. Further, when describing embodiments of the present disclosure, the use of "may" means "one or more embodiments of the present disclosure".

[0068] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the scope of the present disclosure, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section.

[0069] In an example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0070] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. It will also be understood that when the terms "comprises / comprising", "have / having", "include / including", and their variants are used in the present disclosure, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] As used herein, the terms "substantially", "about", "approximately", and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation of the particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0072] When one or more embodiments can be implemented differently, the specific process order may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described.

[0073] In addition, any numerical range disclosed and / or recited herein is intended to include all sub-ranges subsumed within the recited range of the same numerical precision. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the recited minimum value of 1.0 and the recited maximum value of 10.0), e.g., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, by way of example, 2.4 to 7.6. Any maximum numerical limit recited herein is intended to include all lower numerical limits subsumed therein, and any minimum numerical limit recited in this disclosure is intended to include all higher numerical limits subsumed therein. Accordingly, the applicant reserves the right to amend this disclosure, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein.

[0074] The electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Additionally, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0075] Furthermore, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components used to perform the various functions described herein. The computer program instructions are stored in a memory, which may be implemented in a computing device using a standard memory device such as, by way of example, random access memory (RAM). The computer program instructions may also be stored in a non-transitory computer-readable medium such as, by way of example, a compact disc read-only memory (CD-ROM) or a flash drive. Additionally, it will be recognized by those skilled in the art that, without departing from the scope of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed over one or more other computing devices.

[0076] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0077] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 is a block diagram showing a display device according to one or more embodiments.

[0078] Referring to Figure 1 and Figure 2 According to one or more embodiments, a display device 10 is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments may be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to one or more embodiments may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) terminal. Optionally, the display device 10 according to one or more embodiments may be applied to a smart watch, a watch phone, and / or a head-mounted display (HMD) for realizing virtual reality and augmented reality, etc.

[0079] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0080] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1. In the display panel 100, the angles where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be right angles or rounded corners with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a shape similar to another polygon shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may coincide with the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0081] As Figure 2 shown, the display panel 100 includes a display area DAA configured to display an image and a non-display area NDA configured not to display an image. The non-display area NDA may be disposed around the display area DAA along the edge or periphery of the display area DAA.

[0082] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0083] A plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged along the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being arranged along the first direction DR1.

[0084] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0085] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include a plurality of transistors T1 to T6 as shown in Figure 3 or a pixel transistor PTR as shown in Figure 7 , and these transistors may be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see Figure 7 ). For example, the plurality of data transistors of the data driver 700 may be formed of complementary metal oxide semiconductor (CMOS).

[0086] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to any one of the plurality of write scan lines GWL among the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL among the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL among the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1 among the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2 among the plurality of second emission control lines EL2, and any one of the plurality of data lines DL among the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0087] The non-display area NDA includes a scan driver 610, an emission driver 620, and a data driver 700.

[0088] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed in a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of scan transistors and the plurality of light emitting transistors may be formed of CMOS. Although in Figure 2As shown, the scan driver 610 is provided on the left side of the display area DAA and the emission driver 620 is provided on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be provided on at least one of the left and right sides of the display area DAA.

[0089] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS, and sequentially output them to the bias scan lines EBL.

[0090] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals according to the emission timing control signal ECS, and sequentially output them to the first emission control lines EL1. The second emission control driver 622 may generate second emission control signals according to the emission timing control signal ECS, and sequentially output them to the second emission control lines EL2.

[0091] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of data transistors may be formed of CMOS.

[0092] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data lines DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signals of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0093] The heat dissipation layer 200 may overlap with the display panel 100 in a third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate the heat generated from the display panel 100. The heat dissipation layer 200 may include a conductive layer having high thermal conductivity such as graphite, silver (Ag), copper (Cu), and / or aluminum (Al).

[0094] The circuit board 300 may be electrically connected to the first pad portion PDA1 (see Figure 4 ) of the display panel 100 through a conductive bonding member such as an anisotropic conductive film to a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board (FPCB) and / or a flexible thin film having a flexible material. Although the circuit board 300 is shown as being unfolded in Figure 1 , the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The said one end of the circuit board 300 may be the opposite end of the other end of the circuit board 300 which is connected to the plurality of first pads PD1 (see Figure 4 ) of the first pad portion PDA1 (see Figure 4 ) of the display panel 100 through a conductive bonding member.

[0095] The timing control circuit 400 may receive digital video data DATA and timing signals input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0096] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 may generate and / or supply a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described in conjunction with Figure 3 .

[0097] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0098] Optionally, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed in a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the plurality of timing transistors and the plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be disposed between the data driver 700 and the first pad portion PDA1 (see Figure 4 ).

[0099] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments.

[0100] Referring to Figure 3 , the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to the first driving voltage line VSL to which the first driving voltage VSS corresponding to the low potential voltage (see Figure 2 ) is applied, the second driving voltage line VDL to which the second driving voltage VDD corresponding to the high potential voltage (see Figure 2 ) is applied, and the third driving voltage line VIL to which the third driving voltage VINT corresponding to the initialization voltage (see Figure 2 ) is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0101] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0102] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0103] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (referred to herein as "drive current Ids") flowing between the source electrode and the drain electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0104] The second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL may be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0105] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 may be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0106] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0107] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line EBL to connect the third node N3 to the third drive voltage line VIL. Accordingly, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0108] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0109] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0110] A second capacitor CP2 is formed between a gate electrode (i.e., a first node N1) of a first transistor T1 and a second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0111] The first node N1 is a node between the gate electrode of the first transistor T1, the drain electrode of a third transistor T3, another electrode of a first capacitor CP1, and the one electrode of the second capacitor CP2. The second node N2 is a node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of a fourth transistor T4. The third node N3 is a node between the drain electrode of the fourth transistor T4, the source electrode of a fifth transistor T5, and a first electrode of a light-emitting element LE.

[0112] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0113] Although it is shown in Figure 3 that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to the number shown in Figure 3 .

[0114] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 may be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in conjunction with Figure 3 . Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in the present disclosure.

[0115] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments.

[0116] Refer to Figure 4, the display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0117] The scan driver 610 may be disposed on a first side of the display area DAA, and the emission driver 620 may be disposed on a second side of the display area DAA. For example, the scan driver 610 may be disposed on one side of the display area DAA in a first direction DR1, and the emission driver 620 may be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be disposed on the left side of the display area DAA, and the emission driver 620 may be disposed on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be disposed on at least one of the first side and the second side of the display area DAA.

[0118] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 (see Figure 1 ) through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in a second direction DR2.

[0119] The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0120] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 operates normally. The plurality of second pads PD2 may be connected to a jig or a probe during an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board (PCB) made of a rigid material and / or a flexible printed circuit board (FPCB) made of a flexible material.

[0121] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 may be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be disposed on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 may be disposed on the lower side of the display area DAA.

[0122] The second distribution circuit 720 distributes the signals applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 may be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 may be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be disposed on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 may be disposed on the upper side of the display area DAA.

[0123] Figure 5 is a layout diagram showing an example of Figure 4 the display area. Figure 6 is a layout diagram showing an example of Figure 4 the display area.

[0124] Referring to Figure 5 and Figure 6 , each of the plurality of pixels PX includes a first emission area EA1 that is an emission area of the first sub-pixel SP1, a second emission area EA2 that is an emission area of the second sub-pixel SP2, and a third emission area EA3 that is an emission area of the third sub-pixel SP3.

[0125] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape, a circular shape, an oval shape, an atypical planar shape, and / or any other suitable shape.

[0126] The maximum length of the first emission area EA1 in the first direction DR1 may be less than the maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the third emission area EA3 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0127] The maximum length of the first emission region EA1 in the second direction DR2 can be greater than the maximum length of the second emission region EA2 in the second direction DR2 and the maximum length of the third emission region EA3 in the second direction DR2. The maximum length of the second emission region EA2 in the second direction DR2 can be less than the maximum length of the third emission region EA3 in the second direction DR2.

[0128] As Figure 5 and Figure 6 shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have a hexagonal planar shape with six straight lines, but the present disclosure is not limited thereto. In other embodiments, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have other polygonal shapes, circular shapes, elliptical shapes, non - typical planar shapes, and / or any other suitable shapes other than the hexagonal planar shape.

[0129] As Figure 5 shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the second direction DR2. The area of the first emission region EA1, the area of the second emission region EA2, and the area of the third emission region EA3 can be different.

[0130] Optionally, as Figure 6 shown, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to the direction inclined 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be the direction perpendicular to the first diagonal direction DD1.

[0131] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. In this document, the light of the first color can be light in the blue wavelength band, the light of the second color can be light in the green wavelength band, and the light of the third color can be light in the red wavelength band. For example, the blue wavelength band can be a wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band can be a wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band can be a wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0132] In Figure 5 and Figure 6 it is shown that each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission regions.

[0133] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 5 and Figure 6 the layout shown therein. For example, the emission regions of the plurality of pixels PX may be arranged in a bar structure in which the emission regions are arranged along a first direction DR1, a structure in which the emission regions are arranged in a diamond shape, and / or a hexagonal structure in which emission regions having a hexagonal planar shape as shown in Figure 6 are arranged side by side. Such an arrangement structure may be referred to as an RGBG matrix structure (e.g., a matrix structure or an RGBG structure (e.g., a structure)). is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea.

[0134] Figure 7 is a cross-sectional view showing an example of a display panel taken along the line I1-I1' of Figure 5 .

[0135] Referring to Figure 7 , the display panel 100 includes a semiconductor base plate SBP, a light-emitting element base plate EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0136] The semiconductor base plate SBP includes a semiconductor substrate SSUB, a plurality of pixel transistors PTR on the semiconductor substrate SSUB, a plurality of semiconductor insulating layers SINS1 to SINS3 covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR respectively. The plurality of pixel transistors PTR may be the first transistor T1 to the sixth transistor T6 described with reference to Figure 3 Description.

[0137] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0138] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH provided between the source region SA and the drain region DA.

[0139] The semiconductor base plate SBP may further include a bottom insulating layer BINS and a side insulating layer SINS. The bottom insulating layer BINS may be provided between the gate electrode GE and the well region WA. The side insulating layer SINS may be provided on the side surface of the gate electrode GE. The side insulating layer SINS may be provided on the bottom insulating layer BINS.

[0140] Each of the source region SA and the drain region DA may be a region doped with a first type of impurity. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0141] Each of the multiple well regions WA further includes a first lightly doped drain region LDD1 disposed between the channel region CH and the source region SA and a second lightly doped drain region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating layer BINS, the first lightly doped drain region LDD1 can be a region having a lower impurity concentration than the source region SA. Due to the lower insulating layer BINS, the second lightly doped drain region LDD2 can be a region having a lower impurity concentration than the drain region DA. Due to the presence of the first lightly doped drain region LDD1 and the second lightly doped drain region LDD2, the distance between the source region SA and the drain region DA can be increased. Accordingly, the length of the channel region CH of each of the multiple pixel transistors PTR can be increased, such that breakdown and hot carrier phenomena that may be caused by a short channel can be prevented.

[0142] The first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB and the pixel transistor PTR. The first semiconductor insulating layer SINS1 can be formed of a silicon carbonitride (SiCN) and / or silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0143] The second semiconductor insulating layer SINS2 can be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0144] Multiple contact terminals CTE can be disposed on the second semiconductor insulating layer SINS2. Each of the multiple contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of a corresponding one of the multiple pixel transistors PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The multiple contact terminals CTE can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them.

[0145] The third semiconductor insulating layer SINS3 can be disposed on the second semiconductor insulating layer SINS2 on side surfaces of each of the multiple contact terminals CTE. The top surface of each of the multiple contact terminals CTE can be exposed and not covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0146] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate including a polymer such as polyimide. In this case, thin film transistors (e.g., pixel transistors PTR) can be provided on the glass substrate and / or the polymer resin substrate. The glass substrate can be a non-bendable rigid substrate, and the polymer resin substrate can be a flexible substrate capable of being bent or curved.

[0147] The light-emitting element bottom plate EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating layers INS1 to INS9 provided between the first conductive layer ML1 to the eighth conductive layer ML8.

[0148] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor bottom plate SBP, thereby implementing Figure 3 the circuit of the first sub-pixel SP1 shown in. For example, the first transistor T1 to the sixth transistor T6 are only formed in the semiconductor bottom plate SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 (see Figure 3 ) is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0149] The first insulating layer INS1 can be provided on the semiconductor bottom plate SBP. Each of the plurality of first vias VA1 can penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor bottom plate SBP. Each of the plurality of first conductive layers ML1 can be provided on the first insulating layer INS1 and can be connected to the first via VA1.

[0150] The second insulating layer INS2 can be provided on the first insulating layer INS1 and the first conductive layer ML1. Each of the plurality of second vias VA2 can penetrate the second insulating layer INS2 and can be connected to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 can be provided on the second insulating layer INS2 and can be connected to the second via VA2.

[0151] The third insulating layer INS3 can be provided on the second insulating layer INS2 and the second conductive layer ML2. Each of the plurality of third vias VA3 can penetrate the third insulating layer INS3 and can be connected to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 can be provided on the third insulating layer INS3 and can be connected to the third via VA3.

[0152] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the plurality of fourth vias VA4 can penetrate the fourth insulating layer INS4 and can be connected to the exposed third conductive layer ML3. Each of the plurality of fourth vias VA4 can be disposed on the fourth insulating layer INS4 and can be connected to the fourth via VA4.

[0153] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the plurality of fifth vias VA5 can penetrate the fifth insulating layer INS5 and can be connected to the exposed fourth conductive layer ML4. Each of the plurality of fifth vias VA5 can be disposed on the fifth insulating layer INS5 and can be connected to the fifth via VA5.

[0154] The sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the plurality of sixth vias VA6 can penetrate the sixth insulating layer INS6 and can be connected to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 can be disposed on the sixth insulating layer INS6 and can be connected to the sixth via VA6.

[0155] The seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the plurality of seventh vias VA7 can penetrate the seventh insulating layer INS7 and can be connected to the exposed sixth conductive layer ML6. Each of the plurality of seventh vias VA7 can be disposed on the seventh insulating layer INS7 and can be connected to the seventh via VA7.

[0156] The eighth insulating layer INS8 can be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the plurality of eighth vias VA8 can penetrate the eighth insulating layer INS8 and can be connected to the exposed seventh conductive layer ML7. Each of the plurality of eighth vias VA8 can be disposed on the eighth insulating layer INS8 and can be connected to the eighth via VA8.

[0157] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The first via VA1 to the eighth via VA8 can be made of substantially the same material. The first insulating layer INS1 to the eighth insulating layer INS8 can be made of silicon oxide (SiO x)A base inorganic layer is formed, but the present disclosure is not limited thereto.

[0158] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be about The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be about And the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be about

[0159] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be about The thickness of each of the seventh via VA7 and the eighth via VA8 can be about

[0160] The ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0161] Each of the plurality of ninth vias VA9 can penetrate the ninth insulating layer INS9 and can be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The thickness of the ninth via VA9 can be about

[0162] The display element layer EML can be disposed on the light-emitting element base plate EBP. The display element layer EML can include light-emitting elements LE each including a first electrode AND, a light-emitting stack ES, and a second electrode CAT, a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth via VA10, a pixel defining layer PDL, and a plurality of trenches TRC.

[0163] The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL can include at least one of reflective electrodes RL1, RL2, RL3, and RL4. For example, as Figure 7 shown, the reflective electrode layer RL can include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0164] Each of the plurality of first reflective electrodes RL1 can be disposed on the ninth insulating layer INS9 and can be connected to the ninth via VA9. The first reflective electrode RL1 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0165] The plurality of second reflective electrodes RL2 can be respectively disposed on the plurality of first reflective electrodes RL1. The second reflective electrode RL2 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the second reflective electrode RL2 can include aluminum (Al).

[0166] The plurality of third reflective electrodes RL3 can be respectively disposed on the plurality of second reflective electrodes RL2. The third reflective electrode RL3 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the third reflective electrode RL3 can include titanium nitride (TiN).

[0167] A plurality of fourth reflective electrodes RL4 can be respectively disposed on a plurality of third reflective electrodes RL3. The fourth reflective electrode RL4 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the fourth reflective electrode RL4 can include titanium (Ti).

[0168] In one or more embodiments, since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be about and the thickness of the second reflective electrode RL2 can be In one or more other embodiments, as Figure 7 shown, since the fourth reflective electrode RL4 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the second reflective electrode RL2.

[0169] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 can be disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction. In one or more embodiments, the tenth insulating layer INS10 can be disposed on the reflective electrode layer RL in the third sub-pixel SP3. The tenth insulating layer INS10 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto.

[0170] The eleventh insulating layer INS11 can be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be optical auxiliary layers through which the light reflected by the reflective electrode layer RL among the light emitted from the light-emitting element LE passes.

[0171] In one or more embodiments, in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, in order to adjust the resonance distance of the light emitted from the light-emitting element LE, the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 may not be disposed under the first electrode AND of the at least one sub-pixel (e.g., the first sub-pixel SP1). In one or more embodiments, the first electrode AND of the first sub-pixel SP1 may be directly disposed on the reflective electrode layer RL. In one or more embodiments, the eleventh insulating layer INS11 may be disposed under the first electrode AND of the second sub-pixel SP2. In one or more embodiments, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed under the first electrode AND of the third sub-pixel SP3. However, in one or more embodiments, as Figure 7 shown, in all of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the eleventh insulating layer INS11 may be disposed under the first electrode AND, and the tenth insulating layer INS10 may not be disposed under the first electrode AND.

[0172] In one or more embodiments, in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL may be different. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence or thickness of the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7 it is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, but the present disclosure is not limited thereto.

[0173] In addition, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiments of the present disclosure, a twelfth insulating layer (not shown) may be added and disposed under the first electrode AND of the first sub-pixel SP1. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer (not shown) may be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer (not shown) may be disposed under the first electrode AND of the third sub-pixel SP3.

[0174] Each of the plurality of tenth vias VA10 may penetrate the eleventh insulating layer INS11 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and may be connected to the exposed reflective electrode layer RL. The tenth via VA10 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0175] The first electrode AND of each of the plurality of light-emitting elements LE may be disposed on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the first electrode AND of each of the plurality of light-emitting elements LE may be titanium nitride (TiN).

[0176] The pixel defining layer PDL may be disposed on a part of the first electrode AND of each of the plurality of light-emitting elements LE. The pixel defining layer PDL may cover the edge of the first electrode AND of each of the plurality of light-emitting elements LE. The pixel defining layer PDL may be used to separate the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0177] The first emission region EA1 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region where the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0178] The pixel defining layer PDL can include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 can be disposed on the edge of the first electrode AND of each of the plurality of light-emitting elements LE, the second pixel defining layer PDL2 can be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 can be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can be formed of a silicon oxide (SiO x )-based inorganic layer, but the present disclosure is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can each have a thickness of approximately .

[0179] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as one pixel defining layer, the height of one pixel defining layer increases, such that the first encapsulation inorganic layer TFE1 may be cut off due to the step coverage. The step coverage refers to the ratio of the degree of coating a thin film on an inclined portion to the degree of coating a thin film on a flat portion. The lower the step coverage, the more likely the thin film is to be cut off on the inclined portion.

[0180] Therefore, in order to prevent the first encapsulation inorganic layer TFE1 from being cut off due to the step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 can have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining layer PDL1 can be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 can be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined in a first direction DR1 (see Figure 5 ) and a second direction DR2 (see Figure 5 ).

[0181] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In addition, each of the plurality of trenches TRC may penetrate the eleventh insulating layer INS11. In one or more embodiments, the tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0182] At least one trench TRC may be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 two trenches TRC are shown disposed between adjacent sub-pixels SP1, SP2, and SP3, the present disclosure is not limited thereto.

[0183] The light emitting stack ES may include a plurality of intermediate layers. Figure 7 The light emitting stack ES is shown having a three-tandem structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack ES may have a two-tandem structure including two intermediate layers.

[0184] In the three-tandem structure, the light emitting stack ES may have a tandem structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack ES may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be stacked in sequence.

[0185] The first stack layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second stack layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer that emits light of a third color, and a second electron transport layer are stacked in sequence. The third stack layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer that emits light of a second color, and a third electron transport layer are stacked in sequence.

[0186] A first charge generation layer for supplying holes to the second stack layer IL2 and electrons to the first stack layer IL1 may be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stack layer IL1 and a P-type charge generation layer that supplies holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0187] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0188] The first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 may be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or an empty space may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 may be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and may be disposed to cover the second stacked layer IL2 in each of the plurality of trenches TR. That is, in the three-tandem structure, each of the plurality of trenches TRC may be a structure for cutting off the first stacked layer IL1 to the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the two-tandem structure, each of the plurality of trenches TRC may be a structure for cutting off the charge generation layer and the lower intermediate layer disposed between the lower intermediate layer and the upper intermediate layer.

[0189] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trenches TRC refers to the length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, there may be another structure instead of the trench TRC. For example, instead of the trench TRC, an inverted conical partition wall may be disposed in the pixel defining layer PDL.

[0190] The number of stacked layers IL1, IL2, and IL3 emitting different lights is not limited to Figure 7The quantities shown in the figure. For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second stack layer IL2, a third stack layer IL3, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be disposed between the two intermediate layers.

[0191] In addition, Figure 7 It is shown that the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but the present disclosure is not limited thereto. For example, the first stack layer IL1 may be disposed in the first emission region EA1 and may not be disposed in the second emission region EA2 and the third emission region EA3. In addition, the second stack layer IL2 may be disposed in the second emission region EA2 and may not be disposed in the first emission region EA1 and the third emission region EA3. In addition, the third stack layer IL3 may be disposed in the third emission region EA3 and may not be disposed in the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0192] The second electrode CAT may be disposed on the third stack layer IL3. The second electrode CAT may be disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO and / or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium and / or silver). When the second electrode CAT is formed of a semi-transmissive conductive material, the light-emitting efficiency in each of the first pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be improved due to the microcavity effect.

[0193] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one of the inorganic layers TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0194] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed of silicon nitride (SiN x ), silicon oxynitride (SiON), and / or silicon oxide (SiO x) is formed by alternately stacking one or more inorganic layers. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0195] The second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be made of titanium oxide (TiO x ) and / or aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The second encapsulation inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0196] The display panel 100 can further include an organic layer APL. The organic layer APL can be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can be an organic layer such as including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0197] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed on the organic layer APL.

[0198] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1 in the third direction DR3. The first color filter CF1 can transmit light of the first color, that is, light in the blue wavelength band. The blue wavelength band can be about 370 nm to 460 nm. Therefore, the first color filter CF1 can transmit light of the first color among the light emitted from the first emission region EA1.

[0199] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2 in the third direction DR3. The second color filter CF2 can transmit light of the second color, that is, light in the green wavelength band. The green wavelength band can be about 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color among the light emitted from the second emission region EA2.

[0200] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3 in the third direction DR3. The third color filter CF3 can transmit light of the third color, that is, light in the red wavelength band. The red wavelength band can be about 600 nm to 750 nm. Therefore, the third color filter CF3 can transmit light of the third color among the light emitted from the third emission region EA3.

[0201] A plurality of lenses LNS can be respectively disposed on a first color filter CF1, a second color filter CF2, and a third color filter CF3. Each of the plurality of lenses LNS can be a structure for increasing the ratio of light toward the front of the display device 10. Each of the plurality of lenses LNS can have a cross-sectional shape that bulges in the upward direction.

[0202] A filling layer FIL can be disposed on the plurality of lenses LNS. The filling layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in a third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL can be a planarizing layer. The filling layer FIL can be an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0203] A cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate and / or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin substrate, it can be directly applied onto the filling layer FIL.

[0204] A polarizing plate POL can be disposed on one surface of the cover layer CVL. The polarizing plate POL can be a structure for preventing a reduction in visibility caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and / or a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but the present disclosure is not limited thereto. However, when the reduction in visibility caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate POL can be omitted.

[0205] Figure 8 is a layout diagram showing an example of a first pad of a first pad portion Figure 4 of Figure 9 is a cross-sectional view showing an example of a display panel taken along line I2-I2' Figure 8 of

[0206] Referring to Figure 8 and Figure 9 the light-emitting element base plate EBP further includes a pad conductive layer PML.

[0207] Each of the plurality of first pads PD1 includes a first sub-pad BPD and a second sub-pad IPD in which a pad conductive layer PML is separated by a tenth insulating layer INS10. Both the first sub-pad BPD and the second sub-pad IPD can be electrically connected to the pads or bumps of the circuit board 300 (see Figure 1 ). Additionally, the second sub-pad IPD can be connected to a jig or a probe during an inspection process, or can be connected to a circuit board for inspection through a conductive film.

[0208] The area of the first sub-pad BPD can be larger than the area of the second sub-pad IPD. The length of the first sub-pad BPD in a first direction DR1 can be substantially the same as the length of the second sub-pad IPD in the first direction DR1. The length of the first sub-pad BPD in a second direction DR2 can be larger than the length of the second sub-pad IPD in the second direction DR2.

[0209] The pad conductive layer PML can include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The second sub-pad conductive layer SPML2 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the first sub-pad conductive layer SPML1 can be made of aluminum (Al).

[0210] The thickness of the first sub-pad conductive layer SPML1 can be larger than the thickness of the reflective electrode layer RL (see Figure 7 ). For example, the first sub-pad conductive layer SPML1 can have a thickness of approximately . Additionally, the second sub-pad conductive layer SPML2 can be made of titanium nitride (TiN) and can have a thickness of approximately . Because the first sub-pad conductive layer SPML1 is formed to have a very large thickness, even if pressure is applied to the pad conductive layer PML through a jig or a probe during an inspection process, damage to the pad conductive layer PML can be prevented.

[0211] The pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD can be connected to each other and can be connected to the eighth conductive layer ML8 through the ninth via VA9 penetrating the ninth insulating layer INS9. Specifically, the first sub-pad conductive layer SPML1 of the first sub-pad BPD and the first sub-pad conductive layer SPML1 of the second sub-pad IPD can be connected to the eighth conductive layer ML8 through the ninth via VA9 penetrating the ninth insulating layer INS9.

[0212] A part of the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD can be exposed and not covered by the tenth insulating layer INS10. Another part of the top surface of the second sub-pad conductive layer SPML2 in the second sub-pad IPD can be exposed and not covered by the tenth insulating layer INS10. The tenth insulating layer INS10 can include an opening OA for exposing the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD and the second sub-pad IPD.

[0213] The remaining inorganic layer RINS can be disposed on at least a part of the sidewall SW10 of the tenth insulating layer INS10 in each of the plurality of openings OA. The remaining inorganic layer RINS can be a residue of the second package inorganic layer TFE2 (see Figure 7 ) that is not removed and remains in each of the plurality of openings OA during the manufacturing process for etching the second package inorganic layer TFE2. The process of retaining the remaining inorganic layer RINS will be described in detail later in conjunction with Figures 11 to 23 .

[0214] The remaining inorganic layer RINS is a residue of the second package inorganic layer TFE2, and thus the remaining inorganic layer RINS can be made of a material substantially the same as the material of the second package inorganic layer TFE2. For example, the remaining inorganic layer RINS can be formed of titanium oxide (TiO x ) and / or aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The remaining inorganic layer RINS can be formed by an atomic layer deposition (ALD) process.

[0215] The remaining inorganic layer RINS can be disposed on the entire sidewall SW10 of the tenth insulating layer INS10. In this case, the remaining inorganic layer RINS can be in contact with the second sub-pad conductive layer SPML2. The remaining inorganic layer RINS can not be disposed on the top surface of the tenth insulating layer INS10 and the top surface of the second sub-pad conductive layer SPML2.

[0216] Since the remaining inorganic layer RINS is formed by an atomic layer deposition method similar to the second package inorganic layer TFE2, and the first package inorganic layer TFE1 (see Figure 7) Formed by chemical vapor deposition, so the thickness of the remaining inorganic layer RINS can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0217] Figure 10 is a cross-sectional view showing an example of a display panel taken along the Figure 8 line I2 - I2' of.

[0218] Figure 10 The embodiment of Figure 9 differs from the embodiment of

[0219] in that: the remaining inorganic layer RINS is provided on a part of the sidewall SW10 of the tenth insulating layer INS10, rather than on the entire sidewall SW10.

[0219] Referring to Figure 10 , the first sub-remaining inorganic layer RINS1 and the second sub-remaining inorganic layer RINS2 of the remaining inorganic layer RINS can be provided on the sidewall SW10 of the tenth insulating layer INS10 facing the opening OA corresponding to the first sub-pad BPD. The first sub-remaining inorganic layer RINS1 and the second sub-remaining inorganic layer RINS2 can be provided separately from each other.

[0220] The size of the first sub-remaining inorganic layer RINS1 and the size of the second sub-remaining inorganic layer RINS2 can be different from each other. The first sub-remaining inorganic layer RINS1 can be provided near the upper side of the sidewall SW10 of the tenth insulating layer INS10, but the second sub-remaining inorganic layer RINS2 can be provided near the lower side of the sidewall SW10 of the tenth insulating layer INS10.

[0221] Although Figure 10 shows that the first sub-remaining inorganic layer RINS1 is provided away from the upper edge of the sidewall SW10 of the tenth insulating layer INS10, the present disclosure is not limited thereto. The first sub-remaining inorganic layer RINS1 can be provided at the upper edge of the sidewall SW10 of the tenth insulating layer INS10.

[0222] Although Figure 10 shows that the second sub-remaining inorganic layer RINS2 is provided away from the top surface of the second sub-pad conductive layer SPML2, the present disclosure is not limited thereto. The second sub-remaining inorganic layer RINS2 can be in contact with the top surface of the second sub-pad conductive layer SPML2.

[0223] The arrangement positions of the remaining inorganic layer RINS provided on one sidewall SW10 of the tenth insulating layer INS10 facing the opening OA corresponding to the second sub-pad IPD and the arrangement positions of the remaining inorganic layer RINS provided on the other sidewall SW10 of the tenth insulating layer INS10 can be different. For example, in the opening OA corresponding to the second sub-pad IPD, the remaining inorganic layer RINS can be provided at the lower edge of one sidewall SW10 of the tenth insulating layer INS10. In this case, the remaining inorganic layer RINS can be in contact with the top surface of the second sub-pad conductive layer SPML2. In addition, the remaining inorganic layer RINS can be provided in the central region of the other sidewall SW10 of the tenth insulating layer INS10, but the present disclosure is not limited thereto. The remaining inorganic layer RINS can be provided at the upper edge of the other sidewall SW10 of the tenth insulating layer INS10.

[0224] The remaining inorganic layer RINS may not be provided on the top surface of the tenth insulating layer INS10 and the top surface of the second sub-pad conductive layer SPML2.

[0225] Figure 11 is a layout diagram showing an example of the first pad of the first pad portion Figure 4 of. Figure 12 is a cross-sectional view showing an example of a display panel taken along the line I3-I3' Figure 11 of.

[0226] Referring to Figure 11 and Figure 12 , each of the plurality of first pads PD1 includes a first sub-pad BPD and a second sub-pad IPD. Both the first sub-pad BPD and the second sub-pad IPD can be electrically connected to the pads or protrusions of the circuit board 300 (see Figure 1 ). In addition, the second sub-pad IPD can be a pad that is connected to a jig or a probe or a circuit board for inspection during the inspection process.

[0227] The area of the first sub-pad BPD can be larger than the area of the second sub-pad IPD. The length of the first sub-pad BPD in the first direction DR1 can be substantially the same as the length of the second sub-pad IPD in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 can be larger than the length of the second sub-pad IPD in the second direction DR2.

[0228] Each of the first sub-pad BPD and the second sub-pad IPD may include a pad conductive layer PML. The pad conductive layer PML may include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The second sub-pad conductive layer SPML2 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the first sub-pad conductive layer SPML1 may be made of aluminum (Al).

[0229] The thickness of the first sub-pad conductive layer SPML1 may be greater than that of the reflective electrode layer RL (see Figure 7 ). For example, the first sub-pad conductive layer SPML1 may have a thickness of approximately . Additionally, the second sub-pad conductive layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately . Because the first sub-pad conductive layer SPML1 is formed to have a very large thickness, even if pressure is applied to the pad conductive layer PML by a jig or a probe during an inspection process, the pad conductive layer PML can be prevented from being damaged.

[0230] A part of the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD may be exposed and not covered by the tenth insulating layer INS10. Another part of the top surface of the second sub-pad conductive layer SPML2 in the second sub-pad IPD may be exposed and not covered by the tenth insulating layer INS10. That is, the tenth insulating layer INS10 may include an opening OA for exposing the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD and the second sub-pad IPD.

[0231] The pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD are provided separately from each other, but may be connected to the eighth conductive layer ML8 via a ninth via VA9 penetrating the ninth insulating layer INS9. Specifically, the first sub-pad conductive layer SPML1 of the first sub-pad BPD and the first sub-pad conductive layer SPML1 of the second sub-pad IPD may be connected to the eighth conductive layer ML8 via a ninth via VA9 penetrating the ninth insulating layer INS9. Therefore, the pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD may have substantially the same potential.

[0232] AsFigure 11 and Figure 12 As shown in Figure 12 , the pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD are separated or distinguished from each other, so that even if the pad conductive layer PML of the second sub-pad IPD is damaged or destroyed by a jig or a probe during the inspection process, the pad conductive layer PML of the first sub-pad BPD will not be damaged or destroyed. That is to say, by physically separating the second sub-pad IPD used in the inspection process from the first sub-pad BPD connected to the circuit board 300, even if the pad conductive layer PML of the second sub-pad IPD is damaged, the pad conductive layer PML of the first sub-pad BPD can be stably connected to the circuit board 300.

[0233] In the opening OA corresponding to each of the first sub-pad BPD and the second sub-pad IPD, the remaining inorganic layer RINS may be provided on at least a part of the side wall SW10 of the tenth insulating layer INS10. Since the remaining inorganic layer RINS can be combined with Figure 9 and Figure 10 described is basically the same, so the description of the remaining inorganic layer RINS is omitted in Figure 12 .

[0234] Figure 13 is a layout diagram showing an example of the first pad of the first pad portion of Figure 4 . Figure 14 is a cross-sectional view showing an example of a display panel taken along the line I4-I4' of Figure 13 .

[0235] Referring to Figure 13 and Figure 14 , each of the plurality of first pads PD1 includes a first sub-pad BPD, a second sub-pad IPD1, and a third sub-pad IPD2. The first sub-pad BPD, the second sub-pad IPD1, and the third sub-pad IPD2 can all be electrically connected to the pads or bumps of the circuit board 300 (see Figure 1 ). In addition, the second sub-pad IPD1 and the third sub-pad IPD2 can be pads connected to a jig or a probe or a circuit board for inspection during the inspection process. The second sub-pad IPD1 can be a pad for inspecting whether the scan driver 610 (see Figure 4 ), the emission driver 620 (see Figure 4 ), and the data driver 700 (see Figure 4 ) are operating normally, and the third sub-pad IPD2 can be a pad for visually inspecting the display image of the display area DAA (see Figure 4 ) of the display panel 100 (see Figure 4 ).

[0236] The area of the first sub-pad BPD can be larger than the areas of the second sub-pad IPD1 and the third sub-pad IPD2. The length of the first sub-pad BPD in the first direction DR1 can be substantially the same as the length of the second sub-pad IPD1 in the first direction DR1 and the length of the third sub-pad IPD2 in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 can be larger than the length of the second sub-pad IPD1 in the second direction DR2 and the length of the third sub-pad IPD2 in the second direction DR2.

[0237] Each of the first sub-pad BPD, the second sub-pad IPD1, and the third sub-pad IPD2 can include a pad conductive layer PML. The pad conductive layer PML can include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. The second sub-pad conductive layer SPML2 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. For example, the first sub-pad conductive layer SPML1 can be made of aluminum (Al).

[0238] The thickness of the first sub-pad conductive layer SPML1 can be larger than the thickness of the reflective electrode layer RL (see Figure 7 ). For example, the first sub-pad conductive layer SPML1 can have a thickness of approximately . Additionally, the second sub-pad conductive layer SPML2 can be made of titanium nitride (TiN) and can have a thickness of approximately . Since the first sub-pad conductive layer SPML1 is formed to have a very large thickness, even if pressure is applied to the pad conductive layer PML by a jig or a probe during the inspection process, the pad conductive layer PML can be prevented from being damaged.

[0239] A part of the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD may be exposed and not covered by the tenth insulating layer INS10. Another part of the top surface of the second sub-pad conductive layer SPML2 in the second sub-pad IPD1 may be exposed and not covered by the tenth insulating layer INS10. Another part of the top surface of the second sub-pad conductive layer SPML2 in the third sub-pad IPD2 may be exposed and not covered by the tenth insulating layer INS10. That is to say, the tenth insulating layer INS10 may include an opening OA for exposing the top surface of the second sub-pad conductive layer SPML2 in the first sub-pad BPD, the second sub-pad IPD1, and the third sub-pad IPD2.

[0240] The pad conductive layers PML of the first sub-pad BPD, the pad conductive layers PML of the second sub-pad IPD1, and the pad conductive layers PML of the third sub-pad IPD2 are arranged to be separated from each other, but may be connected to the eighth conductive layer ML8 through ninth vias VA9 penetrating the ninth insulating layer INS9. Specifically, the first sub-pad conductive layer SPML1 of the first sub-pad BPD, the first sub-pad conductive layer SPML1 of the second sub-pad IPD1, and the first sub-pad conductive layer SPML1 of the third sub-pad IPD2 may be connected to the eighth conductive layer ML8 through ninth vias VA9 penetrating the ninth insulating layer INS9. Therefore, the pad conductive layers PML of the first sub-pad BPD, the pad conductive layers PML of the second sub-pad IPD1, and the pad conductive layers PML of the third sub-pad IPD2 may have substantially the same potential.

[0241] As Figure 13 and Figure 14 shown in, the pad conductive layers PML of the first sub-pad BPD, the pad conductive layers PML of the second sub-pad IPD1, and the pad conductive layers PML of the third sub-pad IPD2 are separated or distinguished from each other, so that even if the pad conductive layer PML of the second sub-pad IPD1 and / or the pad conductive layer PML of the third sub-pad IPD2 are damaged or destroyed by a fixture or a probe during the inspection process, the pad conductive layer PML of the first sub-pad BPD will not be damaged or destroyed. That is to say, by physically separating the second sub-pad IPD1 and the third sub-pad IPD2 used during the inspection process from the first sub-pad BPD connected to the circuit board 300, even if the second sub-pad IPD1 and the third sub-pad IPD2 are damaged, the first sub-pad BPD can be stably connected to the circuit board 300.

[0242] In each of the openings OA corresponding to the first sub-pad BPD, the second sub-pad IPD1, and the third sub-pad IPD2, a remaining inorganic layer RINS may be formed on at least a part of the sidewall SW10 of the tenth insulating layer INS10. Since the remaining inorganic layer RINS can be combined Figure 9 andFigure 10 is substantially the same as the description, so the description of the remaining inorganic layer RINS is omitted in Figure 14 .

[0243] Figure 15 is a flowchart showing a method for manufacturing a display device according to one or more embodiments. Figures 16 to 27 is a cross-sectional view showing a method for manufacturing a display device according to one or more embodiments.

[0244] Figures 16 to 27 The cross-sectional view shown in Figure 5 may be a cross-sectional view of a display panel taken along the line I1-I1' of Figure 8 and a cross-sectional view of the display panel taken along the line I2-I2' of Figures 15 to 27 . Hereinafter, a method for manufacturing a display device will be described in detail with reference to

[0245] As Figure 16 and Figure 17 shown, a light-emitting element substrate EBP is formed on the semiconductor substrate SBP, and a display element layer EML including a light-emitting element LE is formed on the light-emitting element substrate EBP ( Figure 15 step S110 in

[0246] First, a first conductive layer ML1 to an eighth conductive layer ML8, a first via VA1 to a ninth via VA9, a first insulating layer INS1 to a ninth insulating layer INS9, and a pad conductive layer PML of the light-emitting element substrate EBP are formed on the semiconductor substrate SBP.

[0247] Specifically, a first insulating layer INS1 is formed on a semiconductor substrate SBP. Through a photolithography process, a plurality of contact terminals CTE respectively connected to the semiconductor substrate SBP and a plurality of first vias VA1 penetrating the first insulating layer INS1 are formed. And through a photolithography process, a plurality of first conductive layers ML1 respectively connected to the plurality of first vias VA1 are formed on the first insulating layer INS1. Then, a second insulating layer INS2 is formed on the plurality of first conductive layers ML1. Through a photolithography process, a plurality of second vias VA2 respectively connected to the plurality of first conductive layers ML1 and penetrating the second insulating layer INS2 are formed. And through a photolithography process, a plurality of second conductive layers ML2 respectively connected to the plurality of second vias VA2 are formed on the second insulating layer INS2. Then, a third insulating layer INS3 is formed on the plurality of second conductive layers ML2. Through a photolithography process, a plurality of third vias VA3 respectively connected to the plurality of second conductive layers ML2 and penetrating the third insulating layer INS3 are formed. And through a photolithography process, a plurality of third conductive layers ML3 respectively connected to the plurality of third vias VA3 are formed on the third insulating layer INS3. Then, a fourth insulating layer INS4 is formed on the plurality of third conductive layers ML3. Through a photolithography process, a plurality of fourth vias VA4 respectively connected to the plurality of third conductive layers ML3 and penetrating the fourth insulating layer INS4 are formed. And through a photolithography process, a plurality of fourth conductive layers ML4 respectively connected to the plurality of fourth vias VA4 are formed on the fourth insulating layer INS4.

[0248] Then, a fifth insulating layer INS5 is formed on the plurality of fourth conductive layers ML4. A plurality of fifth vias VA5 that are respectively connected to the plurality of fourth conductive layers ML4 and penetrate the fifth insulating layer INS5 are formed through a photolithography process, and a plurality of fifth conductive layers ML5 that are respectively connected to the plurality of fifth vias VA5 are formed on the fifth insulating layer INS5 through a photolithography process. Then, a sixth insulating layer INS6 is formed on the plurality of fifth conductive layers ML5. A plurality of sixth vias VA6 that are respectively connected to the plurality of fifth conductive layers ML5 and penetrate the sixth insulating layer INS6 are formed through a photolithography process, and a plurality of sixth conductive layers ML6 that are respectively connected to the plurality of sixth vias VA6 are formed on the sixth insulating layer INS6 through a photolithography process. Then, a seventh insulating layer INS7 is formed on the plurality of sixth conductive layers ML6. A plurality of seventh vias VA7 that are respectively connected to the plurality of sixth conductive layers ML6 and penetrate the seventh insulating layer INS7 are formed through a photolithography process, and a plurality of seventh conductive layers ML7 that are respectively connected to the plurality of seventh vias VA7 are formed on the seventh insulating layer INS7 through a photolithography process. Then, an eighth insulating layer INS8 is formed on the plurality of seventh conductive layers ML7. A plurality of eighth vias VA8 that are respectively connected to the plurality of seventh conductive layers ML7 and penetrate the eighth insulating layer INS8 are formed through a photolithography process, and a plurality of eighth conductive layers ML8 that are respectively connected to the plurality of eighth vias VA8 are formed on the eighth insulating layer INS8 through a photolithography process. Then, a ninth insulating layer INS9 is formed on the plurality of eighth conductive layers ML8, and a plurality of ninth vias VA9 that are respectively connected to the plurality of eighth conductive layers ML8 and penetrate the ninth insulating layer INS9 are formed through a photolithography process in the ninth insulating layer INS9.

[0249] Then, in each of the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ), a first sub-pad conductive layer SPML1 of a pad conductive layer PML connected to the plurality of ninth vias VA9 is formed on the ninth insulating layer INS9, and a second sub-pad conductive layer SPML2 is formed on the first sub-pad conductive layer SPML1.

[0250] In addition, a reflective electrode layer RL, a tenth insulating layer INS10, an eleventh insulating layer INS11, a tenth via VA10, a light-emitting element LE, a pixel defining layer PDL, and a plurality of trenches TRC of a display element layer EML are formed on a light-emitting element base plate EBP.

[0251] Specifically, a plurality of first reflective electrodes RL1 of a reflective electrode layer RL are formed on a ninth insulating layer INS9 and are respectively connected to a plurality of ninth vias VA9, and a plurality of second reflective electrodes RL2 of the reflective electrode layer RL are respectively formed on the plurality of first reflective electrodes RL1. Then, a plurality of third reflective electrodes RL3 of the reflective electrode layer RL are respectively formed on the plurality of second reflective electrodes RL2 of the reflective electrode layer RL, and a plurality of fourth reflective electrodes RL4 of the reflective electrode layer RL are respectively formed on the plurality of third reflective electrodes RL3 of the reflective electrode layer RL.

[0252] Then, a tenth insulating layer INS10 is formed between the reflective electrode layers RL, and an eleventh insulating layer INS11 is formed on at least a part of the tenth insulating layer INS10 and the reflective electrode layer RL. In this case, optionally, the eleventh insulating layer INS11 may not be formed in at least one of the emission regions EA1, EA2, and EA3 (for example, the third emission region EA3). In addition, the height of the eleventh insulating layer INS11 may be different in the other emission regions EA1 and EA2.

[0253] Then, a plurality of tenth vias VA10 are formed which are respectively connected to the plurality of fourth reflective electrodes RL4 and penetrate the eleventh insulating layer INS11. In addition, the tenth insulating layer INS10 may be formed to cover the edge of the pad conductive layer PML. In addition, the tenth insulating layer INS10 may be formed on the top surface of the second sub-pad conductive layer SPML2 to separate the first sub-pad BPD and the second sub-pad IPD.

[0254] Then, a plurality of first electrodes AND of a plurality of light-emitting elements LE are formed on the eleventh insulating layer INS11 and are respectively connected to the plurality of tenth vias VA10, and a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3 that cover respective edges of the plurality of first electrodes AND of the pixel defining layer PDL are sequentially formed. Then, a trench TRC is formed that penetrates the first pixel defining layer PDL1, the second pixel defining layer PDL2, the third pixel defining layer PDL3, and the eleventh insulating layer INS11. Then, a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3 of a light-emitting stack ES are formed on the first electrode AND, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In this case, the first stacked layer IL1 and the second stacked layer IL2 may be cut off in each of the plurality of trenches TRC. Then, a second electrode CAT of the light-emitting element LE is formed on the third stacked layer IL3.

[0255] As Figure 18 and Figure 19As shown in Figure 15 , a packaging layer TFE covering the light-emitting element LE is formed on the display element layer EML (step S120 in

[0256] ). On the second electrode CAT, a first packaging inorganic layer TFE1 and a second packaging inorganic layer TFE2 of the packaging layer TFE are sequentially formed. The first packaging inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process, and the second packaging inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process. In this case, the second packaging inorganic layer TFE2 can be formed on the second sub-pad conductive layer SPML2 and the tenth insulating layer INS10 in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ). Conversely, the first packaging inorganic layer TFE1 may not be formed on the second sub-pad conductive layer SPML2 and the tenth insulating layer INS10 in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ).

[0257] As Figure 20 shown, color filters CF1, CF2, and CF3 are formed on the packaging layer TFE (step S130 in Figure 15 ).

[0258] An organic layer APL is formed on the packaging layer TFE, and a first color filter CF1 overlapping the first emission region EA1 in the third direction DR3, a second color filter CF2 overlapping the second emission region EA2 in the third direction DR3, and a third color filter CF3 overlapping the third emission region EA3 in the third direction DR3 are formed on the organic layer APL.

[0259] As Figure 21 and Figure 22 shown, a first lens layer LNL1 is formed on the color filters CF1, CF2, and CF3, and a second lens pattern layer LNL2 is formed on the first lens layer LNL1 (step S140 in Figure 15 ).

[0260] The first lens layer LNL1 can be formed on the color filters CF1, CF2, and CF3, and the first lens layer LNL1 can also be formed on the second packaging inorganic layer TFE2 in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ).

[0261] The second lens pattern layer LNL2 can be formed through a photolithography process. The second lens pattern layer LNL2 can have a pattern shape that bulges upward on the first lens layer LNL1 disposed on the color filters CF1, CF2, and CF3. The second lens pattern layer LNL2 may not be provided at the edges of the color filters CF1, CF2, and CF3. That is, a plurality of second lens pattern layers LNL2 can be provided separately from each other.

[0262] In addition, the second lens pattern layer LNL2 can be formed on the first lens layer LNL1 on the second sub-pad conductive layer SPML2 and the tenth insulating layer INS10 provided in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ). The second lens pattern layer LNL2 may not have a bulging pattern shape in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ) and can be formed to be flat.

[0263] As Figure 23 and Figure 24 shown, dry etching is used to etch the first lens layer LNL1 and the second lens pattern layer LNL2 (see Figure 21 and Figure 22 ) to form a plurality of lenses LNS (step S150 in Figure 15 ).

[0264] Since the second lens pattern layer LNL2 provided on the plurality of color filters CF1, CF2, and CF3 has an upwardly bulging shape, similar to the second lens pattern layer LNL2, a plurality of lenses LNS1, LNS2, and LNS3 can be etched to have an upwardly bulging shape.

[0265] The thickness of the first lens layer LNL1 can be greater than the thickness of the second lens pattern layer LNL2. For example, the first lens layer LNL1 can have a thickness of about 2.5 μm, and the second lens pattern layer LNL2 can have a thickness of about 1.5 μm. In this case, when the thickness of the first lens layer LNL1 etched by dry etching is controlled to be greater than the thickness of the second lens pattern layer LNL2 and less than the thickness of the first lens layer LNL1, even when the first lens layer LNL1 and the second lens pattern layer LNL2 are etched together, the first lens layer LNL1 can remain in the area where the second lens pattern layer LNL2 is not formed. Thus, the plurality of color filters CF1, CF2, and CF3 can be protected. However, the present disclosure is not limited thereto, and the entire first lens layer LNL1 provided in the area where the second lens pattern layer LNL2 is not formed can be etched. In this case, as Figure 23As shown, multiple lenses LNS can be set apart from each other.

[0266] The first lens layer LNL1 and the second lens pattern layer LNL2 can be made of the same material. Optionally, when the first lens layer LNL1 and the second lens pattern layer LNL2 are made of different materials, the etching rates of the first lens layer LNL1 and the second lens pattern layer LNL2 by the etching gas used in dry etching can be substantially the same.

[0267] As Figure 25 and Figure 26 shown, the second encapsulation inorganic layer TFE2 and the first lens layer LNL1 (see Figure 4 ) on the second sub-pad conductive layer SPML2 provided in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 21 and Figure 22 )( Figure 15 step S160 in

[0268] Because the second lens pattern layer LNL2 (see Figure 21 and Figure 22 ) is provided in the entire areas of the first sub-pad BPD and the second sub-pad IPD, the first lens layer LNL1 can be retained in the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4 ) and is not removed in step S150. Because the first sub-pad BPD and the second sub-pad IPD need to be exposed to connect to the conductive adhesive member, the first lens layer LNL1 can be removed by etching the first lens layer LNL1 via a dry etching process. In addition, the second encapsulation inorganic layer TFE2 can also be removed by a dry etching process.

[0269] Optionally, the first lens layer LNL1 and the second encapsulation inorganic layer TFE2 can be removed by a single dry etching process.

[0270] The gas used in the dry etching process can be carbon tetrafluoride (CF 4 ), carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) and / or carbon tetrafluoride (CF 4 ) and argon (Ar).

[0271] In this case, as Figures 25 to 26 shown, it can be in addition to the first pad portion PDA1 (see Figure 4 ) and the second pad portion PDA2 (see Figure 4A mask pattern MP is formed in the remaining area outside () to protect the remaining area from the etching gas. For example, the mask pattern MP can be a photoresist pattern. After the dry etching process, the mask pattern MP can be removed by a stripping process.

[0272] The second encapsulation inorganic layer TFE2 is formed very thin by an atomic layer deposition method, and in addition, during the dry etching process, the first lens layer LNL1 and the second encapsulation inorganic layer TFE2 are removed by an etching gas moving in the vertical direction, so that it may take a long time to remove the second encapsulation inorganic layer TFE2 provided on the sidewall SW10 of the tenth insulating layer INS10. However, by removing the first lens layer LNL1 and the second encapsulation inorganic layer TFE2 through the dry etching process to expose the second sub-pad conductive layer SPML2 in each of the first sub-pad BPD and the second sub-pad IPD, the second encapsulation inorganic layer TFE2 provided on the sidewall SW10 of the tenth insulating layer INS10 is not removed. Therefore, by allowing the second encapsulation inorganic layer TFE2 provided on the sidewall SW10 of the tenth insulating layer INS10 to remain and not be removed, the time required for the dry etching process can be reduced. That is to say, the remaining inorganic layer RINS can be provided on at least a part of the sidewall SW10 of the tenth insulating layer INS10. It has been combined Figure 9 and Figure 10 The position where the remaining inorganic layer RINS remains has been described in detail.

[0273] As Figure 27 shown, a filling layer FIL is formed on a plurality of lenses LNS, and a cover layer CVL ( Figure 15 step S170 in

[0274] is provided on the filling layer FIL).

[0275] The cover layer CVL can be a glass substrate and / or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate, and the filling layer FIL can be used to adhere the cover layer CVL. When the cover layer CVL is a polymer resin substrate, it can be directly applied onto the filling layer FIL. Then, a polarizing plate POL is attached to the cover layer CVL.

[0276] Figure 28 is a perspective view showing a head-mounted display according to one or more embodiments. Figure 29 is a perspective view showing Figure 28 an example of the head-mounted display.

[0277] Referring to Figure 28 and Figure 29, a head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a housing member 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0278] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Since each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in conjunction with Figure 1 and Figure 2 the description will be omitted for the first display device 10_1 and the second display device 10_2.

[0279] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0280] The intermediate frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0281] The control circuit board 1600 may be disposed between the intermediate frame 1400 and the housing member 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connection member. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 2 ), and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through a connection member.

[0282] The control circuit board 1600 may transmit the digital video data DATA corresponding to the left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit the digital video data DATA corresponding to the right-eye image optimized for the user's right eye to the second display device 10_2. Optionally, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0283] The housing member 1100 is configured to accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is arranged to cover an opening surface of the housing member 1100. The housing cover 1200 may include a first eyepiece 1210 disposed at the left eye of the user and a second eyepiece 1220 disposed at the right eye of the user. Figure 28 and Figure 29 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately arranged, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0284] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0285] The head-mounted band 1300 is configured to fix the housing member 1100 to the user's head such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained on the left eye and the right eye of the user. When the housing member 1100 is implemented to be lightweight and compact, the head-mounted display 1000 can provide a spectacle frame as shown in Figure 30 to replace the head-mounted band 1300.

[0286] In addition, the head-mounted display 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a fifth-generation (5G) communication module, a fourth-generation (4G) communication module, a wireless fidelity (Wi-Fi) module, and / or a Bluetooth module.

[0287] Figure 30 is a perspective view showing a head-mounted display according to one or more embodiments.

[0288] Referring to Figure 30, the head-mounted display 1000_1 according to one or more embodiments may be a glasses-type display device in which the housing member 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple arms 1040 and 1050, an optical member 1060, an optical path-changing member 1070, and a housing member 1200_1.

[0289] The housing member 1200_1 may accommodate the display device 10_3, the optical member 1060, and the optical path-changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and may be provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path-changing member 1070. As a result, the user may view, through the right eye, an augmented reality image in which the virtual image displayed on the display device 10_3 and the real image seen through the right-eye lens 1020 are combined.

[0290] Figure 30 It is shown that the housing member 1200_1 is disposed at an end portion on the right side of the support frame 1030, but the present disclosure is not limited thereto. For example, the housing member 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be supplied to the user's left eye. Optionally, the housing member 1200_1 may be disposed at both the left end and the right end of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0291] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. Through reference to the claims and the equivalents to be included therein, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Claims

1. A display device, wherein: The display device comprises: substrate; A plurality of conductive layers are sequentially stacked on the substrate; a reflective electrode layer, located on the plurality of conductive layers; A pad conductive layer, located on the plurality of conductive layers; an insulating layer, covering at least a portion of the pad conductive layer and the reflective electrode layer; A plurality of light emitting elements are located on the insulating layer, each of the plurality of light emitting elements comprising a first electrode, a light emitting stack, and a second electrode; A first encapsulation inorganic layer, located on the second electrode; a second encapsulation inorganic layer, located on the first encapsulation inorganic layer; and An inorganic layer is located on at least a portion of the sidewall of the insulating layer in the opening exposing the pad conductive layer.

2. The display device according to claim 1, wherein: The inorganic layer and the second encapsulating inorganic layer include the same material.

3. The display device according to claim 1, wherein: The second encapsulating inorganic layer and the inorganic layer include at least one of titanium oxide and aluminum oxide.

4. The display device according to claim 1, wherein: The inorganic layer includes a material different from a material of the first encapsulating inorganic layer.

5. The display device according to claim 1, wherein: The first encapsulation inorganic layer includes at least one of silicon nitride, silicon oxynitride and silicon oxide, and Wherein, the inorganic layer includes at least one of titanium oxide and aluminum oxide.

6. The display device according to claim 1, wherein: The inorganic layer contacts the pad conductive layer.

7. The display device according to claim 1, wherein: The inorganic layer is separated from the pad conductive layer.

8. The display device according to claim 1, wherein: The inorganic layer includes a first sub-inorganic layer and a second sub-inorganic layer separated from each other on the sidewall of the insulating layer.

9. The display device according to claim 8, wherein: A size of the first sub-inorganic layer and a size of the second sub-inorganic layer are different from each other.

10. The display device according to claim 8, wherein: At least one of the first sub-inorganic layer and the second sub-inorganic layer is in contact with the pad conductive layer.

11. The display device according to claim 1, wherein: The thickness of the inorganic layer is smaller than the thickness of the first encapsulating inorganic layer.

12. The display device according to claim 1, wherein: The thickness of the pad conductive layer is greater than the thickness of the reflective electrode layer.

13. The display device according to claim 1, wherein: The pad conductive layer is divided into a first sub-pad and a second sub-pad by the insulating layer, and The area of ​​the first sub-pad is different from the area of ​​the second sub-pad.

14. The display device according to claim 13, wherein: The pad conductive layer of the first sub pad and the pad conductive layer of the second sub pad are physically connected to each other.

15. The display device according to claim 13, wherein: The pad conductive layer of the first sub pad and the pad conductive layer of the second sub pad are separated from each other.

16. The display device according to claim 15, wherein: The pad conductive layer of the first sub pad and the pad conductive layer of the second sub pad are electrically connected to at least one conductive layer among the plurality of conductive layers.

17. The display device according to claim 1, wherein: The pad conductive layer is divided into a first sub-pad, a second sub-pad and a third sub-pad by the insulating layer, and Wherein an area of ​​the first sub-pad is different from an area of ​​the second sub-pad, and wherein the area of ​​the first sub-pad is different from an area of ​​the third sub-pad.

18. The display device according to claim 17, wherein: The area of ​​the second sub pad is the same as the area of ​​the third sub pad.

19. The display device according to claim 17, wherein: The pad conductive layer of the first sub pad, the pad conductive layer of the second sub pad, and the pad conductive layer of the third sub pad are separated from each other.

20. The display device according to claim 19, wherein: The pad conductive layer of the first sub pad, the pad conductive layer of the second sub pad, and the pad conductive layer of the third sub pad are electrically connected to at least one conductive layer among the plurality of conductive layers.

21. A method for manufacturing a display device, wherein: The method comprises: sequentially forming a plurality of conductive layers on a substrate; forming a reflective electrode layer on the plurality of conductive layers; forming a pad conductive layer on the plurality of conductive layers; forming an insulating layer covering at least a portion of the pad conductive layer and the reflective electrode layer; forming a plurality of light emitting elements on the insulating layer, each of the plurality of light emitting elements comprising a first electrode, a light emitting stack located on the first electrode, and a second electrode located on the light emitting stack; forming a first encapsulation inorganic layer on the second electrode; forming a second encapsulation inorganic layer on the first encapsulation inorganic layer, the pad conductive layer being exposed by the opening of the insulating layer, and the insulating layer covering at least a portion of the pad conductive layer; forming a plurality of color filters on the second encapsulation inorganic layer; forming a first lens layer on the second encapsulation inorganic layer and the plurality of color filters on the pad conductive layer, and forming a second lens pattern layer including a plurality of convex patterns on the first lens layer; etching the first lens layer and the second lens pattern layer to form a plurality of lenses; and The second encapsulation inorganic layer and the first lens layer located on the pad conductive layer are etched.

22. The method according to claim 21, wherein: The etching of the second encapsulation inorganic layer and the first lens layer located on the pad conductive layer comprises: forming a mask pattern on the plurality of lenses; and The second encapsulation inorganic layer and the first lens layer not covered by the mask pattern are dry-etched using an etching gas.

23. The method according to claim 22, wherein: The etching gas is carbon tetrafluoride, the etching gas is carbon tetrafluoride and oxygen, and / or the etching gas is carbon tetrafluoride and argon.

24. The method according to claim 21, wherein: The thickness of the first lens layer is greater than the thickness of the second lens pattern layer.

25. The method according to claim 21, wherein: When etching the first lens layer and the second lens pattern layer to form the plurality of lenses, a thickness of the first lens layer etched by the etching is greater than a thickness of the second lens pattern layer.

26. A head mounted display, wherein: The head mounted display comprises: at least one display device; a housing member configured to accommodate the at least one display device; and an optical member configured to magnify a display image of the at least one display device or change an optical path, Wherein, the at least one display device comprises: substrate; A plurality of conductive layers are sequentially stacked on the substrate; a reflective electrode layer, located on the plurality of conductive layers; A pad conductive layer, located on the plurality of conductive layers; an insulating layer, covering at least a portion of the pad conductive layer and the reflective electrode layer; A plurality of light emitting elements are located on the insulating layer, each of the plurality of light emitting elements comprising a first electrode, a light emitting stack, and a second electrode; A first encapsulation inorganic layer, located on the second electrode; a second encapsulation inorganic layer, located on the first encapsulation inorganic layer; and An inorganic layer is located on at least a portion of the sidewall of the insulating layer in the opening exposing the pad conductive layer.

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