Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same. The display device may include a substrate having: a first sub-pixel and a second sub-pixel each including a respective emission region; and a non-emission region surrounding the emission region; a respective first electrode in each of the first and second sub-pixels; a bank having a respective bank hole in each of the emission regions and a bank groove in the non-emission region; a first spacer on the bank; a second spacer in the bank trench; an emission layer on the first electrode and the bank trench, and including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and a second electrode on the emission layer.

Description

Technical Field

[0001] The present disclosure relates to a display device such as a light-emitting diode display device and a method for manufacturing a display device, and more particularly to a display device (e.g., a light-emitting diode display device) having a structure for reducing or preventing leakage current between adjacent sub-pixels and a method for manufacturing the display device. Background Art

[0002] Latest display devices that require display information and interact with users who view the information come in various sizes, various shapes, and various functions.

[0003] Display devices may include liquid crystal display (LCD) devices, electrophoretic display (EPD) devices, and light-emitting diode (LED) display devices.

[0004] LED display devices are emissive and can be manufactured to have a light weight and a thin profile because, unlike LCD devices, no additional light source is required. In addition, LED display devices have an advantage in power consumption due to low-voltage driving, and have advantages in color display, response speed, viewing angle, and contrast. As a result, LED display devices have been studied as next-generation displays.

[0005] Although an organic light-emitting diode (OLED) display device may be exemplarily shown as an LED display device, the material of the emission layer is not limited thereto.

[0006] LED display devices display information by lighting a plurality of pixels having an emission layer. According to the method of driving the pixels, LED display devices can be classified into active matrix type LED display devices and passive matrix type LED display devices.

[0007] Active matrix type LED display devices display an image by controlling the current flowing through a light-emitting diode using a thin film transistor (TFT).

[0008] LED display devices have an anode, an emission layer, and a cathode. When a voltage is applied to the anode and the cathode, holes in the anode and electrons in the cathode move to the emission layer. The holes and electrons combine in the emission layer to generate excitons, and light is emitted when the excitons transition from an excited state to a ground state.

[0009] In order to provide high-quality image information, the resolution of LED display devices is gradually increasing. As the resolution increases, the gap distance between adjacent sub-pixels decreases. As a result, due to the leakage current in the lateral direction between adjacent sub-pixels, the image information is distorted.

[0010] Although various methods for preventing lateral leakage current have been proposed to obtain high-resolution LED display devices, they are insufficient and need to be developed. SUMMARY OF THE INVENTION

[0011] Accordingly, embodiments of the present disclosure relate to a light-emitting diode display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0012] An object of the present disclosure is to provide a light-emitting display device having a bank trench including at least one second spacer between adjacent sub-pixels to reduce or prevent lateral leakage current that increases as the gap distance between adjacent sub-pixels decreases.

[0013] Additional features and advantages of the present disclosure will be set forth in the description below, and in part will be obvious to those skilled in the art from the description, or may be learned by practice of the present disclosure. These and other advantages of the present disclosure may be realized and obtained by the structure particularly pointed out in the written description, its claims, and the drawings, or from the structure derived from the written description, its claims, and the drawings.

[0014] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device may include: a substrate having a first sub-pixel and a second sub-pixel each including a respective emission region and a non-emission region surrounding the emission region; respective first electrodes in each of the first sub-pixel and the second sub-pixel; a bank having a respective bank hole in each of the emission regions in the emission region and a bank trench in the non-emission region; a first spacer on the bank; a second spacer in the bank trench; an emission layer on the first electrode and the bank trench and including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and a second electrode on the emission layer.

[0015] In another aspect of the present disclosure, a display device may include: a substrate including a display region and a non-display region adjacent to the display region, the display region having a plurality of sub-pixels and a non-emission region between the plurality of sub-pixels; respective first electrodes in each of the plurality of sub-pixels; a bank dividing the plurality of sub-pixels; an emission layer on the first electrodes; a second electrode on the emission layer; and a cut in the emission layer between two adjacent sub-pixels among the plurality of pixels.

[0016] According to yet another exemplary embodiment of the present disclosure, a method for manufacturing a display device may include: forming a plurality of first electrodes spaced apart from each other on a substrate; forming a bank on the substrate on which the plurality of first electrodes are formed; forming a bank hole in the bank such that a portion of each of the plurality of first electrodes is exposed, and forming a bank trench in the bank between adjacent first electrodes among the plurality of first electrodes; forming a second spacer in the bank trench; forming an emission layer on the second spacer and the bank trench, the emission layer including a plurality of stacked layers and at least one charge generation layer between the plurality of stacked layers; and forming a second electrode on the emission layer.

[0017] It should be understood that the foregoing general description and the following detailed description are both illustrative and exemplary and are intended to provide further explanation of the claimed disclosure without limiting its scope. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0019] Figure 1 is a plan view showing a light-emitting diode display device according to an embodiment of the present disclosure;

[0020] Figure 2 is a plan view showing a sub-pixel of a light-emitting diode display device according to an embodiment of the present disclosure and a bank trench having a second spacer;

[0021] Figure 3 is a cross-sectional view showing a light-emitting diode display device according to an embodiment of the present disclosure;

[0022] Figures 4A to 4D is a cross-sectional view showing a manufacturing process of a light-emitting diode display device according to an embodiment of the present disclosure; and

[0023] Figure 5 is a view showing an emission layer of a light-emitting diode display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The advantages, features, and methods for implementing the present disclosure will be elucidated by the following exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure may be sufficiently thorough and complete to enable those skilled in the art to fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents.

[0025] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. Unless otherwise specified, like reference numerals always refer to like elements.

[0026] In the following description, in cases where a detailed description of related known functions or configurations may unnecessarily obscure the features or aspects of the present disclosure, the detailed description of such known functions or configurations may be omitted or a brief description may be provided.

[0027] In cases where terms such as "comprising", "having", "including", etc. are used, one or more other elements may be added, unless a term such as "only" is used. Elements described in the singular are intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise.

[0028] When interpreting an element, even if no explicit description of the error or tolerance range is provided, the element will be interpreted as including such an error or tolerance range.

[0029] In cases where a positional relationship is described, for example, in cases where the positional relationship between two parts is described using "on", "above", "under", "over", "below", "next to", "near", etc., one or more other parts may be located between the two parts, unless more restrictive terms such as "immediately", "directly", or "closely" are used. For example, in the case where an element or layer is disposed "on" another element or layer, a third layer or third element may be inserted therebetween.

[0030] Although terms such as "first", "second", A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, because these terms are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0031] The features of the various embodiments of the present disclosure may be partially or fully coupled or combined with each other. They may be technically linked and operated in various ways as can be fully understood by those skilled in the art. These embodiments may be performed independently of each other or in association with each other in various combinations.

[0032] Hereinafter, a light-emitting diode display device according to various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 is a plan view showing a light-emitting diode display device according to an embodiment of the present disclosure.

[0034] In Figure 1 , a light-emitting diode (LED) display device 100 according to an embodiment of the present disclosure may include various elements for generating signals or driving a plurality of sub-pixels SP_1, SP_2, and SP_3 in a display area AA. For example, the LED display device 100 may include at least one driving circuit for controlling a display panel. The driving circuit for controlling or driving the sub-pixels SP_1, SP_2, and SP_3 may include a gate driving unit 112, data signal lines, a multiplexer MUX, an electrostatic discharge circuit ESD, a high-level voltage line VDD, a low-level voltage line VSS, and an inverter circuit. The LED display device 100 may also include elements other than those for driving the sub-pixels SP_1, SP_2, and SP_3. For example, the LED display device 100 may include elements providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, and a haptic feedback. These elements may be arranged in a non-display area NA or connected to an external circuit of a connection interface.

[0035] The substrate 110 may include a display area AA and a non-display area NA. In the display area AA of the substrate 110, a plurality of pixels P are arranged and an image is displayed. In the non-display area NA of the substrate 110, no image is displayed. For example, the non-display area NA may be referred to as a border area and is not limited thereto. The non-display area NA may be arranged adjacent to the display area AA and may be arranged more externally than the display area AA. Alternatively, the non-display area NA may be arranged to surround all or a part of the display area AA. The non-display area NA may be an area where a plurality of sub-pixels SP_1, SP_2, and SP_3 are not arranged and is not limited thereto.

[0036] Each pixel P in the display area AA may include a plurality of sub-pixels SP_1, SP_2, and SP_3. Each sub-pixel SP_1, SP_2, and SP_3 is a single unit that emits light. The plurality of sub-pixels SP_1, SP_2, and SP_3 may include a red sub-pixel SP_R, a green sub-pixel SP_G, a blue sub-pixel SP_B, and / or a white sub-pixel, and is not limited thereto.

[0037] Each sub-pixel SP_1, SP_2, and SP_3 includes a light-emitting diode and a sub-pixel circuit. For example, each sub-pixel SP_1, SP_2, and SP_3 may include a light-emitting diode for displaying an image and a sub-pixel circuit for driving or controlling the light-emitting diode.

[0038] Each sub-pixel SP may include a plurality of transistors, one or more capacitors, and a plurality of lines. For example, each sub-pixel SP may have a 2T1C structure including two transistors and one capacitor. Alternatively, each sub-pixel SP may have one of 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, and 8T2C structures.

[0039] The non-display area NA is an area where a plurality of lines and a plurality of driving circuits for driving the plurality of sub-pixels SP_1, SP_2, and SP_3 in the display area AA are arranged. For example, a plurality of integrated circuits (ICs) and driving circuits (such as a gate driving unit 112 and a data driving unit) may be arranged in the non-display area NA.

[0040] Although in Figure 1 the non-display area NA surrounds the display area AA having a rectangular shape, the shapes and arrangements of the adjacent display area AA and non-display area NA are not limited thereto. The display area AA and the non-display area NA may have shapes corresponding to the design of the electronic device having the LED display device 100. The display area AA and the non-display area NA may have a circular shape corresponding to a watch for a wearable device and may have a free form for a dashboard. For example, the display area AA may have one of a pentagonal, hexagonal, octagonal, circular, and elliptical shape, and is not limited thereto.

[0041] The non-display area NA may include a bending area BA. The bending area BA may be arranged between the display area AA and the pad portion 114 of the non-display area NA. The bending area BA may be an area where a connection line portion is arranged.

[0042] The bending region BA may be a region where a part of the substrate 110 is bent so that the pad portion 114 and an external module joined to the pad portion 114 are disposed above the rear surface of the substrate 110. For example, since the bending region BA is bent toward the rear surface of the substrate 110, the external module joined to the pad portion 114 of the substrate 110 moves toward the rear surface of the substrate 110 and is not recognized in the plan view of the substrate 110. Although Figure 1 the display device 100 may be shown in a plan view before the bending region BA is bent such that the pad portion 114 is Figure 1 visible, after the bending region BA is bent, the pad portion 114 may be disposed at the rear side of the display device 100 such that it is no longer visible from the front side of the display device 100. In addition, since the bending region BA is bent, the size of the non-display region NA in the plan view of the user is reduced, thereby obtaining a narrow bezel. Although the bending region BA is disposed in the non-display region NA in the LED display device 100, it is not limited thereto. For example, the bending region BA may be disposed in the display region AA, and the display region AA may be bent in various directions such that the bending region BA of the display region AA has an effect similar to that of the bending region BA of the non-display region NA.

[0043] The pad portion 114 is disposed at one side of the non-display region NA. The pad portion 114 is a metal pattern to which an external module, such as a flexible printed circuit board (FPCB) and a chip on film (COF), is joined. Although the pad portion 114 is disposed adjacent to one side of the substrate 110, the shape and the arrangement of the pad portion 114 are not limited thereto.

[0044] The gate driving unit 112 that supplies a gate signal to the thin film transistor (TFT) may be disposed at the other side of the non-display region NA. The gate driving unit 112 may include a plurality of gate driving circuits, and the plurality of gate driving circuits may be directly formed on the substrate 110. For example, the gate driving unit 112 directly formed on the substrate 110 may have an in-panel gate (GIP) type.

[0045] The gate driving unit 112 may be disposed between the dam portion DAM of the display region AA and the non-display region NA.

[0046] The high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX, the electrostatic discharge circuit ESD, and a plurality of connection line portions may be disposed between the display region AA and the pad portion 114 of the non-display region NA.

[0047] The high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX, and the electrostatic discharge circuit ESD may be disposed between the display region AA and the bending region BA.

[0048] A plurality of connection line portions may be arranged in the non-display area NA. For example, the plurality of connection line portions may be arranged in a bending area BA where the substrate 110 is bent in the non-display area NA. The plurality of connection line portions may be structures for transmitting signals (voltages) of an external module bonded to the pad portion 114 to the display area AA or a circuit unit (such as the gate driving unit 112). For example, a plurality of signals, such as signals for driving the gate driving unit 112, data signals, high-level voltages, and low-level voltages, may be transmitted through the plurality of connection line portions.

[0049] The dam portion DAM is arranged in the non-display area NA to surround all or a part of the display area AA. The dam portion DAM may be arranged adjacent to the display area AA and may be arranged outside the display area AA.

[0050] The dam portion DAM may be arranged at the periphery of the display area AA to adjust the flow of the organic material for the second encapsulation layer on the light-emitting diode. The dam portion DAM may be arranged as one or more.

[0051] The dam portion DAM may be arranged between the display area AA, the high-level voltage line VDD, the low-level voltage line VSS, the multiplexer MUX, and the electrostatic discharge circuit ESD.

[0052] The crack detection line PCD may be arranged in the non-display area NA of the substrate 110.

[0053] The crack detection line PCD may be arranged between the end of the substrate 110 and the dam portion DAM. Alternatively, the crack detection line PCD may be arranged under the dam portion DAM to partially overlap the dam portion DAM.

[0054] Figure 2 is a plan view showing a sub-pixel of a light-emitting diode display device according to an embodiment of the present disclosure and a bank trench having a second spacer.

[0055] In Figure 2 the substrate 110 may include an emission area EA and a non-emission area NEA surrounding the emission area EA. The emission areas EA may be arranged as a plurality of spaced-apart ones. The non-emission area NEA may be arranged to surround the emission areas EA.

[0056] The emission area EA is an area where light is emitted to the outside. As Figure 3 shown, the emission area EA may be an area where the bank portion 320 is not arranged.

[0057] The non-emission area NEA is an area where light is not emitted to the outside. As Figure 3As shown, the non-emitting area NEA can be an area where the embankment portion 320 is arranged.

[0058] Each pixel P in the display area AA can include a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3.

[0059] Each of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can include an emission area EA.

[0060] Each pixel P can include one sub-pixel that emits light corresponding to different colors. For example, each pixel P can include one first sub-pixel SP_1, one second sub-pixel SP_2, and one third sub-pixel SP_3 corresponding to different colors.

[0061] Alternatively, each pixel P can include multiple sub-pixels that emit light corresponding to different colors. For example, each pixel P can include one first sub-pixel SP_1, two second sub-pixels SP_2, and one third sub-pixel SP_3 corresponding to different colors.

[0062] The first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can have one of the shapes of a rectangle, a pentagon, a hexagon, an octagon, a circle, and an ellipse, and is not limited thereto.

[0063] The first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can emit light corresponding to different colors. For example, the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can emit light corresponding to at least one of red, green, and blue.

[0064] The third sub-pixel SP_3 can have a size larger than that of the first sub-pixel SP_1 and the second sub-pixel SP_2. As Figure 2 shown, the third sub-pixel SP_3 can be larger than the first sub-pixel SP_1 and larger than the second sub-pixel SP_2.

[0065] In a light-emitting diode display device, as the resolution increases, the gap distance between the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 decreases.

[0066] The LED display device 100 can have an emission layer that includes a plurality of stacked layers (emission units) and a charge generation layer between the plurality of stacked layers. The charge generation layer can adjust the charge balance between the plurality of stacked layers.

[0067] The charge generation layer may have a plurality of layers including a first charge generation layer and a second charge generation layer. Each of the first charge generation layer and the second charge generation layer may have a negative charge generation layer and a positive charge generation layer. The first charge generation layer may include an alkali metal such as lithium (Li), sodium (Na), potassium (K), and cesium (Cs), or an organic layer doped with one of magnesium (Mg), strontium (Sr), barium (Ba), and radium (Ra).

[0068] The metal in the charge generation layer may cause lateral leakage current (LLC). For example, when a sub-pixel is driven, due to the leakage current in the lateral direction between adjacent sub-pixels, the adjacent sub-pixels may emit weak light, and the image information may be distorted.

[0069] The first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 may have different driving voltages for emitting light.

[0070] For example, the driving voltage for emitting blue light may be greater than the driving voltage for emitting red light or green light.

[0071] When the third sub-pixel SP_3 is driven, the adjacent sub-pixels may be driven to emit weak light. The electrons of the third sub-pixel SP_3 are transmitted to the adjacent sub-pixels through the charge generation layer continuously arranged between the adjacent sub-pixels. As a result, the third sub-pixel SP_3 may have a state similar to that of the adjacent sub-pixels in the off state and may emit weak light. Therefore, the color purity is reduced and the color reproducibility is reduced. Specifically, weak light may appear at relatively low gray levels.

[0072] The lateral leakage current can be reduced or minimized by arranging the bank trench BT having the second spacer 340 in the non-emitting area NEA between adjacent sub-pixels.

[0073] Although in Figure 2 the second spacer 340 is arranged to surround each of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3, in another embodiment, the second spacer 340 may be arranged to surround some of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3. In some examples, the second spacer 340 may be arranged to surround only the third sub-pixel SP_3 configured to emit blue light. Since these sub-pixels have the highest driving voltage, there is a greater risk of leakage current from these sub-pixels to adjacent sub-pixels.

[0074] The emission layer 350 is disposed on the first electrode 310 and the bank trench BT having the second spacer 340. In some example embodiments, since the emission layer 350 between adjacent sub-pixels is cut by the bank trench BT having the second spacer 340, the case where electrons in the emission layer 350 of a sub-pixel are transmitted to an adjacent sub-pixel is minimized.

[0075] Since the lateral leakage current between adjacent sub-pixels is reduced or minimized, the recognition degradation between adjacent sub-pixels at a relatively low gray level is reduced and the color reproducibility is improved.

[0076] Although in Figure 2 the second spacer 340 and the bank trench BT are disposed between the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3, in another embodiment, the second spacer 340 and the bank trench BT may be omitted between adjacent sub-pixels. In other words, corresponding instances of the second spacer 340 and the bank trench BT may be disposed between a pair of adjacent sub-pixels or between multiple pairs of adjacent sub-pixels or between all pairs of adjacent sub-pixels.

[0077] The first spacer 330 may be disposed to have a predetermined gap distance from the plurality of sub-pixels SP_1, SP_2, and SP_3. For example, the first spacer 330 may have a gap distance from the plurality of sub-pixels SP_1, SP_2, and SP_3 and may be surrounded by the plurality of sub-pixels SP_1, SP_2, and SP_3. Although in Figure 2 one first spacer 330 is surrounded by four sub-pixels SP_1, SP_2, and SP_3, it is not limited thereto. The first spacer 330 may provide a gap between the sub-pixels SP_1, SP_2, and SP_3 and may be separated from the sub-pixels SP_1, SP_2, and SP_3 through the corresponding gap. As used herein, the first spacer 330 may be referred to as an upper bank spacer, and the second spacer 340 may be referred to as a middle bank spacer. It will be understood that “first” and “second” are only used as labels for referring to the spacers and should not be considered restrictive.

[0078] Sub-pixels emitting light of the same color may be symmetrically disposed with respect to the first spacer 330. For example, the second sub-pixels SP_2 may be disposed to face each other with respect to the first spacer 330. The first spacer 330 may be disposed at the central region of the sub-pixels emitting light of the same color.

[0079] The first spacer 330 may buffer the space between the substrate 110 having the emission layer 350 and the upper substrate (encapsulation layer 400) to minimize the breakage of the LED display device 100 due to an external impact.

[0080] In addition, the first spacer 330 can protect the emission layer 350. For example, the emission layer 350 can be formed using a fine metal mask (FMM), and the fine metal mask may warp due to its weight. Since the fine metal mask contacts the first spacer 330, deterioration or deformation of the bank 320 caused by contact between the fine metal mask and the bank 320 is prevented.

[0081] Figure 3 is a cross-sectional view showing a light-emitting diode display device according to an embodiment of the present disclosure, and Figures 4A to 4D is a cross-sectional view showing a manufacturing process of a light-emitting diode display device according to an embodiment of the present disclosure. Figure 3 is taken along Figure 2 the line I-I'.

[0082] In Figure 3 it, the substrate 110 supports various elements of the LED display device 100. The substrate 110 can include glass or a flexible plastic material.

[0083] For example, the substrate 110 can include one of polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone, and polycarbonate, and is not limited thereto.

[0084] When the substrate 110 includes polyimide (PI), the substrate 110 can include two PI layers or two PI layers and an inorganic layer between the two PI layers.

[0085] The buffer layer 120 is disposed over the entire substrate 110.

[0086] The buffer layer 120 can include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The buffer layer 120 can include an organic insulating material and is not limited thereto.

[0087] The buffer layer 120 can have a single layer or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx). When the buffer layer 120 has multiple layers, the silicon oxide (SiOx) layer and the silicon nitride (SiNx) layer can be alternately disposed.

[0088] Depending on the type and material of the substrate 110 and the structure and type of the thin film transistor, the buffer layer 120 can be omitted.

[0089] The thin film transistor 200 can be disposed over the buffer layer 120. The thin film transistor 200 can include a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode.

[0090] Although in Figure 3 and Figures 4A to 4DThe medium voltage driving thin film transistor is shown as thin film transistor 200, but the LED display device 100 may also include other thin film transistors, such as switching thin film transistors. Although in Figure 3 and Figures 4A to 4D the thin film transistor 200 has a top gate structure, the thin film transistor may have other structures, such as a bottom gate structure.

[0091] The semiconductor pattern 210 of the thin film transistor 200 is disposed on the buffer layer 120.

[0092] The semiconductor pattern 210 may include a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material may include low temperature polycrystalline silicon, and is not limited thereto. When the semiconductor pattern 210 includes a polycrystalline semiconductor material, power consumption is reduced and reliability is improved.

[0093] The semiconductor pattern 210 may include an oxide semiconductor material. For example, the oxide semiconductor material may include one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), and is not limited thereto. When the semiconductor pattern 210 includes an oxide semiconductor material, the effect of blocking leakage current is improved, and the brightness change of the sub-pixel under low frequency driving is minimized.

[0094] When the semiconductor pattern 210 includes a polycrystalline semiconductor material or an oxide semiconductor material, a part of the semiconductor pattern 210 may include a conductive region.

[0095] The semiconductor pattern 210 may include amorphous silicon (a-Si) or an organic semiconductor material such as pentacene, and is not limited thereto.

[0096] The first insulating layer 130 is disposed on the semiconductor pattern 210.

[0097] The first insulating layer 130 may be disposed between the semiconductor pattern 210 and the gate electrode 230 to insulate the semiconductor pattern 210 from the gate electrode 230.

[0098] The first insulating layer 130 may include an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx). The first insulating layer 130 may include an organic insulating material, and is not limited thereto.

[0099] The first insulating layer 130 may have contact holes to electrically connect the source electrode 250 and the drain electrode 270 to the semiconductor pattern 210.

[0100] The gate electrode 230 of the thin film transistor 200 is disposed on the first insulating layer 130 to overlap with the semiconductor pattern 210.

[0101] The gate electrode 230 may include one or an alloy of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), and may have a single layer or multiple layers thereof. However, it is not limited thereto.

[0102] The second insulating layer 140 is disposed on the gate electrode 230.

[0103] The second insulating layer 140 is disposed between the gate electrode 230 and the source electrode 250 and between the gate electrode 230 and the drain electrode 270 to insulate the gate electrode 230 from the source electrode 250 and the drain electrode 270.

[0104] The second insulating layer 140 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The second insulating layer 140 may include an organic insulating material and is not limited thereto.

[0105] The second insulating layer 140 may have contact holes to electrically connect the source electrode 250 and the drain electrode 270 to the semiconductor pattern 210.

[0106] The source electrode 250 and the drain electrode 270 are disposed on the second insulating layer 140.

[0107] The source electrode 250 and the drain electrode 270 may be connected to the semiconductor pattern 210 through the contact holes in the first insulating layer 130 and the second insulating layer 140.

[0108] The source electrode 250 and the drain electrode 270 may include one or an alloy of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), and may have a single layer or multiple layers thereof. However, it is not limited thereto.

[0109] For example, the source electrode 250 and the drain electrode 270 may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), and is not limited thereto.

[0110] The passivation layer 150 is disposed on the source electrode 250 and the drain electrode 270.

[0111] The passivation layer 150 may protect the thin film transistor 200. The passivation layer 150 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The passivation layer 150 may include an organic insulating material and is not limited thereto.

[0112] The passivation layer 150 may have contact holes to electrically connect the thin film transistor 200 and the connection electrode 170.

[0113] According to the structure and type of the thin film transistor 200, the passivation layer 150 can be omitted.

[0114] The planarization layer 160 can be disposed on the passivation layer 150 or the thin film transistor 200.

[0115] The planarization layer 160 can protect the thin film transistor 200 and can reduce or planarize the step difference caused by various patterns.

[0116] The planarization layer 160 can include an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, and is not limited thereto.

[0117] Based on the arrangement of the electrodes, the planarization layer 160 can have a single layer or multiple layers.

[0118] In the LED display device 100, since the number of signal lines increases as the resolution increases, the signal lines cannot be formed as a single layer with a predetermined gap distance. As a result, the signal lines can have multiple layers for sufficient margin. In addition, when the planarization layer 160 has multiple dielectric materials, the planarization layer 160 can be used as a capacitor between metal layers.

[0119] The planarization layer 160 can include a first planarization layer 161 and a second planarization layer 162.

[0120] For example, contact holes can be formed in the first planarization layer 161, and the connection electrode 170 can be disposed in the contact holes of the first planarization layer 161. The second planarization layer 162 having contact holes can be disposed on the first planarization layer 161 and the connection electrode 170. The first electrode (e.g., anode) 310 can be disposed in the contact holes of the second planarization layer 162. As a result, the thin film transistor 200 and the first electrode 310 can be electrically connected to each other through the connection electrode 170.

[0121] One end of the connection electrode 170 can be connected to the thin film transistor, and the other end of the connection electrode 170 can be connected to the first electrode 310.

[0122] The connection electrode 170 can include one or an alloy of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and transparent conductive oxide (TCO), and can have a single layer or multiple layers thereof. However, it is not limited thereto.

[0123] Based on the structure and type of the LED display device 100, the connection electrode 170 can be omitted.

[0124] The first electrode 310 may be disposed on the planarization layer 160. The first electrode 310 may be disposed in a part of the non-emission region NEA and the emission region EA.

[0125] When the LED display device 100 has a top emission type, the first electrode 310 may be used as a reflective electrode including an opaque conductive material. The first electrode 310 may include one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr), or an alloy thereof. For example, the first electrode 310 may have a three-layer structure of silver (Ag) / lead (Pb) / copper (Cu), and is not limited thereto. Alternatively, the first electrode 310 may also include a transparent conductive material having a relatively high work function, such as indium tin oxide (ITO).

[0126] When the LED display device 100 has a bottom emission type, the first electrode 310 may be used as a transparent electrode of a transparent conductive material. The first electrode 310 may include one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0127] The bank 320 may be disposed on the first electrode 310 and the planarization layer 160.

[0128] The bank 320 may divide the plurality of sub-pixels SP to minimize the light blur effect or light blur problem and prevent color mixing at various viewing angles.

[0129] The bank 320 may define the emission region EA and the non-emission region NEA, and may be disposed in the non-emission region NEA.

[0130] The bank 320 may have a bank hole BH exposing the first electrode 310, and may have a bank trench BT in the non-emission region NEA between adjacent sub-pixels.

[0131] The bank 320 may include at least one of an inorganic insulating material (such as silicon nitride (SiNx) and silicon oxide (SiOx)), an organic insulating material (such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin), and a photoresist including a black pigment), and is not limited thereto.

[0132] The bank 320 may be transparent, or may be black or colored. The bank 320 may be disposed to cover the end portion of the first electrode 310.

[0133] The bank trench BT may be formed by removing a part of the bank 320. When the bank 320 is completely removed in the region of the bank trench BT, the bank trench BT may expose the planarization layer 160. Although Figure 3The embankment portion 320 is completely removed in the area of the embankment trench BT, but in another embodiment, the embankment portion 320 may be partially removed. The thickness of the embankment portion 320 in the area of the embankment trench BT may be one-half to one-third of the thickness of the embankment portion 320 in other areas.

[0134] The embankment trench BT may overlap with the first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C.

[0135] Reference will be made to Figures 4A to 4D Describe the manufacturing process of the embankment trench BT.

[0136] At least one first spacer 330 may be disposed on the embankment portion 320. The first spacer 330 may include the same material as the embankment portion 320. The first spacer 330 may be formed simultaneously with the embankment portion 320, or may be formed by a process different from that of the embankment portion 320.

[0137] The thickness of the first spacer 330 may be greater than the thickness of the embankment portion 320. For example, the thickness of the first spacer 330 may be in the range of about 1 μm to about 2 μm.

[0138] The second spacer 340 may be disposed on the embankment portion 320 and the planarization layer 160. At least a part of the second spacer 340 may be disposed on at least a part of the embankment portion 320. The edge of the second spacer 340 may be disposed on the corresponding edge of the embankment portion 320, while the center of the second spacer 340 may not be disposed on the embankment portion 320.

[0139] In some exemplary embodiments, since the emission layer 350 or the second electrode 360 is cut by the second spacer 340, the movement of electrons in the emission layer 350 to adjacent sub-pixels is prevented. As a result, even when the gap distance between adjacent sub-pixels is reduced, the lateral leakage current can be minimized due to the second spacer 340.

[0140] The second spacer 340 may be disposed in the embankment trench BT, or may cover a part of the sidewall of the embankment trench BT.

[0141] The second spacer 340 may have an inverted conical shape. For example, the second spacer 340 may have a bottom surface and a top surface, and the size of the top surface of the second spacer 340 may be larger than the size of the bottom surface of the second spacer 340.

[0142] The second spacer 340 may include the same material as the embankment portion 320 or the first spacer 330. Reference will be made to Figures 4A to 4D Describe the manufacturing process of the second spacer 340.

[0143] The thickness of the second spacer 340 may be greater than the thickness of the bank 320.

[0144] The second height or vertical distance H2 from the substrate 110 to the second spacer 340 may be less than the first height or vertical distance H1 from the substrate 110 to the first spacer 330. Since the second spacer 340 is disposed in the bank trench BT formed by partially removing the bank 320, the height or vertical distance of the top of the second spacer 340 relative to the substrate 110 may be less than the height or vertical distance of the top of the first spacer 330 on the bank 320 relative to the substrate 110. The height and vertical distance herein refer to the direction / azimuth perpendicular to the display surface of the display device (i.e., perpendicular to the substrate 110). Alternatively or additionally, as Figure 3 depicted, the fourth height H4 of the second spacer 340 may be less than the third height H3 of the first spacer 330.

[0145] When the second height or vertical distance H2 of the second spacer 340 relative to the substrate 110 is the same as or similar to the first height or vertical distance H1 of the top of the first spacer 330 relative to the substrate 110, the second spacer 340 may contact the fine metal mask (FMM) for forming the emission layer 350, thereby deforming or being damaged. In an embodiment of the present disclosure, since the second spacer 340 is disposed in the bank trench BT, the first spacer 330 rather than the second spacer 340 contacts the fine metal mask, and deformation or damage of the second spacer 340 is prevented.

[0146] The second spacer 340 may include at least three spacer patterns. For example, the second spacer may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c.

[0147] The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be arranged to be separated from each other. The spacer pattern holes PH may be arranged between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, the first spacer pattern hole PH may be arranged between the first spacer pattern 340a and the second spacer pattern 340b, and the second spacer pattern hole PH may be arranged between the spacer pattern 340b and the third spacer pattern 340c. In some examples, the second spacer 340 may include a first spacer pattern, a second spacer pattern, and a third spacer pattern, with a first spacer pattern hole PH between the first spacer pattern and the second spacer pattern, and a second spacer pattern hole PH between the second spacer pattern and the third spacer pattern. The second spacer may include at least a first spacer pattern and a second spacer pattern with spacer pattern holes therebetween. Increasing the number of spacer patterns and spacer pattern holes may advantageously further reduce the leakage current between sub-pixels. The second spacer including the spacer pattern may prevent the emission layer 350 (and the second electrode 360) from forming or depositing on the side slope of the second spacer. This is because the spacer pattern forms a protrusion, which means these side slopes are shielded to prevent deposition from above. This enables the formation of discontinuities / cuts / gaps in the emission layer 350, thereby reducing the leakage current between sub-pixels.

[0148] At least one of the spacer patterns may be arranged to be separated from the bank 320. For example, the spacer pattern 340b of the second spacer 340 may be arranged to be separated from the bank 320. The second spacer pattern 340b may be wider than the first spacer pattern 340a and wider than the third spacer pattern 340c.

[0149] At least one of the spacer patterns may be arranged to cover a part of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be arranged to cover a part of the bank 320.

[0150] Although in Figure 3 the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 cover a part of the bank 320, in another embodiment, the second spacer 340 may include a plurality of second spacer patterns 340b separated from the bank 320 in the bank trench BT.

[0151] Although in Figure 3 the second spacer 340 includes three spacer patterns, the number of spacer patterns may be changed according to the design and is not limited thereto.

[0152] The emission layer 350 may be disposed on the first electrode 310, the bank 320, the first spacer 330, the second spacer 340, and the planarization layer 160.

[0153] In some example embodiments, since the emission layer 350 is cut by the second spacer 340 and the second spacer hole PH in the non-emission area NEA, electrons in the emission layer 350 are prevented from moving to adjacent sub-pixels. As a result, even when the gap distance between adjacent sub-pixels is reduced, the lateral leakage current can be minimized. The emission layer 350 may not form a continuous layer, but may include a plurality of cuts, gaps, or discontinuities that separate corresponding portions of the emission layer 350. This may be due to the second spacer 340 in the bank trench BT. Specifically, the emission layer 350 may include a discontinuity between a portion thereof disposed on the bank 320 and a portion thereof disposed on the first spacer pattern 340a, may include a discontinuity between a portion thereof disposed on the first spacer pattern 340a and a portion thereof disposed on the second spacer pattern 340b (i.e., due to the first spacer pattern hole PH), may include a discontinuity between a portion thereof disposed on the second spacer pattern 340b and a portion thereof disposed on the third spacer pattern 340c (i.e., due to the second spacer pattern hole PH), and / or may include a discontinuity between a portion thereof disposed on the third spacer pattern 340c and a portion thereof disposed on the bank 320. As used herein, a cut in a layer may refer to a cut that passes through the layer, i.e., a complete cut through the layer, or a surface cut in the layer, i.e., a cut that partially passes through the layer (i.e., a thickness reduction). In some examples, the thickness of the emission layer 350 may be reduced in the region of the second spacer 340. For example, the second spacer 340 may include one or more side slopes on which the emission layer 350 is thinner, irregular, or discontinuous. Thus, the transmission of leakage current through the emission region in this area can be reduced. In other words, in the region of the second spacer 340, the deposition of the emission layer 350 may be reduced such that, in use, the transmission of leakage current in this area is reduced. In the region of the second spacer 340, the emission layer 350 may be discontinuous or may be non-uniform.

[0154] A portion of the emission layer 350 may be disposed on the planarization layer 160, and a portion of the emission layer 350 may be disposed in the bank trench BT. A portion of the emission layer 350 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340, i.e., disposed in the spacer pattern hole PH.

[0155] The emission layer 350 may include a plurality of stacked layers (emission units). For example, the emission layer 350 may include ( Figure 5the first stack 351 and the second stack 353 and ( Figure 5 the charge generation layer 352). Reference will be made to Figure 5 describe the structure of the emission layer 350.

[0156] The second electrode (e.g., the cathode) 360 may be disposed on the emission layer 350.

[0157] The second electrode 360 may be cut by the second spacer 340 in the non-emission area NEA. The second electrode 360 may not form a continuous layer, but may include a plurality of cuts, gaps, or discontinuities that separate the corresponding portions of the second electrode 360 and correspond to the cuts / gaps / discontinuities of the emission layer 350.

[0158] A portion of the second electrode 360 may be disposed in the bank trench BT, and a portion of the second electrode 360 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340, i.e., disposed in the spacer pattern holes.

[0159] For example, each of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c has an inverted conical shape, wherein the side surfaces of each spacer pattern 340a, 340b, and 340c form an acute angle with the top surface of the planarization layer 162. As a result, the emission layer 350 and the second electrode 360 may be cut between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c, and the residual layer RL having the emission layer 350 and the second electrode 360 may be disposed on the planarization layer 162 between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, the term "residual layer" RL may be used to refer to the emission layer 350 and the second electrode 360 disposed in the spacer pattern holes PH of the second spacer 340. The portion of the emission layer 350 included in the residual layer RL may be separated from the portion of the emission layer 350 disposed on the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. The portion of the second electrode 360 included in the residual layer RL may be separated from the portion of the second electrode 360 disposed on the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. The portion of the emission layer 350 disposed on one or more of the spacer patterns 340a, 340b, 340c may be separated from the portion of the emission layer 350 disposed on the adjacent bank 320. The portion of the second electrode 360 disposed on one or more of the spacer patterns 340a, 340b, 340c may be separated from the portion of the second electrode 360 disposed on the adjacent bank 320.

[0160] The second electrode 360 can supply electrons to the emission layer 350 and can include a conductive material having a relatively low work function.

[0161] When the LED display device 100 has a top emission type, the second electrode 360 can serve as a transparent electrode including a transparent conductive material. The second electrode 360 can include one of indium tin oxide (ITO) and indium zinc (IZO) oxide.

[0162] Alternatively, the second electrode 360 can include a translucent conductive material. For example, the second electrode 360 can include at least one of alloys such as lithium fluoride / aluminum (LiF / Al), cesium fluoride / aluminum (CsF / Al), magnesium: silver (Mg:Ag), calcium / silver (Ca / Ag), lithium fluoride / magnesium: silver (LiF / Mg:Ag), lithium fluoride / calcium / silver (LiF / Ca / Ag), and lithium fluoride / calcium: silver (LiF / Ca:Ag).

[0163] When the LED display device 100 has a bottom emission type, the second electrode 360 can serve as a reflective electrode including an opaque conductive material. For example, the second electrode 360 can include one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr), or an alloy thereof.

[0164] Although not shown, a cover layer (CPL) can be disposed on the second electrode 360.

[0165] The cover layer can protect the second electrode 360 and can improve the light extraction effect of the emission layer 350. The cover layer can have a single layer or multiple layers and is not limited thereto.

[0166] Based on the structure and type of the LED display device 100, the cover layer can be omitted.

[0167] The encapsulation layer 400 can be disposed on the second electrode 360 or the cover layer. The encapsulation layer 400 can protect the first electrode 310, the emission layer 350, and the second electrode 360 from external moisture, oxygen, or particles. For example, the encapsulation layer 400 can block the penetration of oxygen and moisture from the outside to prevent the oxidation of the materials of the first electrode 310, the second electrode 360, and the emission layer 350.

[0168] The encapsulation layer 400 can include a transparent material such that the light emitted from the emission layer 350 can pass through the encapsulation layer 400.

[0169] The encapsulation layer 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 for blocking the penetration of moisture or oxygen. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may have a structure of sequential lamination.

[0170] The first encapsulation layer 410 and the third encapsulation layer 430 may include inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and aluminum oxide (AlyOz), and are not limited thereto. The first encapsulation layer 410 and the third encapsulation layer 430 may be formed by a vacuum film forming method such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), and are not limited thereto.

[0171] Each of the first encapsulation layer 410 and the third encapsulation layer 430 may have a multi-layer including at least two layers. For example, the first encapsulation layer 410 may have three layers of silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx), and is not limited thereto. Alternatively, the first encapsulation layer 410 may have four layers of silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx) / silicon oxide (SiOx), and is not limited thereto.

[0172] The second encapsulation layer 420 may cover the particles generated in the manufacturing process. The second encapsulation layer 420 may planarize the surface of the first encapsulation layer 410. For example, the second encapsulation layer 420 may be referred to as a particle covering layer.

[0173] The second encapsulation layer 420 may include an organic material of a polymer such as silicon oxycarbide (SiOCz), epoxy resin, polyimide, polyethylene, and acrylate, and is not limited thereto.

[0174] The second encapsulation layer 420 may include a thermally curable material that can be cured by heat or a photocurable material that can be cured by light.

[0175] The touch sensing layer 500 may be disposed on the encapsulation layer 400.

[0176] The touch sensing layer 500 may include a first touch electrode 540_R, a first touch connection electrode 520, a second touch electrode, and a second touch connection electrode 540_C.

[0177] A part of the first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may be disposed to overlap with the second spacer 340 and / or the bank trench BT.

[0178] The first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may have a mesh pattern in which metal lines each having a relatively narrow width cross each other. The mesh pattern may have a rhombus shape. Alternatively, the mesh pattern may have one of a rectangle, a pentagon, a hexagon, a circle, and an ellipse, and is not limited thereto.

[0179] The first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may include an opaque conductive material having a relatively low resistance. For example, the first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may include one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and may have a single layer or multiple layers thereof. However, it is not limited thereto.

[0180] For example, the first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), and is not limited thereto.

[0181] The first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may include the same material as the source electrode 250 and the drain electrode 270.

[0182] The touch buffer layer 510 may be disposed on the encapsulation layer 400. The touch buffer layer 510 may prevent a solution (developer or etchant) used in the manufacturing process of the touch sensing layer 500 or external moisture from penetrating into the emission layer 350. In addition, due to the touch buffer layer 510, multiple touch sensing metals on the touch buffer layer 510 can be prevented from being cut by an external impact, and interference signals generated when the touch sensing layer 500 is driven can be blocked.

[0183] The touch buffer layer 510 may include at least one of an inorganic insulating material (such as silicon nitride (SiNx) and silicon oxide (SiOx)) and an organic insulating material (such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin), and is not limited thereto.

[0184] The first touch connection electrode 520 may be disposed on the touch buffer layer 510.

[0185] For example, the first touch connection electrode 520 may be disposed between first touch electrodes 540_R adjacent in a first direction (X direction). The first touch connection electrode 520 may electrically connect a plurality of first touch electrodes 540_R spaced apart from and adjacent to each other in the first direction (X direction), and is not limited thereto.

[0186] The first touch connection electrode 520 may be disposed to overlap with a second touch connection electrode 540_C that connects second touch electrodes adjacent in a second direction (Y direction). Since the first touch connection electrode 520 and the second touch connection electrode 540_C are disposed in different layers, the first touch connection electrode 520 and the second touch connection electrode 540_C may be electrically insulated.

[0187] The touch insulating layer 530 may be disposed on the touch buffer layer 510 and the first touch connection electrode 520.

[0188] The touch insulating layer 530 may have contact holes for electrically connecting the first touch electrode 540_R and the first touch connection electrode 520.

[0189] The touch insulating layer 530 may electrically insulate the first touch connection electrode 520 and the second touch connection electrode 540_C.

[0190] The touch insulating layer 530 may have a single layer or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx), and is not limited thereto.

[0191] The first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C may be disposed on the touch insulating layer 530.

[0192] The first touch electrode 540_R and the second touch electrode may be disposed to be spaced apart from each other. A plurality of first touch electrodes 540_R may be spaced apart from each other along the first direction (X direction). The first touch electrodes 540_R adjacent in the first direction (X direction) may be connected to the first touch connection electrode 520 between the first touch electrodes 540_R. For example, adjacent first touch electrodes 540_R may be connected to the first touch connection electrode 520 through contact holes in the touch insulating layer 530.

[0193] The second touch electrodes adjacent in the second direction (Y direction) may be connected to each other through the second touch connection electrode 540_C. The second touch electrode and the second touch connection electrode 540_C may be formed in the same layer. For example, the second touch connection electrode 540_C may be disposed in the same layer as the second touch electrode and between the second touch electrodes. The second touch connection electrode 540_C may be formed to extend from the second touch electrode.

[0194] The first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C can be formed by the same process.

[0195] The touch planarization layer 550 can be disposed on the first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C.

[0196] The touch driving circuit can receive a touch sensing signal from the first touch electrode 540_R and can send a touch driving signal to the second touch electrode. The touch driving circuit can use the mutual capacitance between the first touch electrode 540_R and the second touch electrode to detect a user's touch. For example, when a touch occurs in the LED display device 100, the capacitance between the first touch electrode 540_R and the second touch electrode can change. The touch driving circuit can detect the change in capacitance to calculate the touch coordinates.

[0197] The manufacturing process of the bank trench BT and the second spacer 340 will be described below.

[0198] In Figure 4A the first electrode 310 is formed on the substrate 110 having the thin film transistor 200 and in the emission region EA.

[0199] In Figure 4B the bank 320 and the first spacer 330 are formed in the non-emission region NEA of the substrate 110 having the first electrode 310.

[0200] The bank 320 can include a bank hole BH that exposes the first electrode 310 in the emission region EA. The bank hole BH can be formed by removing a part of the bank 320.

[0201] At least one first spacer 330 can be disposed on the bank 320.

[0202] Although the bank 320 and the first spacer 330 are formed by the same process using a halftone mask in Figure 4B in another embodiment, the bank 320 and the first spacer 330 can be formed by different processes.

[0203] In Figure 4C the bank trench BT is formed between adjacent sub-pixels. The bank trench BT can be formed by etching a part of the bank 320. The planarization layer 160 can be exposed through the bank trench BT.

[0204] Although in Figure 4CIn the case where the entire embankment 320 is removed in the region where the embankment trench BT is arranged, but in another embodiment, a part of the embankment 320 may be removed. For example, by removing a part of the embankment 320 instead of the entire embankment 320, a part of the embankment 320 may be retained on the planarization layer 160 in the region where the embankment trench BT is arranged.

[0205] In Figure 4D the second spacer 340 may be formed in the embankment trench BT.

[0206] The second spacer 340 may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c. The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be arranged to be spaced apart from each other. Spacer pattern holes PH may be arranged between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c.

[0207] At least one of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340 may cover a part of the embankment 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be arranged to be spaced apart from the embankment 320.

[0208] Although the embankment hole BH, the embankment trench BT, the first spacer 330, and the second spacer 340 are formed by different processes in Figures 4A to 4D in another embodiment, the embankment hole BH and the embankment trench BT may be formed simultaneously, and then the first spacer 330 and the second spacer 340 may be formed simultaneously.

[0209] Figure 5 is a view showing an emission layer of a light-emitting diode display device according to an embodiment of the present disclosure.

[0210] Although in Figure 5 the emission layer includes two stacks (emission units) and one charge generation layer, in another embodiment, the emission layer may include three or more stacks and two or more charge generation layers.

[0211] In Figure 5 the emission layer 350 may include a plurality of stacks (emission units). For example, the emission layer 350 may include a first stack 351, a second stack 353, and a charge generation layer 352 between the first stack 351 and the second stack 353.

[0212] The first electrode (e.g., anode) 310, the first stack 351, the charge generation layer 352, the second stack 353, and the second electrode (e.g., cathode) 360 may be sequentially disposed on a substrate 110 having a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3.

[0213] The first stack 351 may include a hole injection layer 351-A, a first hole transport layer 351-B, a first emission material layer 351-C, and a first electron transport layer 351-D.

[0214] The second stack 353 may include a second hole transport layer 353-A, a second emission material layer 353-B, a second electron transport layer 353-C, and an electron injection layer 353-D.

[0215] The charge generation layer 352 may include a negative (N) type charge generation layer n-CGL that assists electron injection into the first stack 351 and a positive (P) type charge generation layer p-CGL that assists hole injection into the second stack 353.

[0216] Although not shown, an electron blocking layer may be disposed between the first hole injection layer 351-A and the first emission material layer 351-C, and a hole blocking layer may be disposed between the first emission material layer 351-C and the charge generation layer 352. In addition, an electron blocking layer may be disposed between the charge generation layer 352 and the second emission material layer 353-B, and a hole blocking layer may be disposed between the second emission material layer 353-B and the electron injection layer 353-D.

[0217] A part of the layer of the emission layer 350 may be cut between adjacent sub-pixels through a bank trench BT including a second spacer 340 below the emission layer 350. As a result, electrons in the emission layer 350 are prevented from moving to adjacent sub-pixels. Specifically, recognition degradation between adjacent sub-pixels at relatively low gray levels is reduced, and color reproducibility is improved.

[0218] The first emission material layer 351-C and the second emission material layer 353-B may be disposed corresponding to each sub-pixel and spaced apart from each other. For example, the first emission material layer 351-C and the second emission material layer 353-B may be disposed to overlap with the end of the bank 320 and the bank hole BH.

[0219] The hole injection layer 351-A may assist in the injection of holes. The hole injection layer 351-A may include at least one of HATCN (1,4,5,8,9,11-hexaazatriphenylene-hexanitrile), CuPc (copper phthalocyanine), PEDOT (poly(3,4)-ethylenedioxythiophene), PANI (polyaniline), and NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), and is not limited thereto.

[0220] The first hole transport layer 351-B and the second hole transport layer 353-A can assist in the transport of holes. The first hole transport layer 351-B and the second hole transport layer 353-A can include at least one of NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), s-TAD, and MTDATA (4,4',4”-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine), and is not limited thereto.

[0221] The first electron transport layer 351-D and the second electron transport layer 353-C can assist in the transport of electrons. The first electron transport layer 351-D and the second electron transport layer 353-C can include at least one of Alq3 (tris(8-hydroxyquinoline)aluminum), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ, spiro-PBD, BAlq, and SAlq, and is not limited thereto.

[0222] The electron injection layer 353-D assists in the injection of electrons. The electron injection layer can include at least one of Alq3 (tris(8-hydroxyquinoline)aluminum), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ, spiro-PBD, BAlq, and SAlq, and is not limited thereto.

[0223] The first emissive material layer 351-C and the second emissive material layer 353-B can be disposed in the bank hole BH and spaced apart from each other between adjacent sub-pixels. For example, the first emissive material layer 351-C and the second emissive material layer 353-B can be deposited in each sub-pixel using a fine metal mask (FMM).

[0224] The first emissive material layer 351-C and the second emissive material layer 353-B can overlap each other and can emit light corresponding to the same color. The first emissive material layer 351-C and the second emissive material layer 353-B can emit light of the same wavelength, and is not limited thereto.

[0225] The first emissive material layer 351-C and the second emissive material layer 353-B can include emissive materials that emit red light, green light, and blue light, and the emissive materials can be formed using phosphorescent materials or fluorescent materials.

[0226] For example, the first red emission material layer 351R and the second red emission material layer 353R in the first sub-pixel SP_1 may be formed of a phosphorescent material, or may be formed of a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene. The above phosphorescent material includes a host material of CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)) and a doping material of one of PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetonate iridium), PQIr(tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). However, it is not limited thereto.

[0227] For example, the first green emission material layer 351G and the second green emission material layer 353G in the second sub-pixel SP_2 may be formed of a phosphorescent material including a host material of CBP or mCP and a doping material of an Ir complex including Ir(ppy)3 (fac-tris(2-phenylpyridine)iridium), or may be formed of a fluorescent material including Alq3 (tris(8-hydroxyquinoline)aluminum). However, it is not limited thereto.

[0228] For example, the first blue emission material layer 351B and the second blue emission material layer 353B in the third sub-pixel SP_3 may be formed of a phosphorescent material including a host material of CBP or mCP and a doping material of (4,6-F2ppy)2Irpic, or may be formed of a fluorescent material including one of spiro-DPVBi, spiro-6P, distyryl benzene (DSB), distyryl arylene (DSA), PFO polymer, and PPV polymer. However, it is not limited thereto.

[0229] The first emission material layer 351-C and the second emission material layer 353-B may include an auxiliary emission material layer. For example, the auxiliary emission material layer may be disposed above or below the first emission material layer 351-C and the second emission material layer 353-B. The auxiliary emission material layer may emit light of the same color or a different color from the first emission material layer 351-C and the second emission material layer 353-B.

[0230] The N-type charge generation layer n-CGL may be formed of one of an alkali metal, an alkali metal compound, an organic material, and an alloy thereof for injecting electrons. For example, the N-type charge generation layer n-CGL may have a mixed layer of an N-type material such as an anthracene derivative doped with lithium (Li) or cesium (Cs), and is not limited thereto.

[0231] The p-type charge generation layer p-CGL can be formed of an organic material for a hole injection layer. For example, the p-type charge generation layer p-CGL can have a single layer of a p-type material such as HATCN or F4-TCNQ, and is not limited thereto.

[0232] Each of the first stack 351, the second stack 353, and the charge generation layer 352 may have multiple layers or may be omitted.

[0233] Therefore, in the LED display device according to an embodiment of the present disclosure, since the bank trench having at least one second spacer is disposed between adjacent sub-pixels, the lateral leakage current that increases with the gap distance between adjacent sub-pixels is reduced or blocked.

[0234] In some exemplary embodiments, since the emission layer is cut by the bank trench having at least one second spacer between adjacent sub-pixels, electrons in the emission layer are prevented from moving to adjacent sub-pixels.

[0235] Since the lateral leakage current between adjacent sub-pixels is reduced or blocked, the recognition degradation between adjacent sub-pixels at a relatively low gray level is reduced, and the color reproducibility is improved.

[0236] Exemplary embodiments of the present disclosure may also be described as follows:

[0237] According to an exemplary embodiment of the present disclosure, a display device may include: a substrate having a first sub-pixel and a second sub-pixel each including a corresponding emission region; and a non-emission region surrounding the emission region; a corresponding first electrode in each of the first sub-pixel and the second sub-pixel; a bank having a corresponding bank hole in the emission region and a bank trench in the non-emission region; a first spacer on the bank; a second spacer in the bank trench; an emission layer on the first electrode and the bank trench, and including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and a second electrode on the emission layer.

[0238] In some exemplary embodiments, the second spacer may have an inverted conical shape.

[0239] In some exemplary embodiments, the height of the top of the second spacer with respect to the substrate may be different from the height of the top of the first spacer with respect to the substrate.

[0240] In some exemplary embodiments, the height of the top of the second spacer with respect to the substrate may be less than the height of the top of the first spacer with respect to the substrate.

[0241] In some exemplary embodiments, the thickness of the second spacer may be greater than the thickness of the bank.

[0242] In some exemplary embodiments, the second spacer may include at least a first spacer pattern and a second spacer pattern, with a spacer pattern hole therebetween.

[0243] In some exemplary embodiments, the second spacer may include at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, where there is a first spacer pattern hole between the first spacer pattern and the second spacer pattern, and a second spacer pattern hole between the second spacer pattern and the third spacer pattern.

[0244] In some exemplary embodiments, at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern covers a portion of the bank.

[0245] In some exemplary embodiments, the display device may further include: thin film transistors on a substrate; and a planarization layer on the thin film transistors.

[0246] In some exemplary embodiments, the bank trench may expose the planarization layer.

[0247] In some exemplary embodiments, the second spacer may be disposed on the planarization layer.

[0248] In some exemplary embodiments, the emission layer may be disposed on the planarization layer.

[0249] In some exemplary embodiments, the emission layer may include a cut formed by the second spacer in a non-emission region.

[0250] In some exemplary embodiments, at least one charge generation layer may include a first charge generation layer and a second charge generation layer.

[0251] In some exemplary embodiments, each of a plurality of stacked layers may include an emission material layer.

[0252] In some exemplary embodiments, the display device may further include: a encapsulation layer on the second electrode; and a touch sensing layer on the encapsulation layer.

[0253] In some exemplary embodiments, the touch sensing layer may include a first touch electrode and a second touch electrode overlapping the second spacer.

[0254] In some exemplary embodiments, the height of the second spacer may be less than the height of the first spacer.

[0255] According to another exemplary embodiment of the present disclosure, a display device may include: a substrate including a display area and a non-display area adjacent to the display area, the display area having a plurality of sub-pixels and non-emission areas between the plurality of sub-pixels; corresponding first electrodes in each of the plurality of sub-pixels; a bank dividing the plurality of sub-pixels; an emission layer on the first electrodes; a second electrode on the emission layer; and a notch in / between the emission layers of two adjacent sub-pixels among the plurality of sub-pixels.

[0256] In some exemplary embodiments, the bank may include a plurality of bank holes respectively corresponding to the plurality of sub-pixels and a bank groove corresponding to the non-emission area.

[0257] In some exemplary embodiments, the display device may further include first spacers on the bank.

[0258] In some exemplary embodiments, the notch may be formed by second spacers in the bank groove.

[0259] In some exemplary embodiments, the second spacers may include the same material as the bank.

[0260] In some exemplary embodiments, the height of the second spacers may be less than the height of the first spacers.

[0261] According to yet another exemplary embodiment of the present disclosure, a method for manufacturing a display device may include: forming a plurality of first electrodes spaced apart from each other on a substrate; forming a bank on the substrate on which the plurality of first electrodes are formed; forming bank holes in the bank such that portions of each of the plurality of first electrodes are exposed, and forming a bank groove in the bank between adjacent first electrodes among the plurality of first electrodes; forming second spacers in the bank groove; forming an emission layer on the second spacers and the bank groove, the emission layer including a plurality of stacked layers and at least one charge generation layer between the plurality of stacked layers; and forming a second electrode on the emission layer.

[0262] In some exemplary embodiments, the method may further include forming first spacers on the bank simultaneously with the second spacers.

[0263] Although the cutting portion has been mainly described herein with reference to exemplary embodiments in which the cutting portion includes second spacers in the bank groove, the cutting portion may have other forms according to actual needs.

[0264] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate having: a first sub-pixel and a second sub-pixel each including a corresponding emission region; and a non-emission region surrounding the emission region; a corresponding first electrode in each of the first sub-pixel and the second sub-pixel; a bank having a corresponding bank hole in each of the emission regions and a bank trench in the non-emission region; a first spacer on the bank; a second spacer in the bank trench; an emission layer on the first electrode and the bank trench, and including a plurality of stacked layers and at least one charge generation layer between the plurality of stacked layers; and a second electrode on the emission layer.

2. The display device according to claim 1, wherein, the second spacer has an inverted conical shape.

3. The display device according to claim 1, wherein, the height of the top of the second spacer relative to the substrate is different from the height of the top of the first spacer relative to the substrate.

4. The display device according to claim 1, wherein, the height of the top of the second spacer relative to the substrate is less than the height of the top of the first spacer relative to the substrate.

5. The display device according to claim 1, wherein, the thickness of the second spacer is greater than the thickness of the bank.

6. The display device according to claim 1, wherein, the second spacer includes at least a first spacer pattern and a second spacer pattern, and there is a spacer pattern hole between the first spacer pattern and the second spacer pattern.

7. The display device according to claim 1, wherein, the second spacer includes at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, wherein there is a first spacer pattern hole between the first spacer pattern and the second spacer pattern, and there is a second spacer pattern hole between the second spacer pattern and the third spacer pattern.

8. The display device according to claim 7, wherein, at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern covers a part of the bank.

9. The display device according to claim 1, further comprising: a thin film transistor on the substrate; and a planarization layer on the thin film transistor.

10. The display device according to claim 9, wherein, the bank trench exposes the planarization layer.

11. The display device according to claim 9, wherein, the second spacer is disposed on the planarization layer.

12. The display device according to claim 9, wherein, the emission layer is disposed on the planarization layer.

13. The display device according to claim 1, wherein, the emission layer includes a cut formed through the second spacer in the non-emission region.

14. The display device according to claim 1, wherein, the at least one charge generation layer includes a first charge generation layer and a second charge generation layer.

15. The display device according to claim 1, wherein, Each of the plurality of stacked layers includes an emissive material layer.

16. The display device according to claim 1, further comprising: a encapsulation layer on the second electrode; and a touch sensing layer on the encapsulation layer.

17. The display device according to claim 16, wherein the touch sensing layer includes a first touch electrode and a second touch electrode that overlap with the second spacer.

18. The display device according to any one of the preceding claims, wherein the height of the second spacer is less than the height of the first spacer.

19. A display device, comprising: a substrate including: a display area having a plurality of sub-pixels and a non-emissive area between the plurality of sub-pixels; and a non-display area adjacent to the display area; a corresponding first electrode in each of the plurality of sub-pixels; a bank that divides the plurality of sub-pixels; an emissive layer on the first electrode; a second electrode on the emissive layer; and a cut in the emissive layer between two adjacent sub-pixels of the plurality of sub-pixels.

20. The display device according to claim 19, wherein the bank includes a plurality of bank holes respectively corresponding to the plurality of sub-pixels and a bank trench corresponding to the non-emissive area.

21. The display device according to claim 19, further comprising a first spacer on the bank.

22. The display device according to claim 21, wherein the cut is formed by a second spacer in the bank trench.

23. The display device according to claim 22, wherein the second spacer includes the same material as the bank.

24. The display device according to claim 22, wherein the height of the second spacer is less than the height of the first spacer.

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