Data cache space management method, system and device and storage medium

Abstract

The invention relates to the technical field of solid state disks, and discloses a data cache space management method, system and device and a storage medium. The data cache space management method comprises the following steps: obtaining the total length of to-be-written data in a write access request; writing the to-be-written data into the idle data cache space in batches according to the access rate and the total length of the external module, and storing the cache address of the sub-cache space where the sub-data written each time is located and the incidence relation between the cache addresses of the sub-data written two adjacent times in the same write access request. According to the invention, the size of the cache space can be flexibly configured for any external module according to actual requirements, the access rate of each external module is met, the waste of the cache space can be effectively avoided, the full utilization of cache resources is ensured, and the chip cost is reduced. In addition, according to the method, the sub-data, stored at different positions, of the same access request are associated, so that the integrity of the data is ensured.

Description

Technical Field

[0001] This application relates to the technical field of solid-state drives, and particularly to a method, system, device, and storage medium for managing data cache space. Background Art

[0002] In the chip design process, the data cache buffer plays an important role. Reasonably and efficiently utilizing the size of the data cache buffer can greatly reduce the cost of the entire chip.

[0003] In traditional chip design, when multiple external modules access the same data cache buffer, a fixed-size cache buffer is usually allocated to each external module in advance, allowing each external module to access its own cache space. This can not only ensure the access rate of each external module but also achieve good isolation. However, this design will cause waste of the data cache buffer. Because in the actual operation of the chip, not all external modules will work simultaneously. If an external module is not running, it will always occupy a part of the unused cache space in the data buffer, resulting in waste of resources and increasing the cost of the chip. Summary of the Invention

[0004] The main purpose of this application is to provide a method, system, device, and storage medium for managing data cache space, aiming to solve the technical problem of how to efficiently utilize cache resources.

[0005] In the first aspect of this application, a method for managing data cache space is provided. The method for managing data cache space includes:

[0006] If a write access request from a first external module is obtained, obtain the first total length of the data to be written in the write access request;

[0007] Obtain the current free address information of the data cache space;

[0008] According to the access rate of the first external module and the first total length, batch-write the data to be written into the free data cache space corresponding to the current free address information, store the cache addresses of the sub-cache spaces where the sub-data written each time is located, and store the association relationship between the cache addresses of the sub-data written in two adjacent times in the same write access request.

[0009] Optionally, in the first implementation manner of the first aspect of the present application, the data to be written is written in batches into the free data cache space corresponding to the current free address information according to the access rate of the first external module and the first total length, the cache addresses of the sub-cache spaces where the sub-data written each time is stored, and the association relationship between the cache addresses of the adjacent two sub-data written in the same write access request includes:

[0010] Obtain the starting write address of the free data cache space;

[0011] According to the access rate of the first external module, use the first batch of sub-data to be written in the data to be written as the current sub-data to be written, and use the starting write address as the current write address;

[0012] Write the current sub-data to be written into the sub-cache space corresponding to the current write address;

[0013] Store the mapping relationship between the current sub-data to be written and the current write address;

[0014] Calculate the remaining write length according to the first total length of the data to be written and the length of the sub-data already written;

[0015] If the remaining write length is not 0, obtain the next sub-data to be written and the corresponding next write address of the current sub-data to be written;

[0016] Store the association relationship between the current write address and the next write address;

[0017] Use the next sub-data to be written as the current sub-data to be written, and use the next write address as the current write address, and execute the steps of writing the current sub-data to be written into the sub-cache space corresponding to the current write address and subsequent steps until the remaining write length is 0.

[0018] Optionally, in the second implementation manner of the first aspect of the present application, the method for managing the data cache space further includes:

[0019] If a read access request from the second external module is obtained, obtain the second total length of the data to be read in the read access request and the starting read address;

[0020] According to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of the sub-data to be read in the data to be read, sequentially read each sub-data to be read from the starting read address from the data cache space.

[0021] Optionally, in the third implementation manner of the first aspect of the present application, according to the association relationship between the second total length, the access rate of the second external module, and the cache addresses of each to-be-read sub-data in the to-be-read data, each to-be-read sub-data is sequentially read from the starting read address in the data cache space, including:

[0022] Taking the starting read address as the current to-be-read address;

[0023] Reading the current to-be-read sub-data from the data cache space according to the current to-be-read address and the access rate of the second external module, and transmitting the read current sub-data to the second external module;

[0024] Calculating the remaining read length according to the second total length of the to-be-read data and the length of the already-read sub-data;

[0025] If the remaining read length is not 0, obtaining the next to-be-read address of the current to-be-read address according to the association relationship between the current to-be-read sub-data and the cache address of the next to-be-read sub-data;

[0026] Taking the next to-be-read address as the current to-be-read address, and executing the steps of reading the current to-be-read sub-data from the data cache space according to the current to-be-read address and the access rate of the second external module, and transmitting the read current sub-data to the second external module and subsequent steps until the remaining read length is 0.

[0027] Optionally, in the fourth implementation manner of the first aspect of the present application, the method for managing the data cache space further includes:

[0028] Recycling the sub-cache space of the already-read sub-data.

[0029] Optionally, in the fifth implementation manner of the first aspect of the present application, before obtaining the current free address information of the data cache space, the method for managing the data cache space further includes:

[0030] Dividing the data cache space into multiple sub-cache spaces according to the access granularity of the data, and allocating a unique cache address to each sub-cache space.

[0031] The present application further provides a management system for a data cache space, and the management system for the data cache space includes: a write command control module, a first address control module, and a second address control module;

[0032] The write command control module is configured to obtain the first total length of the data to be written in the write access request if a write access request of the first external module is obtained;

[0033] The write command control module is further configured to obtain the current free address information of the data cache space through the first address control module;

[0034] The write command control module is further configured to batch-write the data to be written into the free data cache space corresponding to the current free address information according to the access rate of the first external module and the first total length;

[0035] The first address control module is used to store the cache address of the sub-cache space where the sub-data written each time is located;

[0036] The second address control module is used to store the association relationship between the cache addresses of the sub-data written in two adjacent times in the same write access request.

[0037] Optionally, in the first implementation manner of the second aspect of the present application, the management system of the data cache space further includes: a read command control module;

[0038] The read command control module is configured to, if a read access request from a second external module is obtained, obtain the second total length and the starting read address of the data to be read out in the read access request;

[0039] The read command control module is further configured to sequentially read out each sub-data to be read from the data cache space starting from the starting read address according to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of the sub-data to be read out in the data to be read out obtained from the second address control module.

[0040] A third aspect of the present application provides a computer device, including: a memory and at least one processor, wherein instructions are stored in the memory; the at least one processor calls the instructions in the memory to enable the computer device to execute the above-mentioned management method of the data cache space.

[0041] A fourth aspect of the present application provides a computer-readable storage medium, in which instructions are stored, and when the instructions are run on a computer, the computer is enabled to execute the above-mentioned management method of the data cache space.

[0042] Based on the access request of the external module, the present application can flexibly configure the cache space size for any external module according to actual needs. If some external modules are no longer in use, they will not occupy the cache space, efficiently utilizing the cache space, meeting the access rates of each external module, effectively avoiding the waste of the cache space, saving the cache space, ensuring the full utilization of the cache resources, reducing the chip cost, and realizing the shared management of the cache space. The present application also associates the sub-data stored in different sub-cache spaces of the same access request through cache addresses, effectively ensuring the integrity of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic flowchart of the first embodiment of the management method of the data cache space in the embodiment of the present application;

[0044] Figure 2 It is a schematic diagram of an external module accessing a data cache space in the prior art;

[0045] Figure 3 It is an interaction schematic diagram between an external module and a data control module in an embodiment of the present application;

[0046] Figure 4 It is a structural block diagram of a management system for a data cache space in an embodiment of the present application;

[0047] Figure 5 It is a schematic diagram of the relationship between a first address control module and a second address control module and a data cache space in an embodiment of the present application;

[0048] Figure 6 It is a schematic diagram of reading data in an embodiment of the present application;

[0049] Figure 7 It is an interaction schematic diagram of each module of a management system for a data cache space in an embodiment of the present application;

[0050] Figure 8 It is a schematic diagram of an embodiment of a computer device in an embodiment of the present application. Detailed implementation manners

[0051] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the term "comprising" or "having" and any variation thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] In the prior art, in traditional module design, when there are multiple external modules accessing the same data cache buffer, a fixed-size cache buffer is allocated to each module in advance so that each module can access its own cache space.

[0053] Such as Figure 2As shown in the figure, assume that Module A and Module B access the data cache space Data_buf at a rate of 50 KB / s, and Module C accesses it at a rate of 100 KB / s. In the traditional design, 50 KB, 50 KB, and 100 KB of data cache spaces Data_A, Data_B, and Data_C are fixedly allocated to modules A, B, and C respectively during the initialization phase. However, during actual operation, for example, in a certain application scenario, Module C may not be required to work, and only Modules A and B are needed. This will result in the data blocks in the data cache space allocated to Module C, such as Data_C, never being accessed, and these data blocks cannot be provided for Modules A and B to use either.

[0054] It can be seen from this that the traditional chip design scheme needs to allocate the maximum cache space for each module according to the transmission rates of all external modules. If an external module is not used, it will cause a large amount of waste of the cache space. Moreover, the traditional chip design uses a fixed allocation method, which has poor flexibility. The failure to fully utilize the internal cache space will also increase the cost of the chip.

[0055] Based on the above problems, the present application provides a management scheme for data cache space.

[0056] Refer to Figure 1 , an embodiment of the present application provides a management method for data cache space. The management method for data cache space includes:

[0057] S100: If a write access request from a first external module is obtained, obtain the first total length of the data to be written in the write access request.

[0058] Specifically, the management method for data cache space in this embodiment can be applied to a cache control module or a data control module Data_ctrl in a management system for data cache space. The data control module Data_ctrl is used to manage the data cache space according to the access requests of any external module, that is, to perform management such as reading or writing on the data cache space. The data control module Data_ctrl can interact with multiple external modules, and all external modules share the data cache space.

[0059] As Figure 3 shown is an interaction schematic diagram between an external module and a data control module in an embodiment of the present application; refer to Figure 3, Module A, Module B, and Module C all access the data cache space Data_buf through the data control module Data_ctrl. The data cache space Data_buf does not need to allocate fixed sub-cache spaces or sub-data blocks for Module A, Module B, and Module C. All external modules such as Module A, Module B, and Module C share the data cache space Data_buf, and all external modules use a part of the cache space in the data cache space Data_buf according to actual needs.

[0060] In this embodiment, a target access request or a target command request of any one or more first external modules can be obtained, where the target access request is a read access request or a write access request.

[0061] The first external module can read data from or write data to the data cache space.

[0062] If a write access request (or a write command) is obtained, the total length of the data to be written in the write access request is recorded as the first total length. The first total length is the write length information of the data to be written.

[0063] S200: Obtain the current free address information of the data cache space.

[0064] Specifically, the data cache space includes used cache space and unused cache space. This embodiment records the address information of the used cache space and the unused cache space respectively. Since data needs to be written, therefore, the current free address information of the unused cache space needs to be obtained.

[0065] S300: Batch-write the data to be written into the free data cache space corresponding to the current free address information according to the access rate of the first external module and the first total length, store the cache address of the sub-cache space where each written sub-data is located, and store the association relationship between the cache addresses of adjacent sub-data written in the same write access request.

[0066] Specifically, the access rates of different external modules may be different. For example, the access rates of Module A and Module B are 50 kb / s, and the access rate of Module C is 100 kb / s.

[0067] This embodiment can determine the size of the data written each time according to the access rate of the first external module and the access granularity of the data.

[0068] If the first total length of the data to be written is greater than the access rate of the first external module (i.e., the maximum data length that can be written per second), the data to be written will be written into the free data cache space in batches in sequence. Each written sub-data is a part of the data to be written, and different sub-data are written into different sub-storage spaces. Therefore, different sub-data correspond to different cache addresses.

[0069] To ensure data integrity, in addition to recording the mapping relationship or correspondence between sub-data and cache addresses in this embodiment, the association relationship between the cache addresses of two adjacent sub-data will also be stored. After the data waiting to be written is completely written, if the written data needs to be read later, the sub-data can be read in sequence according to the association relationship between the cache addresses of adjacent sub-data and spliced into complete data, ensuring data integrity.

[0070] Based on the access request of the external module, this embodiment can flexibly configure the cache space size for any external module according to actual needs. If some external modules are no longer in use, they will not occupy the cache space, efficiently utilizing the cache space. It not only meets the access rate of each external module but also effectively avoids waste of the cache space, saves the cache space, ensures full utilization of the cache resources, reduces the chip cost, and realizes shared management of the cache space. This embodiment also associates the sub-data stored in different sub-cache spaces for the same access request through cache addresses, effectively ensuring data integrity.

[0071] In one embodiment, in step S300, according to the access rate of the first external module and the first total length, the data to be written is written into the free data cache space corresponding to the current free address information in batches, the cache address of the sub-cache space where each written sub-data is located is stored, and the association relationship between the cache addresses of two adjacent sub-data written in the same write access request is stored, including:

[0072] Obtain the starting write address of the free data cache space;

[0073] According to the access rate of the first external module, take the first batch of sub-data to be written in the data to be written as the current sub-data to be written, and take the starting write address as the current write address;

[0074] Write the current sub-data to be written into the sub-cache space corresponding to the current write address;

[0075] Store the mapping relationship between the current sub-data to be written and the current write address;

[0076] Calculate the remaining write length according to the first total length of the data to be written and the length of the already written sub-data;

[0077] If the remaining write length is not 0, obtain the next sub-data to be written and the corresponding next write address of the current sub-data to be written;

[0078] Store the association relationship between the current write address and the next write address;

[0079] Take the next sub-data to be written as the current sub-data to be written, and the next write address as the current write address, and perform the steps of writing the current sub-data to be written into the sub-cache space corresponding to the current write address and subsequent steps until the remaining write length is 0.

[0080] Specifically, in this embodiment, according to the write command of the first external module, the data write operation is completed.

[0081] Obtain the starting write address start_addr of the free data cache space, write the first batch of sub-data to be written into the sub-cache space corresponding to the starting write address start_addr, and record the mapping relationship between the first batch of sub-data to be written and the starting write address start_addr.

[0082] Calculate the remaining write length, the remaining write length new_length_w = the first total length length - the length of the sub-data that has been written data_size. Among them, the sub-data that has been written includes the current sub-data to be written and the historically written sub-data. The data length of each sub-data to be written can be determined according to the access granularity of the data and the access rate of the first external module.

[0083] Here, the remaining write length new_length_w - 1 = the first total length length - the data length of the first batch of sub-data to be written.

[0084] If the remaining write length new_length_w - 1 is not 0, it means that the write operation has not been completed. Obtain the second batch of sub-data to be written in the data to be written, obtain the next write address from the free data cache space, that is, the second write address, and write the second batch of sub-data to be written to the second write address.

[0085] Record the mapping relationship between the second batch of sub-data to be written and the second write address.

[0086] At the same time, store the association relationship between the starting write address and the second write address.

[0087] Calculate the remaining write length, the remaining write length new_length_w = the first total length length - the length of the sub-data that has been written data_size. Here, the remaining write length new_length_w - 2 = the first total length length - the data length of the first batch of sub-data to be written - the data length of the second batch of sub-data to be written.

[0088] If the remaining write length new_length_w - 2 is not 0, it indicates that the write operation is not completed. Obtain the third batch of sub-data to be written in the data to be written, obtain the next write address to be written, i.e., the third write address, from the free data cache space, and write the third batch of sub-data to be written to the third write address.

[0089] Record the mapping relationship between the third batch of sub-data to be written and the third write address.

[0090] Meanwhile, store the association relationship between the second write address and the third write address.

[0091] The remaining sub-data to be written are written to other sub-cache spaces by analogy according to the above description until all the data to be written are written to the data cache space.

[0092] By associating the starting write address, the second write address, the third write address... the write addresses to be waited for, all the sub-data of the same data to be written are chained together, which is convenient for subsequent sequential reading and ensures the integrity and correctness of the data.

[0093] In a specific embodiment, the two associated cache addresses are written into the corresponding entry to achieve data chaining, and the address pairs of different groups correspond to different entries.

[0094] In this embodiment, according to the total length of the data to be written, the data to be written are written into each sub-cache space in batches through a loop, and the association relationship between the cache addresses of adjacent sub-data is established, which is convenient for sequential reading during data reading and ensures the integrity of the data.

[0095] In this embodiment, through a small amount of logic, the data cache buffer accessed by multiple external modules is formed into a linked list management method by configuring the minimum granularity of the data. In some application scenarios, even if an external module is no longer used, this external module will not occupy the cache space, thus efficiently utilizing the cache space. It not only ensures the access rate of all modules but also saves the cache space, greatly reducing the cost of the chip.

[0096] In one embodiment, the method for managing the data cache space further includes:

[0097] If a read access request from the second external module is obtained, obtain the second total length and the starting read address of the data to be read out in the read access request;

[0098] According to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of each sub-data to be read out in the data to be read out, sequentially read each sub-data to be read out from the starting read address in the data cache space.

[0099] Specifically, in this embodiment, a target access request or a target command request of any one or more second external modules can be obtained, where the target access request is a read access request or a write access request.

[0100] The second external module can read data from or write data to the data cache space.

[0101] The access rate of the second external module is limited. Therefore, if the data length of the data to be read out is long, the sub-data needs to be read out in batches.

[0102] If a read access request (or a read command) is obtained, the total length of the data to be read out in the read access request is recorded as the second total length, and the starting read address is obtained. The second total length is the read length information of the data to be read out. The starting read address is the cache address of the sub-cache space corresponding to the first batch of sub-data to be read out (starting sub-data to be read out).

[0103] According to the association relationship between the cache addresses of each sub-data to be read out and the starting read address, the cache address of each sub-data to be read out can be determined; according to the mapping relationship between the sub-data to be read out and the cache address of the sub-cache space where it is stored, each sub-data to be read out can be read out according to the cache address. Thus, all the sub-data to be read out starting from the starting read address can be read out in sequence.

[0104] In this embodiment, according to the association relationship of the cache addresses between the sub-data stored in different sub-cache spaces in the data cache space, each sub-data can be read out quickly and efficiently to obtain the complete data.

[0105] In one embodiment, according to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of each sub-data to be read out in the data to be read out, each sub-data to be read out is sequentially read from the data cache space starting from the starting read address, including:

[0106] Taking the starting read address as the current read address to be read out;

[0107] Reading the current sub-data to be read out from the data cache space according to the current read address to be read out and the access rate of the second external module, and transmitting the read current sub-data to the second external module;

[0108] Calculating the remaining read length according to the second total length of the data to be read out and the length of the sub-data that has been read out;

[0109] If the remaining read length is not 0, then according to the association relationship between the cache address of the current sub-data to be read out and the cache address of the next sub-data to be read out, the next read address to be read out of the current read address is obtained;

[0110] Take the next address to be read out as the current address to be read out, and execute the steps of reading the current sub-data to be read out from the data cache space according to the current address to be read out and the access rate of the second external module, and transmitting the read current sub-data to the second external module and subsequent steps until the remaining read length is 0.

[0111] Specifically, the data length of each sub-data to be read out can be determined according to the starting read address, the access rate of the second external module, and the granularity of the read data.

[0112] Determine the data length of the first sub-data to be read out according to the initial read address, the access rate of the second external module, and the granularity of the read data. Read the first sub-data to be read out from the data cache space according to the initial read address, and transmit the read first sub-data to the second external module.

[0113] According to the second total length of the data to be read out and the length of the sub-data that has been read out, the remaining read length can be calculated, and then it can be determined whether the read command has been completed. The remaining read length new_length_r = the second total length length - the length of the sub-data that has been read out data_size.

[0114] The sub-data that has been read out includes the current sub-data to be read out and the historical sub-data that has been read out.

[0115] Here, the remaining read length new_length_r - 1 = the second total length length - the data length of the first sub-data to be read out.

[0116] If the remaining read length new_length_r - 1 is not 0, it means that the read operation has not been completed. Since the cache address of the first sub-data to be read out is associated with the cache address of the second sub-data to be read out, the cache address of the second sub-data to be read out, that is, the second address to be read out, can be obtained according to the starting read address.

[0117] Read the second sub-data to be read out from the data cache space according to the second address to be read out, and transmit the read second sub-data to the second external module.

[0118] Here, the remaining read length new_length_r - 2 = the second total length length - the data length of the first sub-data to be read out - the data length of the second sub-data to be read out.

[0119] If the remaining read length new_length_r - 2 is not 0, it means that the read operation has not been completed. Since the cache address of the second sub-data to be read out is associated with the cache address of the third sub-data to be read out, the cache address of the third sub-data to be read out, that is, the third address to be read out, can be obtained according to the second address to be read out.

[0120] Read the third sub-data to be read from the data cache space according to the third address to be read, and transfer the read third sub-data to the second external module.

[0121] Other sub-data to be read are read from different sub-cache spaces of the data cache space by analogy according to the above steps.

[0122] In this embodiment, according to the association relationship of the cache addresses of adjacent sub-data, each sub-data can be read sequentially, and the sub-data can be pipelined, which ensures the integrity of the data and also ensures the read data bandwidth.

[0123] In one embodiment, the management method of the data cache space further includes:

[0124] Recycle the sub-cache space of the read sub-data.

[0125] Specifically, if the sub-data stored in a sub-cache space has been read by an external module, the sub-cache space can be recycled.

[0126] Recycling the sub-cache space is equivalent to writing the cache address of the sub-cache space back to the free address information to update the free address information, realizing the recycling of the address, which is convenient for the sub-cache space corresponding to the recycled address to be used when data needs to be written next time.

[0127] The recycling of the cache address can be executed immediately after the sub-data is read, which can ensure that the sub-cache space is recycled immediately and put into reuse immediately, effectively alleviating the tension of the cache space and making full use of the cache space and resources.

[0128] In addition, after recycling the sub-cache space, the data in the sub-cache space after the address is recycled can also be cleared.

[0129] In this embodiment, through address recycling, the sub-cache space where the data has been read can be effectively managed and recycled, the cache resources are released, which is convenient for subsequent external modules to use, and effectively ensures the reuse of the cache space.

[0130] In one embodiment, before step S200 of obtaining the current free address information of the data cache space, the management method of the data cache space further includes:

[0131] Divide the data cache space into multiple sub-cache spaces according to the access granularity of the data, and assign a unique cache address to each sub-cache space.

[0132] Specifically, configure the access granularity data_size of the sub-cache space (data block) of the data cache space Data_buf, and allocate the maximum cache space of the data cache space Data_buf. Divide the maximum cache space of the data cache space Data_buf into multiple sub-cache spaces according to the access granularity data_size, and set or allocate a unique cache address for each sub-cache space.

[0133] Suppose the size of the data cache space Data_buf is 100KB, and the access granularity for reading one data each time is 1KB. Then the data cache space can be divided into 100 sub-cache spaces, and 100 cache addresses are generated at the same time. If the access granularity is 5KB, the data cache space can be divided into 20 sub-cache spaces, and 20 cache addresses are generated at the same time. And so on, any size of data cache space can be divided into multiple sub-cache spaces according to the access granularity.

[0134] Among them, the access granularity can be the access granularity for reading one data.

[0135] Use the allocated cache address as the address information, and perform initialization according to the address information in the initialization stage, then the initialization process can be completed.

[0136] In this embodiment, any size of data cache space is automatically divided into multiple sub-cache spaces through the access granularity, and a unique address is allocated for each sub-cache space.

[0137] Figure 4 It is the structural block diagram of the management system of the data cache space in an embodiment of the present application; refer to Figure 4 This management system of the data cache space includes: a write command control module 10, a first address control module 20, and a second address control module 30;

[0138] The write command control module 10 is used to obtain the first total length of the data to be written in the write access request if a write access request from the first external module is obtained;

[0139] The write command control module 10 is further used to obtain the current free address information of the data cache space through the first address control module 20;

[0140] The write command control module 10 is further used to batch-write the data to be written into the free data cache space corresponding to the current free address information according to the access rate of the first external module and the first total length;

[0141] The first address control module 20 is used to store the cache address of the sub-cache space where the sub-data written each time is located;

[0142] The second address control module 30 is used to store the association relationship between the cache addresses of adjacent two writes of sub-data in the same write access request.

[0143] Specifically, the management system of the data cache space includes a data control module Data_ctrl, and the data control module Data_ctrl includes a wr_pld_ctrl module (write command control module 10), a cur_addr_ctrl module (first address control module 20 or current address control module), and an nxt_addr_ctrl module (second address control module 30 or next address control module);

[0144] The wr_pld_ctrl module: processes the write command request or write access request arbitrated by the arbiter module, obtains the current free address information of the data cache space Data_buf through the first address control module 20, and writes the data to be written in the write access request into the free data cache space corresponding to the current free address information.

[0145] The wr_pld_ctrl module: is also used to write the association relationship between the cache addresses of adjacent two writes of sub-data to the second address control module 30 (i.e., the nxt_addr_ctrl module).

[0146] The cur_addr_ctrl module: manages the space address information corresponding to the free data cache space of the data cache space Data_buf and the address information of the used data cache space.

[0147] The nxt_addr_ctrl module: manages the association relationship between the cache address of the previous sub-data and the cache address of the next sub-data in the data cache space Data_buf.

[0148] Such as Figure 5 shown is a schematic diagram of the relationship between the first address control module 20 and the second address control module 30 and the data cache space in an embodiment of the present application; referring to Figure 5 , the address in the entry of cur_addr corresponds one-to-one with the sub-data stored in the sub-cache space in the data cache space Data_buf, and the associated address in the entry of nxt_addr points to the sub-data in the next sub-cache space in the data cache space Data_buf, so that the data of the entire command can be normally chained together to form a complete read command or write command.

[0149] For example, the cache address of a sub-data a is address 1, and the address 2 of its next sub-data b is associated with address 1. Therefore, the address 2 of the next sub-data b can be determined. According to address 2, the sub-data b can be read from the data cache space. The address 3 of the next sub-data c of the sub-data b is associated with address 2. Therefore, the address 3 of the sub-data c can be determined. According to address 3, the sub-data c can be read from the data cache space. And so on, all sub-data can be read.

[0150] In one embodiment, the management system of the data cache space further includes: a read command control module 40;

[0151] The read command control module 40 is configured to, if a read access request from a second external module is obtained, obtain the second total length and the starting read address of the data to be read out in the read access request;

[0152] The read command control module 40 is further configured to, according to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of the sub-data to be read out in the data to be read out obtained from the second address control module 30, sequentially read out each sub-data to be read out from the starting read address in the data cache space.

[0153] Specifically, the data control module Data_ctrl further includes an Rd_pld_ctrl module (i.e., the read command control module 40 (not shown in the figure)).

[0154] The Rd_pld_ctrl module: processes the read command request (read access request) arbitrated by the arbiter module, obtains the cache position of the sub-data to be read out in the data cache space Data_buf according to the read address information of the second external module, reads out the sub-data and transmits it to the external module, and at the same time obtains the cache position of the next sub-data to be read out of the read access request through the nxt_addr_ctrl module, and reads out and transmits the sub-data after that.

[0155] In one embodiment, the write command control module 10 is specifically configured to obtain the starting write address of the idle data cache space through the first address control module 20;

[0156] The write command control module 10 is further specifically configured to, according to the access rate of the first external module, use the first batch of sub-data to be written in the data to be written as the current sub-data to be written, use the starting write address as the current write address, and write the current sub-data to be written into the sub-cache space corresponding to the current write address;

[0157] The first address control module 20 is specifically configured to store the mapping relationship between the current sub-data to be written and the current write address;

[0158] The write command control module 10 is further configured to calculate the remaining write length according to the first total length of the data to be written and the length of the written sub-data. If the remaining write length is not 0, obtain the next sub-data to be written of the current sub-data to be written and obtain the corresponding next write address through the first address control module 20;

[0159] The second address control module 30 is specifically configured to store the association relationship between the current write address and the next write address;

[0160] The write command control module 10 is further configured to use the next sub-data to be written as the current sub-data to be written, use the next write address as the current write address, and execute the process of writing the current sub-data to be written into the sub-cache space corresponding to the current write address and subsequent processes until the remaining write length is 0.

[0161] Specifically, the wr_pld_ctrl module obtains the write length information length of the write command from the first external module. The wr_pld_ctrl module obtains the starting write address start_addr from the cur_addr_ctrl module as the current write address cur_addr. And write the first sub-data to be written into the starting write address. At the same time, calculate the remaining write length length, and the remaining write length new_length_w = the first total length length - the length of the written sub-data data_size. Determine whether the length of the write command has been used up according to the remaining write length. If the remaining write length new_length_w is 0, the write command is completed. If the remaining write length new_length_w is not 0, the wr_pld_ctrl module continues to obtain a new new_cur_addr address information from the cur_addr_ctrl module as the next write address, and write the second batch of sub-data to be written into the next write address new_cur_addr. At the same time, recalculate the remaining write length. The wr_pld_ctrl module writes the next write address (new_cur_addr) into the entry corresponding to the current write address (cur_addr) in the second address control module 30 (nxt_addr_ctrl module). Complete the data chaining process. Repeat the above steps to execute the write command until the write command is completed.

[0162] In one embodiment, the read command control module 40 is specifically configured to use the starting read address as the current read address, read the current sub-data to be read from the data cache space according to the current read address and the access rate of the second external module, and transmit the read current sub-data to the second external module;

[0163] The read command control module 40 is further specifically configured to calculate the remaining read length according to the second total length of the data to be read and the length of the read sub-data.

[0164] The read command control module 40 is further specifically configured to, if the remaining read length is not 0, obtain the next read address of the current read address through the association relationship between the cache addresses of the current sub-data to be read and the next sub-data to be read in the second address control module 30.

[0165] The read command control module 40 is further specifically configured to use the next read address as the current read address, and execute the process of reading the current sub-data to be read from the data cache space according to the current read address and the access rate of the second external module, and transmitting the read current sub-data to the second external module and subsequent processes until the remaining read length is 0.

[0166] Specifically, the read command control module 40 obtains the start read address start_addr and the read length information length (the second total length) of the read command of the second external module.

[0167] According to the start read address start_addr, the corresponding first sub-data to be read (belonging to the current sub-data to be read) is obtained from the data cache space Data_buf and transmitted to the second external module. The read command control module 40 will also obtain the associated address nxt_addr of the start read address start_addr in the second address control module 30 nxt_addr_ctrl, where nxt_addr is the cache address of the next sub-data to be read. The purpose of this is to enable the data to be pipelined and ensure the read data bandwidth. The start read address start_addr is the current read address.

[0168] At this time, calculate the remaining read length new_length_r = the second total length length - the length of the read sub-data data_size.

[0169] After reading out the current sub-data to be read, write the current read address back to the first address control module 20 cur_addr_ctrl module for address recycling.

[0170] Determine whether the remaining read length has been used up. If the remaining read length is 0, the read command is completed. If the remaining read length is not 0, obtain the storage location of the next batch of sub-data to be read out in the data cache space Data_buf through the second address control module 30 (nxt_addr_ctrl), that is, obtain the next read address. Read the next sub-data to be read from the data cache space according to the next read address, and transmit the read sub-data to the second external module. By analogy with the above steps until all sub-data are read, the read operation is completed.

[0171] Such as Figure 6 is a schematic diagram of reading data in an embodiment of the present application; refer to Figure 6 , obtain the starting read address start_addr and the second total length len, and read the first sub-data to be read data_1 according to the starting read address start_addr; according to the association relationship between the cache address start_addr of the first sub-data to be read data_1 and the cache address of the second sub-data to be read data_2, obtain the cache address of the second sub-data to be read data_2, that is, the second read address nex_addr_a, and read the second sub-data to be read data_2 according to the second read address nex_addr_a; according to the association relationship between the cache address nex_addr_a of the second sub-data to be read data_2 and the cache address of the third sub-data to be read data_3, obtain the cache address of the third sub-data to be read data_3, that is, the third read address nex_addr_b, and read the third sub-data to be read data_3 according to the third read address nex_addr_b; by analogy, read out all sub-data data_1 - data_n, and transmit all sub-data data_1 - data_n to the second external module. The second external module can obtain the complete data according to the sub-data received successively.

[0172] Figure 7 is an interaction schematic diagram of each module of the data cache space management system in an embodiment of the present application; refer to Figure 7, Module A, Module B, and Module C can respectively send read access requests Module_A_rd, Module_B_rd, and Module_C_rd. The arbiter can transmit the read access requests after arbitration to rd_pld_ctrl, i.e., the read command control module 40. Rd_pld_ctrl obtains the current address to be read out from the first address control module 20, i.e., the cur_addr_ctrl module, and reads out the first sub-data to be read out from the data buffer space Data_buf according to the current address to be read out. Rd_pld_ctrl also obtains the next address to be read out of the current address to be read out from the second address control module 30, i.e., the nex_addr_ctrl module, that is, obtains the buffer address of the next sub-data to be read out, and reads out the next sub-data to be read out from the data buffer space Data_buf according to the next address to be read out. And so on, read out all the sub-data included in the data to be read.

[0173] , Module A, Module B, and Module C can respectively send write access requests Module_A_wr, Module_B_wr, and Module_C_wr. The arbiter can transmit the write access requests after arbitration to wr_pld_ctrl, i.e., the write command control module 10. Wr_pld_ctrl obtains the current free address of the currently available free data buffer space from the first address control module 20, i.e., the cur_addr_ctrl module. Wr_pld_ctrl writes the first sub-data to be written into the sub-buffer space corresponding to the first address to be written. Wr_pld_ctrl obtains the second address to be written through the cur_addr_ctrl module and writes the second sub-data to be written into the sub-buffer space corresponding to the second address to be written. Wr_pld_ctrl also writes the association relationship between the second address to be written and the first address to be written into the second address control module 30, i.e., the nxt_addr_ctrl. Wr_pld_ctrl obtains the third address to be written through the cur_addr_ctrl module and writes the third sub-data to be written into the sub-buffer space corresponding to the third address to be written. Wr_pld_ctrl also writes the association relationship between the third address to be written and the second address to be written into the second address control module 30, i.e., the nxt_addr_ctrl. And so on, write all the data to be written into the data buffer space Data_buf.

[0174] In one embodiment, the management system of the data buffer space further includes: a recycling module for recycling the sub-buffer space of the read-out sub-data.

[0175] In one embodiment, the management system of the data buffer space further includes:

[0176] A partitioning module, configured to partition a data cache space into multiple sub-cache spaces according to the access granularity of data, and assign a unique cache address to each sub-cache space.

[0177] Specifically, according to the maximum cache space of the allocated data cache space Data_buf, configure the access granularity data_size of the sub-cache space of Data_buf, partition the maximum cache space according to the access granularity, and assign a unique address to each sub-cache space. Fill the allocated address information into the first address control module 20, i.e., the cur_addr_ctrl module, during the initialization phase to complete the initialization process.

[0178] Assume that the size of Data_buf is 100KB, and the access granularity for reading one data each time is 1KB, then 100 cur_addr information is required; if the access granularity is 5KB, then 20 cur_addr address information is required.

[0179] This application realizes the sharing process of the data cache space buffer, saves the size of the cache space, ensures the access rate, and saves the cost of the chip.

[0180] Figure 8 It is a schematic structural diagram of a computer device provided by an embodiment of this application. The computer device 700 may vary greatly due to different configurations or performances, and may include one or more processors (central processing units, CPUs) 710 (for example, one or more processors) and a memory 720, and one or more storage media 730 for storing application programs 733 or data 732 (for example, one or more mass storage devices). Among them, the memory 720 and the storage media 730 may be transient storage or persistent storage. The program stored in the storage media 730 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the computer device 700. Further, the processor 710 may be configured to communicate with the storage media 730 and execute a series of instruction operations in the storage media 730 on the computer device 700.

[0181] The computer device 700 may further include one or more power supplies 740, one or more wired or wireless network interfaces 750, one or more input / output interfaces 760, and / or one or more operating systems 731, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, and so on. Those skilled in the art can understand, Figure 8The computer device structure shown does not constitute a limitation on the computer device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0182] This application also provides a computer device, which includes a memory and a processor. Computer-readable instructions are stored in the memory. When the computer-readable instructions are executed by the processor, the processor is caused to execute the steps of the method for managing the data cache space in the above-mentioned embodiments.

[0183] This application also provides a computer-readable storage medium. The computer-readable storage medium may be a non-volatile computer-readable storage medium, or may also be a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions run on a computer, the computer is caused to execute the steps of the method for managing the data cache space.

[0184] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0185] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0186] The above, the above embodiments are only used to illustrate the technical solution of this application and are not intended to limit it; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of this application.

Claims

1. A method for managing data cache space, characterized in that: The data cache space management method includes: If a write access request from the first external module is obtained, obtaining a first total length of the data to be written in the write access request; Get the current free address information of the data cache space; According to the access rate of the first external module and the first total length, the data to be written are written in batches to the free data cache space corresponding to the current free address information, the cache address of the sub-cache space where the sub-data written each time is located is stored, and the association relationship between the cache addresses of the sub-data written twice adjacently in the same write access request is stored.

2. The data cache space management method according to claim 1, characterized in that: The step of writing the data to be written in batches to the idle data cache space corresponding to the current idle address information according to the access rate of the first external module and the first total length, storing the cache address of the sub-cache space where the sub-data written each time is located, and storing the association relationship between the cache addresses of two adjacent sub-data written in the same write access request includes: Get the starting write address of the free data cache space; According to the access rate of the first external module, taking the first batch of sub-data to be written in the data to be written as the current sub-data to be written, and taking the starting write address as the current address to be written; Write the sub-data to be written into the sub-cache space corresponding to the address to be written; storing a mapping relationship between the sub-data currently to be written and the address currently to be written; Calculating a remaining write length according to the first total length of the data to be written and the length of the sub-data that has been written; If the remaining write length is not 0, obtaining the next sub-data to be written of the current sub-data to be written and the corresponding next address to be written; Storing the association relationship between the current address to be written and the next address to be written; The next sub-data to be written is used as the current sub-data to be written, and the next address to be written is used as the current address to be written, and the step of writing the current sub-data to be written into the sub-cache space corresponding to the current address to be written and subsequent steps are executed until the remaining write length is 0.

3. The data cache space management method according to claim 1, characterized in that: The data cache space management method also includes: If a read access request from a second external module is obtained, obtaining a second total length of the data to be read and a start read address in the read access request; According to the second total length, the access rate of the second external module and the association between the cache addresses of the sub-data to be read in the data to be read, the sub-data to be read are read sequentially from the data cache space starting from the start read address.

4. The data cache space management method according to claim 3, characterized in that: The step of sequentially reading each sub-data to be read from the data cache space starting from the start read address according to the second total length, the access rate of the second external module, and the association relationship between the cache addresses of each sub-data to be read in the data to be read includes: Using the starting read address as the current address to be read out; Reading the current sub-data to be read from the data cache space according to the current address to be read and the access rate of the second external module, and transmitting the read current sub-data to the second external module; Calculating a remaining read length according to the second total length of the data to be read and the length of the sub-data that has been read; If the remaining read length is not 0, obtaining the next to-be-read address of the current to-be-read address according to the association relationship between the current to-be-read sub-data and the cache address of the next to-be-read sub-data; The next address to be read is used as the current address to be read, and the steps of reading the current sub-data to be read from the data cache space according to the current address to be read and the access rate of the second external module, and transferring the read current sub-data to the second external module and subsequent steps are performed until the remaining read length is 0.

5. The data cache space management method according to claim 3, characterized in that: The data cache space management method also includes: The sub-cache space of the sub-data that has been read out is reclaimed.

6. The data cache space management method according to claim 1, characterized in that: Before obtaining the current free address information of the data cache space, the data cache space management method further includes: The data cache space is divided into multiple sub-cache spaces according to the data access granularity, and a unique cache address is assigned to each sub-cache space.

7. A data cache space management system, characterized in that: The management system of the data cache space includes: a write command control module, a first address control module and a second address control module; The write command control module is configured to obtain a first total length of data to be written in the write access request if a write access request from a first external module is obtained; The write command control module is further used to obtain current free address information of the data cache space through the first address control module; The write command control module is further used to write the data to be written into the idle data cache space corresponding to the current idle address information in batches according to the access rate of the first external module and the first total length; The first address control module is used to store the cache address of the sub-cache space where the sub-data written each time is located; The second address control module is used to store the association relationship between the cache addresses of two adjacent sub-data written in the same write access request.

8. The data cache space management system according to claim 7, characterized in that: The management system of the data cache space also includes: a read command control module; The read command control module is used to obtain a second total length and a starting read address of the data to be read in the read access request if a read access request from the second external module is obtained; The read command control module is also used to read each sub-data to be read out from the data cache space in sequence starting from the starting read address based on the second total length, the access rate of the second external module and the association between the cache addresses of each sub-data to be read out in the data to be read out obtained from the second address control module.

9. A computer device, characterized in that: The computer device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory to enable the computer device to execute the data cache space management method according to any one of claims 1 to 6.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by the processor, the method for managing the data cache space as described in any one of claims 1 to 6 is implemented.

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