A sensitivity design method for an ultra-wide frequency range, high sensitivity receiver

Abstract

The application discloses a sensitivity design method of an ultra-wide frequency range and high-sensitivity receiver, which comprises the following steps: step 1, according to the design values of the sensitivity, radio frequency bandwidth and minimum demodulation signal-to-noise ratio of the ultra-wide frequency range and high-sensitivity receiver, the initial design of the receiver is completed, and the receiver is composed of multiple cascaded modules; step 2, the maximum system noise coefficient of the receiver designed in step 1 is calculated; step 3, according to the index requirements of each cascaded module, the maximum system noise coefficient of the receiver is distributed to each cascaded module; step 4, according to the distribution result of step 3, the device selection and circuit design of each cascaded module are optimized to realize the noise coefficient requirements of each cascaded module; and step 5, the sensitivity index of the receiver obtained after the optimization in step 4 is calculated, if the design requirements are met, the design is completed, otherwise, step 3 is returned, the system noise coefficient distribution is adjusted, and the design requirements are met until the sensitivity index meets the design requirements.

Description

Technical Field

[0001] This invention belongs to the field of microwave receiver design technology, and specifically relates to a sensitivity design method for a receiver with an ultra-wide frequency range and high sensitivity. Background Technology

[0002] A receiver is an electronic device that receives radio signals. It is widely used in wireless communication systems in various fields, and its performance plays a decisive role in the reliability of wireless communication systems.

[0003] To simulate real electromagnetic signals from various equipment and various environmental interference signals, and to achieve real-time detection and storage of spectrum signals or electromagnetic interference signals in different frequency bands, the receiver needs to have the ability to detect and monitor signals over an ultra-wide frequency range.

[0004] Furthermore, when equipment is in extreme environments, electromagnetic signals may be interfered with by various factors, such as weather, geographical location, electromagnetic shielding interference, and electromagnetic activity in space. To ensure stable reception of information across different frequency bands even in weak signal environments, ultra-wide frequency range receivers require high sensitivity. However, currently, the sensitivity specifications of most receivers are obtained through measurement after development, rarely taking them into account during the receiver design phase. Especially for ultra-wide frequency range receivers, which require a frequency segmentation design approach and contain multiple RF links and cascaded modules, thorough design and optimization of sensitivity specifications are essential during the design phase. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide a sensitivity design method for an ultra-wide frequency range, high-sensitivity receiver. First, the sensitivity index allocation and design of the whole machine are completed by theoretical demonstration. Then, the sensitivity index of the whole machine is calculated based on the actual device parameters. The calculation results are then fed back for optimization, and finally the sensitivity design of the ultra-wide frequency range, high-sensitivity receiver is realized, so that the obtained receiver can still stably receive information of different frequency bands in a weak signal environment.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A sensitivity design method for an ultra-wide frequency range, high-sensitivity receiver includes the following steps:

[0008] Step 1: Based on the design values ​​of ultra-wide frequency range, high sensitivity receiver sensitivity, RF bandwidth and minimum demodulation signal-to-noise ratio, complete the initial design of the receiver, which consists of multiple cascaded modules;

[0009] Step 2: Calculate the maximum system noise figure of the receiver designed in Step 1;

[0010] Step 3: Based on the performance requirements of each inductor module, allocate the maximum system noise figure of the receiver to each inductor module;

[0011] Step 4: Based on the allocation results in Step 3, optimize the component selection and circuit design of each stage of the cascade module to achieve the noise figure requirements of each stage of the cascade module;

[0012] Step 5: Calculate the sensitivity index of the receiver obtained after optimization in Step 4. If it meets the design requirements, the design is completed; otherwise, return to Step 3 and adjust the system noise figure distribution until the sensitivity index meets the design requirements.

[0013] In one embodiment, step 1 has an ultra-wide frequency range of 30MHz to 26.5GHz. The receiver adopts a design method of radio frequency receiving link, analog-to-digital conversion and digital signal processing. It consists of a radio frequency front-end and an ADC analog-to-digital converter. The radio frequency front-end is divided into 5 cascaded modules, and the ADC analog-to-digital converter is regarded as a device with noise characteristics as the 6th cascaded module.

[0014] In one embodiment, the RF front end adopts a frequency segmentation design method. In the 30MHz to 1.4GHz frequency band, a signal direct-to-ADC analog-to-digital converter design is adopted, i.e., a direct-through channel. In other frequency bands, a superheterodyne frequency conversion circuit design is adopted to downconvert signals of different input frequencies to fixed intermediate frequency signals, i.e., a frequency conversion channel.

[0015] In one embodiment, for either a through-channel or a frequency conversion channel, the division of the RF front-end into 5 cascaded modules is as follows:

[0016] The first-stage cascade module consists of all components from the input port of the receiving channel to the first-stage amplifier, including fixed attenuators, switches, and digitally controlled attenuators; the second-stage cascade module is the first-stage amplifier; the third-stage cascade module consists of all components between the first-stage amplifier and the second-stage amplifier; the fourth-stage cascade module is the second-stage amplifier; and the fifth-stage cascade module is the RF channel combination circuit.

[0017] In one embodiment, the frequency conversion channel is divided into three frequency bands: 0.4GHz to 3GHz, 2GHz to 18GHz, and 17GHz to 26.5GHz. The common circuit for the three frequency bands is the first-level cascade module to the fourth-level cascade module, and the fifth-level cascade module is the circuit of each frequency band.

[0018] In one embodiment, step 2 involves calculating the maximum system noise figure of the receiver using the following formula:

[0019]

[0020] Among them, NFmax Represents the maximum system noise figure. and The values ​​for sensitivity, RF bandwidth, and minimum demodulation signal-to-noise ratio are represented by NF, respectively. max The value represents the upper limit of receiver system noise that meets the receiver sensitivity design requirements.

[0021] In one embodiment, step 3, while meeting the design specifications of each cascade module, allocates the smallest possible noise figure to the preceding cascade module and maximizes the gain of each cascade module, with the receiver's maximum system noise figure NF. max The noise figure and power gain of each cascade module satisfy the following relationship:

[0022]

[0023] F n G is the noise figure of the nth cascaded module. n-1 It is the power gain of the (n-1)th cascaded module, where n is the total number of cascaded modules.

[0024] In one embodiment, step 4 involves optimizing the following approach: first, determining the ADC (Analog-to-Digital Converter) device selection; then, calculating the system noise of the ADC; and finally, optimizing the system noise and gain of the RF front-end to ensure that the overall noise figure is within the required range.

[0025] In one embodiment, the sensitivity index is calculated using the maximum gain of the receiving link, as follows:

[0026] Calculate the sensitivity indicators of the direct-through channel and the frequency conversion channel separately;

[0027] The noise figure and gain of each stage of the cascade module are determined by the parameters of the actual RF devices and ADC analog-to-digital converters used.

[0028] In one embodiment, the noise figure of the ADC is calculated using the following formula:

[0029] F AD =FSIP-NSD-(-174)

[0030] Among them, F AD The noise figure of the ADC is represented by , FSIP represents the full-load power of the ADC, and NSD represents the noise density of the ADC.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] (1) The present invention divides the ultra-wideband microwave signal into different channels with different frequency bands. First, the sensitivity index allocation and design of the whole machine is completed channel by channel by theoretical demonstration. Then, the sensitivity index of the whole machine is calculated channel by channel based on the actual device parameters, and the design is optimized according to the calculation results.

[0033] (2) The present invention can comprehensively consider the frequency range, sensitivity index and other indexes of the receiver, and use the iterative method to find the compromise between the design of each index and complete the optimal design.

[0034] (3) The present invention can meet the requirements of real-time detection and storage of spectrum signals or electromagnetic interference signals of different frequency bands, and can also meet the requirements of stable information reception in weak signal environments. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0036] Figure 1 This is a flowchart of a sensitivity design and calculation method for an ultra-wide frequency range, high-sensitivity receiver proposed according to the present invention.

[0037] Figure 2 This is a schematic diagram of the cascaded system noise model according to the present invention.

[0038] Figure 3 This is a schematic diagram of the frequency segmentation design of the receiver RF front-end according to the present invention.

[0039] Figure 4 This is a schematic diagram of the noise model of the receiver ADC analog-to-digital converter module system according to the present invention.

[0040] Figure 5 These are the receiver through-channel cascaded NF calculation parameters according to an embodiment of the present invention.

[0041] Figure 6 These are the receiver frequency conversion channel cascade NF calculation parameters according to an embodiment of the present invention. Detailed Implementation

[0042] To better illustrate the purpose and advantages of the present invention, the present invention will be described clearly and completely below with reference to the accompanying drawings and embodiments.

[0043] To fully optimize sensitivity parameters during the design phase, this invention provides a receiver sensitivity design method. In this invention, the receiver refers to an ultra-wide frequency range, high-sensitivity receiver. The ultra-wide frequency range is defined as 30MHz to 26.5GHz, and high sensitivity is defined as a sensitivity of less than -120dBm.

[0044] The technical approach of this invention can be generally described as follows:

[0045] First, the receiver initial design is completed using a frequency segmentation approach, and the maximum noise figure is calculated based on the receiver's RF design bandwidth and the minimum demodulation signal-to-noise ratio. Second, the maximum noise figure is allocated to each stage of the in-line module according to the receiver initial design. Third, the receiver design is optimized step by step based on the allocation results of the maximum noise figure, and the selection of components and circuit design are adjusted. Finally, the sensitivity index of the whole machine is calculated based on the actual component parameters, and iterative optimization is performed until the sensitivity index of the whole machine meets the design requirements.

[0046] Specifically, refer to Figure 1 The receiver sensitivity design method of the present invention mainly includes the following steps:

[0047] The first step is to complete the initial design of the receiver based on the design values ​​of ultra-wide frequency range, high sensitivity, RF bandwidth, and minimum demodulation signal-to-noise ratio.

[0048] In this invention, because the receiver has an ultra-wide frequency range and analysis bandwidth, the receiver is usually designed using a frequency segmentation method and consists of multiple cascaded modules.

[0049] As one possible implementation, the ultra-wide frequency range high-sensitivity receiver of this invention, with a frequency range of 30MHz to 26.5GHz, employs a design method of RF receiving link, analog-to-digital conversion, and digital signal processing, mainly composed of an RF front-end and an ADC (Analog-to-Digital Converter). The RF front-end is divided into five cascaded modules: switching attenuation, first-stage amplification, attenuation, second-stage amplification, and circuit combination. The ADC is cascaded with the RF front-end and can therefore be considered as a device with noise characteristics, serving as the sixth cascaded module. The system noise model of the ADC module is as follows: Figure 2 As shown.

[0050] The radio frequency front-end of this invention adopts a frequency segmentation design method. Within the 30MHz to 1.4GHz frequency band, to avoid the influence of spurious signal components, a direct-to-ADC design is used, i.e., a direct-through channel. In the remaining frequency bands, a superheterodyne frequency conversion circuit design is used to down-convert signals of different input frequencies to a fixed intermediate frequency signal, i.e., a frequency conversion channel. Specifically, it is divided into three frequency bands: 0.4GHz to 3GHz, 2GHz to 18GHz, and 17GHz to 26.5GHz. Figure 3 As shown. Within the aforementioned ultra-wide frequency range, from the direct channel to the frequency conversion channel, there are cross-bands between adjacent frequency bands. In this embodiment of the invention, the frequency range of the cross-band is 1 GHz, thereby satisfying the requirement of having a 1 GHz bandwidth at any frequency point.

[0051] Regardless of whether it's a through-channel or a frequency conversion channel, this invention divides the RF front-end into 5 cascaded modules, the specific implementation of which is as follows:

[0052] The first-stage cascade module consists of all components from the input port of the receiving channel to the first-stage amplifier, mainly including fixed attenuators, switches, digitally controlled attenuators, etc.; the second-stage cascade module is the first-stage amplifier; the third-stage cascade module consists of all components between the first-stage amplifier and the second-stage amplifier; the fourth-stage cascade module is the second-stage amplifier; and the fifth-stage cascade module is the RF channel combination circuit.

[0053] As one possible implementation, the common circuit for the three frequency bands of the frequency conversion channel of this invention consists of cascaded modules from the first stage to the fourth stage, with the fifth stage containing its own circuitry. Thus, the components of the through-channel mainly include filters, attenuators, and amplifiers, while the components of the frequency conversion channel include all the components of the common circuit, such as the first-stage amplifier and attenuator, switches, the second-stage amplifier and attenuator, and the combined circuits such as switches, filters, and mixers used in each frequency band.

[0054] The second step is to calculate the maximum system noise figure of the receiver designed in the first step, based on the design values ​​of RF bandwidth and minimum demodulation signal-to-noise ratio.

[0055] The formula for calculating receiver sensitivity is:

[0056] S = -174 + NF + SNR min +10log(BW)

[0057] Where S is the calculated receiver sensitivity, -174 dBm / Hz is the thermal noise power spectral density at room temperature, NF is the system noise figure, and SNR is the signal strength. min BW is the minimum demodulation signal-to-noise ratio of the receiver, and BW is the radio frequency bandwidth.

[0058] Therefore, the formula for calculating the maximum system noise figure of the receiver is:

[0059] Among them, NF max Represents the maximum system noise figure. and The values ​​for sensitivity, RF bandwidth, and minimum demodulation signal-to-noise ratio are represented by NF, respectively. max The value represents the upper limit of receiver system noise that may meet the receiver sensitivity design requirements.

[0060]

[0061] Among them, NF max Represents the maximum system noise figure. and The values ​​for sensitivity, RF bandwidth, and minimum demodulation signal-to-noise ratio are represented by NF, respectively. max The value represents the upper limit of receiver system noise that can meet the receiver sensitivity design requirements.

[0062] As one possible implementation, the receiver of this invention has a frequency range of 30MHz to 26.5GHz and a sensitivity design specification of -125dBm / kHz. The receiver is required to achieve a minimum signal-to-noise ratio (SNR) of 3dB for signal recognition. min =3dB. To improve receiver sensitivity, the system noise figure should be as low as possible in the design. With a design bandwidth of 1kHz, the maximum system noise figure is: [The maximum system noise figure would be:]

[0063]

[0064] That is, when the system noise figure is less than 16dB, the receiving sensitivity can be less than -125dBm / kHz.

[0065] The third step is to allocate the receiver's maximum system noise figure to each in-line module according to the performance requirements of each in-line module.

[0066] like Figure 4 As shown, the total noise figure F of the n-stage cascaded module is related to the noise figure and power gain of each stage of the cascaded module. In this step, the maximum system noise figure NF of the receiver is... max As the total noise figure F, we have:

[0067]

[0068] F n G is the noise figure of the nth cascaded module. n-1 It is the power gain of the (n-1)th cascaded module, where n is the total number of cascaded modules.

[0069] Since the noise figure of a cascaded module is primarily determined by the noise figure of its preceding stages, a smaller noise figure and higher power gain in the preceding stages will result in a smaller noise figure for the cascaded module. Therefore, allocating the system noise figure F requires comprehensive consideration of sensitivity specifications and the design specifications of each cascaded module. The goal is to allocate the smallest possible noise figure to the preceding cascaded modules while maximizing the gain of each cascaded module, all while meeting the design specifications of each cascaded module.

[0070] Because of the design approach employing RF receiver links, analog-to-digital conversion, and digital signal processing, the noise figures of each stage of the system's interconnected modules can be allocated according to the formulas described above. Specifically, the receiver links of this receiver, whose noise figures are related, can be summarized as the RF front-end and the ADC (Analog-to-Digital Converter).

[0071] As one possible implementation, sensitivity specifications for ultra-wide frequency range high-sensitivity receivers are allocated, requiring the RF front-end to have a noise figure (NF) within 10dB and a receiver link gain greater than 70dB; and requiring the ADC (analog-to-digital converter) to have a noise spectral density less than -150dBfs / Hz. These requirements are the result of a comprehensive consideration of project requirements and sensitivity specifications.

[0072] The fourth step is to optimize the design of the ultra-wide frequency range, high-sensitivity receiver based on the allocation results of the previous step. That is, by optimizing and adjusting the component selection and circuit design of each stage of the cascade module, the noise figure requirements of each stage of the cascade module are met, thereby achieving the sensitivity and other performance requirements of the entire system.

[0073] As one possible implementation, the noise figure of an ADC (Analog-to-Digital Converter) is calculated from its noise spectral density. Typically, the noise figure of an ADC is above 20dB. From the perspective of cascading an ADC in an RF circuit, to prevent the ADC's noise figure from significantly affecting the system noise figure, the gain should be optimized in the RF front-end design to keep the overall noise figure within the required range. The specific optimization approach involves first determining the ADC device selection, then calculating the ADC's system noise based on the selection, and finally optimizing the system noise and gain values ​​of the RF front-end.

[0074] The fifth step is to calculate the sensitivity index based on the optimized receiver design. If the receiver sensitivity index meets the design requirements, the design is complete. If the sensitivity index does not meet the design requirements, return to the third step, adjust the system noise distribution, and perform optimization design and index calculation again until the sensitivity index meets the design requirements.

[0075] As one possible implementation, the receiver of this invention receives the signal, adjusts the signal to a certain power through a direct-through channel or a frequency conversion channel, inputs it to an ADC (Analog-to-Digital Converter), and then outputs it for subsequent signal processing. The worst-case scenario where signal processing is possible is that even though the gain of the RF channel has reached its maximum, the input power can only reach -110dBm, i.e., the minimum input power. At this point, the RF channel gain is at its maximum; therefore, the maximum gain of the receiver link is used in the receiver sensitivity calculation.

[0076] As one possible implementation, when calculating the sensitivity index using the maximum gain of the receiving link, the parameters of the first stage are the total attenuation of the fixed attenuator, switch, digitally controlled attenuator, etc. before the first stage amplifier at the input port of the receiving channel; the parameters of the second stage are the performance parameters of the first stage amplifier; the parameters of the third stage are the attenuation after the first stage amplifier; the parameters of the fourth stage are the performance parameters of the second stage amplifier; the parameters of the fifth stage are the parameters of the subsequent RF channel combination circuit; and the parameters of the sixth stage are the parameters of the ADC analog-to-digital converter.

[0077] First, the noise figure and gain of the six-stage cascaded module of the receiver link are calculated. These are determined by the actual RF devices used in the receiver design, such as amplifiers, digitally controlled attenuators, switches, filters, and the parameters of the ADC analog-to-digital converter.

[0078] The ADC (Analog-to-Digital Converter) selected in the design has a noise spectral density of -151 dBfs / Hz, a full-scale input power of 2 dBm, and a dynamic range of 85 dB. After conversion, its noise figure is 25 dB. The noise figure and gain values ​​for each of the other RF circuit stages are given after combining several components, as shown in the table below.

[0079] Table 1. NF and gain at each level of the through channel

[0080]

[0081] Then, software was used for calculation, with the noise bandwidth (NOISE BW) set to 0.001MHz, S / N to 3dB, and the preset temperature for the calculated values ​​to be 25℃. The calculation parameters are as follows: Figure 5 As shown.

[0082] The calculation results show that the noise figure of the direct-connect receiver link is 8.02dB and the noise floor is -165.96dBm / Hz. Therefore, within a 1kHz bandwidth, its sensitivity is -132.96dBm, which meets the requirement of -125dBm / kHz.

[0083] Furthermore, when the receiver operates at its widest 1GHz bandwidth, the gain of the direct-connect receiver link is 78dB. Therefore, the total output power of the channel is -165.96 + 78 + 90 = 2.04dBm, and the useful signal output power is -110 + 78 = -32dBm. It can be seen that under this gain condition, the channel output power is within the ADC's operating range. The channel operates normally at its widest signal bandwidth, and it also operates normally at other smaller bandwidths.

[0084] As one possible implementation, the sensitivity of the frequency conversion channel is calculated using the same method as the direct-through channel. For the three frequency bands of the frequency conversion channel (0.4GHz~4GHz, 3GHz~18GHz, 17GHz~26.5GHz), the common circuitry for each frequency band is from stage 1 to stage 4. Stage 5 is a custom circuit, and stage 6 is an ADC (Analog-to-Digital Converter). The noise figure and gain of each cascaded module are determined by the actual RF components used in the design, such as amplifiers, attenuators, switches, filters, mixers, etc., as well as the parameters of the ADC. It is evident that stages 1 to 4 and stage 6 are shared across the three frequency bands, so their noise figures and gain data are identical. The gain of stage 5 is also designed to be a consistent value, while the noise figure varies from 12dB to 14dB. Therefore, in the calculation, the worst value of 14dB is used as the noise figure value for circuit #5.

[0085] Similarly, the ADC selected for the design has a noise figure of 25dB, as shown in the table below:

[0086] Table 2 NF and gain of each stage of the frequency converter channel

[0087]

[0088] Then, software was used for calculation, with the noise bandwidth (NOISE BW) set to 0.001MHz, S / N to 3dB, and the preset temperature for the calculated values ​​to be 25℃. The calculation parameters are as follows: Figure 6 As shown.

[0089] The calculation results show that the noise figure of the frequency conversion receiving link is 9.85dB, that is, the noise floor of the system is -164.13dBm / Hz. Therefore, within a 1kHz bandwidth, its sensitivity is -131.13dBm, which meets the requirement that the receiving sensitivity is less than -125dBm / kHz.

[0090] Furthermore, when the receiver operates at the widest 1GHz bandwidth, the gain of the frequency conversion receiving link is 76dB. Therefore, the total output power of the channel is -164.13 + 76 + 90 = 1.87dBm, and the useful signal output power is -110 + 76 = -34dBm. It can be seen that under this link gain condition, the channel output power is also within the ADC's operating range. The channel operates normally under the widest signal bandwidth, and it also operates normally under other smaller bandwidths.

[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A sensitivity design method for an ultra-wide frequency range, high-sensitivity receiver, characterized in that, Includes the following steps: Step 1: Based on the design values ​​of ultra-wide frequency range, high sensitivity receiver sensitivity, RF bandwidth and minimum demodulation signal-to-noise ratio, complete the initial design of the receiver, which consists of multiple cascaded modules; Step 2: Calculate the maximum system noise figure of the receiver designed in Step 1. The formula is: Among them, NF max Represents the maximum system noise figure. and The values ​​for sensitivity, RF bandwidth, and minimum demodulation signal-to-noise ratio are represented by NF, respectively. max The value represents the upper limit of receiver system noise that meets the receiver sensitivity design requirements; Step 3: Based on the performance requirements of each inductor module, allocate the maximum system noise figure of the receiver to each inductor module; While meeting the design specifications of each cascade module, allocate the smallest possible noise figure to the front-end cascade module and maximize the gain of each cascade module. The maximum system noise figure NF of the receiver is [missing value]. max The noise figure and power gain of each cascade module satisfy the following relationship: F n G is the noise figure of the nth cascaded module. n-1 It is the power gain of the (n-1)th cascaded module, where n is the total number of cascaded modules; Step 4: Based on the allocation results in Step 3, optimize the component selection and circuit design of each cascade module to achieve the noise figure requirements of each cascade module; the optimization approach is as follows: First, determine the selection of ADC analog-to-digital converter components, then calculate the system noise of the ADC analog-to-digital converter, and then optimize the system noise and gain value of the RF front end to make the overall noise figure within the required range; Step 5: Calculate the sensitivity index of the receiver obtained after optimization in Step 4. If it meets the design requirements, the design is completed; otherwise, return to Step 3 and adjust the system noise figure distribution until the sensitivity index meets the design requirements.

2. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 1, characterized in that, In step 1, the ultra-wide frequency range is 30MHz to 26.5GHz. The receiver adopts a design method of radio frequency receiving link, analog-to-digital conversion and digital signal processing. It consists of radio frequency front-end and ADC analog-to-digital converter. The radio frequency front-end is divided into 5 cascaded modules. The ADC analog-to-digital converter is regarded as a device with noise characteristics and is used as the 6th cascaded module.

3. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 2, characterized in that, The radio frequency front end adopts a frequency segmentation design method. In the 30MHz to 1.4GHz frequency band, a signal direct-to-ADC analog-to-digital converter design is adopted, i.e., a direct-through channel. In other frequency bands, a superheterodyne frequency converter circuit design is used to downconvert signals of different input frequencies into fixed intermediate frequency signals, i.e., frequency conversion channels.

4. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 3, characterized in that, For both through-channel and frequency conversion channels, the division of the RF front-end into 5 cascaded modules is as follows: The first-stage cascade module consists of all components from the input port of the receiving channel to the first-stage amplifier, including fixed attenuators, switches, and digitally controlled attenuators; the second-stage cascade module is the first-stage amplifier; the third-stage cascade module consists of all components between the first-stage amplifier and the second-stage amplifier; the fourth-stage cascade module is the second-stage amplifier; and the fifth-stage cascade module is the RF channel combination circuit.

5. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 4, characterized in that, The frequency conversion channel is divided into three frequency bands: 0.4GHz to 3GHz, 2GHz to 18GHz, and 17GHz to 26.5GHz. The common circuit for the three frequency bands is the first-level cascade module to the fourth-level cascade module, and the fifth-level cascade module is the circuit of each frequency band.

6. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 3, characterized in that, The sensitivity index is calculated using the maximum gain of the receiving link, as follows: Calculate the sensitivity indicators of the direct-through channel and the frequency conversion channel separately; The noise figure and gain of each stage of the cascade module are determined by the parameters of the actual RF devices and ADC analog-to-digital converters used.

7. The sensitivity design method for the ultra-wide frequency range, high-sensitivity receiver according to claim 1, characterized in that, The noise figure calculation formula for the ADC analog-to-digital converter is as follows: F AD =FSIP-NSD-(-174) Among them, F AD The noise figure of the ADC is represented by , FSIP represents the full-load power of the ADC, and NSD represents the noise density of the ADC.

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