Display device

Abstract

A display device includes: a display panel including a plurality of blocks in which pixels are arranged in each block; and an afterimage compensation circuit configured to receive an input image signal and generate a compensated image signal by compensating the input image signal based on degradation information for each of the plurality of blocks, a storage area including a first storage area that accumulates degradation data for each of the plurality of blocks at each of a plurality of backup times in a preset backup period and a second storage area that stores information on a final backup time among the plurality of backup times; and a compensation unit configured to receive the cumulative degradation data stored in the first storage area as degradation information and compensate the input image signal based on the cumulative degradation data to generate a compensated image signal.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device capable of compensating for an afterimage. Background Art

[0002] Among the display devices, light emitting display devices use light emitting diodes that generate light through recombination of electrons and holes. These display devices offer advantages such as fast response speed and low power consumption.

[0003] The light-emitting display device includes a display panel having pixels arranged along data lines and scan lines. Each pixel generally includes a light-emitting diode and a pixel circuit that regulates the current flowing through the light-emitting diode. The pixel circuit adjusts the current in response to a data signal, thereby causing the emission of light with a predetermined brightness corresponding to the current level. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device capable of effectively compensating for afterimages even when operating at a low frequency.

[0005] According to an embodiment of the present disclosure, a display device is provided, which includes: a display panel including a plurality of blocks, wherein a plurality of pixels are arranged in each block; and an afterimage compensation circuit configured to receive an input image signal and generate a compensated image signal by compensating the input image signal based on degradation information for each of the plurality of blocks, wherein the afterimage compensation circuit includes: a non-volatile memory including a first storage area accumulating degradation data for each of the plurality of blocks at each of a plurality of backup times in a preset backup period and a second storage area storing information about a final backup time among the plurality of backup times; and a compensation unit configured to receive the accumulated degradation data stored in the first storage area as the degradation information, and compensate the input image signal based on the accumulated degradation data to generate the compensated image signal.

[0006] The afterimage compensation circuit further includes: a sampling unit configured to set a sampling line and sample a line image signal originating from the sampling line based on the compensation image signal; a data processing unit configured to generate degradation data for the sampling line based on the line image signal; and a volatile memory configured to store the degradation data.

[0007] The sampling unit sequentially selects one of the sampling lines in units of reference frames.

[0008] The reference frame includes a frame.

[0009] The final backup time is the last backup time just before power is turned off, and when power is turned on, the sampling unit sets a reference sampling line among the sampling lines based on information about the final backup time and starts a sampling operation from the reference sampling line.

[0010] The information about the final backup time includes at least one of the number of a final reference frame at the final backup time, the number of a final sampling line at the final backup time, and the number of blocks included in the final sampling line.

[0011] The plurality of blocks are arranged in a first direction and a second direction intersecting the first direction, and the sampling line extends in the first direction or the second direction.

[0012] Each of the plurality of blocks includes a plurality of sub-blocks arranged in a first direction and a second direction, and wherein the sampling unit samples a compensated image signal corresponding to a first sub-block of a block in a first sampling line included in a first reference frame as a first line image signal, and samples a compensated image signal corresponding to a first sub-block of a block in a second sampling line included in a second reference frame as a second line image signal.

[0013] At each of a plurality of backup times, the degraded data stored in the volatile memory is backed up to a first storage area of ​​the nonvolatile memory.

[0014] Each of the plurality of blocks includes a plurality of sub-blocks, and wherein the sampling unit performs sampling on one sub-block included in each of the blocks located on a selected sampling line among the sampling lines.

[0015] The display panel includes: a first display area operating at a first frequency; and a second display area operating at a second frequency lower than the first frequency.

[0016] The first display area displays an image in units of a first driving frame, the second display area displays an image in units of a second driving frame, and the second driving frame includes a full frame and one or more partial frames.

[0017] The sampling unit sequentially selects one of the sampling lines in units of reference frames, and the reference frame is set based on the full frame.

[0018] The duration of the preset backup period varies depending on the time that has elapsed since power was turned on.

[0019] According to an embodiment of the present disclosure, a display device is provided, which includes: a display panel including a plurality of blocks, wherein a plurality of pixels are arranged in each block; and an afterimage compensation circuit configured to receive an input image signal and generate a compensated image signal by compensating the input image signal based on degradation information for each of the plurality of blocks, wherein the afterimage compensation circuit includes: a non-volatile memory that accumulates degradation data for each of the plurality of blocks at each of a plurality of backup times in a preset backup period; a compensation unit configured to receive the accumulated degradation data as the degradation information from the non-volatile memory, and compensate the input image signal based on the accumulated degradation data to generate the compensated image signal; and a backup period adjustment unit configured to change the duration of the preset backup period based on a driving frequency of the display panel.

[0020] The display panel operates above a reference frequency in a first driving mode and operates at a frequency lower than the reference frequency in a second driving mode, and wherein the backup period adjustment unit adjusts the duration of a preset backup period in the second driving mode to be greater than the duration of the preset backup period in the first driving mode.

[0021] The display panel includes: a first display area, operating at a first frequency; and a second display area, operating at a second frequency lower than the first frequency, and wherein the first display area displays an image in units of a first drive frame, the second display area displays an image in units of a second drive frame, and the second drive frame includes a full frame and one or more partial frames.

[0022] The backup period adjustment unit sets a duration of a preset backup period based on the second frequency.

[0023] The afterimage compensation circuit further includes: a sampling unit configured to set a sampling line and sample a line image signal corresponding to the sampling line by using the compensation image signal; a data processing unit configured to generate degradation data corresponding to the sampling line by using the line image signal; and a volatile memory configured to store the degradation data.

[0024] At each of a plurality of backup times, the degraded data stored in the volatile memory is backed up to the nonvolatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0026] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0027] Figure 2Ais an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2B is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0029] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 4 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 5A is a timing diagram for describing the operation of a pixel in a first driving mode according to an embodiment of the present disclosure.

[0032] Figure 5B is a timing diagram for describing the operation of a pixel in the second driving mode according to an embodiment of the present disclosure.

[0033] Figure 6 is a block diagram of an afterimage compensation circuit according to an embodiment of the present disclosure.

[0034] Fig. 7A is a plan view of a display panel according to an embodiment of the present disclosure.

[0035] FIG. 7B to FIG. 7D is a diagram illustrating a sampling process of a sampling unit according to an embodiment of the present disclosure.

[0036] Figure 8 and Fig. 9 is a diagram for describing a sampling operation according to an embodiment of the present disclosure.

[0037] Fig.10 is a flowchart illustrating an operation process of an afterimage compensation circuit according to an embodiment of the present disclosure.

[0038] Fig.11A is a plan view illustrating a screen of a display device according to an embodiment of the present disclosure.

[0039] Fig. 11B is a diagram for describing an operation of a display device in a normal frequency mode according to an embodiment of the present disclosure.

[0040] Fig. 11C is a diagram for describing an operation of a display device in a multi-frequency mode according to an embodiment of the present disclosure.

[0041] Fig.12 is a block diagram of an afterimage compensation circuit according to an embodiment of the present disclosure.

[0042] Fig.13is a diagram illustrating differently set backup periods in a first driving mode and a second driving mode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In the specification, when a component (or region, layer, portion, etc.) is referred to as being "on", "connected to" or "coupled to" another component, it should be understood that the first component may be directly on, directly connected to or directly coupled to the second component, or there may be intervening components therebetween.

[0044] The same reference numerals refer to similar components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to clearly describe the technical content. The term "and / or" refers to one or more combinations of the associated listed items.

[0045] For the purpose of distinction, the terms "first", "second", etc. are used to describe various components, but do not imply any limitation on the components. For example, a component referred to as "first" may be renamed as "second", and vice versa. Unless otherwise specified, singular terms include plural forms.

[0046] The terms "under", "beneath", "on", "over", etc. are used to describe the positional relationships of components as illustrated in the drawings. These terms are relative and are used with reference to the orientation shown in the drawings.

[0047] It will be understood that the terms “includes,” “comprising,” “having,” etc. indicate the presence of features, quantities, steps, operations, elements or components, or a combination thereof, described in the specification, but do not exclude the possibility of additional features, quantities, steps, operations, elements or components, or a combination thereof.

[0048] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this article have the meanings commonly understood by technicians in the relevant fields. In addition, unless explicitly defined in the present disclosure, the terms defined in the commonly used dictionaries should be interpreted in accordance with their meanings in the context of the relevant technology and should not be interpreted as overly formal or idealized definitions.

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0051] Reference Figure 1, the electronic device ED according to an embodiment of the present disclosure may have a rectangular shape having short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto, and the electronic device ED may have various shapes such as a circular shape or other polygonal shapes.

[0052] The electronic device ED may be a device that operates based on an electrical signal. The electronic device ED may include various forms and applications. For example, the electronic device ED may be applied to electronic devices such as smart phones, smart watches, computers (e.g., tablet computers, notebook computers), smart TVs, and navigation systems.

[0053] Hereinafter, a normal direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is referred to as a third direction DR3. In this specification, "when viewed in a plan view" refers to a viewing angle from the third direction DR3.

[0054] An upper surface of the electronic device ED may be referred to as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the electronic device ED may be presented to a user through the display surface IS.

[0055] The display surface IS may be divided into a transparent area TA and a frame area BZA. The transparent area TA may be an area where an image IM is displayed, thereby allowing a user to visually perceive the image IM. In the present embodiment, the transparent area TA is illustrated as a quadrilateral whose vertices are rounded. However, this is merely an example; the transmissive area TA may have various shapes and is not limited to any one embodiment.

[0056] The border area BZA is adjacent to the transparent area TA. The border area BZA may have a specific color. The border area BZA may surround the transparent area TA, thereby defining the shape of the transparent area TA. However, the border area BZA is illustrated by way of example. The border area BZA may be provided only close to one side of the transparent area TA or may be completely omitted.

[0057] The electronic device ED is capable of detecting external inputs from the surrounding environment. These external inputs may include various types of inputs such as physical contact with a part of the user's body like a hand or contact with a separate device such as an active pen or a digitizer. In addition, the external inputs may include actions such as hovering near the electronic device ED or adjacent to it at a predetermined distance. The external inputs may also take various forms including force, pressure, temperature, and light.

[0058] Figure 2A is an exploded perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 2Bis a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0059] Reference Figure 2A and Figure 2B , the electronic device ED may include a display device DD, an electronic module and a housing EDC. The display device DD may include a window WM and a display module DM, and may be accommodated in the housing EDC. In this embodiment, the window WM and the housing EDC are combined to form the appearance of the electronic device ED.

[0060] The front surface of the window WM defines the display surface IS of the electronic device ED. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multi-layer or single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other by an adhesive or may include a glass substrate and a plastic film bonded to each other by an adhesive.

[0061] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0062] The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0063] Reference Figure 2B , the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. According to the present disclosure, the display panel DP may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel or a rigid display panel folded about a folding axis.

[0064] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material of the synthetic resin layer is not particularly limited. As another example, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0065] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL is disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes a circuit element and at least one insulating layer. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The external information may be biometric information. As an example of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, or an illumination sensor. In addition, the sensor may be an optical sensor that optically recognizes biometric information. The circuit layer DP_CL may further include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0066] The element layer DP_ED may include a light emitting element included in each pixel and a light receiving element included in each sensor. As an example of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that detects light reflected by or responds to a user's fingerprint. In other words, the light receiving element may be a sensor designed to detect light reflected from or respond to a user's fingerprint.

[0067] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The inorganic layer includes an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic layer may include but is not particularly limited to a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0068] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to an embodiment of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a continuous process. For example, when the input sensing layer ISL is directly disposed on the display panel DP, the adhesive film is not disposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be disposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL is not manufactured with the display panel DP by a continuous process, but is manufactured with the display panel DP by a separate process and may then be fixed to the upper surface of the display panel DP with an adhesive film.

[0069] The input sensing layer ISL may sense an external input (e.g., a user's touch) and convert it into a predetermined input signal. Then, the input signal is provided to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input in a capacitive manner. The display panel DP may receive an input signal from the input sensing layer ISL and may generate an image corresponding to the input signal.

[0070] The display module DM may further include an anti-reflection layer ARL. The anti-reflection layer ARL reduces the reflectivity of external light incident from the upper side of the window WM. As an example of the present disclosure, the anti-reflection layer ARL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. The anti-reflection layer ARL may be disposed between the display panel DP and the input sensing layer ISL. The anti-reflection layer ARL may include a plurality of color filters and a black matrix. The arrangement of the color filters may be based on a plurality of pixels PX (refer to Figure 3 ) is determined by the color of the light generated by the anti-reflection layer ARL. Alternatively, the anti-reflection layer ARL may include a phase retarder and / or a polarizer. The phase retarder may be a film type or liquid crystal coating type retarder and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or liquid crystal coating type polarizer. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific direction. The phase retarder and the polarizer may be implemented with one polarizing film.

[0071] According to an embodiment of the present disclosure, the display device DD may further include an adhesive layer AL. The window WM may be attached to the anti-reflection layer ARL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure-sensitive adhesive.

[0072] The display module DM may further include a display driving circuit DIC (or a display driving chip) and a flexible circuit film FCB. As an example of the present disclosure, the display driving circuit DIC may be constructed in a chip form and may be mounted on the flexible circuit film FCB. However, the present disclosure is not limited thereto. Alternatively, the display driving circuit DIC may be disposed on the display panel DP.

[0073] The flexible circuit film FCB may be coupled to the display panel DP. The flexible circuit film FCB may be coupled to one end of the display panel DP to electrically connect the display driving circuit DIC to the display panel DP.

[0074] The display module DM may further include a touch driving circuit electrically connected to the input sensing layer ISL.

[0075] The electronic module may include a main circuit board MCB. As an example of the present disclosure, the main circuit board MCB may be electrically connected to the flexible circuit film FCB through a connector CNT. The main circuit board MCB may be equipped with a main processor MCU and a power management circuit PMIC (or a power management chip). The main processor MCU and the power management circuit PMIC may be electrically connected to the display drive circuit DIC through a connector CNT.

[0076] The main processor MCU can control the overall operation of the electronic device ED. The main processor MCU may include one or more of a central processing unit (CPU) and an application processor (AP). The main processor MCU may further include one or more of a graphics processing unit, a communication processor, and an image signal processor. The main processor MCU may provide image signals and various control signals required for displaying images to the display drive circuit DIC.

[0077] The power management circuit PMIC may receive an external power source (e.g., a battery voltage). As an example, the power management circuit PMIC may generate a voltage to be supplied to the display device DD based on the external power source. The power management circuit PMIC may include at least one regulator capable of generating an output voltage having various voltage levels based on the external power source.

[0078] Figure 2A The power management circuit PMIC is shown as a chip mounted on the main circuit board MCB, but the present disclosure is not limited thereto. For example, the power management circuit PMIC may be included in the display device DD, such as being mounted as a chip on a flexible circuit film FCB.

[0079] In addition to the main circuit board MCB, the main processor MCU and the power management circuit PMIC, the electronic module may further include various functional modules such as a camera module and a sensor module.

[0080] The housing EDC is combined with the window WM. The housing EDC is combined with the window WM to provide a predetermined internal space. The display device DD and the electronic module can be accommodated in the internal space of the housing EDC. The housing EDC may include a material with relatively high rigidity. For example, the housing EDC may include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing EDC can reliably protect the display device DD and the components of the electronic module accommodated in the internal space from external impacts.

[0081] A battery module that supplies power required for overall operations of the display device DD may be provided between the display module DM and the case EDC.

[0082] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0083] Reference Figure 3 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 , a scan driving circuit 300 , a light emitting driving circuit 350 , and a voltage generator 400 .

[0084] The drive controller 100 is driven from the main processor MCU (refer to Figure 2A ) receives input image signals RGB and control signals CTRL. The control signals CTRL may include a vertical synchronization signal, an input data enable signal, and a main clock signal. The drive controller 100 generates a first drive control signal SCS, a second drive control signal DCS, and a third drive control signal ECS based on the control signal CTRL. The drive controller 100 may be referred to as a timing controller.

[0085] As an example of the present disclosure, the driving controller 100 may include an afterimage compensation circuit 150. The afterimage compensation circuit 150 receives an input image signal RGB, compensates the input image signal RGB based on degradation information, and generates a compensated image signal RGB′ (refer to Figure 6 The driving controller 100 generates the image data DATA by converting the data format of the compensated image signal RGB′ to comply with the interface specification of the data driving circuit 200 . Figure 3 An example is illustrated in which the afterimage compensation circuit 150 is included in the drive controller 100. However, this is not a limitation; the afterimage compensation circuit 150 can also be configured separately from the drive controller 100.

[0086] The data driving circuit 200 receives the second driving control signal DCS and the image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data DATA. Here, "m" is an integer of 1 or more.

[0087] The scan driving circuit 300 receives a first driving control signal SCS from the driving controller 100. The scan driving circuit 300 may output a scan signal to the scan line in response to the first driving control signal SCS.

[0088] The voltage generator 400 generates voltages for operating the display panel DP. In an embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT.

[0089] The display panel DP includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. In the display area DA, the initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the light emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap with each other. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the light emission control lines EML1 to EMLn extend in a first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the light emission control lines EML1 to EMLn are spaced apart from each other in a second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. Here, "n" is an integer of 1 or more.

[0090] A plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, light emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. Each of the plurality of pixels PX may be electrically connected to four scan lines. For example, the pixels of the first row may be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, the first write scan line SWL1, and the second write scan line SWL2. In addition, the pixels of the second row may be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, the second write scan line SWL2, and the third write scan line SWL3. However, the number of scan lines connected to each pixel PX is not limited to this arrangement and can be varied in different configurations. Alternatively, each of the plurality of pixels PX may be electrically connected to five scan lines. In this case, the display panel DP may also include a black scan line.

[0091] The scan driving circuit 300 may be disposed in the non-display area NDA of the display panel DP. The scan driving circuit 300 receives a first driving control signal SCS from the driving controller 100. In response to the first driving control signal SCS, the scan driving circuit 300 outputs an initialization scan signal to the initialization scan lines SIL1 to SILn, outputs a compensation scan signal to the compensation scan lines SCL1 to SCLn, and outputs a write scan signal to the write scan lines SWL1 to SWLn+1.

[0092] The light emitting driving circuit 350 receives the third driving control signal ECS from the driving controller 100. The light emitting driving circuit 350 may output the light emitting control signal to the light emitting control lines EML1 to EMLn in response to the third driving control signal ECS. In an embodiment, the scan driving circuit 300 may be connected to the light emitting control lines EML1 to EMLn. In this case, the scan driving circuit 300 may output the light emitting control signal to the light emitting control lines EML1 to EMLn.

[0093] Each of the plurality of pixels PX includes a light emitting element and a pixel circuit for controlling the light emission of the light emitting element. The pixel circuit may include a capacitor and a plurality of transistors. The scanning driving circuit 300 and the light emitting driving circuit 350 may include transistors formed by the same process as the pixel circuit.

[0094] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT from the voltage generator 400 .

[0095] Figure 4 is a circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 5A is a timing diagram for describing the operation of a pixel in a first driving mode according to an embodiment of the present disclosure, and Figure 5B is a timing diagram for describing the operation of a pixel in the second driving mode according to an embodiment of the present disclosure.

[0096] Figure 4 Graphics Figure 3 1 is an equivalent circuit diagram of one pixel PXij among the plurality of pixels PX illustrated in FIG. Since each of the plurality of pixels PX has the same circuit structure, only the circuit structure of the pixel PXij will be described, and additional description of the remaining pixels will be omitted to avoid redundancy.

[0097] Reference Figure 4, the pixel PXij is connected to the i-th data line DLi (hereinafter referred to as the data line) among the data lines DL1 to DLm and the j-th emission control line EMLj (hereinafter referred to as the emission control line) among the emission control lines EML1 to EMLn. The pixel PXij is connected to the j-th initialization scan line SILj (hereinafter referred to as the initialization scan line) among the initialization scan lines SIL1 to SILn, the j-th write scan line SWLj (hereinafter referred to as the first write scan line) among the write scan lines SWL1 to SWLn+1, and the j+1-th write scan line SWLj+1 (hereinafter referred to as the second write scan line or the black scan line) among the write scan lines SWL1 to SWLn+1. In addition, the pixel PXij is connected to the j-th compensation scan line SCLj (hereinafter referred to as the compensation scan line) among the compensation scan lines SCL1 to SCLn. Alternatively, the pixel PXij may be connected to a separate j-th black scan line instead of the j+1-th write scan line SWLj+1.

[0098] The pixel PXij includes a light emitting element ED and a pixel circuit PXC. The light emitting element ED may include a light emitting diode. The light emitting diode may include an organic light emitting material, an inorganic light emitting material, a quantum dot or a quantum rod as a light emitting layer.

[0099] The pixel circuit PXC includes first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst. Each of the first to seventh transistors T1 to T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first to seventh transistors T1 to T7 may be P-type transistors, while others may be N-type transistors. For example, among the first to seventh transistors T1 to T7, the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors using an oxide semiconductor as a semiconductor layer. However, the configuration of the pixel circuit PXC according to the present disclosure is not limited to Figure 4 Since the configuration of the pixel circuit PXC can be modified and implemented in various ways, Figure 4 The pixel circuit PXC illustrated in FIG. 1 is only an example. For example, all of the first to seventh transistors T1 to T7 may be P-type transistors or N-type transistors.

[0100] The initialization scan line SILj, the compensation scan line SCLj, the first write scan line SWLj, the second write scan line SWLj+1, and the light emitting control line EMLj can respectively transmit the jth initialization scan signal SIj (hereinafter, referred to as the initialization scan signal), the jth compensation scan signal SCj (hereinafter, referred to as the compensation scan signal), the jth write scan signal SWj and the j+1th write scan signal SWj+1 (hereinafter, respectively referred to as the first write scan signal and the second write scan signal) and the jth light emitting control signal EMj (hereinafter, referred to as the light emitting control signal) to the pixel PXij. The data line DLi transmits the data signal Di to the pixel PXij. The data signal Di may have the same value as that transmitted by the display device DD (refer to Figure 3 ) The first to fourth driving voltage lines VL1, VL2, VL3 and VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT and the second initialization voltage AINT to the pixel PXij, respectively.

[0101] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to the first end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted by the data line DLi based on the switching operation of the second transistor T2, and then supply the driving current Id to the light emitting element ED.

[0102] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the first write scan line SWLj. The second transistor T2 can be turned on by a first write scan signal SWj received through the first write scan line SWLj. When the first write scan signal SWj is activated, the second transistor T2 transmits the data signal Di from the data line DLi to the first electrode of the first transistor T1.

[0103] The third transistor T3 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 may be turned on by a compensation scan signal SCj received through the compensation scan line SCLj. In this case, the gate electrode and the second electrode of the first transistor T1 may be connected to each other so that the first transistor T1 may be diode-connected.

[0104] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 to which the first initialization voltage VINT is transmitted, and a gate electrode connected to the initialization scan line SILj. The fourth transistor T4 may be turned on by the initialization scan signal SIj received through the initialization scan line SILj. When the initialization scan signal SIj is activated, the fourth transistor T4 may initialize the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage VINT to the gate electrode of the first transistor T1.

[0105] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emission control line EMLj.

[0106] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the light emitting control line EMLj.

[0107] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on by the emission control signal EMj received through the emission control line EMLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED.

[0108] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4 to which the second initialization voltage AINT is transmitted, and a gate electrode connected to the second write scan line SWLj+1.

[0109] As described above, a first end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and a second end of the capacitor Cst is connected to the first driving voltage line VL1. A cathode of the light emitting element ED may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS.

[0110] Reference Figure 3 , Figure 5A and Figure 5B, the display device DD may be operated in a first drive mode or a second drive mode. The first drive mode may be a drive mode in which the display panel DP operates above a reference frequency, and the second drive mode may be a drive mode in which the display panel DP operates at a frequency lower than the reference frequency. For example, the reference frequency may be 60 Hz. The first drive mode may be referred to as a reference drive mode operating at a reference frequency, and it may also be a high-frequency drive mode operating at a frequency higher than the reference frequency (e.g., 120 Hz, 240 Hz, or 480 Hz). The second drive mode is referred to as a low-frequency drive mode operating at a frequency lower than the reference frequency (e.g., 30 Hz, 10 Hz, 2 Hz, or 1 Hz).

[0111] In the first driving mode, the display panel DP may display images for a plurality of first driving frames F1. When the display panel DP operates at a frequency of 60 Hz in the first driving mode, the display panel DP may display 60 images each corresponding to 60 first driving frames F1 within one second.

[0112] When a high-level initialization scan signal SIj is provided through the initialization scan line SILj during the initialization period AP1 of the first driving frame F1, the fourth transistor T4 is turned on in response to the high-level initialization scan signal SIj. The first initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the voltage level of the gate electrode of the first transistor T1 is initialized to the first initialization voltage VINT.

[0113] Next, when a high-level compensation scan signal SCj is supplied through the compensation scan line SCLj during the compensation period AP2 of the first driving frame F1, the third transistor T3 is turned on. The compensation period AP2 may not overlap with the initialization period AP1. During the compensation period AP2, the first transistor T1 is diode-connected and forward biased by the turned-on third transistor T3.

[0114] As an example of the present disclosure, the activation period of the compensation scan signal SCj (for example, the period corresponding to the compensation period AP2) is a period in which the compensation scan signal SCj has a high level, and the activation period of the initialization scan signal SIj (for example, the period corresponding to the initialization period AP1) is a period in which the initialization scan signal SIj has a high level. The activation period of the compensation scan signal SCj may not overlap with the activation period of the initialization scan signal SIj. The activation period of the initialization scan signal SIj may be before the activation period of the compensation scan signal SCj. When the third transistor T3 and the fourth transistor T4 are P-type transistors, the activation period of the compensation scan signal SCj (for example, the period corresponding to the compensation period AP2) may be a period in which the compensation scan signal SCj has a low level, and the activation period of the initialization scan signal SIj (for example, the period corresponding to the initialization period AP1) may be a period in which the initialization scan signal SIj has a low level.

[0115] The compensation period AP2 may include a data write period AP3 in which the first write scan signal SWj is generated at a low level. During the data write period AP3, the second transistor T2 is turned on by the first write scan signal SWj at a low level. Accordingly, a compensation voltage (Di-Vth) obtained by lowering the voltage of the data signal Di supplied from the data line DLi by the threshold voltage (Vth) of the first transistor T1 is applied to the gate electrode of the first transistor T1. In other words, the potential of the gate electrode of the first transistor T1 may be the compensation voltage (Di-Vth).

[0116] The first driving voltage ELVDD and the compensation voltage (Di-Vth) may be applied to the first and second terminals of the capacitor Cst, and charges corresponding to a voltage difference between the terminals may be stored in the capacitor Cst.

[0117] The seventh transistor T7 is turned on by receiving the second write scan signal SWLj+1 of a low level through the second write scan line SWLj+1. Some of the drive current Id may flow out as a bypass current Ibp through the seventh transistor T7.

[0118] When the pixel PXij displays a black image, even if the minimum drive current of the first transistor T1 flows as the drive current Id, the emission of light by the light emitting element ED can also hinder the correct display of the black image. In order to solve this problem, the seventh transistor T7 in the pixel PXij according to the embodiment of the present disclosure can transfer a part of the minimum drive current of the first transistor T1 to an alternative current path, thereby creating a bypass current Ibp. The minimum drive current of the first transistor T1 refers to the current flowing into the first transistor T1 when its gate-source voltage is less than the threshold voltage (Vth) and the first transistor T1 is effectively turned off. Under these conditions, the minimum drive current (for example, a current of 10pA or less) still flows into the first transistor T1 and is transmitted to the light emitting element ED, thereby allowing a black grayscale image to be displayed. Although the bypass current Ibp has a relatively large effect on the minimum drive current when displaying a black image, it has a small effect on the drive current Id when displaying other images such as normal or white images. Accordingly, when a black image is displayed, a current (e.g., a light emitting current Ied) obtained by subtracting the amount of the bypass current Ibp flowing out through the seventh transistor T7 from the driving current Id is provided to the light emitting element ED, resulting in a clearer representation of the black image. Accordingly, the pixel PXij can implement an accurate black grayscale image using the seventh transistor T7, and as a result, the contrast can be improved.

[0119] Next, the light emitting control signal EMj supplied from the light emitting control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the light emitting control signal EMj of the low level. Accordingly, a driving current Id is generated based on a voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD. The driving current Id is supplied to the light emitting element ED through the sixth transistor T6, thereby allowing the light emitting current Ied to flow through the light emitting element ED.

[0120] In the second driving mode, the display panel DP can display images for a plurality of second driving frames F2. Figure 5BAs illustrated in , each second drive frame F2 may include a write frame WF and "p" hold frames HF1 to HFp. Here, "p" may be an integer of 1 or greater. As an example of the present disclosure, the write frame WF and each of the "p" hold frames HF1 to HFp may have a duration corresponding to the first drive frame F1. For example, when the display panel DP operates at a frequency of 1 Hz, in the second drive mode, the display panel DP displays an image for 1 second during one second drive frame F2. In addition, each second drive frame F2 may include a write frame WF and 59 hold frames HF1 to HFp. In this case, "p" may be 59. When the display panel DP operates at a frequency of 10 Hz, in the second drive mode, the display panel DP displays an image for 1 / 10 second during one second drive frame F2. In addition, each second drive frame F2 may include a write frame WF and 5 hold frames HF1 to HFp. In this case, "p" may be 5.

[0121] During the write frame WF, the initialization scan signal SIj, the compensation scan signal SCj, and the first write scan signal SWj and the second write scan signal SWj+1 may each be activated. In the "p" hold frames HF1 to HFp, the first write scan signal SWj and the second write scan signal SWj+1 are activated, and the initialization scan signal SIj and the compensation scan signal SCj are deactivated. The light emitting control signal EMj may be activated in the write frame WF and the "p" hold frames HF1 to HFp.

[0122] In the second driving mode, the initialization scan signal SIj and the compensation scan signal SCj may be output at a frequency lower than a reference frequency, and the emission control signal EMj and the first and second write scan signals SWj+1 may be output at the reference frequency.

[0123] Like the first driving frame F1, the writing frame WF may include an initialization period AP1, a compensation period AP2, and a data writing period AP3. During the data writing period AP3, the data signal Di is applied to the data line DLi.

[0124] Each of the "p" holding frames HF1 to HFp may not include the initialization period AP1 and the compensation period AP2, but may include only the data writing period AP3. During the "p" holding frames HF1 to HFp, the initialization scan signal SIj and the compensation scan signal SCj are maintained in a deactivated state. Therefore, during the "p" number of holding frames HF1 to HFp, the light emitting element ED may maintain the light emitting current Ied flowing into the light emitting element ED during the writing frame WF, and each of the "p" number of holding frames HF1 to HFp may maintain the image displayed during the writing frame WF.

[0125] Figure 6 is a block diagram of an afterimage compensation circuit according to an embodiment of the present disclosure. Fig. 7A is a plan view of a display panel according to an embodiment of the present disclosure, and FIG. 7B to FIG. 7D is a diagram illustrating a sampling process of a sampling unit according to an embodiment of the present disclosure.

[0126] Reference Figure 6 The afterimage compensation circuit 150 includes a compensation unit 151 , a non-volatile memory 152 , a sampling unit 153 , a data processing unit 154 and a volatile memory 155 .

[0127] The compensation unit 151 receives the input image signal RGB and compensates the input image signal RGB based on the accumulated degradation data ADD stored in the nonvolatile memory 152 to generate a compensated image signal RGB′.

[0128] The nonvolatile memory 152 includes a first storage area 152a and a second storage area 152b. At each backup time of a plurality of backup times occurring in a preset backup period, the degradation data IDD is backed up in the first storage area 152a. Accordingly, the nonvolatile memory 152 accumulates the new degradation data IDD with the previously stored cumulative degradation data in the first storage area 152a, so that the result is cumulative degradation data ADD. The cumulative degradation data ADD stored in the first storage area 152a is provided as degradation information to the compensation unit 151, which then performs degradation compensation processing based on the data.

[0129] The information I_FAT about the backup time is stored in the second storage area 152b. The information I_FAT about the backup time stored in the second storage area 152b is provided to the sampling unit 153, and the sampling unit 153 determines the sampling position based on the information I_FAT. Specifically, in order to perform the first sampling operation when the power is turned on, the sampling unit 153 may determine the sampling position with reference to the information I_FAT about the last backup time (e.g., the final backup time) just before the power is turned off.

[0130] Reference Fig. 7A , the display panel DP may display an image IM. The display panel DP may include a display area DA in which the image IM is displayed and a non-display area NDA adjacent to the display area DA. The display area DA of the display panel DP may include a plurality of blocks BLK. The display area DA may be divided into a plurality of blocks BLK. Fig. 7A In FIG. 1 , the display area DA is illustratively divided into 16 blocks BLK, but the number of blocks BLK is not limited thereto. Fig. 7A In the example, a plurality of blocks BLK are provided in a 4×4 grid.

[0131] As time progresses, afterimages due to degradation may develop in the display area DA of the display panel DP. The extent of afterimages in the display area DA may vary between different blocks BLK. The display device DD according to an embodiment of the present disclosure compensates for the brightness of the image IM displayed in each block BLK of the display panel DP based on degradation information specific to each of the blocks BLK.

[0132] In an embodiment, a plurality of sub-blocks SB may be disposed in each block BLLK of a plurality of blocks BLK. A plurality of sub-blocks SB may be arranged in a first direction DR1 and a second direction DR2. A plurality of pixels PX may be disposed in each sub-block SB. The size of each sub-block SB may be determined based on the number of pixels PX included in each sub-block SB. For example, as the number of pixels PX included in each sub-block SB increases, the size of each sub-block SB becomes larger. On the contrary, as the number of pixels PX included in each sub-block SB decreases, the size of each sub-block SB becomes smaller. For example, 64 pixels PX may be disposed in each sub-block SB.

[0133] Fig. 7A The structure in which one block BLK includes 16 sub-blocks SB is shown in the figure, but the number of sub-blocks SB is not limited thereto. In the present embodiment, compensation for degradation (hereinafter referred to as degradation compensation) can be performed in units of sub-blocks SB. As the number of sub-blocks SB included in each block BLK increases, the accuracy of degradation compensation can be improved.

[0134] Reference Figure 6 as well as FIG. 7B to FIG. 7D , the sampling unit 153 may receive the compensated image signal RGB' from the compensation unit 151 and may sample some of the compensated image signal RGB'. The sampling unit 153 may be configured to set a sampling line and sample a line image signal from the sampling line based on the compensated image signal RGB' (in other words, the line image signal corresponding to the sampling line is sampled by using the compensated image signal RGB').

[0135] As an example of the present disclosure, the sampling unit 153 performs sampling on some of the blocks BLK1 to BLK16 using a reference frame as a unit. As an example of the present disclosure, the reference frame may be one frame. FIG. 7B to FIG. 7D A case in which the sampling unit 153 performs sampling on four blocks per frame is illustrated, but the present disclosure is not limited thereto.

[0136] The sampling unit 153 may set the sampling lines RL1 to RL4 in the display area DA, and may perform a sampling operation by sequentially selecting one of the sampling lines RL1 to RL4 in the first direction DR1 or the second direction DR2 . FIG. 7B to FIG. 7DThe structure in which each of the sampling lines RL1 to RL4 extends in the first direction DR1 and is arranged in the second direction DR2 is illustrated, but the present disclosure is not limited thereto. When the display area DA includes 4×4 blocks, each of the sampling lines RL1 to RL4 may include 4 blocks, and sampling all of the blocks BLK1 to BLK16 once may occupy a total of 4 frames. As an example of the present disclosure, each of the blocks BLK1 to BLK16 may include 16 sub-blocks of a plurality of sub-blocks SB1_1 to SB16_16. When one of the 16 sub-blocks is sampled in each frame, 16 frames are required to sample a total of 16 sub-blocks. Therefore, sampling all of the sub-blocks SB1_1 to SB16_16 included in all of the blocks BLK1 to BLK16 once may require a total of 64 frames. The 64 frames required to sample all of the sub-blocks SB1_1 to SB16_16 included in all of the blocks BLK1 to BLK16 once may be referred to as one sampling period. The sampling unit 153 may perform a sampling operation by repeating a sampling period. The sampling unit 153 may perform sampling on one sub-block in each block included in a selected sampling line among the sampling lines RL1 to RL4.

[0137] like Figure 7B As illustrated in , sampling of blocks (e.g., first blocks BLK1 to fourth blocks BLK4) located on the first sampling line RL1 in the first frame f1 (or the first reference frame) is performed. Compensated image signals of the first sub-blocks SB1_1, SB2_1, SB3_1, and SB4_1 in each of the first blocks BLK1 to the fourth blocks BLK4 in the first frame f1 may be sampled as first line image signals. Compensated image signals of the first sub-blocks SB5_1, SB6_1, SB7_1, and SB8_1 in each of the blocks (e.g., fifth blocks BLK5 to eighth blocks BLK8) located on the second sampling line RL2 in the second frame f2 may be sampled as second line image signals. In the third frame f3, sampling is performed on blocks (e.g., ninth blocks BLK9 to twelfth blocks BLK12) located on the third sampling line RL3. The compensation image signal of the first sub-blocks SB9_1, SB10_1, SB11_1, and SB12_1 in each of the 9th to 12th blocks BLK9 to BLK12 in the third frame f3 may be sampled as a third line image signal. The compensation image signal of the first sub-blocks SB13_1, SB14_1, SB15_1, and SB16_1 in each of the blocks (e.g., the 13th to 16th blocks BLK13 to BLK16) on the fourth sampling line RL4 in the fourth frame f4 may be sampled as a fourth line image signal.

[0138] like Figure 7CAs illustrated in FIG. 1 , the compensation image signal of the second sub-block SB1_2, SB2_2, SB3_2, and SB4_2 in each of the first to fourth blocks BLK1 to BLK4 located on the first sampling line RL1 in the fifth frame f5 may be sampled as the fifth line image signal. The compensation image signal of the second sub-block SB5_2, SB6_2, SB7_2, and SB8_2 in each of the fifth to eighth blocks BLK5 to BLK8 located on the second sampling line RL2 in the sixth frame f6 may be sampled as the sixth line image signal. The compensation image signal of the second sub-block SB9_2, SB10_2, SB11_2, and SB12_2 in each of the ninth to twelfth blocks BLK9 to BLK12 located on the third sampling line RL3 in the seventh frame f7 may be sampled as the seventh line image signal. The compensated image signals of the second sub-blocks SB13_2 , SB14_2 , SB15_2 , and SB16_2 in each of the 13th to 16th blocks BLK13 to BLK16 located on the fourth sampling line RL4 in the eighth frame f8 may be sampled as the eighth line image signals.

[0139] like Fig.7D As illustrated in FIG. 1 , the compensation image signal of the 16th sub-block SB1_16, SB2_16, SB3_16, and SB4_16 in each of the first block BLK1 to the fourth block BLK4 located on the first sampling line RL1 in the 61st frame f61 may be sampled as the 61st line image signal. The compensation image signal of the 16th sub-block SB5_16, SB6_16, SB7_16, and SB8_16 in each of the fifth block BLK5 to the eighth block BLK8 located on the second sampling line RL2 in the 62nd frame f62 may be sampled as the 62nd line image signal. The compensation image signal of the 16th sub-block SB9_16, SB10_16, SB11_16, and SB12_16 in each of the ninth block BLK9 to the twelfth block BLK12 located on the third sampling line RL3 in the 63rd frame f63 may be sampled as the 63rd line image signal. The compensated image signal of the 16th sub-blocks SB13_16, SB14_16, SB15_16, and SB16_16 in each of the 13th to 16th blocks BLK13 to BLK16 located on the fourth sampling line RL4 in the 64th frame f64 may be sampled as a 64th line image signal.

[0140] The sampling unit 153 may sequentially provide the sampled first line image signal to the 64th line image signal to the data processing unit 154. The data processing unit 154 may generate degradation data for each of the first line image signal to the 64th line image signal and may store the generated degradation data in the volatile memory 155. The degradation data stored in the volatile memory 155 may be backed up (or accumulated) in the nonvolatile memory 152 at a plurality of backup times occurring according to a preset backup period.

[0141] As an example of the present disclosure, the preset backup period may have a duration that increases sequentially from the power-on time to the predetermined time, and after the predetermined time, it remains fixed. For example, after power-on, the first backup period may be set to 2 minutes, the second backup period may be set to 5 minutes, and from the third backup period onwards, it may be fixed to 10 minutes. The duration of the preset backup period may vary depending on the time that has passed since power-on.

[0142] Figure 8 is a diagram for describing a case in which a sampling operation is performed in a second direction according to an embodiment of the present disclosure. Fig. 9 is a diagram for describing a case in which a sampling operation is performed in a first direction according to an embodiment of the present disclosure.

[0143] Reference Figure 6 and Figure 8 , when power is turned on for the first sampling operation, the sampling unit 153 may load information about the final backup time Tf from the nonvolatile memory 152. The final backup time Tf refers to the last backup time recorded just before power is turned off. As an example of the present disclosure, the information about the final backup time Tf may include one or more of the following information: the number of the final reference frame of the final backup time Tf; the number of the final sampling line of the final backup time Tf; and the number of the blocks included in the final sampling line.

[0144] When there is no record history of the final backup time Tf stored in the nonvolatile memory 152, or if the second storage area 152b of the nonvolatile memory 152 has been reset, the sampling unit 153 may start a sampling operation from the first sampling line RL1 in the first frame f1 after power is turned on. Thereafter, in the second frame f2, the sampling unit 153 may perform a sampling operation on the second sampling line RL2, and in the k-th frame fk, the sampling unit 153 may perform a sampling operation on the k-th sampling line RLk.

[0145] The first frame f1 to the k-th frame fk may correspond to the first backup period. Accordingly, when the sampling operation for the k-th sampling line RLk is terminated, the volatile memory 155 may accumulate the degradation data IDD in the first storage area 152a of the nonvolatile memory 152 at the first backup time T1. In addition, at the first backup time T1, the second storage area 152b of the nonvolatile memory 152 may store information about the first backup time T1 (e.g., at least one of the number of the k-th frame fk, the number of the k-th sampling line RLk sampled at the k-th frame fk, and the number of the block included in the k-th sampling line RLk).

[0146] Even if the duration of the first backup period is shorter than one sampling period, the sampling unit 153 determines the sampling position based on the information about the first backup time T1. As a result, after the first backup time T1, the sampling unit 153 can continue to sample the k+1th sampling line RLk+1 in the k+1th frame fk+1.

[0147] Thereafter, after performing the sampling operation for the k+2th sampling line RLk+2 in the k+2th frame fk+2, the power may be turned off immediately. In this case, the final backup time Tf may coincide with the first backup time T1, and the number of the kth frame fk may be considered as the number of the final reference frame.

[0148] When the power is turned on again, the sampling unit 153 may load the information about the final backup time Tf stored in the second storage area 152b of the nonvolatile memory 152. For example, if the number of the k-th frame fk is stored as part of the information about the final backup time Tf, the sampling unit 153 may start the sampling operation from the k+1-th sampling line RLk+1 corresponding to the next frame of the k-th frame fk (e.g., the k+1-th frame fk+1). In this scenario, the k+1-th frame fk+1 becomes the starting frame, and the k+1-th sampling line RLk+1 serves as a reference sampling line. Therefore, the sampling unit 153 starts the sampling operation from the sampling line (e.g., the k+1-th sampling line RLk+1) that directly follows the k-th sampling line RLk sampled at the final backup time Tf.

[0149] Thereafter, in the k+2th frame fk+2, the sampling unit 153 performs a sampling operation on the k+2th sampling line RLk+2. When the sampling for the 2kth sampling line RL2k is completed, the volatile memory 155 may accumulate the degradation data IDD in the first storage area 152a of the nonvolatile memory 152 at the first backup time T1. In addition, at the first backup time T1, the second storage area 152b of the nonvolatile memory 152 may store information about the first backup time T1 (e.g., at least one of the number of the 2kth frame f2k, the number of the 2kth sampling line RL2k sampled in the 2kth frame f2k, and the number of the block included in the 2kth sampling line RL2k).

[0150] Even if the duration of the first backup period is shorter than one sampling period, the sampling unit 153 determines the sampling position based on the information about the first backup time T1. As a result, the sampling unit 153 can continue the sampling operation for the 2k+1th sampling line RL2k+1 in the 2k+1th frame f2k+1 after the first backup time T1.

[0151] Afterwards, the sampling unit 153 may perform a sampling operation for the 2k+2th sampling line RL2k+2 in the 2k+2th frame f2k+2, thereby completing one sampling period even if the power is turned off midway. Once one sampling period is completed, the sampling unit 153 may start from the first frame f1 and perform sampling from the first sampling line RL1 again. The first frame f1 to the g-th frame fg may correspond to the second backup period. Accordingly, when the sampling for the g-th sampling line RLg is completed, the volatile memory 155 may accumulate the degradation data IDD in the first storage area 152a of the nonvolatile memory 152 at the second backup time T2.

[0152] In addition, at the second backup time T2, the second storage area 152b of the nonvolatile memory 152 may store information about the second backup time T2 (e.g., at least one of the number of the g-th frame fg, the number of the g-th sampling line RLg sampled at the g-th frame fg, and the number of the block included in the g-th sampling line RLg). Thereafter, after the sampling operation for the g+1-th sampling line RLg+1 in the g+1-th frame fg+1 is completed, the power may be turned off immediately. In this case, the final backup time Tf is recorded as the second backup time T2.

[0153] When the power is turned on again, the sampling unit 153 may load the information about the final backup time Tf stored in the second storage area 152b of the nonvolatile memory 152. For example, when the number of the g-th frame fg is stored as the information about the final backup time Tf, the sampling unit 153 may start the sampling operation from the g+1-th sampling line RLg+1 by adding "1" to the g-th sampling line RLg corresponding to the g-th frame fg. In other words, if the number of the g-th frame fg is stored as part of the information about the final backup time Tf, the sampling unit 153 may start the sampling operation from the g+1-th sampling line RLg+1 by incrementing the g-th sampling line RLg corresponding to the g-th frame fg by one.

[0154] In this way, when the information about the backup time is stored in the second storage area 152b of the nonvolatile memory 152, even when the power is turned off, the information about the final backup time Tf is retained in the nonvolatile memory 152. Accordingly, when the power is turned on again, the sampling unit 153 determines the sampling position based on the information about the final backup time Tf. This allows the sampling unit 153 to continue sampling the sampling line that was not sampled due to the power being turned off, resulting in a more efficient sampling operation.

[0155] In addition, in the second driving mode operating at a low frequency, there may be a situation where the duration of one backup period is shorter than one sampling period. In such a case, storing information about the backup time in the second storage area 152b of the non-volatile memory 152 helps prevent the accumulation of degradation data only in a specific area. As a result, even in the second driving mode, the afterimage compensation circuit 150 is able to store degradation data consistently across the entire display area DA. This consistent data storage enables the afterimage compensation circuit 150 to perform accurate degradation compensation, thereby improving display quality by reducing the afterimage effect.

[0156] exist Figure 8 In the embodiment, the sampling lines RL1 to RLk+2, RL2k to RL2k+2, RLg, and RLg+1 may extend in the first direction DR1. However, the present disclosure is not limited thereto.

[0157] like Figure 6 and Fig. 9 As illustrated in , the sampling lines RL1 to RLk+2, RLg, and RLg+1 may extend in the second direction DR2.

[0158] The first frame f1 to the k-th frame fk may correspond to the first backup period. Accordingly, when the sampling operation on the k-th sampling line RLk is terminated, the volatile memory 155 may accumulate the degradation data IDD in the first storage area 152a of the nonvolatile memory 152 at the first backup time T1. In addition, at the first backup time T1, the second storage area 152b of the nonvolatile memory 152 may store information about the first backup time T1, such as at least one of the number of the k-th frame fk, the number of the k-th sampling line RLk sampled at the k-th frame fk, and the number of the block included in the k-th sampling line RLk. Thereafter, after performing the sampling operation for the k+1-th sampling line RLk+1 in the k+1-th frame fk+1, the power may be turned off immediately. In this case, the final backup time Tf may be the first backup time T1.

[0159] When the power is turned on again, the sampling unit 153 may load the information about the final backup time Tf stored in the second storage area 152b of the nonvolatile memory 152. For example, when the number of the k-th frame fk is stored as the information about the final backup time Tf, the sampling unit 153 may start the sampling operation from the k+1-th sampling line RLk+1 by adding "1" to the k-th sampling line RLk corresponding to the k-th frame fk.

[0160] In detail, in the k+1th frame fk+1, the sampling unit 153 may perform a sampling operation on a sampling line (e.g., the k+1th sampling line RLk+1) directly following the kth sampling line RLk sampled at the final backup time Tf. The sampling unit 153 may continue the sampling operation from the k+3th frame fk+3 until the final sampling line RLk+3, and even if the power is turned off halfway, one sampling period may be completed. When one sampling period is completed, the sampling unit 153 may restart sampling from the first sampling line RL1 in the first frame f1. The k+1th frame fk+1 to the gth frame fg may correspond to the first backup period. Accordingly, when the sampling for the gth sampling line RLg is completed, the volatile memory 155 may accumulate the degradation data IDD in the first storage area 152a of the nonvolatile memory 152 at the first backup time T1.

[0161] Thereafter, after performing the sampling operation for the g+1th sampling line RLg+1 in the g+1th frame fg+1, the power may be immediately turned off. In this case, the final backup time Tf may be the first backup time T1.

[0162] When the power is turned on again, the sampling unit 153 may load the information about the final backup time Tf stored in the second storage area 152b of the nonvolatile memory 152. For example, when the number of the g-th frame fg is stored as the information about the final backup time Tf, the sampling unit 153 may start the sampling operation from the g+1-th sampling line RLg+1 by adding "1" to the g-th sampling line RLg corresponding to the g-th frame fg.

[0163] In this way, when the duration of one backup period in the second driving mode is shorter than one sampling period, storing the information about the backup time in the second storage area 152b of the nonvolatile memory 152 helps prevent the accumulation of degradation data only in a specific area. Therefore, even in the second driving mode, the afterimage compensation circuit 150 can store degradation data a consistent number of times throughout the entire display area DA. As a result, accurate degradation compensation can be performed, thereby improving display quality by reducing the occurrence of afterimages.

[0164] Fig.10 is a flowchart illustrating an operation process of an afterimage compensation circuit according to an embodiment of the present disclosure.

[0165] Reference Figure 6 and Fig.10 , the afterimage compensation circuit 150 may start operating when power is turned on (eg, a power-on time).

[0166] First, the sampling unit 153 may load information about the final backup time stored in the second storage area 152b of the nonvolatile memory 152. When the number of the reference frame is stored in the second storage area 152b, the sampling unit 153 may load the number of the final reference frame (or reference frames) for the final backup time (step S100).

[0167] The sampling unit 153 may set a start frame by adding "1" to the loaded reference frame number and may perform a sampling operation starting from a reference sampling line corresponding to the start frame (step S200). In other words, a line image signal for a sampling line may be sampled through the sampling operation, and the data processing unit 154 may generate degradation data for the sampling line based on the line image signal.

[0168] After that, the degradation data may be stored in the volatile memory 155 (step S300). The degradation data stored in the volatile memory 155 may be accumulated in the nonvolatile memory 152 at each preset backup period. The afterimage compensation circuit 150 determines whether the backup time has been reached (step S400). If the backup time has not been reached, the afterimage compensation circuit 150 moves to operation S100 and repeats the sampling operation. If the backup time has been reached, the afterimage compensation circuit 150 may store the degradation data and the reference frame number in the nonvolatile memory 152 (step S500).

[0169] When the storage operation is completed, it is determined whether to continue the sampling operation (step S600). If it is determined that the sampling operation should continue, the process returns to operation S100 and repeats the sampling operation. Otherwise, the sampling operation can end.

[0170] Fig.11A is a plan view illustrating a screen of a display device according to an embodiment of the present disclosure. Fig. 11B is a diagram for describing an operation of a display device in a normal frequency mode according to an embodiment of the present disclosure, and Fig. 11C is a diagram for describing an operation of a display device in a multi-frequency mode according to an embodiment of the present disclosure.

[0171] Reference FIG. 11A to FIG. 11C , the display device DDa can display images in the normal frequency mode NFM or the multi-frequency mode MFM. In the normal frequency mode NFM, the display area DA of the display device DDa is not divided into a plurality of display areas having different driving frequencies. For example, in the normal frequency mode NFM, the display area DA operates at one driving frequency, and in the normal frequency mode NFM, the driving frequency of the display area DA can be referred to as a normal frequency. For example, the normal frequency can be 60 Hz or 120 Hz. In the normal frequency mode NFM, 60 images corresponding to the first frame F1 to the 60th frame F60 can be displayed in the display area DA of the display device DDa for 1 second (1 sec).

[0172] In the multi-frequency mode MFM, the display area DA of the display device DDa is divided into a plurality of display areas with different driving frequencies. As an example of the present disclosure, in the multi-frequency mode MFM, the display area DA may include a first display area DA1 and a second display area DA2. The first display area DA1 and the second display area DA2 are arranged adjacent to each other in the second direction DR2. The driving frequency (or first frequency) of the first display area DA1 may be a frequency higher than or equal to the normal frequency, and the driving frequency (or second frequency) of the second display area DA2 may be a frequency less than the normal frequency. For example, when the normal frequency is 60Hz, the driving frequency of the first display area DA1 may be 90Hz, 100Hz, 120Hz, 240Hz or 480Hz, and the driving frequency of the second display area DA2 may be 1Hz, 20Hz, 30Hz, 40Hz, etc.

[0173] As an example of the present disclosure, the first display area DA1 may be an area for displaying a moving image (hereinafter referred to as the first image IM1) that requires high-speed driving. The second display area DA2 may be an area for displaying a still image (hereinafter referred to as the second image IM2) that does not require high-speed driving or a text image with a long change period. Therefore, when a still image and a moving image are displayed simultaneously on the screen of the display device DDa, by operating the display device DDa in the multi-frequency mode MFM, the display quality of the moving image can be improved, and the total power consumption can be reduced.

[0174] In the multi-frequency mode MFM, an image may be displayed in the display area DA of the display device DDa for a plurality of drive frames DF. Each of the drive frames DF includes a full frame FF in which the first display area DA1 and the second display area DA2 are driven and partial frames HF1 to HF99 in which only the first display area DA1 is driven. Each of the partial frames HF1 to HF99 may have a duration shorter than that of the full frame FF. The number of partial frames HF1 to HF99 included in each drive frame DF may be the same or different. Each drive frame DF may be a period from the time when the current full frame FF starts to the time when the next full frame FF starts.

[0175] As an example of the present disclosure, during each drive frame DF, the first display area DA1 may operate at 100 Hz, and the second display area DA2 may operate at 1 Hz. In this case, each drive frame DF has a duration corresponding to 1 second (1 sec) and may include one full frame FF and 99 partial frames HF1 to HF99. During each drive frame DF, 100 first images IM1 corresponding to one full frame FF and 99 partial frames HF1 to HF99 may be displayed in the first display area DA1 of the display device DDa, and one second image IM2 corresponding to one full frame FF may be displayed in the second display area DA2.

[0176] exist Fig. 11C In the figure, for the convenience of description, in the multi-frequency mode MFM, although the driving frequency of the first display area DA1 is 100Hz and the driving frequency of the second display area DA2 is 1Hz as an example, the present disclosure is not limited thereto. For example, the driving frequency of the first display area DA1 may be 100Hz, and the driving frequency of the second display area DA2 may be 20Hz. In this case, during each driving frame DF, five first images IM1 corresponding to one full frame FF and four partial frames are displayed in the first display area DA1 of the display device DD, and one second image IM2 corresponding to one full frame FF may be displayed in the second display area DA2. In addition, the driving frequency of the first display area DA1 may be 90Hz, and the driving frequency of the second display area DA2 may be 30Hz. In this case, during each driving frame DF, three first images IM1 corresponding to one full frame FF and two partial frames are displayed in the first display area DA1 of the display device DD, and one second image IM2 corresponding to one full frame FF may be displayed in the second display area DA2.

[0177] In this scenario, in the multi-frequency mode MFM where a high frequency region (e.g., the first display area DA1) and a low frequency region (e.g., the second display area DA2) exist within a single display area DA, the full frame FF is used as a reference frame. However, during the sampling operation, a partial frame may not be considered as a reference frame. In other words, the sampling unit 153 (reference Figure 6 ) can perform the sampling operation in units of one full frame FF. Accordingly, the sampling operation can be performed based on the characteristics of the low-frequency region.

[0178] Even when operating in the multi-frequency mode MFM, there may be a case where the duration of one backup period is shorter than one sampling period. In such a case, storing information about the backup time in the second storage area 152b of the non-volatile memory 152 can solve the problem of accumulating degradation data only for a specific area. As a result, even in the multi-frequency mode MFM, the afterimage compensation circuit 150 can store degradation data consistently across the entire display area DA. Accordingly, the afterimage compensation circuit 150 can perform accurate degradation compensation, thereby improving display quality by reducing afterimage-related degradation.

[0179] Fig.12 is a block diagram of an afterimage compensation circuit according to an embodiment of the present disclosure. Fig.13 2 is a diagram illustrating differently set backup periods in a first driving mode and a second driving mode according to an embodiment of the present disclosure. Fig.12 In the same reference numerals as in Figure 6 The same components as those in and additional description of these components will be omitted to avoid redundancy.

[0180] Reference Fig.12 and Fig.13 The afterimage compensation circuit 150 a according to an embodiment of the present disclosure includes a compensation unit 151 , a nonvolatile memory 156 , a sampling unit 153 , a data processing unit 154 , a volatile memory 155 , and a backup period adjustment unit 157 .

[0181] At each of a plurality of backup times occurring in a preset backup period, the degradation data IDD is accumulated in the nonvolatile memory 156. The sampling unit 153 may sequentially provide the sampled line image signals to the data processing unit 154. The data processing unit 154 may generate the degradation data IDD for each line image signal and may store the generated degradation data IDD in the volatile memory 155. The degradation data IDD stored in the volatile memory 155 may be accumulated in the nonvolatile memory 156 at each of a plurality of backup times occurring in the preset backup period.

[0182] The backup period adjustment unit 157 may change the backup period depending on the driving mode of the display device DD. For example, the display device DD may operate in a first driving mode FDM or a second driving mode SDM. The first driving mode FDM may be a driving mode in which the display panel DP operates above a reference frequency, and the second driving mode SDM may be a driving mode in which the display panel DP operates at a frequency lower than the reference frequency.

[0183] In the first driving mode FDM in which the display device DD operates at a reference frequency or higher, the degradation data IDD may be backed up to the nonvolatile memory 156 during a preset reference backup period. Fig.13 As illustrated in , under the first driving mode FDM, the reference backup period increases sequentially from the power-on time T0 to the predetermined time (e.g., the 3-1 backup time T3), and after the predetermined time, the reference backup period may have a fixed value. The 1-1 backup period TP1 corresponds to the period from the power-on time T0 to the 1-1 backup time T1, and the 1-2 backup period TP2 corresponds to the period from the 1-1 backup time T1 to the 2-1 backup time T2. The 1-3 backup period TP3 corresponds to the period from the 2-1 backup time T2 to the 3-1 backup time T3 and the period from the 3-1 backup time T3 to the 4-1 backup time T4. For example, the 1-1 backup period TP1 may be set to 2 minutes, the 1-2 backup period TP2 may be set to 5 minutes, and the backup period starting from the 1-3 backup period TP3 may be set to 10 minutes.

[0184] In the second driving mode SDM in which the display device DD operates below the reference frequency, the backup period adjustment unit 157 may generate a variable backup period different from the preset reference backup period. Accordingly, in the second driving mode SDM, the degraded data IDD may be backed up in the nonvolatile memory 156 with a variable backup period. In the second driving mode SDM, the variable backup period may be changed based on the driving frequency.

[0185] like Fig.13 As illustrated in , under the second driving mode SDM, the variable backup period increases sequentially from the power-on time T0 to the predetermined time (e.g., the 3-2 backup time T3a), and after the predetermined time, the variable backup period may have a fixed value. The 2-1 backup period TP1a corresponds to the period from the power-on time T0 to the 1-2 backup time T1a, and the 2-2 backup period TP2a corresponds to the period from the 1-2 backup time T1a to the 2-2 backup time T2a. The 2-3 backup period TP3a ​​corresponds to the period from the 2-2 backup time T2a to the 3-2 backup time T3a. As an example of the present disclosure, the 2-1 backup period TP1a may be greater than the 1-1 backup period TP1, the 2-2 backup period TP2a may be greater than the 1-2 backup period TP2, and the 2-3 backup period TP3a ​​may be greater than the 1-3 backup period TP3. For example, the 2-1 backup period TP1a may be set to 5 minutes, the 2-2 backup period TP2a may be set to 10 minutes, and the backup period starting from the 2-3 backup period TP3a ​​may be set to 20 minutes.

[0186] The duration of each of the 2-1 backup period TP1a, the 2-2 backup period TP2a, and the 2-3 backup period TP3a ​​can be changed based on the driving frequency of the second driving mode SDM. For example, when the driving frequency of the second driving mode SDM is 10 Hz and when the driving frequency of the second driving mode SDM is 1 Hz, the 2-1 backup period TP1a, the 2-2 backup period TP2a, and the 2-3 backup period TP3a ​​can each have a different duration.

[0187] In this case, by increasing the duration of the backup period under the second driving mode SDM operated at a low frequency, the problem of the backup period being shorter than one sampling period can be solved. This adjustment prevents the accumulation of degradation data for a specific area under the second driving mode SDM. As a result, the afterimage compensation circuit 150a is able to store degradation data consistently across the entire display area DA under the second driving mode SDM. Accordingly, even under the second driving mode SDM, the afterimage compensation circuit 150a can accurately compensate for degradation, thereby improving the reduction in display quality due to afterimages.

[0188] like FIG. 11A to FIG. 11C As illustrated in the figure, in a multi-frequency mode MFM in which a high-frequency area (e.g., a first display area DA1) and a low-frequency area (e.g., a second display area DA2) exist in one display area DA, the backup period adjustment unit 157 can set the duration of the backup period based on the driving frequency (e.g., the second frequency) of the second display area DA2.

[0189] According to an embodiment of the present disclosure, since a storage area for storing information about the backup time is provided in a nonvolatile memory, information about the final backup time is retained in the nonvolatile memory even when the power is turned off. When the power is turned on again, the sampling unit can determine the sampling position based on the information about the final backup time. As a result, the sampling unit can subsequently sample the line that was not sampled because the power was turned off. This function allows the afterimage compensation circuit to prevent the phenomenon of missing the sampling operation in a specific area when operating in the low frequency mode or the multi-frequency mode.

[0190] Although the embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions can be made without departing from the scope and spirit of the present disclosure as set forth in the claims. Accordingly, the technical scope of the present disclosure is not limited to the detailed description provided herein.

Claims

1. A display device, comprising: A display panel including a plurality of blocks, wherein a plurality of pixels are arranged in each block; and an afterimage compensation circuit configured to receive an input image signal and generate a compensated image signal by compensating the input image signal based on degradation information for each of the plurality of blocks, Wherein, the afterimage compensation circuit comprises: a nonvolatile memory including a first storage area accumulating degraded data for each of the plurality of blocks at each of a plurality of backup times in a preset backup period and a second storage area storing information on a final backup time among the plurality of backup times; and The compensation unit is configured to receive the accumulated degradation data stored in the first storage area as the degradation information, and compensate the input image signal based on the accumulated degradation data to generate the compensated image signal.

2. The display device according to claim 1, wherein: The afterimage compensation circuit further comprises: a sampling unit configured to set a sampling line and sample a line image signal originating from the sampling line based on the compensated image signal; a data processing unit configured to generate degradation data for the sampling line based on the line image signal; and The volatile memory is configured to store the degradation data.

3. The display device according to claim 2, wherein: The sampling unit sequentially selects one of the sampling lines in units of reference frames.

4. The display device according to claim 3, wherein: The reference frame includes a frame.

5. The display device according to claim 2, wherein: The final backup time is the last backup time just before power is turned off, and Wherein, when the power is turned on, the sampling unit sets a reference sampling line among the sampling lines based on the information about the final backup time, and starts a sampling operation from the reference sampling line.

6. The display device according to claim 5, wherein: The information about the final backup time includes at least one of a number of a final reference frame at the final backup time, a number of a final sampling line at the final backup time, and a number of blocks included in the final sampling line.

7. The display device according to claim 2, wherein: The plurality of blocks are arranged in a first direction and in a second direction intersecting the first direction, and The sampling line extends in the first direction or the second direction.

8. The display device according to claim 7, wherein: Each of the plurality of blocks includes a plurality of sub-blocks arranged in the first direction and the second direction, and The sampling unit samples a compensated image signal corresponding to a first subblock of a block in a first sampling line included in a first reference frame as a first line image signal, and samples a compensated image signal corresponding to a first subblock of a block in a second sampling line included in a second reference frame as a second line image signal.

9. The display device according to claim 2, wherein: The degraded data stored in the volatile memory is backed up to the first storage area of ​​the nonvolatile memory at each of the plurality of backup times.

10. The display device according to claim 2, wherein: Each block of the plurality of blocks includes a plurality of sub-blocks, and The sampling unit performs sampling on a sub-block included in each block located on a selected sampling line among the sampling lines.

11. The display device according to claim 2, wherein: The display panel comprises: A first display area operates at a first frequency; and The second display area operates at a second frequency lower than the first frequency.

12. The display device according to claim 11, wherein: The first display area displays an image in units of a first drive frame. The second display area displays an image in units of second drive frames, and The second driving frame includes a full frame and one or more partial frames.

13. The display device according to claim 12, wherein: The sampling unit sequentially selects one of the sampling lines in units of reference frames, and The reference frame is set based on the full frame.

14. The display device according to any one of claims 1 to 13, wherein: The duration of the preset backup period varies depending on the time that has elapsed since power was turned on.

15. A display device, comprising: A display panel including a plurality of blocks, wherein a plurality of pixels are arranged in each block; and an afterimage compensation circuit configured to receive an input image signal and generate a compensated image signal by compensating the input image signal based on degradation information for each of the plurality of blocks, Wherein, the afterimage compensation circuit comprises: a nonvolatile memory that accumulates degradation data for each of the plurality of blocks at each of a plurality of backup times in a preset backup period; a compensation unit configured to receive accumulated degradation data from the nonvolatile memory as the degradation information, and compensate the input image signal based on the accumulated degradation data to generate the compensated image signal; and The backup period adjustment unit is configured to change the duration of the preset backup period based on the driving frequency of the display panel.

16. The display device according to claim 15, wherein: The display panel operates at a frequency above a reference frequency in a first driving mode and operates at a frequency lower than the reference frequency in a second driving mode, and The backup period adjustment unit adjusts the duration of the preset backup period in the second driving mode to be greater than the duration of the preset backup period in the first driving mode.

17. The display device according to claim 15, wherein: The display panel comprises: A first display area operates at a first frequency; and a second display area operating at a second frequency lower than the first frequency, and The first display area displays images in units of first drive frames. The second display area displays an image in units of second drive frames, and The second driving frame includes a full frame and one or more partial frames.

18. The display device according to claim 17, wherein: The backup period adjustment unit sets the duration of the preset backup period based on the second frequency.

19. The display device according to any one of claims 15 to 18, wherein: The afterimage compensation circuit further comprises: a sampling unit configured to set a sampling line and sample a line image signal corresponding to the sampling line by using the compensation image signal; A data processing unit configured to generate degradation data corresponding to the sampling line by using the line image signal; and The volatile memory is configured to store the degradation data.

20. The display device according to claim 19, wherein: The degraded data stored in the volatile memory is backed up to the nonvolatile memory at each of the plurality of backup times.

Images