Reconstruction systems, access methods, devices, media, and products for various storage modes

Abstract

The present application discloses a reconstruction system, access method, device, medium and product for multiple storage modes, which relates to the field of electronic information technology. Compared with the conventional situation where different storage modes correspond to different storage spaces, resulting in a large storage resource overhead, multiple storage modes share a preset storage space, saving storage space while reducing storage resource overhead. By adopting the corresponding connection method of the comparator, inverter and buffer group, through hardware design adjustment, the current data storage status of the preset storage space can be determined in real time, while improving the accuracy of judgment, reducing transmission delay and improving the reliability of the system. Multiple storage modes realize the selection of different access storage modes by selecting signals, and at the same time, realize the arbitrary switching of two access storage modes to realize storage methods of different modes and improve the flexibility of data storage access.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a reconstruction system, access method, device, medium and product of multiple storage modes. Background Art

[0002] In digital circuit design, data is stored using various storage modes corresponding to volatile memory cells (such as random access memory (RAM) and first-in, first-out memory (FIFO)). To accommodate the different storage modes, various volatile memory cells are configured with dedicated storage spaces. Each volatile memory cell occupies a specific storage space. Consequently, when data is stored in storage space according to storage mode A at the same time, the storage space allocated for storage mode B remains idle and wasted, resulting in significant storage overhead.

[0003] Therefore, how to reduce storage overhead to save storage space is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The present application provides a reconstruction system, access method, device, medium and product for multiple storage modes to at least solve the problem of high storage overhead in related technologies where multiple storage modes occupy different storage spaces.

[0005] The present application provides a reconstruction system for multiple storage modes, including a storage module having a counting unit, wherein the counting unit includes a comparator, an inverter, and a buffer group; the multiple storage modes include at least a random access storage mode and a sequential access storage mode; the random access storage mode and the sequential access storage mode share the same preset storage space;

[0006] The input end of the buffer group is connected to the comparator, and the enable end is connected to the inverter, for outputting a data count mark of a current access operation; the comparator receives a storage quantity signal of a preset storage space and a threshold signal to determine a current access operation; the inverter receives a storage mode selection signal;

[0007] The buffer group corresponds to the random access storage mode when in a blocked state; and corresponds to the sequential access storage mode when in a conducting state, so that the access device can access and process the target data according to the current access operation and the data counting mark.

[0008] This application provides a data access method in multiple storage modes, including:

[0009] Get the current access operation and target data;

[0010] In the sequential access storage mode, the target data is accessed and processed according to the current access operation and the data counting mark; wherein the logic circuit function corresponding to the data counting mark is implemented by the reconstruction system of the multiple storage modes.

[0011] This application also provides a true random number access method, including:

[0012] Get true random numbers;

[0013] When the true random number causes data congestion, suspending access processing to the true random number;

[0014] When the true random number is discontinuous, a backup data source is obtained to replace the true random number, and the replaced true random number is used for access processing; wherein the process of the true random number access processing is completed as the steps of the data access method with multiple storage modes.

[0015] This application also provides a method for accessing plaintext data, including:

[0016] Get plaintext data;

[0017] When the first data format of the encrypted plaintext data is different from the second data format of the plaintext data, performing format conversion processing on the plaintext data according to the second data format to obtain target plaintext data;

[0018] Access processing is performed on the target plaintext data to encrypt the plaintext data; wherein the access processing process is completed as the steps of the data access method in multiple storage modes.

[0019] The present application also provides an electronic device, comprising: a memory for storing a computer program; a processor for implementing the steps of the data access method in multiple storage modes, or the true random number access method, or the plaintext data access method when executing the computer program.

[0020] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the computer program implements the data access method of the multiple storage modes, or the true random number access method, or the steps of the plaintext data access method.

[0021] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the data access method of multiple storage modes, or the true random number access method, or the steps of the plaintext data access method.

[0022] The present application discloses a system that utilizes multiple storage modes, primarily random access and sequential access. Firstly, regardless of the storage mode, a single preset storage space is used to access target data. This reduces storage resource overhead, as opposed to conventional systems where different storage modes correspond to separate storage spaces. This system utilizes a single preset storage space for multiple storage modes, saving storage space and reducing storage resource overhead. Secondly, the present application utilizes a corresponding connection scheme for comparators, inverters, and buffer groups. Through hardware design adjustments, the current data storage status of the preset storage space can be determined in real time, improving accuracy while reducing transmission delays and enhancing system reliability. The buffer group corresponds to the random access storage mode when blocked and to the sequential access storage mode when on. Specifically, the output is valid when the storage mode is sequential access. The access process involves accessing the target data in the preset storage space based on the current access operation and the data count flag corresponding to the preset storage space output by the buffer group. Considering the different storage characteristics of the two storage modes, during the sequential access storage mode, the data count flag is used to check the data storage status of the preset storage space, facilitating subsequent access processing and improving access efficiency. On the third aspect, multiple storage modes realize the selection of different access storage modes through selection signals. At the same time, the two access storage modes are switched at will to realize storage methods of different modes. The access process of the sequential access storage mode is compared with the access process of the random access storage mode. Considering the overwriting write and read characteristics of the random access storage mode, normal reading and writing can be achieved even if the data storage status of the preset storage space is full. Before the sequential access storage mode is actually accessed, it is necessary to check the data count mark to save the writing access process when the data storage is full and the reading access process when the data storage is empty. Through this application, the random access storage mode and the sequential access storage mode share a preset storage space, thereby improving the flexibility of data storage access.

[0023] Therefore, the problem of large storage overhead corresponding to different storage spaces in conventional multiple storage modes can be solved, and the access processing of the sequential access storage mode can be realized by connecting the various logic devices of the counting unit. At the same time, multiple storage modes share a preset storage space, reducing storage overhead to save storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A structural diagram of a reconstruction system with multiple storage modes provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the structure of a random access storage mode provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a sequential access storage mode provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of an access operation between a control module and a client provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of two access operations between a control module and a client provided in an embodiment of the present application;

[0030] Figure 6 A circuit diagram of a control module and a client's logic circuit for reading and writing operations on a storage module, respectively, provided in an embodiment of the present application;

[0031] Figure 7 A flowchart of a data access method in multiple storage modes provided in an embodiment of the present application;

[0032] Figure 8 Another storage schematic diagram based on a sequential access storage mode provided in an embodiment of the present application;

[0033] Figure 9 A flowchart of data movement provided in an embodiment of the present application;

[0034] Figure 10 A schematic diagram of the interface connections between modules in an FPGA provided in an embodiment of the present application;

[0035] Figure 11 A state transition diagram of a control module state machine provided in an embodiment of the present application;

[0036] Figure 12 A state transition diagram of a data receiving module state machine provided in an embodiment of the present application;

[0037] Figure 13 A flowchart of a true random number access method provided in an embodiment of the present application;

[0038] Figure 14 A schematic diagram of a true random number scenario provided in an embodiment of the present application;

[0039] Figure 15 A flowchart of a method for accessing plaintext data provided in an embodiment of the present application;

[0040] Figure 16 A cryptographic module data conversion diagram provided in an embodiment of the present application;

[0041] Figure 17 A data format conversion process flow chart provided in an embodiment of the present application;

[0042] Figure 18 A structural diagram of a data access device with multiple storage modes provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0045] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0046] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the data access method of multiple storage modes depends, the specific application environment architecture or specific hardware architecture is described here. In the field of digital circuit design, multiple volatile storage units are used as data storage areas. After the field-programmable gate array (FPGA) loses power, the data stored in the volatile storage unit will be lost. Therefore, the volatile storage unit is only used as a temporary cache area for data. Since the storage modes of each volatile storage unit are different and each has its own advantages and disadvantages, the storage modes of multiple volatile storage units are used simultaneously during the design process to meet the needs of use. However, the storage space corresponding to each of the multiple volatile storage units is large, and thus there is a defect of large storage resource overhead. The reconstruction system of multiple storage modes provided by this application can solve the above technical problems.

[0047] To achieve the reconstruction of multiple storage modes in a system, the volatile storage unit is controlled by designing the state machines of the control module, data receiving module, and storage module, so that the storage module can realize the functions of multiple storage modes according to the user's settings.

[0048] Figure 1 A structural diagram of a reconstruction system with multiple storage modes provided in an embodiment of the present application, such as Figure 1 As shown, a storage module including a counting unit includes a comparator 11, an inverter 12 and a buffer group 13; multiple storage modes include at least a random access storage mode and a sequential access storage mode: the random access storage mode and the sequential access storage mode share the same preset storage space;

[0049] The input end of the buffer group 13 is connected to the comparator 11, and the enable end is connected to the inverter 12, for outputting the data count mark of the current access operation; the comparator 11 receives the storage quantity signal of the preset storage space and the threshold signal to determine the current access operation; the inverter 12 receives the storage mode selection signal;

[0050] The buffer group 13 corresponds to a random access storage mode when in a blocked state; and corresponds to a sequential access storage mode when in a conducting state, so that the access control device can access and process the target data according to the current access operation and the data counting mark.

[0051] Specifically, the reconstruction system includes a storage module having a counting unit. The counting unit is primarily used to count the amount of data in the storage module. The counting process is combined with a comparator and an inverter, and a data count mark of the current access operation is output through the output of the buffer group. The input of the buffer group is connected to the comparator, and the enable terminal is connected to the inverter. The comparator receives a storage quantity signal of a preset storage space and a threshold signal to determine whether the current access operation corresponds to a read operation or a write operation. The inverter receives a storage mode selection signal, such as CS=0 or 1. When CS=1, subsequent access is performed in a random access storage mode, and when CS=0, subsequent access is performed in a sequential access storage mode. The setting of the storage mode selection signal can be an instruction issued by the host computer or a setting of the control module. This application does not specifically limit the conversion between the two storage modes. The storage mode can be selected based on conventional settings or based on the task. This application mainly sets the access processing process under different storage modes. The current access operation can be a read operation or a write operation. In this embodiment, taking into account the read and write operations between the control module, the storage module and the data receiving module, it is possible to implement only one access operation between any two modules, or it is possible to implement two access operations between any two modules. There is no limitation here and it can be set according to actual conditions.

[0052] The buffer group corresponds to the random access storage mode when in the blocked state and the sequential access storage mode when in the conductive state. The blocked state is caused by a low level input to the enable terminal, while the conductive state corresponds to a high level input to the enable terminal. Considering the inverter setting, when receiving the random access storage mode, the inverter output is low, which means that the random access storage mode is invalid. Conversely, the sequential access storage mode is valid.

[0053] This application takes into account the conventional random access storage mode, which can achieve an overwrite feature. If the storage space is full during a write operation, an overwrite can be achieved, so there is no need for a counting unit. Regarding the sequential access storage mode, the overwrite feature cannot be achieved. When the storage space is full, it is necessary to wait for a free address before writing. Therefore, the full and dissipated storage space conditions are obtained using a counting unit, that is, the data counting tag is known. Therefore, during access processing, the access control device only needs to access the target data according to the current access operation and the data counting tag.

[0054] Multiple storage modes include at least random access storage mode and sequential access storage mode. Random access storage mode here only corresponds to the same type, which can be static random access memory (SRAM), dynamic random access memory (DRAM) or random access memory (RAM), etc. It allows users to randomly access any location in the memory and can quickly read or write data at any address without the need for sequential access. Figure 2 A schematic diagram of a random access storage mode provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, addressing is required before operations are performed. Data is written to / read from the memory cells according to the address, for example, writing Data1 to the cell at address 0x0001 and reading Data3 from the cell at address 0x0003. The advantage of RAM is its long data lifetime. After reading data from a certain address cell, the data remains in that cell until it is overwritten by new data. However, its disadvantage is that data access speed is slow when the amount of data is large. Addressing is required before data operations can be performed. The address of each memory cell to be written / read must be given before data can be written / read from the cell.

[0055] Sequential access storage mode, mainly FIFO, is based on a data structure that is read in the order in which it was written, that is, the earliest written data is read first. Figure 3 A structural diagram of a sequential access storage mode provided in an embodiment of the present application is shown as follows: Figure 3 As shown, data can be continuously manipulated, written into the FIFO in the order in which it enters. When reading data, data at the bottom of the FIFO is read sequentially, with the data that enters the FIFO first being read out first. For example, Data0 enters the FIFO first and is read out first. The advantage of a FIFO is that it doesn't require complex address management and can continuously read and write data, resulting in high data access efficiency and suitable for high-speed data processing scenarios. However, its disadvantage is that data can only be processed sequentially, making it unsuitable for situations where specific data needs to be processed first.

[0056] Regarding when to perform the corresponding storage mode, the storage mode select signal can be read. If CS=1, subsequent access is performed in random access storage mode. When CS=0, subsequent access is performed in sequential access storage mode. The specific value of the flag bit can vary and is not limited here. It can be set according to actual conditions.

[0057] When the current storage mode is the random access storage mode, the target data in the preset storage space is accessed and processed according to the current access operation. This includes the access process of writing the target data to the preset storage space and the access process of reading the target data from the preset storage space. There is no limitation here. This is the same as the conventional access processing, or it can be different.

[0058] When the current storage mode is the sequential access storage mode, the target data is accessed and processed according to the current access operation and the data counting mark. In addition to the access type being the same as the read and write operations in the above embodiment, the data counting mark is additionally added. This is because the sequential access storage mode cannot achieve the feature of overwriting. The data counting mark represents the data storage status of the preset storage space.

[0059] When storing data in the preset storage space, if the storage space is full, no subsequent writing will be performed. Therefore, a data count mark is used to mark when writing can be performed, so that the target data can be written to the preset storage space. If the storage space is empty, no subsequent reading will be performed. The data count mark is used to mark when reading can be performed, so that the target data can be read from the preset storage space.

[0060] The output of the data counting mark is realized by the logic circuit of the counting unit corresponding to the preset storage space, and the output value depends on the number of data in each storage unit of the preset storage space, that is, the counting unit records and accumulates.

[0061] Compared to conventional solutions that directly receive a flag bit to represent the data count, this embodiment uses a hardware-based logic circuit design, enabling real-time response and avoiding the latency associated with software-based accumulation and transmission to the controller or data receiving module. The logic circuitry of this embodiment is tightly integrated with the rest of the system's hardware, minimizing external interference and improving overall system performance.

[0062] According to the embodiments of the present application, since the various storage modes are primarily classified as random access storage mode and sequential access storage mode, firstly, regardless of the storage mode, a preset storage space is shared for accessing target data. Compared to conventional storage modes where different storage modes correspond to different storage spaces, resulting in high storage resource overhead, the present application utilizes a single preset storage space for multiple storage modes, saving storage space and reducing storage resource overhead. Secondly, the present application utilizes a corresponding connection method for the comparator, inverter, and buffer group. Through hardware design adjustments, the current data storage status of the preset storage space can be determined in real time, improving judgment accuracy while reducing transmission delay and enhancing system reliability. The buffer group corresponds to the random access storage mode when blocked and to the sequential access storage mode when conducting, i.e., the output is valid when the storage mode is the sequential access storage mode. The access process accesses the target data in the preset storage space based on the current access operation and the data count flag corresponding to the preset storage space output by the buffer group. Considering the different storage characteristics of the two storage modes, during the sequential access storage mode, the data storage status of the preset storage space is checked based on the data count flag to facilitate subsequent access processing and improve access efficiency. On the third aspect, multiple storage modes realize the selection of different access storage modes through selection signals. At the same time, the two access storage modes are switched at will to realize storage methods of different modes. The access process of the sequential access storage mode is compared with the access process of the random access storage mode. Considering the overwriting write and read characteristics of the random access storage mode, normal reading and writing can be achieved even if the data storage status of the preset storage space is full. Before the sequential access storage mode is actually accessed, it is necessary to check the data count mark to save the writing access process when the data storage is full and the reading access process when the data storage is empty. Through this application, the random access storage mode and the sequential access storage mode share a preset storage space, thereby improving the flexibility of data storage access.

[0063] Therefore, the problem of large storage overhead corresponding to different storage spaces in conventional multiple storage modes can be solved, and the access processing of the sequential access storage mode can be realized by connecting the various logic devices of the counting unit. At the same time, multiple storage modes share a preset storage space, reducing storage overhead to save storage space.

[0064] In some embodiments, the buffer group includes a first buffer group including a first buffer and a second buffer;

[0065] The input terminals of the first buffer and the second buffer are both connected to the comparator, and the enable terminals are both connected to the inverter; the first buffer is used to output a write mark, and the second buffer is used to output a read mark.

[0066] Specifically, in this embodiment, considering that access operations include read operations and write operations, which correspond to different flags, in random access storage mode, the write flag and read flag signals are in a high-impedance state. In sequential access storage mode, the write flag Full indicates writing (Full=0) or prohibiting writing (Full=1), and the read flag (Empty) indicates reading (Empty=0) or prohibiting reading (Empty=1).

[0067] A write mark is outputted through the output end of the first buffer, and a read mark is outputted through the output end of the second buffer, for reference when accessing target data in a sequential access storage mode.

[0068] The connection relationship between the first buffer and the second buffer provided in this embodiment is targeted in the sequential access storage mode. By setting the write mark and the read mark, the accuracy of writing and reading during the access process of the sequential access storage mode is ensured, preventing data congestion or data discontinuity.

[0069] In some embodiments, the comparator includes a first comparator and a second comparator, and the inverter includes a first inverter and a second inverter;

[0070] The first comparator and the second comparator each receive a storage quantity signal at a first terminal; the first comparator receives a total storage quantity signal of the threshold signal at a second terminal, and an output terminal is connected to an input terminal of the first buffer; the second comparator receives a value signal of the threshold signal at a second terminal, and an output terminal is connected to an input terminal of the second buffer;

[0071] The first inverter and the second inverter each receive a storage mode selection signal at their input terminals; the output terminal of the first inverter is connected to the enable terminal of the first buffer; and the output terminal of the second inverter is connected to the enable terminal of the second buffer.

[0072] Specifically, if Figure 1As shown, the first buffer group (Tri_1~Tri2): when the enable terminal (en) of the buffer is at a high level, the buffer is turned on and can output data; when the enable terminal is at a low level, the buffer is blocked and data cannot be output. At this time, the output terminal is in a high-impedance state.

[0073] Regarding the storage quantity signal, it can be obtained directly or determined through the accumulator (ADD). When using the accumulator, the number of data in each storage unit in the storage area is counted and the count value cnt (0≤cnt≤M) is output.

[0074] The first comparator, also known as the equality detector (JMP), compares input terminals 1 and 2. When input terminal 1 = the value of input terminal 2, JMP outputs a high level; when input terminal 1 ≠ the value of input terminal 2, JMP outputs a low level.

[0075] The second comparator compares input terminals 1 and 2. When the value of input terminal 1 is less than the value of input terminal 2, the comparator outputs a high level; when the value of input terminal 1 is greater than or equal to the value of input terminal 2, the comparator outputs a low level.

[0076] The first inverter (NOT_1) and the second inverter (NOT_2) are implemented by NOT gates, which invert the input values ​​and output them.

[0077] The accumulator (ADD) has an input connected to the output port of a storage unit in a preset storage space, and an output connected to the first terminals of each of the first and second comparators to output a storage quantity signal. The first comparator receives a total storage quantity signal (M) corresponding to a threshold signal at its second terminal, and its output is connected to the input of the first buffer. The second comparator receives a value signal "1" corresponding to the threshold signal at its second terminal, and its output is connected to the input of the second buffer.

[0078] The storage mode selection signal is input to the input terminals of the first and second inverters, respectively. The output terminal of the first inverter is connected to the enable terminal of the first buffer, and the output terminal of the second inverter is connected to the enable terminal of the second buffer. The output terminal of the first buffer outputs a write flag (Full), and the output terminal of the second buffer outputs a read flag (Empty).

[0079] This embodiment provides a method for comparing the connection relationship between the logic devices by counting the number of units, and responding to the data storage status of the storage space in real time to improve the accuracy of the judgment.

[0080] In some embodiments, the process of outputting the status of the first buffer and the second buffer includes:

[0081] When the storage mode selection signal is the random access storage mode, the first inverter and the second inverter both output the second level, and it is determined that the first buffer and the second buffer are in a blocking state;

[0082] When the storage mode selection signal is the sequential access storage mode, the first inverter and the second inverter both output the first level, and it is determined that the first buffer and the second buffer are in the on state.

[0083] Specifically, when the storage mode selection signal is the random access storage mode, the first inverter and the second inverter both output the second level, and the signals at the enable ends of the first buffer and the second buffer are determined to be the second level, corresponding to the first buffer and the second buffer being in a blocked state.

[0084] When the storage mode selection signal is the sequential access storage mode, the first inverter and the second inverter both output the first level, and the signals at the enable ends of the first buffer and the second buffer are determined to be the first level, corresponding to the first buffer and the second buffer being in the on state.

[0085] In conjunction with the above embodiment, when an accumulator is used, the count value cnt of the accumulator (ADD) is output to terminal 1 of the first comparator and terminal 1 of the second comparator, respectively. Alternatively, a storage quantity signal can be directly obtained and input to the corresponding terminals 1 of the first and second comparators, respectively. The value corresponding to input terminal 2 of the first comparator is M, and the value corresponding to input terminal 2 of the second comparator is '1'. The output of the first comparator is connected to the input of the first buffer, and the output of the second comparator is connected to the input of the second buffer. The mode select signal CS is connected to the inputs of the first and second inverters, respectively. The output of the first inverter is connected to the enable terminal en of the first buffer, and the output of the second inverter is connected to the enable terminal en of the second buffer. The output of the first buffer is a Full signal, and the output of the second buffer is an Empty signal.

[0086] When the mode selection signal is 1, the random access storage mode is selected, and CS becomes '0' after passing through the first inverter and the second inverter. At this time, the en terminals of the first buffer and the second buffer are low, the tri-state buffer is in a blocked state, and the Full and Empty signals are in a high-impedance state;

[0087] When the mode selection signal is 0, the sequential access storage mode is selected. CS becomes '1' after passing through the first inverter and the second inverter. At this time, the en terminals of the first buffer and the second buffer are high, and the tri-state buffer is in the on state. At this time, the output of the Full and Empty signals depends on the count value cnt of ADD.

[0088] The state output process of the first buffer and the second buffer provided in this embodiment is effective for the sequential access storage mode in combination with the random access storage mode and the sequential access storage mode, thereby improving the flexible switching between the sequential access storage mode and the random access storage mode and realizing access processing of different storage modes while sharing the same preset storage space.

[0089] In some embodiments, the process of outputting the data count mark includes:

[0090] When the storage quantity signal is 0, the first comparator outputs the second level, and outputs a write mark through the first buffer as write; the second comparator outputs the first level, and outputs a read mark through the second buffer as read-prohibit;

[0091] Alternatively, when the storage quantity signal is greater than or equal to 1 and less than the total storage quantity signal, the first comparator outputs a second level, and after passing through the first buffer, outputs a write mark as write; the second comparator outputs a second level, and after passing through the second buffer, outputs a read mark as read;

[0092] Alternatively, when the storage quantity signal is equal to the total storage quantity signal, the first comparator outputs a first level, and after passing through the first buffer, the output write mark is write-prohibited; the second comparator outputs a second level, and after passing through the second buffer, the output read mark is read.

[0093] Specifically, when cnt = 0: After the first comparator compares input terminals 1 and 2, since 0 ≠ M, the first comparator outputs a low level. After passing through the first buffer, the Full signal is '0'. Correspondingly, the second comparator's input terminal 1 (value 0) is less than input terminal 2 (value 1). The second comparator outputs a high level. After passing through the second buffer, the Empty signal is '1'. This indicates that the input is not full and the output is empty.

[0094] Or, when 1≤cnt<M: the Full signal is '0', and the second comparator outputs a low level because input terminal 1 ≥ input terminal 2, making the Empty signal '0'; this means that the input is not full and the output is not empty;

[0095] Alternatively, when cnt=M: the first comparator outputs a high level because input 1 = input 2, making the Full signal '1'; the second comparator outputs an Empty signal still '0' because input 1 > input 2; this indicates that the input is full but the output is not empty.

[0096] The logical relationship between the various logic devices of the logic circuit provided in this embodiment can determine the current data storage status of the preset storage space in real time, thereby improving the judgment accuracy, reducing transmission delays, and improving system reliability.

[0097] In some embodiments, the access control device includes a control module and a data receiving module; wherein, ports corresponding to write operations and read operations are set between each module of the control module, the storage module and the data receiving module to implement the access processing process of read and write operations between the control module and the storage module and between the storage module and the data receiving module.

[0098] It should be noted that the access control device includes a control module and a data receiving module. Basic operation is that the control module writes target data to the storage module, and the data receiving module reads data from the storage module. The data receiving module of the access control device in this embodiment can be located in the reconstruction system or on the client side, without limitation. The data receiving module can be configured based on actual circumstances. In other words, the access control device can be located in or outside the reconstruction system.

[0099] Figure 4 A schematic diagram of an access operation between a control module and a client provided in an embodiment of the present application is shown as follows: Figure 4 As shown, the control module controls the storage module, enabling reconfiguration between random access and sequential access storage modes. The control module receives data from an external data source (host computer) or uses data stored in the control module to write data to the storage module. The data receiving module acts as a client, reading data from the storage module. The data receiving module can be external to the FPGA, such as a standalone chip or module, or internal to the FPGA as a submodule. In this example, two groups of ports are configured. The control module writes data to the storage module via the write port, and the data receiving module reads data from the storage module via the read port. This dual port configuration allows the control module and data receiving module to access the storage module simultaneously. As soon as the control module writes data to the storage module, the data receiving module can read it, eliminating the need to wait until all data has been written to the storage module before the data receiving module can read it. This improves data processing speed.

[0100] Compared with the conventional technical solution that has a random access storage mode or a sequential access storage mode, the corresponding storage space will set two ways of setting the corresponding storage modules between the control module and the client, that is, two write operation ports are set between the control module and the storage module, one write operation port is connected to the storage module a accessed in the random access storage mode, and the other write operation port is connected to the storage module b accessed in the sequential access storage mode. Two read operation ports are set between the storage module and the client, one read operation port reads from the storage module a in the random access storage mode, and the other read operation port reads from the storage module b in the sequential access storage mode. Compared with the conventional method of setting two storage modules, the present application only sets one storage module for reading, so that the functions of different storage modes can be reused in the same storage module, saving storage space. In addition, setting two groups of ports can realize simultaneous access operations on the storage module, thereby improving data processing speed.

[0101] In addition, in this embodiment, Figure 5 A schematic diagram of two access operations between a control module and a client provided in an embodiment of the present application, such as Figure 5 As shown, in this embodiment, the control module and the client independently perform writing and reading operations on the storage module.

[0102] In this embodiment, there is a port setting for write operation and read operation between every two modules, so that each module can independently perform write and read operations on the storage module, thereby improving data processing speed and flexibility.

[0103] In some embodiments, the buffer group further includes a second buffer group;

[0104] The output end of the first buffer group is connected to the input end of the second buffer group;

[0105] The enable terminal of the second buffer group receives the register value;

[0106] The output end of the second buffer group outputs a data counting mark. When the register value is 1, the second buffer group is in a conducting state. When the register value is 0, the second buffer group is in a blocking state.

[0107] Specifically, Figure 6 A circuit diagram of a control module and a client's read and write operation logic circuit for a storage module provided in an embodiment of the present application, such as Figure 6 As shown, by adding an additional second buffer group, any access control device can realize access processing of read operations and write operations in a sequential access storage mode by adding the second buffer group and an additional register value.

[0108] In some embodiments, the second buffer group includes a third buffer, a fourth buffer, a fifth buffer, and a sixth buffer; the register value includes a first register value and a second register value;

[0109] The input ends of the third buffer and the fourth buffer are connected to the output end of the first buffer, and are used for outputting corresponding write marks of the control module and the data receiving module;

[0110] The input ends of the fifth buffer and the sixth buffer are connected to the output end of the second buffer, and are used for outputting the corresponding read marks of the control module and the data receiving module;

[0111] The third buffer and the fifth buffer each have an enable terminal to receive the first register value; the fourth buffer and the sixth buffer each have an enable terminal to receive the second register value.

[0112] Specifically, if Figure 6 As shown, a second 1-bit buffer group (Tri_3 through Tri_6) is added, along with the first and second register values. This allows the Full and Empty signals to be divided into two groups when CS = '0': Full_A and Empty_A are provided to the control module, while Full_B and Empty_B are provided to the data receiving module. By setting a register (Prio), the data storage status in FIFO mode can be queried, preventing conflicts between the control module and the data receiving module when reading and writing to the storage unit. The initialized Prio values ​​are A = '0' and B = '0'. At this point, Tri_3 through Tri_6 are in a blocked state, outputting high-impedance signals. It should be noted that A and B in this embodiment represent the first and second register values, respectively.

[0113] The third and fourth buffers each have their inputs connected to the output of the first buffer, corresponding to the write flag (Full_A) of the output control module and the write flag (Full_B) of the data receiving module. The fifth and sixth buffers each have their inputs connected to the output of the second buffer, corresponding to the read flag (Empty_A) of the output control module and the read flag (Empty_B) of the data receiving module.

[0114] The third and fifth buffers each receive a first register value at their enable terminals. When the first register value is 1, the control module outputs a read flag or a write flag when performing a read or write operation. In this case, when the first register value is set to 1 and the second register value is set to 0, the data receiving modules corresponding to the output terminals of the fourth and sixth buffers are disabled.

[0115] The fourth and sixth buffers each receive a second register value at their enable terminals. When the second register value is 1, the data receiving module performs a read or write operation and outputs a read flag or a write flag. At this time, when the second register value is set to 1, the first register value is set to 0, and the control modules corresponding to the output terminals of the third and fifth buffers are disabled.

[0116] The control module and the data receiving module provided in this embodiment respectively output corresponding data counting marks when performing read operations on the storage module, thereby improving data processing efficiency and increasing the flexibility of access operations.

[0117] In some embodiments, the process of outputting the data count mark of the second buffer group includes:

[0118] When the control module performs a read operation or a write operation, the first register value is set to 1 and the second register value is set to 0, and the output ends of the third buffer and the fifth buffer are determined to output a read mark or a write mark respectively;

[0119] Alternatively, when the data receiving module performs a read operation or a write operation, the first register value is set to 0 and the second register value is set to 1, and the output ends of the fourth buffer and the sixth buffer are determined to output a corresponding read mark or a corresponding write mark.

[0120] Specifically, based on the logical principles of the above-mentioned logic circuit, when the control module needs to read / write the storage area, it sets A='1', B='0' to turn on the third buffer and the fifth buffer, so that the Full_A and Empty_A signals can be obtained; when the control module completes reading / writing the storage area, it sets A='0', B='0' to release the control right of the signal; that is, the first register value and the second register value are reset.

[0121] When the data receiving module needs to read / write the storage area, it sets A='0', B='1' to turn on the fourth and sixth buffers, so that the Full_B and Empty_B signals can be obtained; when the data receiving module completes reading / writing the storage area, it sets A='0', B='0' to release control of the signal.

[0122] This embodiment provides a method for releasing the control right of the signal after the access is completed, so as to facilitate the access processing of other subsequent access operations and further improve the data processing efficiency.

[0123] In some embodiments, further comprising a seventh buffer;

[0124] The input end of the seventh buffer is connected to the first data output port of the control module, the enable end is connected to the write enable port, and the output end is connected to the write data port of the storage module;

[0125] The seventh buffer is configured to be turned on when the write enable port outputs the first level, and to write the target data into the storage module.

[0126] like Figure 6 As shown, the seventh buffer's input is connected to the control module's first data output port (DATA_A_out[7…0]), its enable port is connected to the write enable port (A_wren), and its output is connected to the storage module's write data port (D_in[7…0]). The write enable signal (wren) is connected to the en terminal. When wren = '1', data from the first data output port (DATA_A_out[7…0]) can be output to the storage area through the seventh buffer. When wren = '0', data from the first data output port (DATA_A_out[7…0]) is blocked by the seventh buffer and cannot be written to the storage area.

[0127] The seventh buffer provided in this embodiment is configured with the ports of the control module and the storage module, so that the control module can smoothly write the target data into the storage module, thereby ensuring the accuracy of data circulation.

[0128] In some embodiments, further comprising an eighth buffer, a ninth buffer, and a tenth buffer;

[0129] The output end of the eighth buffer is connected to the first data input port of the control module, the enable end is connected to the read enable port, and the input end is connected to the read data port of the storage module;

[0130] The input end of the ninth buffer is connected to the second data output port of the data receiving module, the enable end is connected to the write enable port of the data receiving module, and the output end is connected to the write data port of the storage module;

[0131] The output end of the tenth buffer is connected to the second data input port of the data receiving module, the enable end is connected to the read enable port of the data receiving module, and the input end is connected to the read data port of the storage module.

[0132] like Figure 6 As shown, 8-bit buffers (eighth, ninth, and tenth buffers) are added. A first data input port (DATA_A_in[7…0]) and a read enable port (A_rden) are added to the control module. Reading from a storage cell is possible only when the control module sets A_rden to '1'; reading from a storage cell is disabled when A_rden is '0'. The data receiving module also adds a second data output port (DATA_B_out[7…0]), a write enable port (B_wren), and a read enable port (B_rden).

[0133] The output end of the eighth buffer is connected to the first data input port (DATA_A_in[7...0]) of the control module, the enable end is connected to the read enable port (A_rden), and the input end is connected to the read data port (A_D_out[7...0]) of the storage module;

[0134] The input end of the ninth buffer is connected to the second data output port (DATA_B_out [7…0]) of the data receiving module, the enable end is connected to the write enable port (B_wden) of the data receiving module, and the output end is connected to the write data port (B_D_in [7…0]) of the storage module;

[0135] The output end of the tenth buffer is connected to the second data input port (DATA_B_in[7……0]) of the data receiving module, the enable end is connected to the read enable port (B_rden) of the data receiving module, and the input end is connected to the read data port (B_D_out[7……0]) of the storage module.

[0136] This embodiment provides that when the control module and the data receiving module respectively operate the storage module, the corresponding buffers are set through their respective ports to determine when to be turned on and when to be blocked, so as to ensure smooth data reading operations and improve the orderliness of access operations.

[0137] Furthermore, this application also provides a data access method in multiple storage modes. Figure 7 A flowchart of a data access method in multiple storage modes provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the method includes:

[0138] S11: Get the current access operation and target data;

[0139] S12: In the sequential access storage mode, access processing is performed on the target data according to the current access operation and the data counting mark; wherein the logic circuit function corresponding to the data counting mark is implemented by a reconstruction system of multiple storage modes.

[0140] Specifically, in this embodiment, it should be noted that in random access storage mode, the process may be the same as or different from conventional access processing, in combination with the situations described in the above embodiments, and this is not limited here. In sequential access storage mode, the target data is accessed and processed based on the current access operation and the data count flag, and the implementation method is the same as that of the corresponding embodiments in the above embodiments, and will not be repeated here.

[0141] For descriptions of features in the embodiments corresponding to the data access methods of multiple storage modes, please refer to the relevant descriptions of the embodiments corresponding to the reconstruction systems of multiple storage modes, which will not be repeated here.

[0142] In some embodiments, during access processing in a sequential access storage mode, storage addresses are pre-set for storage data of storage units in a preset storage space to implement access processing according to the storage addresses.

[0143] Specifically, compared with the conventional random access storage mode in which address information is accessed sequentially, this embodiment adds a corresponding storage address in each storage unit, so that when writing data, the address of a certain storage unit and the number of data to be written can be given arbitrarily. The address is automatically incremented after each data is written to achieve continuous writing of multiple data, for example, starting from address 0x0001, 3 data Data1~Data3 are written continuously, thereby improving the deficiency of the existing technology that it can only write sequentially from the top of the FIFO; and it can realize the data overwriting writing method, that is, when there is data in a certain storage unit, the new data can be used to overwrite the old data.

[0144] When the sequential access storage mode provided in this embodiment is used for access processing, the storage address of the storage data of the storage unit of the preset storage space is set in advance to realize access processing according to the storage address, thereby improving the flexibility and diversity of the addressing method of accessing the preset storage space of the sequential access storage mode, and also improving the efficiency of data reading and writing.

[0145] In some embodiments, when the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including:

[0146] Obtaining first target sub-data of a storage unit and a corresponding data address;

[0147] Controlling the access control device to read the first target sub-data according to the data address;

[0148] The next second target sub-data of the first target sub-data is migrated to the data address as the new first target sub-data for reading until all the target data are read.

[0149] Specifically, Figure 8 Another storage diagram based on the sequential access storage mode provided in the embodiment of the present application is as follows: Figure 8 As shown in the figure, using FIFO as an example, when reading data, multiple data can be read continuously starting from any storage unit. After each data is read, the data in the subsequent units are automatically moved forward, improving the existing technology that can only read sequentially from the bottom of the FIFO. For example, after reading data 1 from address 0x0001, data 2 is moved to address 0x0001, data 3 is moved to address 0x0002, and so on.

[0150] When CS = '0', the storage module's state machine 3 reads the specific address value ADDR_B[n...0] sent by the data receiving module and the value len2 of register 2. Each time the data receiving module reads a piece of data, state machine 3 sequentially shifts the data following the address unit Addr, thus implementing the FIFO data flow function. For example, if Address = 0x0001 and len2 = 2, after the data receiving module reads data Data_1 from 0x0001, state machine 3 sequentially shifts data Data_2 from 0x0002 to 0x0001, data Data_3 from 0x0003 to 0x0002, and so on. Subsequently, the data receiving module continues to read data Data_2 from 0x0001, and state machine 3 shifts data Data_3 from 0x0002 to 0x0001, and so on.

[0151] Specific reading method: Obtain the first target sub-data and the corresponding data address of the storage unit, and control the access control device to read the first target sub-data based on the data address. The access control device can be a data receiving module or a control module, and this is not limited here. When reading the target data of the storage module based on the data receiving module, the data receiving module is controlled to read the first target sub-data from the data address via the data read port (D_out[7…0]) of the data receiving module, so as to receive the first target sub-data from the second data input port (DATA_B_in[7…0]) corresponding to the second port (ADDR_B[n…0]). The address information of the first target sub-data is left blank, and the next second target sub-data of the first target sub-data is moved to the data address of the first target sub-data as the new first target sub-data. The process then returns to the step of controlling the data receiving module to read the first target sub-data from the data address via the data read port until all the target data are read.

[0152] Regarding the volatile storage area of ​​the storage module, the size of the storage area and the data width of each storage unit can be set by the administrator / user, for example, 8 bits × M is set, and each storage unit is 8 bits, corresponding to the data output interface width of the control module; , which is related to the width of the address interface (ADDR_A[n……0]) of the control module: for example, when n=7, it is an 8-bit address [7……0], Therefore, the storage area contains 256 storage units, and the storage area size is 256×8 bits. The storage unit can also be set to 16 bits, 32 bits, etc., which is not specifically limited in this application.

[0153] Implementation process of state machine 3 in the storage module:

[0154] (1) When the data receiving module gives the address of the storage unit through the ADDR_B[n……0] interface, it enters the start state and the state machine sets the temporary variables ptr and len;

[0155] (2) len stores the value len2 of register 2 read;

[0156] (3) ptr stores the address value Addr read from the ADDR_B[n……0] interface;

[0157] (4) The state machine delays one clock cycle Clk, waiting for the data receiving module to read 1 data in the storage unit at address Addr;

[0158] (5) Then determine whether the address unit of Addr+1 is empty. If it is empty, it means there is no data and the process ends. If it is not empty, it means there is data. The data in the address unit of Addr+1 is moved to the address unit of Addr, that is, Data[ptr]=Data[ptr+1], and the ptr value is increased by 1 to process the next data. The data after the address of Addr+1 is moved forward in sequence until the last storage unit is processed or an empty storage unit is detected. At this point, the data receiving module has read a data from the address of Addr, and the state machine 3 has completed the data movement after the address of Addr.

[0159] (6) Determine whether the data receiving module has read len data. If not, jump to step (3) and reassign Addr to ptr and repeat (4) and (5) until the data receiving module has read len data.

[0160] Figure 9 A flowchart of data movement provided in an embodiment of the present application is as follows: Figure 9 Shown, including:

[0161] S21: Read the register value of register 2 of the data receiving module;

[0162] S22: The temporary variable storage of the state machine 3 of the storage module reads the address value from the second port;

[0163] S23: State machine 3 delays one clock cycle, waiting for the data receiving module to read a data of the address value storage unit;

[0164] S24: Determine whether the address unit corresponding to the address value plus 1 is empty; if it is empty, end; if not, proceed to step S25;

[0165] S25: Move the data of the address unit corresponding to the address value plus 1 to the storage unit corresponding to the address value, so that the temporary variable is increased by 1, and the register value of register 2 is reduced by 1 to process the next data, so that the data after the address unit corresponding to the address value plus 1 is moved forward, and return to step S24 until the register value is equal to 0, and end.

[0166] When the data receiving module gives the address of the storage unit through the ADDR_B[n...0] interface, it enters the start state, and the state machine sets temporary variables ptr and len; len stores the value len2 read from register 2; ptr stores the address value Addr read from the ADDR_B[n...0] interface; state machine 3 delays one clock cycle Clk, waiting for the data receiving module to read 1 data in the address Addr storage unit; then determines whether the address unit Addr+1 is empty. If it is empty, it means there is no data and the process ends; if it is not empty, it means there is data and the address Addr+1 is set. The data in the address unit is moved to the Addr address unit, that is, Data[ptr]=Data[ptr+1], and the ptr value is increased by 1 to process the next data, so that the data after the Addr+1 address is moved forward in sequence until the last storage unit is processed or an empty storage unit is detected; at this point, the data receiving module has read a data from the Addr address, and state machine 3 completes the data forward movement after the Addr address; it is determined whether the data receiving module has read len data. If not, jump to step (3) to reassign Addr to ptr and repeat the execution.

[0167] In this embodiment, data movement involves the automatic migration of data from subsequent units after each data read. This automatic migration mechanism ensures that subsequent data is immediately added after each data read, reducing data read latency and improving data processing efficiency. This ensures the continuity of the data stream and avoids processing delays caused by data discontinuities. Automatic migration ensures timely data access and processing, avoiding overflows caused by data accumulation in sequential access storage structures. It also prevents "starvation" on the reader side due to insufficient data.

[0168] In some other embodiments, when the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including:

[0169] Get multiple consecutive data and corresponding data addresses;

[0170] Controlling the access control device to read a plurality of continuous data according to the data address;

[0171] Correspondingly, after completing the read access of the target data, it also includes:

[0172] The target data at the next data address of the data address of the storage unit is migrated to the data address.

[0173] Specifically, obtaining the first target sub-data to the Nth target sub-data of the storage unit and the corresponding data addresses respectively;

[0174] Controlling the data receiving module to read target data from the data address via the read data port, so as to receive the target data to the second data input port corresponding to the second port;

[0175] Correspondingly, after completing the read access of the target data, it also includes:

[0176] The address information of the first to Nth target sub-data is left vacant, and data of the address information next to the address information of the first to Nth target sub-data in the storage unit is migrated to the address information of the first to Nth target sub-data.

[0177] Specifically, compared with the above embodiment, this embodiment performs automatic migration after reading N data each time. In the case where the target data consists of multiple sub-target data, the multiple consecutive sub-target data are read at one time to be received by the data receiving module.

[0178] In this embodiment, data movement reduces the number of read operations by reading multiple data points at a time, thereby improving data processing efficiency. Batch reading reduces the waiting time between each read operation, making the data flow more continuous. By reducing the frequency of read operations, the error rate that may be caused by frequent operations is reduced.

[0179] In some embodiments, when the current access operation is a write operation and the control module writes data to the storage module, access processing is performed on the target data according to the current access operation and the data count tag, including:

[0180] When the write state information of the control module is a write operation and the data count mark is a write mark, entering the write data state of the target data;

[0181] Writing the target data from the first data output port corresponding to the first port of the control module to the write data port of the storage module;

[0182] The register mark value of the control module is reduced by 1 and the address information is increased by 1 to enter the waiting state;

[0183] When the updated register mark value is greater than 0 and the data count mark is a write mark, the next target data is written until the register mark value is 0, thereby completing the write processing of all target data.

[0184] Specifically, the write status information and the first port corresponding to the control module are obtained; the data stored in the first port is used as the target data; when the write status information is a write operation and the data count mark is a write mark, the write data state of the target data is entered; the write data port corresponding to the storage module is obtained; the target data is written from the first data output port corresponding to the first port to the write data port; the register mark value of the control module is reduced by 1, and the address information of the control module is increased by 1, and the waiting state of the control module is entered; when the updated register mark value is greater than 0 and the data count mark is a write mark, the step of entering the write data state of the target data is returned to write the next target data until the register mark value is 0, completing the access processing of all target data of the control module to the preset storage space.

[0185] Figure 10 A schematic diagram of the interface connection between modules in an FPGA provided in an embodiment of the present application is shown as follows: Figure 10 As shown, a set of write operation ports exists between the control module and the storage module, including a mode select signal interface (CS), a first port (ADDR_A[n…0]), a first data output port (DATA_A_out[7…0]), a write enable port (wren) corresponding to the write operation instruction, and a data count flag port (Full). The left-hand side interfaces of the control module include a clock signal interface (Clk) and a reset signal interface (Reset). The FPGA interface settings connect to the clock module, reset module, and power supply for subsequent normal access processing. The clock module, which can be a clock source such as a crystal oscillator, provides the system clock signal CLK for the FPGA. The reset module, which provides the system reset signal RST after the FPGA is powered on, provides the operating voltage for the FPGA.

[0186] Clk: clock signal, connected to the system clock signal of FPGA;

[0187] Reset: reset signal, connected to the system reset signal of FPGA;

[0188] CS: Mode selection signal for random access storage mode and sequential access storage mode. When the control module or host computer sets CS='1', the storage module implements the random access storage mode function; when CS='0', it implements the sequential access storage mode function;

[0189] ADDR_A[n……0]: address output interface, used to address the storage unit of the storage module. For example, when n=7, it is 8-bit address [7……0]. The addressing range is storage units;

[0190] DATA_A_out[7…0]: data output interface, used to write data to the storage unit of the storage module;

[0191] wren: write enable signal, high level is valid, only after setting wren='1' can the storage unit be written, when wren='0', data cannot be written to the storage unit;

[0192] Full: This signal is valid when CS='0' (sequential access storage mode), indicating whether the storage space of the sequential access storage mode is full. Full='1' means that the data input into the storage area is full and no more data can be written to the storage unit; Full='0' means that the data is not full and data can continue to be written to the storage unit.

[0193] State machine 1: write the acquired external data into the storage area;

[0194] Register 1: stores the number of data len1 written to the storage module. The specific value is set and modified by the control module; it can also be set by external host computer software.

[0195] Figure 11 A state transition diagram of a control module state machine provided in an embodiment of the present application is shown as follows: Figure 11 As shown, it includes idle IDLE, write length WR_LEN, RAM mode (write address WR_ADDR, write data WR_DATA, wait WAIT), FIFO mode (write address WR_ADDR, write data WR_DATA, wait WAIT), and end FINAL state.

[0196] In sequential access storage mode, the control module accesses the storage module for writing. This requires obtaining the corresponding write status information and the corresponding first port (ADDR_A[n…0]) of the control module. In this application, the data at the address of the first port is used as the target data. When the write status is a write operation and the data count is set to the write flag, the control module enters the write data state. This is the case when the write address state (WR_ADDR) and the data count is set to the write flag (Full=0). The control module then enters the write data state (WR_DATA). At this point, the control module obtains the corresponding write data port (D_in[7…0]). The target data is written from the first data output port (DATA_A_out[7…0]) corresponding to the first port to the storage address of the write data port. After writing one data point, the register flag value (len1) of register 1 of the control module is decremented by 1, the control module's address information is incremented by 1 (Addr+1), and the control module enters the wait state (WAIT).

[0197] In the waiting state, the state machine 1 of the control module jumps according to the register mark value. When the updated register mark value is greater than 0 and the data count mark is the write mark, it switches to the write data state again for execution until all the target data is written to the storage module. At this time, the register mark value is 0 and enters the end state (FINAL).

[0198] In the FINAL state, state machine 1 ends the current data writing process and returns to IDLE to start the next data writing process.

[0199] Before selecting between random access storage mode and sequential access storage mode, the state machine enters the idle state (IDLE) when the FPGA is powered on and reset; after the reset, it enters the write length state (WR_LEN), writes the number of data to register 1, and sets the CS value to determine which storage mode to use for access processing.

[0200] Similarly, during the write access operation in the random access storage mode, the random access storage mode is entered when CS='1' is set; the write address state (WR_ADDR) is entered, and a specific address value is given through the port ADDR_A[n……0] to address the corresponding storage unit in the storage area, and then the write data state (WR_DATA) is entered; in the WR_DATA state, data is written to the storage unit with the storage area address ADDR_A[n……0] of the write data port (D_in[7……0]) through the first data output port (DATA_A_out[7……0]), and the len1 value in register 1 is reduced by 1, and then the wait state WAIT is entered; in the WAIT state, the state machine jumps according to the len1 value. When len1>0, it jumps to the WR_ADDR state for execution, gives the address of the next storage unit, and then performs the write data operation until all the data are written to the storage unit, at which time len1 becomes 0 and the state machine enters the end state FINAL.

[0201] The write operation access processing based on the sequential access storage mode provided in this embodiment enables data to complete the write operation in accordance with the sequential access storage mode through the combined control of the state machine and register of the control module, thereby improving the flexibility and diversity of the write access processing process.

[0202] In some embodiments, when the current access operation is a read operation and the storage module is read by the data receiving module, access processing is performed on the target data according to the current access operation and the data counting mark, including:

[0203] When the read state information of the data receiving module is a read operation and the data count mark is a read mark, entering the target data read data state;

[0204] Reading the target data from the data read port of the storage module to the second data input port corresponding to the second port of the data receiving module;

[0205] Decrease the register flag value of the data receiving module by 1 and enter the waiting state;

[0206] When the updated register mark value is greater than 0 and the data count mark is a read mark, the next target data is read until the register mark value is 0, thereby completing the reading process of all target data.

[0207] Specifically, the read status information and the second port corresponding to the data receiving module are obtained; when the read status information is a read operation and the data count mark is a read mark, the read data state of the target data is entered; the read data port corresponding to the storage module is obtained; the data of the read data port is used as the target data; the target data is read from the read data port to the second data input port corresponding to the second port; the register mark value of the data receiving module is reduced by 1, and the waiting state of the data receiving module is entered; when the updated register mark value is greater than 0 and the data count mark is a read mark, the step of entering the read data state of the target data is returned to read the next target data until the register mark value is 0, completing the access processing of all target data of the data receiving module to the preset storage space.

[0208] like Figure 10 As shown, there is a set of read operation ports between the storage module and the data receiving module, including a clock signal interface (Clk), a reset signal interface (Reset), a mode selection signal interface (CS), a second port (ADDR_B[n……0]), a second data input port (DATA_B_in[7……0]), and a data count mark bit port (Empty).

[0209] Clk: system clock signal connected to FPGA;

[0210] Reset: Connect to the reset signal of FPGA;

[0211] CS: connected to the CS of the control module;

[0212] ADDR_B[n……0]: address output interface, used to address the storage unit of the storage module; similarly, n corresponds to the number of storage units M, ;

[0213] DATA_B_in[7…0]: data input interface, reads data from the storage unit of the storage module;

[0214] Empty: This signal is valid when CS='0' (sequential access storage mode), indicating whether the storage space of the sequential access storage mode is empty. Empty='1' means that there is no data in the storage area, it is in an empty state, and data cannot be read from the storage area; Empty='0' means that there is data in the storage area, it is in a non-empty state, and data can be read.

[0215] State machine 2: read data from the storage area;

[0216] Register 2: stores the data quantity len2 read from the storage area. The specific value is set and modified by the data receiving module.

[0217] Figure 12 A state transition diagram of a data receiving module state machine provided in an embodiment of the present application is shown as follows: Figure 12 As shown, it includes idle IDLE, write length WR_LEN, RAM mode (read address RD_ADDR, read data RD_DATA, wait WAIT), FIFO mode (read address RD_ADDR, read data RD_DATA, wait WAIT), and end FINAL and other states.

[0218] In sequential access storage mode, the access operation is the process of the data receiving module accessing the storage module for reading. It is necessary to obtain the read status information and the corresponding second port (ADDR_B[n…0]) of the data receiving module. When the read status information indicates a read operation and the data count flag is a read flag, the module enters the read data state. That is, when the read address state (RD_ADDR) and the data count flag is a read flag (Empty=0), the module enters the read data state (RD_DATA). At this time, the corresponding read data port (D_out[7…0]) of the storage module is obtained, and the target data is read from the read data port to the second data input port (DATA_B_in[7…0]) corresponding to the second port. In other words, the target data is read from the storage unit at the storage area address Addr, the register flag value (len2) of register 2 of the data receiving module is decremented by 1, and the module enters the wait state (WAIT).

[0219] In the waiting state, the state machine 2 of the data receiving module jumps according to the register tag value. When the updated register tag value is greater than 0 and the data count mark is the read tag, it switches to the read data state for execution again, that is, continues to read the next data from the Addr address until all the target data are written to the data receiving module. At this time, the register tag value is 0 and enters the end state (FINAL).

[0220] In the FINAL state, state machine 2 ends the current data reading process and returns to IDLE to start the next data reading process.

[0221] Before selecting between random access storage mode and sequential access storage mode, the FPGA enters the idle state (IDLE) when it is powered on and reset; after the reset, it enters the write length (WR_LEN) state and writes the number of data to be read to register 2; and reads the CS signal to determine whether it is random access storage mode or sequential access storage mode.

[0222] Similarly, during the read access operation of the random access storage mode, the random access storage mode is entered when CS='1' is read: the read address state (RD_ADDR) is entered, and the specific address value is given through the port ADDR_B[n...0] to address the corresponding storage unit in the storage area, and then the read data state (RD_DATA) is entered; in the RD_DATA state, a data is read from the unit with the storage area address ADDR_B[n...0] through the data port D_out[7...0], and the len2 value in register 2 is reduced by 1, and then the wait state WAIT is entered; in the WAIT state, the state machine jumps according to the len2 value. When len2>0, it jumps to RD_ADDR for execution, that is, the address of the next storage unit is given and the data read operation is performed until len2 data are read, the len2 value becomes 0, and the end state FINAL is entered.

[0223] The read operation access processing based on the sequential access storage mode provided in this embodiment enables data to complete the read operation in accordance with the sequential access storage mode through the combined control of the state machine and register of the data receiving module, thereby improving the flexibility and diversity of the read access processing process.

[0224] Furthermore, this application also provides a true random number access method, Figure 13 A flowchart of a true random number access method provided in an embodiment of the present application is shown in FIG. Figure 13 As shown, the method includes:

[0225] S31: Get true random number;

[0226] S32: When the true random number causes a data blocking mechanism, suspending access processing to the true random number;

[0227] S33: when the true random number is discontinuous, obtaining a backup data source to replace the true random number, and using the replaced true random number to perform access processing;

[0228] The process of truly random number access processing is completed as steps of data access methods in multiple storage modes.

[0229] Specifically, Figure 14 A schematic diagram of a true random number scenario provided in an embodiment of the present application is shown in FIG. Figure 14As shown, random numbers are frequently used in cryptographic applications. When true random numbers are generated quickly and the control module transfers the data to the storage area, if the client reads the data slowly, a mismatch between the write and read speeds can occur, leading to problems such as data loss and data blocking. If the external true random number module generates data slowly, or in abnormal situations such as failures or resets, and the client reads data quickly, the data transmitter cannot properly provide data to the client. This can lead to the client reading empty data from the storage area, resulting in discontinuous data and the occurrence of a data continuity mechanism.

[0230] When the data blocking mechanism mentioned above occurs, access to the true random number will be suspended to wait for the read consistency before resuming data transmission. When data discontinuity occurs, it is necessary to use an alternative data source to replace the true random number and continue access processing.

[0231] It should be noted that, when the true random number of this embodiment is accessed using the above-mentioned data access method, it is sufficient that the true random number corresponds to the target data.

[0232] The true random number access method provided in this embodiment, in addition to achieving the beneficial effects of the data access method of the above-mentioned multiple storage modes, also realizes the interaction between the client and the random number generator, and the random number blocking and synchronization mechanism.

[0233] In some embodiments, it further includes:

[0234] Presetting a third register value and a fourth register value;

[0235] When the true random number received by the control module causes data congestion, the third register value is set to 1, and the write enable signal corresponding to the control module is set to 0 to suspend access processing;

[0236] When the true random numbers received by the data receiving module are discontinuous, the fourth register value is set to 1, the standby data source is used to replace the true random numbers, and the replaced true random numbers are used for access processing.

[0237] Specifically, when to suspend access to data and when to use the backup data source needs to be set through registers, that is, the setting of the third register value and the fourth register value.

[0238] Data blocking mechanism: A register Busy is set in the storage module. The data receiving module sets Busy='1' to indicate that it is busy. When the control module detects Busy='1', it sets the write enable signal A_wren='0' to suspend data transmission; data transmission is resumed after Busy becomes '0'.

[0239] To improve the data continuity mechanism, a register Req is set in the storage module. When Empty_B = '1', the data receiving module sets Req = '1' to indicate that empty data has been read and there is a need to continue reading data. When the control module detects Req = '1', it uses the backup data source (pseudo-random number module through software) to continue the data transmission process; data transmission is suspended after Req becomes '0'.

[0240] The flag setting based on the third register value and the fourth register value provided in this embodiment improves data recognition efficiency and also implements a data synchronization mechanism between the client and the random number generation module.

[0241] Furthermore, this application also provides a method for accessing plaintext data. Figure 15 A flowchart of a method for accessing plaintext data provided in an embodiment of the present application is shown in FIG. Figure 15 As shown, the method includes:

[0242] S41: Obtain plaintext data;

[0243] S42: When the first data format of the encrypted plaintext data is different from the second data format of the plaintext data, performing format conversion processing on the plaintext data according to the second data format to obtain target plaintext data;

[0244] S43: performing access processing on the target plaintext data to encrypt the plaintext data;

[0245] The access processing process is completed as follows: the steps of the data access method in various storage modes.

[0246] Specifically, Figure 16 A cryptographic module data conversion diagram provided in an embodiment of the present application is as follows: Figure 16 The following figure illustrates the Data Encryption Standard (DES) algorithm cryptographic module. DES encrypts data in 64-bit blocks. Data in the host computer can be organized in either big-endian (high-order bytes are stored at low addresses) or little-endian (low-order bytes are stored at low addresses). DES modules also operate in either big-endian or little-endian format. If the host computer's data organization differs from that of the cryptographic module, the DES module may experience encryption errors and fail to obtain correct data.

[0247] When the first data format of the encrypted plaintext data is the same as the second data format of the plaintext data, the plaintext data can be directly read through the storage module and then encrypted without adjusting the data format.

[0248] When the first data format of the encrypted plaintext data differs from the second data format of the plaintext data, the formats must be converted before transmission to the cryptographic module, i.e., the data receiving module. The transmission process here is the same as the access processing process of the data access method for multiple storage modes described above and will not be further described here.

[0249] The plaintext data access method provided in this embodiment, in addition to achieving the beneficial effects of the above-mentioned data access method, also realizes automatic big-endian-little-endian matching between the host computer and the password module data, thereby ensuring the correctness of the password data.

[0250] In some embodiments, the comparison process of the first data format and the second data format includes:

[0251] Presetting the fifth register value;

[0252] Using the plaintext data transmitted to the encryption module as the first data;

[0253] encrypting the first sub-data of the first data;

[0254] If an error occurs in the encryption process, the fifth register value is set to 1, and it is determined that the first data format of the encrypted plaintext data is different from the second data format of the plaintext data;

[0255] If the encryption process is correct, the fifth register value is set to 0, and it is determined that the first data format of the encrypted plaintext data is the same as the second data format of the plaintext data.

[0256] Specifically, during this process, a fifth register value (i.e., the Error register value) is set in the storage module. When the cryptographic module (data receiving module) receives the first sub-data of the first data, encryption processing is performed. If an error occurs during the encryption process, the fifth register value is set to 1, and it is determined that the processing formats are different. If the encryption process is successful, the fifth register value is set to 0, and it is determined that the processing formats are the same.

[0257] When the cryptographic module processes data in Little-Endian format and the data in the host computer is in Little-Endian format, the data formats of the cryptographic module and the host computer are consistent. In this case, the cryptographic module can obtain the correct result when encrypting the data, and there is no need to set the Error register. If the control module reads Error = '0', there is no need to adjust the data format.

[0258] If the cryptographic module processes data in Little-Endian format and the host computer receives data in Big-Endian format, an error will occur during the encryption process after receiving the first Big-Endian data from the host computer, and the expected result will not be generated. The cryptographic module then sets the Error register to '1'. The data format conversion module reads Error = '1' and, starting with the second data, reverses each 64-bit data from the host computer, converting the Big-Endian data to Little-Endian format. After this conversion, the data is transferred to the storage module. This ensures that the DES cryptographic module generates correctly encrypted data from the second data onward.

[0259] Similarly, when the cryptographic module processes data in Big-Endian format, the processing process of the data format conversion module is the same as that of the above embodiment. When Error='0' is detected, it is not necessary to reverse the byte order in the 64-bit data. For each 64-bit data received from the host computer, Data[7...0], Data[15...8], ..., Data[63...56] are output in sequence, and correspondingly transmitted to the storage module 0x(k), 0x(k+1), ..., 0x(k+7) (k≥0) address units; when Error='1' is detected, it is necessary to reverse the byte order in the 64-bit data. For each 64-bit data received from the host computer, Data[63...56], Data[55...48], ..., Data[7...0] are output in sequence, and correspondingly transmitted to the storage module 0x(k), 0x(k+1), ..., 0x(k+7) (k≥0) address units.

[0260] Figure 17 A data format conversion process flow chart provided in an embodiment of the present application is as follows: Figure 17 Shown, including:

[0261] S44: Determine whether the value of the fifth register is 1; if so, proceed to step S45; if not, proceed to step S48;

[0262] S45: Determine that the data interval is 7;

[0263] S46: Reverse the order of the current first data to obtain processed first data;

[0264] S47: Subtract 1 from the reverse order processing data packet to obtain the next second data as the new current first data, and return to step S46; until the reverse order processing data packet is 0;

[0265] S48: Output the processed data packets one by one.

[0266] The comparison process of the processing formats provided in this embodiment simplifies the results presented by the comparison process and improves data processing efficiency.

[0267] The embodiment of the present application also provides a data access device with multiple storage modes. Figure 18 This is a structural diagram of a data access device with multiple storage modes provided in an embodiment of the present application, such as Figure 18 As shown, the device includes:

[0268] Acquisition module 21, acquires current access operation and target data;

[0269] The access module 22 performs access processing on the target data according to the current access operation and the data counting mark in the sequential access storage mode; wherein the logic circuit function corresponding to the data counting mark is implemented by a reconstruction system of multiple storage modes.

[0270] For descriptions of features in the embodiments corresponding to the data access devices in multiple storage modes, reference can be made to the relevant descriptions of the embodiments corresponding to the data access methods in multiple storage modes, which will not be described in detail here.

[0271] Furthermore, an embodiment of the present application also provides a true random number access device. For the description of the features in the embodiment corresponding to the true random number access device, please refer to the relevant description of the embodiment corresponding to the true random number access method, which will not be repeated here.

[0272] Furthermore, an embodiment of the present application also provides a plaintext data access device. For the description of the features in the embodiment corresponding to the plaintext data access device, please refer to the relevant description of the embodiment corresponding to the plaintext data access method, which will not be repeated here.

[0273] An embodiment of the present application also provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute any one of the above-mentioned data access methods in multiple storage modes, or, such as a true random number access method, or, such as the steps of a plaintext data access method.

[0274] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute any one of the above-mentioned data access methods in multiple storage modes, or, such as a true random number access method, or, such as the steps of a plaintext data access method, when running.

[0275] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0276] An embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned data access methods in multiple storage modes, or, such as a true random number access method, or, such as a plaintext data access method.

[0277] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing any of the above-mentioned data access methods in multiple storage modes, or, such as a true random number access method, or, such as the steps of a plaintext data access method.

[0278] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0279] The above describes in detail a data access method, electronic device, medium, and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, various improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A reconstruction system for multiple storage modes, characterized in that: A storage module including a counting unit, wherein the counting unit includes a comparator, an inverter, and a buffer group; multiple storage modes include at least a random access storage mode and a sequential access storage mode; the random access storage mode and the sequential access storage mode share the same preset storage space; The input end of the buffer group is connected to the comparator, and the enable end is connected to the inverter, for outputting a data count mark of a current access operation; the comparator receives a storage quantity signal of a preset storage space and a threshold signal to determine a current access operation; the inverter receives a storage mode selection signal; The buffer group corresponds to the random access storage mode when in a blocking state; and corresponds to the sequential access storage mode when in a conducting state, so that the access control device can access the target data according to the current access operation and the data counting mark.

2. The reconstruction system of multiple storage modes according to claim 1, characterized in that: The buffer group includes a first buffer group, and the first buffer group includes a first buffer and a second buffer; The input terminals of the first buffer and the second buffer are both connected to the comparator, and the enable terminals are both connected to the inverter; the first buffer is used to output a write mark, and the second buffer is used to output a read mark.

3. The reconstruction system of multiple storage modes according to claim 2, characterized in that: The comparator includes a first comparator and a second comparator, and the inverter includes a first inverter and a second inverter; The first comparator and the second comparator each receive the storage quantity signal at a first terminal; the first comparator receives a total storage quantity signal of the threshold signal at a second terminal, and an output terminal is connected to the input terminal of the first buffer; the second comparator receives a numerical value signal of the threshold signal at a second terminal, and an output terminal is connected to the input terminal of the second buffer; The first inverter and the second inverter each receive the storage mode selection signal at an input terminal; The output end of the first inverter is connected to the enable end of the first buffer; the output end of the second inverter is connected to the enable end of the second buffer.

4. The reconstruction system of multiple storage modes according to claim 3, characterized in that: The state output process of the first buffer and the second buffer includes: When the storage mode selection signal is a random access storage mode, the first inverter and the second inverter both output a second level, and it is determined that the first buffer and the second buffer are in a blocking state; When the storage mode selection signal is a sequential access storage mode, the first inverter and the second inverter both output a first level, and it is determined that the first buffer and the second buffer are in a conducting state.

5. The reconstruction system of multiple storage modes according to claim 4, characterized in that: The output process of the data counting mark includes: When the storage quantity signal is 0, the first comparator outputs the second level, and outputs the write mark as write through the first buffer; the second comparator outputs the first level, and outputs the read mark as read prohibition through the second buffer; Alternatively, when the storage quantity signal is greater than or equal to 1 and less than the total storage quantity signal, the first comparator outputs a second level, and after passing through the first buffer, the write mark is output as write; the second comparator outputs a second level, and after passing through the second buffer, the read mark is output as read; Alternatively, when the storage quantity signal is equal to the total storage quantity signal, the first comparator outputs a first level, and after passing through the first buffer, the write mark is output as write-prohibited; the second comparator outputs a second level, and after passing through the second buffer, the read mark is output as read.

6. The reconstruction system of multiple storage modes according to claim 3, characterized in that: The access control device includes a control module and a data receiving module; wherein, ports corresponding to write operations and read operations are set between each of the control module, the storage module and the data receiving module to implement the access processing process of read and write operations between the control module and the storage module and between the storage module and the data receiving module.

7. The reconstruction system of multiple storage modes according to claim 6, characterized in that: The buffer group further includes a second buffer group; The output end of the first buffer group is connected to the input end of the second buffer group; An enable terminal of the second buffer group receives a register value; The output end of the second buffer group outputs the data counting mark. When the register value is 1, the second buffer group is in a conducting state. When the register value is 0, the second buffer group is in a blocking state.

8. The reconstruction system of multiple storage modes according to claim 7, characterized in that: The second buffer group includes a third buffer, a fourth buffer, a fifth buffer and a sixth buffer; the register value includes a first register value and a second register value; The input ends of the third buffer and the fourth buffer are connected to the output end of the first buffer, and are used for the corresponding write mark outputs of the control module and the data receiving module; The input ends of the fifth buffer and the sixth buffer are connected to the output end of the second buffer, and are used for the corresponding read mark outputs of the control module and the data receiving module; The third buffer and the fifth buffer each enable terminal to receive the first register value; the fourth buffer and the sixth buffer each enable terminal to receive the second register value.

9. The reconstruction system of multiple storage modes according to claim 8, characterized in that: The output process of the data count mark of the second buffer group includes: When the control module performs a read operation or a write operation, the first register value is set to 1 and the second register value is set to 0, and the output ends of the third buffer and the fifth buffer are determined to output a read flag or a write flag respectively; Alternatively, when the data receiving module performs a read operation or a write operation, the first register value is set to 0 and the second register value is set to 1, and the output ends of the fourth buffer and the sixth buffer are determined to output a read mark or a write mark accordingly.

10. The reconstruction system of multiple storage modes according to claim 5, characterized in that: The access control device includes a control module and a data receiving module; and also includes a seventh buffer; The input end of the seventh buffer is connected to the first data output port of the control module, the enable end is connected to the write enable port, and the output end is connected to the write data port of the storage module; The seventh buffer is configured to be turned on when the write enable port outputs a first level, and to write the target data into the storage module.

11. The reconstruction system of multiple storage modes according to claim 9, characterized in that: Also included are an eighth buffer, a ninth buffer, and a tenth buffer; The output end of the eighth buffer is connected to the first data input port of the control module, the enable end is connected to the read enable port, and the input end is connected to the read data port of the storage module; The input end of the ninth buffer is connected to the second data output port of the data receiving module, the enable end is connected to the write enable port of the data receiving module, and the output end is connected to the write data port of the storage module; The output end of the tenth buffer is connected to the second data input port of the data receiving module, the enable end is connected to the read enable port of the data receiving module, and the input end is connected to the read data port of the storage module.

12. A data access method in multiple storage modes, characterized in that: include: Get the current access operation and target data; In a sequential access storage mode, the target data is accessed and processed according to the current access operation and the data counting mark; wherein the logic circuit function corresponding to the data counting mark is implemented by a reconstruction system of multiple storage modes as described in any one of claims 1 to 11.

13. The data access method of multiple storage modes according to claim 12, characterized in that: During the access processing in the sequential access storage mode, storage addresses are pre-set for the storage data of the storage units in the preset storage space to implement access processing according to the storage addresses.

14. The data access method of multiple storage modes according to claim 13, characterized in that: When the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including: Acquire the first target sub-data and the corresponding data address of the storage unit; Controlling the access control device to read the first target sub-data according to the data address; The next second target sub-data of the first target sub-data is migrated to the data address as the new first target sub-data for reading until the target data is completely read.

15. The data access method of multiple storage modes according to claim 13, characterized in that: When the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including: Get multiple consecutive data and corresponding data addresses; Controlling the access control device to read a plurality of continuous data according to the data address; Correspondingly, after completing the read access of the target data, the method further includes: The data of the target data at a data address next to the data address of the storage unit is migrated to the data address.

16. The data access method of multiple storage modes according to claim 12, characterized in that: The access control device includes a control module and a data receiving module; when the current access operation is a write operation and the control module writes data to the storage module, the access control device performs access processing on the target data according to the current access operation and the data counting mark, including: When the write state information of the control module is a write operation and the data counting mark is a write mark, entering a write data state of the target data; Writing the target data from the first data output port corresponding to the first port of the control module to the write data port of the storage module; The register mark value of the control module is reduced by 1 and the address information is increased by 1 to enter the waiting state; When the updated register mark value is greater than 0 and the data count mark is a write mark, the next target data is written until the register mark value is 0, thereby completing the write processing of all target data.

17. The data access method of multiple storage modes according to claim 12, characterized in that: The access control device includes a control module and a data receiving module; when the current access operation is a read operation and the storage module is read by the data receiving module, access processing is performed on the target data according to the current access operation and the data counting mark, including: When the read state information of the data receiving module is a read operation and the data counting mark is a read mark, entering a read data state of the target data; Reading the target data from the data read port of the storage module to the second data input port corresponding to the second port of the data receiving module; Decrease the register flag value of the data receiving module by 1 and enter the waiting state; When the updated register mark value is greater than 0 and the data count mark is a read mark, the next target data is read until the register mark value is 0, thereby completing the reading process of all target data.

18. A true random number access method, characterized in that: include: Get true random numbers; When the true random number causes data congestion, suspending access processing to the true random number; When the true random number is discontinuous, an alternative data source is obtained to replace the true random number, and the replaced true random number is used for access processing; wherein the process of true random number access processing is completed according to the steps of the data access method of multiple storage modes as described in any one of claims 12 to 17.

19. The true random number access method according to claim 18, wherein: The access control device includes a control module and a data receiving module; and further includes: Presetting a third register value and a fourth register value; When the true random number received by the control module causes data congestion, the third register value is set to 1, and the write enable signal corresponding to the control module is set to 0 to suspend access processing; When the true random numbers received by the data receiving module are discontinuous, the fourth register value is set to 1, the standby data source is used to replace the true random numbers, and the replaced true random numbers are used for access processing.

20. A method for accessing plaintext data, characterized in that: include: Get plaintext data; When the first data format of the encrypted plaintext data is different from the second data format of the plaintext data, performing format conversion processing on the plaintext data according to the second data format to obtain target plaintext data; Access processing is performed on the target plaintext data to encrypt the plaintext data; wherein the access processing process is completed according to the steps of the data access method with multiple storage modes as described in any one of claims 12 to 17.

21. The plaintext data access method according to claim 20, characterized in that: The comparison process of the first data format and the second data format includes: Presetting the fifth register value; Using the plaintext data transmitted to the encryption module as the first data; encrypting the first sub-data of the first data; If an error occurs in the encryption process, the fifth register value is set to 1, and it is determined that the first data format for encrypting the plaintext data is different from the second data format for the plaintext data; If the encryption process is correct, the fifth register value is set to 0, and it is determined that the first data format of the encrypted plaintext data is the same as the second data format of the plaintext data.

22. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21 when executing the computer program.

23. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21.

24. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, it implements the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21.

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