A method of asynchronously recording reorder processor register rename checkpoints and rollbacks
By using an asynchronous recording and rollback method that separates scalar and vector renaming modules, the problem of coupling between vector register and scalar register renaming in RISC-V processors is solved, achieving efficient exception handling and performance optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING YIHUA CLOUD NETWORK TECH CO LTD
- Filing Date
- 2025-05-13
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional register renaming techniques are ineffective in resolving the coupling problem of renaming vector registers and scalar registers caused by the V Extension of RISC-V processors, leading to increased instruction latency and affecting processor execution performance.
It adopts a method of separating scalar and vector renaming modules, asynchronously records renaming checkpoints and rollbacks of out-of-order processor registers, independently manages the renaming and history tables of scalar and vector instructions, utilizes global instruction numbers and history pointers for collaborative recovery, and supports flexible configuration of vector length and parallel rollback.
It improves exception handling efficiency, reduces overall recovery latency, adapts to differences in instruction completion order and commit order, avoids coupling between scalar and vector processing paths, and improves processor performance.
Smart Images
Figure CN120123005B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of checkpointing and rollback technology, specifically to a method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks. Background Technology
[0002] The purpose of register renaming technology is to solve the register alias problem in traditional architectures. In out-of-order execution processors, operand dependencies become complex because instructions may be executed in different orders, especially since the same register may be modified in different instructions. Register renaming eliminates write-after-read (WAR) and write-after-write (WAW) conflicts by assigning different logical registers to physical registers. By resolving data dependencies, more instructions can be executed in parallel. It enables out-of-order execution and reduces performance bottlenecks caused by data dependencies. For traditional out-of-order processors, the register renaming function is implemented within the same component, so checking points and recovery after exceptions can also be implemented within this component. However, this approach currently struggles to address the challenges posed by the V Extension in RISC-V processors. The V Extension defines parameters such as vector length, vector register group multiplier setting, and control and status registers (CSRs) that change the number of registers operated on by a vector instruction. This flexible configuration makes it impossible to efficiently implement the renaming of vector registers and scalar registers in the same component. Vector instructions require more processing, while scalar instructions do not, and for scalar instructions, the increased instruction latency impacts processor performance. Therefore, the renaming of scalar and vector registers, the establishment of checkpoints, and exception recovery all need to be implemented in different modules. Summary of the Invention
[0003] By separating the scalar and vector renaming modules, the coupling problem caused by the dynamic configuration of the RISC-V V Extension control register is solved, and asynchronous rollback of scalar and vector checkpoints is supported to adapt to the difference between the instruction completion order and the commit order in out-of-order execution, thereby overcoming the problems mentioned in the background technology.
[0004] Based on the above technical concept, the technical solution adopted by this invention is as follows:
[0005] A method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks includes the following steps:
[0006] The S1 scalar instruction processing step maps all instructions from logical registers to physical registers through the scalar register renaming module and records the historical mapping relationship of the scalar target register. All instructions include vector instructions and scalar instructions.
[0007] The S2 vector instruction processing step, after scalar instruction dispatch, maps vector instructions from logical registers to physical registers through the vector register renaming module, supporting flexible configuration of vector length.
[0008] The S3 checkpoint recording step records checkpoints for scalar and vector instructions.
[0009] The S4 management history table step generates scalar history tables and vector history tables based on instructions.
[0010] The S5 abnormal rollback procedure includes a scalar rollback phase, a vector rollback phase, and a parallel recovery phase.
[0011] Further defining the above technical solution, the S1 scalar instruction processing step includes a scalar register renaming step, a scalar history mapping recording step, and a history pointer passing step. The scalar register renaming step maps logical registers to physical registers through a scalar renaming table (sRAT). The scalar register uses a register freelist to allocate physical registers, ensuring no data dependency conflicts between scalar instructions. The scalar history mapping recording step includes writing the old logical-physical mapping relationship of the scalar target register into the scalar renaming history table (Scalar HistoryTable) and updating the write pointer. The history table is stored in the order of instruction execution and supports rollback by pointer. Passing the history pointer includes binding the history table pointer to the instruction and sending it to the instruction dispatch module along with the instruction.
[0012] Further defining the above technical solution, the S2 vector instruction processing step includes a vector register renaming step and a vector history mapping recording step. The vector register renaming step maps vector logical registers to physical registers through a vector renaming table (vRAT), supporting dynamic configuration of vector length (VL) and register set specification (VLMUL). Vector registers use an independent vector free list to allocate physical registers, adapting to the parallelism requirements of vector instructions. The vector history mapping recording step includes writing the old logical-physical mapping relationship of the vector target register into a vector history table (Vector History Table), indexed by the global instruction number (Global ID). The history table supports rollback by global number range, avoiding dependency confusion caused by out-of-order execution of vector instructions.
[0013] Further defining the above technical solution, the S3 checkpoint recording step includes a scalar checkpoint stage and a vector checkpoint stage. The scalar checkpoint stage records the scalar renaming table (sRAT), free list, and history table pointers before each scalar instruction is dispatched, and transmits them to the vector module through the instruction dispatch module. The vector checkpoint stage records the vector renaming table (vRAT), free list, and associated scalar checkpoint global number when a vector instruction is dispatched.
[0014] Further defining the above technical solution, in the S4 management history table step, the scalar history table records the mapping changes of the scalar target register in the order of instructions, and needs to be rolled back to the state before the specified pointer when released; the vector history table records the mapping relationship of vector instructions using the global instruction number as an index, and rolls back according to the number range when released.
[0015] Further defining the above technical solution, the S5 exception rollback step comprises the following steps: scalar rollback is used to locate the scalar history pointer of the exception instruction → find the most recent scalar checkpoint to restore sRAT and the free list → if no checkpoint is found, rollback is performed from the history pointer to the exception point; vector rollback is used to locate the global number of the exception instruction → find the associated vector checkpoint to restore vRAT and the free list → if no checkpoint is found, rollback is performed from the global number of the scalar checkpoint to the exception point; parallel recovery is used for concurrent execution of scalar and vector rollbacks, with the vector module synchronously completing state recovery through a backpressure mechanism.
[0016] Further defining the above technical solution, the S4 historical table management step also includes a historical mapping record step. The historical mapping record step includes a scalar historical table and write pointer management. The scalar historical table stores triples (logical register, old physical register, and new physical register) in the order of instruction execution. The write pointer management maintains the historical table write pointer (HTWP). For each recorded historical mapping of an instruction, the pointer is incremented, and the pointer value is carried to subsequent modules with the instruction for locating the recovery starting point during rollback.
[0017] Further defining the above technical solution, the S5 anomaly rollback step includes an anomaly detection and localization stage, a scalar state recovery stage, and a vector state recovery stage. The anomaly detection and localization stage includes anomaly signal capture and instruction pointer backtracking. When branch prediction fails, is interrupted, or an anomaly occurs, the ROB (Reorder Buffer) records the original PC address and commit status of the abnormal instruction. The instruction pointer backtracking stage searches for the corresponding scalar history table pointer (HTWP) and global ID (GID) in the instruction dispatch module based on the original PC of the abnormal instruction.
[0018] Further defining the above technical solution, the scalar state recovery step includes checkpoint matching and state overwriting. Checkpoint matching searches for the nearest checkpoint ≥ HTWP in the scalar checkpoint linked list. If no matching checkpoint is found, the current HTWP is rolled back to the anomaly point. The sRAT and Freelist of the checkpoint are directly written into the hardware registers to overwrite the current state and release the physical registers of the history table between the checkpoint and the anomaly point.
[0019] Further defining the above technical solution, the vector state recovery step includes a global number matching step that searches for the nearest checkpoint with a value greater than or equal to GID in the vector checkpoint list. If no matching checkpoint is found, the checkpoint rolls back from GID=1024 to the anomaly point, writes the checkpoint's vRAT and V-Freelist to the hardware register, overwrites the current state, and releases the physical register of the history table between the checkpoint and the anomaly point.
[0020] Further limitations on the above technical solution include an instruction dispatch module. After receiving an instruction, the instruction dispatch module sends the instruction to an instruction reordering buffer for caching. The instruction reordering buffer distinguishes between scalar instructions and vector instructions, and submits different instructions in the order of instructions. During the instruction order submission process, scalar instructions and vector instructions are executed out of order according to the out-of-order execution of scalar instructions and vector instructions. When scalar instructions and vector instructions are executed, different instructions are passed to the scalar instruction dispatch and vector instruction dispatch points, and vector instructions are preprocessed.
[0021] Compared with the prior art, the beneficial effects of the present invention are:
[0022] 1. Asynchronous recording and recovery: scalar and vector checkpoints are recorded independently, and recovery is carried out in coordination with global instruction numbers and history pointers during rollback, improving the efficiency of exception handling;
[0023] 2. It flexibly adapts to vector instructions and supports dynamic configuration of the vector length control register, avoiding coupling between scalar and vector processing paths;
[0024] 3. Parallel rollback optimization: scalar and vector modules recover their states concurrently, and the backpressure mechanism ensures correctness and reduces overall recovery latency. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a flowchart illustrating a method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks according to the present invention; wherein: 1. All instructions; 2. Scalar register renaming module; 3. Scalar checkpoint; 4. Register renaming table; 5. Register free list; 6. Renaming history table; 7. Instruction dispatch module; 8. Instruction reordering cache; 9. Scalar instruction dispatch; 10. Vector instruction dispatch; 11. Instruction sequential commit; 12. Out-of-order execution of scalar instructions; 13. Vector instruction preprocessing; 14. Vector register renaming module; 15. Vector checkpoint; 19. Out-of-order execution of vector instructions. Detailed Implementation
[0027] The following is in conjunction with the appendix Figure 1 The present invention will be described in further detail below.
[0028] Example 1: This example provides a method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks, such as... Figure 1 As shown, it includes the following steps:
[0029] The S1 scalar instruction processing step maps all instructions 1 from logical registers to physical registers through the scalar register renaming module 2, and records the historical mapping relationship of the scalar target register. All instructions 1 include vector instructions and scalar instructions.
[0030] The S2 vector instruction processing step, after the scalar instruction is dispatched, maps the vector instruction from the logical register to the physical register through the vector register renaming module 14, and supports flexible configuration of the vector length.
[0031] S3 records the steps, which record scalar and vector instructions;
[0032] The S4 management history table step generates scalar history tables and vector history tables based on instructions.
[0033] The S5 abnormal rollback procedure includes a scalar rollback phase, a vector rollback phase, and a parallel recovery phase.
[0034] The S1 scalar instruction processing step further includes a scalar register renaming step, a scalar history mapping recording step, and a history pointer passing step. The scalar register renaming step maps logical registers to physical registers through the scalar renaming table (sRAT). The scalar registers use the register free list 5 (Freelist) to allocate physical registers, ensuring that there are no data dependency conflicts between scalar instructions. The scalar history mapping recording step includes writing the old logical-physical mapping relationship of the scalar target register into the scalar renaming history table 6 (Scalar History Table) and updating the write pointer. The history table is stored in the order of instruction execution and supports rollback by pointer. The history pointer passing step includes binding the history table pointer to the instruction and sending it to the instruction dispatch module along with the instruction.
[0035] The S2 vector instruction processing step further includes a vector register renaming stage and a vector history mapping recording stage. The vector register renaming stage maps vector logical registers to physical registers through the vector renaming table (vRAT), supports dynamic configuration of vector length (VL) and register set specification (VLMUL), and uses an independent vector free list to allocate physical registers to adapt to the parallelism requirements of vector instructions. The vector history mapping recording stage includes writing the old logical-physical mapping relationship of the vector target register into the vector history table (Vector History Table), indexed by the global instruction number (Global ID). The history table supports rollback by global number range to avoid dependency confusion caused by out-of-order execution of vector instructions.
[0036] The S3 recording step includes a scalar phase and a vector phase. The scalar phase records the scalar renaming table (sRAT), free list, and history table pointer before each scalar instruction is dispatched, and passes them to the vector module through the instruction dispatch module. The vector phase records the vector renaming table (vRAT), free list, and associated scalar global number when a vector instruction is dispatched.
[0037] The S4 management history table step includes a scalar history table that records the mapping changes of scalar target registers in the order of instructions, and needs to roll back to the state before the specified pointer when released; and a vector history table that records the mapping relationship of vector instructions using the global instruction number as an index, and rolls back according to the number range when released.
[0038] The S5 exception rollback step includes the following steps: scalar rollback is used to locate the scalar history pointer of the exception instruction → search for the most recent scalar recovery sRAT and the free list → if not found, rollback from the history pointer to the exception point; vector rollback is used to locate the global number of the exception instruction → search for the associated vector recovery vRAT and the free list → if not found, rollback from the scalar global number to the exception point; parallel recovery is used for concurrent execution of scalar and vector rollbacks, with the vector module synchronously completing state recovery through a backpressure mechanism.
[0039] The S4 management history table step further includes a history mapping record step, which includes a scalar history table and write pointer management. The scalar history table stores triples (logical register, old physical register, and new physical register) in the order of instruction execution. The write pointer management maintains the history table write pointer (HTWP). For each recorded history mapping of an instruction, the pointer is incremented, and the pointer value is carried to subsequent modules with the instruction for locating the recovery starting point during rollback.
[0040] The S5 anomaly rollback step includes an anomaly detection and localization stage, a scalar state recovery stage, and a vector state recovery stage. The anomaly detection and localization stage includes anomaly signal capture and instruction pointer backtracking. When a branch prediction fails, is interrupted, or an anomaly occurs, the ROB (Reorder Buffer) records the original PC address and commit status of the abnormal instruction. The instruction pointer backtracking stage searches for the corresponding scalar history table pointer (HTWP) and global ID (GID) in the instruction dispatch module based on the original PC of the abnormal instruction.
[0041] The scalar state recovery process includes matching and state overwriting. Matching involves searching for the nearest match ≥ HTWP in the scalar linked list. If no match is found, the current HTWP is rolled back to the point of failure. The sRAT and Freelist are directly written to the hardware registers to overwrite the current state and release the physical registers of the history table between the point of failure and the point of failure.
[0042] The vector state recovery process includes a global number matching step. In the vector linked list, the nearest one with a value greater than or equal to GID is searched. If no match is found, the process rolls back from GID=1024 to the point of failure, writes vRAT and V-Freelist to the hardware registers, overwrites the current state, and releases the physical registers of the history table between the point of failure and the point of failure.
[0043] It also includes an instruction dispatch module 7. After receiving an instruction, the instruction dispatch module 7 sends the instruction to the instruction reordering buffer 8 for caching. The instruction reordering buffer 8 distinguishes between scalar instructions and vector instructions, and submits different instructions in the order of instructions 11. During the instruction order submission process 11, scalar instructions and vector instructions are executed out of order according to the out-of-order execution of scalar instructions 12 and out-of-order execution of vector instructions 19. When scalar instructions and vector instructions are executed, different instructions are passed to scalar instruction dispatch 9 and vector instruction dispatch 10, and vector instructions are preprocessed 13.
[0044] The renaming logic for scalars and vectors, record renaming, and history tables are handled in different modules. By using instruction reordering to cache the recovery pointers and instruction numbers of the two tables, the two tables can be restored to their state before the same instruction renaming. The rollback process of the two renaming modules is parallel, and if the rollback time of the vector renaming module is long, the scalar renaming module can start working directly without synchronizing the state of the vector renaming module. The backpressure mechanism of the vector renaming module ensures the correctness of the processing.
[0045] Example 2: This example provides a method for asynchronously recording out-of-order processor register renaming and rollback, such as... Figure 1 As shown, it includes the following steps:
[0046] The functions of renaming, recording, and renaming history for scalar and vector registers are implemented in two separate modules. The process of recording and renaming history is as follows:
[0047] 1. All instructions 1 are processed by scalar register renaming module 2, which renames the scalar logical registers used in scalar and vector instructions to physical registers;
[0048] 2. Record the logical-to-physical mapping relationship before the scalar target register of the instruction in the rename history table 6, record the pointer of the write table, and send it to the instruction dispatch module along with the instruction;
[0049] 3. The scalar register renaming module 2 determines when to record based on a certain strategy, and the recorded content (including the register renaming table 16, the free list, and the pointer to the renaming history table 6 at this time) is carried in the first subsequent vector instruction after the scalar is recorded.
[0050] 4. After the instructions enter the instruction dispatch module in sequence, they need to enter the instruction reordering cache (stored together with the rename history table 6 pointer carried by the instruction) and obtain a global number;
[0051] 5. The scalar instruction with the global number is then dispatched out of order into the scalar out-of-order execution module;
[0052] 6. Vector instructions with global numbers are then dispatched and sequentially enter the vector instruction preprocessing module, and then sequentially enter the vector register renaming module 14 to rename the vector logic registers used in the vector instructions to physical registers.
[0053] 7. Record the logical-to-physical mapping relationship before the vector target register in renaming history table 6, which is indexed by the instruction global number;
[0054] 8. Vector register renaming module 14 records the identifier carried by the instruction, and the recorded content should include the global number of this vector instruction;
[0055] 9. Vector instructions reordered through vector register renaming module 14 are executed in out-of-order vector instruction order;
[0056] 10. After the scalar instruction reordering module and the vector instruction reordering module have completed execution, they return a completion status to the instruction reordering cache;
[0057] 11. Instruction reordering cache is committed sequentially according to the original instruction order. The scalar rename history table 6 pointer is used to release scalars smaller than that pointer and scalar rename history table 6 entries. The instruction global number is used to release vectors smaller than that instruction's global code and vector rename history table 6 entries. Releasing rename history table 6 entries requires placing the released physical registers into the corresponding register free list 5 and the register free list 5 of all records.
[0058] The rollback process is as follows:
[0059] 1. When an exception occurs during instruction execution, a branch instruction prediction error occurs, or an interrupt occurs, this information must be sent to the instruction reordering cache. The instruction reordering cache determines which instruction state the processor should restore to.
[0060] 2. Obtain the pointer to the scalar renaming history table 6 of this instruction, send it to the scalar register renaming module 2, find the scalar renaming history table 6 pointer that is closest to this pointer and is greater than this pointer, and directly write the stored register renaming table 16 and free list status into the register renaming table 16 and free list. If not found, proceed directly to step 3.
[0061] 3. Restore the scalar rename history table 6 entries between the pointers of the instruction's scalar rename history table 6 and the pointer of the current scalar rename history table 6 (if not found in step 2, use the current scalar rename history table 6 write pointer instead) to register rename table 16, and put the previous physical register of the modified register rename table 16 entries into register free list 5.
[0062] 4. Steps 2 and 3 above can be performed simultaneously. Obtain the instruction global number of this instruction and send it to the vector register renaming module 14. Find the instruction global number of the vector instruction that is closest to this instruction global number and is greater than this instruction global number. Write the status of the stored register renaming table 16 and free list directly into the register renaming table 16 and free list. If not found, you can proceed directly to step 5.
[0063] 5. Restore the vector renaming history table 6 entry between the instruction global number and the instruction global number to the register renaming table 16 (if not found in step 4, use the current scalar renaming history table 6 write pointer instead), and put the previous physical register of the modified register renaming table 16 entry into the register free list 5.
[0064] 6. After steps 2 and 3 are completed, scalar instruction renaming can continue. If steps 4 and 5 are not completed, the vector register renaming module 14 will block instruction entry and push forward. After steps 2, 3, 4, and 5 are completed, both scalar and vector instructions can run normally.
[0065] Scalars and vectors are not in a one-to-one correspondence; it's possible that there might be no vector between two scalars on the timeline. This can happen when there are no vector instructions between the two scalars. This situation does not affect the correctness or performance of the functionality; it's a normal processing procedure.
[0066] Data Structures:
[0067] Register renaming table 16: This table is used to store the mapping relationship between logical registers and physical registers.
[0068] Register Free List 5: This table is used to store unmapped physical registers.
[0069] Write-back process: After the instruction is committed (retire), the physical registers are written back to the free list.
[0070] Rename and Rewind
[0071] Rename rollback is an operation that requires renaming the rollback register when the processor detects an error during out-of-order execution (such as a branch prediction error) or other situations that require rollback (such as exceptions or interrupts).
[0072] Implementation method:
[0073] 1) Save rename history:
[0074] During execution, the processor updates the rename table in real time, recording the latest logical register-to-physical register mapping. To enable rollback when needed, the processor records the mapping of the target register before the rename for each instruction. When an exception occurs, the rename table mapping can be restored through the records in the Rename History Table, up to the state before the instruction that caused the exception.
[0075] 2) Save the rename table (Checkpoint):
[0076] In practical processor design, rollback needs to be performed efficiently and quickly. Therefore, the processor records all information in the renaming table at certain times according to a certain strategy. During rollback, it first returns to the position closest to the point of error, and then searches the renaming history table 6 to perform the rollback. The processor can maintain multiple tables. The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, so that those skilled in the art can understand and apply the present invention. It should not be considered that the specific implementation of the present invention is limited to these descriptions.
Claims
1. A method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks, characterized in that, Includes the following steps: S1 scalar instruction processing step, this step completes the mapping of all instructions (1) from logical registers to physical registers through the scalar register renaming module (2), and records the historical mapping relationship of the scalar target register. All instructions (1) include vector instructions and scalar instructions; The S2 vector instruction processing step is performed after the scalar instruction is dispatched. The vector instruction is mapped from the logical register to the physical register through the vector register renaming module (14), which supports flexible configuration of the vector length. The S3 checkpoint recording step records checkpoints for scalar and vector instructions. The S4 management history table step generates scalar history tables and vector history tables based on instructions. The S5 abnormal rollback procedure includes a scalar rollback phase, a vector rollback phase, and a parallel recovery phase. The S1 scalar instruction processing step further includes a scalar register renaming step, a scalar history mapping recording step, and a history pointer passing step. The scalar register renaming step maps logical registers to physical registers through a scalar renaming table. The scalar register uses the register free list (5) to allocate physical registers, ensuring that there are no data dependency conflicts between scalar instructions. The scalar history mapping recording step includes writing the old logical-physical mapping relationship of the scalar target register into the scalar renaming history table (6) and updating the write pointer. The history table is stored in the order of instruction execution and supports rollback by pointer. The history pointer passing step includes binding the history table pointer to the instruction and sending it to the instruction dispatch module along with the instruction. The S2 vector instruction processing step further includes a vector register renaming step and a vector history mapping recording step. The vector register renaming step maps the vector logical register to the physical register through the vector renaming table, supports dynamic configuration of vector length and register group specifications, and uses an independent vector free list to allocate physical registers to adapt to the parallelism requirements of vector instructions. The vector history mapping recording step includes writing the old logical-physical mapping relationship of the vector target register into the vector renaming history table (6), using the global instruction number as the index. The history table supports rollback by the global number range to avoid dependency confusion caused by out-of-order execution of vector instructions (19). The S3 checkpoint recording step includes a scalar checkpoint (3) step and a vector checkpoint (15) step. The scalar checkpoint (3) step records the scalar renaming table, free list and history table pointer before each scalar instruction is dispatched, and passes them to the vector module through the instruction dispatch module. The vector checkpoint (15) step records the vector renaming table, free list and associated scalar checkpoint (3) global number when the vector instruction is dispatched. The S4 management history table step includes a scalar history table that records the mapping changes of scalar target registers in the order of instructions, and needs to roll back to the state before the specified pointer when released; and a vector history table that records the mapping relationship of vector instructions using the global instruction number as an index, and rolls back according to the number range when released.
2. The method for asynchronous recording out-of-order processor register renaming checkpoints and rollbacks according to claim 1, characterized in that, The S5 abnormal rollback step includes the following steps: scalar rollback is used to locate the scalar history pointer of the abnormal instruction → find the most recent scalar checkpoint (3) and restore sRAT and the free list → if there is no checkpoint, roll back from the history pointer to the abnormal point; vector rollback is used to locate the global number of the abnormal instruction → find the associated vector checkpoint (15) and restore vRAT and the free list → if there is no checkpoint, roll back from the global number of the scalar checkpoint (3) to the abnormal point; parallel recovery is used for concurrent execution of scalar and vector rollback, and the vector module synchronously completes state recovery through the backpressure mechanism.
3. The method for asynchronous recording out-of-order processor register renaming checkpoints and rollbacks according to claim 2, characterized in that, The S4 management history table step further includes a history mapping record step, which includes a scalar history table and write pointer management. The scalar history table stores triples in the order of instruction execution. The write pointer management maintains the write pointers of the history table. For each recorded history mapping of an instruction, the pointer is incremented, and the pointer value is carried to subsequent modules with the instruction for locating the recovery starting point during rollback.
4. The method for asynchronous recording out-of-order processor register renaming checkpoints and rollbacks according to claim 3, characterized in that, The S5 anomaly rollback step includes an anomaly detection and localization stage, a scalar state recovery stage, and a vector state recovery stage. The anomaly detection and localization stage includes anomaly signal capture and instruction pointer backtracking. When a branch prediction fails, is interrupted, or an anomaly occurs, the ROB records the original PC address and commit status of the abnormal instruction. The instruction pointer backtracking stage searches for the corresponding scalar history table pointer and global number in the instruction dispatch module based on the original PC of the abnormal instruction.
5. The method for asynchronous recording out-of-order processor register renaming checkpoints and rollbacks according to claim 4, characterized in that, The scalar state recovery step includes checkpoint matching and state overwriting. Checkpoint matching searches for the nearest checkpoint ≥ HTWP in the scalar checkpoint (3) linked list. If no matching checkpoint is found, the current HTWP is rolled back to the exception point. The sRAT and Freelist of the checkpoint are directly written into the hardware register to overwrite the current state and the physical register of the history table between the checkpoint and the exception point is released. The vector state recovery step includes a global number matching step. Searches for the nearest checkpoint ≥ GID in the vector checkpoint (15) linked list. If no matching checkpoint is found, the GID=1024 is rolled back to the exception point and the vRAT and V-Freelist of the checkpoint are written into the hardware register to overwrite the current state and the physical register of the history table between the checkpoint and the exception point is released.
6. The method for asynchronous recording out-of-order processor register renaming checkpoints and rollbacks according to claim 5, characterized in that, It also includes an instruction dispatch module (7). After receiving an instruction, the instruction dispatch module (7) sends the instruction to the instruction reordering buffer (8) for caching. In the instruction reordering buffer (8), scalar instructions and vector instructions are distinguished and different instructions are submitted in the order of instructions (11). During the process of submitting instructions in the order of instructions (11), scalar instructions and vector instructions are executed out of order according to the out-of-order execution of scalar instructions (12) and out-of-order execution of vector instructions (19). When scalar instructions and vector instructions are executed, different instructions are passed to the scalar instruction dispatch (9) and the vector instruction dispatch (10) and vector instruction preprocessing is performed on the vector instructions (13).