A memristor array-based hidden markov model forward algorithm classifier and a method for operating the same

Abstract

This invention belongs to the technical field of microelectronic devices, and discloses a hidden Markov model forward algorithm classifier based on a memristor array and its manipulation method. The classifier includes: a memristor array, a transimpedance amplifier, an analog-to-digital converter, a digital-to-analog converter, a data distributor, a serial-to-parallel converter, and a parallel-to-serial converter; the parallel-to-serial converter and the data distributor are used to process the newly received parallel digital signal β. p1 ~β pN The serial digital signal β is obtained by sequentially inputting it to different bit lines of the first memristor array. s1 ~β sN The serial-to-parallel converter converts the serial digital signal β s1 ~β sN By simultaneously inputting different bit lines of the second memristor array in parallel, a parallel digital signal β is obtained. p1 ~β pN The input is then converted from parallel to serial to enable iterative computation. Based on this classifier, the computational efficiency of the forward algorithm for Hidden Markov Models can be improved while reducing computational power consumption.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronic devices, and more particularly, relates to a hidden Markov model forward algorithm classifier based on a memristor array and a control method thereof. BACKGROUND

[0002] A hidden Markov model (HMM) is a statistical learning model, which is widely used in pattern recognition, speech recognition, biological sequence analysis and other fields. The traditional HMM classifier mainly adopts a software implementation method, and the traditional architecture adopts a Von Neumann architecture design with storage and calculation separated. Data needs to be frequently transmitted between the memory and the operation unit, which not only leads to a reduction in computing efficiency, but also causes high power consumption. In addition, the design of a large-scale computing unit and data storage unit often occupies a large chip area, which is not suitable for the needs of resource-limited embedded devices and edge computing scenarios. With the development of artificial intelligence technology, the demand for algorithm hardware acceleration is increasingly urgent.

[0003] How to improve the computing efficiency and reduce the computing power consumption of the forward algorithm of the hidden Markov model is an important topic to be discussed at present. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a hidden Markov model forward algorithm classifier based on a memristor array and a control method thereof, which aims to improve the computing efficiency and reduce the computing power consumption of the forward algorithm of the hidden Markov model.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present application, a hidden Markov model forward algorithm classifier based on a memristor array is provided, which comprises: first and second memristor arrays, first and second transimpedance amplifiers, first and second analog-to-digital converters, first and second digital-to-analog converters, a data distributor, a serial-to-parallel converter and a parallel-to-serial converter.

[0006] The basic unit of each memristor array comprises a non-volatile memristor and a switch connected in series, the conductance of the memristor is adjustable, the control ends of the switches of the same column basic units are connected to the same word line, the input ends of the same row basic units are connected to the same bit line, and the output ends of the same column basic units are connected to the same selection line.

[0007] The parallel-to-serial converter is used to input the newly received parallel digital signal in a serial manner to the data distributor; the data distributor is used to select only one row of the first memristor array at a time to make the digital signal The digital signals of the input rows are converted into voltages by the first digital-to-analog converter and then input into the bit lines of the corresponding rows and the calculation is performed by the memristors of the gated column, and the selection lines of the gated column output the serial current I s1 ~I sN ;I s1 ~I sN The voltage converted by the first trans-impedance amplifier is then converted into a serial digital signal by the first analog-to-digital converter ;

[0008] The serial-to-parallel converter is used to convert the serial digital signal The N rows of the second memristor array are simultaneously input in a parallel manner, the digital signals of the input rows are converted into voltages by the second digital-to-analog converter and then input into the bit lines of the corresponding rows and the calculation is performed by the memristors of the gated column, and the selection lines of the gated column output the parallel current I p1 ~I pN ;I p1 ~I pN The voltage converted by the second trans-impedance amplifier is then converted into a new parallel digital signal by the second analog-to-digital converter and input into the parallel-to-serial converter.

[0009] Optionally, the classifier further comprises a data selector between the first analog-to-digital converter and the serial-to-parallel converter, and the data selector is used to select only the selection lines corresponding to the selected columns of the first memristor array at a time.

[0010] Optionally, the serial-to-parallel converter and the parallel-to-serial converter are both shift registers.

[0011] Optionally, the classifier further comprises a write module, which is used to map the transpose matrix of the state transition matrix in the forward algorithm into the second memristor array in the form of a conductance state matrix, and map the emission matrix B in the forward algorithm into the first memristor array in the form of a conductance state matrix.

[0012] Optionally, the classifier further comprises a first timing control module, a second timing control module and a first address control module.

[0013] The first timing control module is used to control the serial-to-parallel converter to input the newly received parallel digital signal in a serial manner into the data distributor;

[0014] The first address control module is used to control the data distributor to sequentially gate the N rows of the first memristor array to make the sequentially gated rows of the array;

[0015] The second timing control module is used to control the parallel-to-serial converter to input the serial digital signal The N rows of the second memristor array are input simultaneously in parallel.

[0016] Optionally, the memristor used is a TiN / Ti / HfOx / TiN stacked memristor.

[0017] Optionally, the switch used is a transistor.

[0018] The present invention also provides a method for manipulating a Hidden Markov Model forward algorithm classifier based on a memristor array as described above, comprising:

[0019] Simultaneously, columns 1 to N of the second memristor array are selected; the second memristor array stores the transpose of the N*N state transition matrix in the forward algorithm in the form of a conductance matrix;

[0020] Based on the observation sequence O=(O1,O2,...,O T ) Perform column gating on the first memristor array, O t Let t be the t-th observation component, and T be the total number of time points. The 0th observation component is selected at time t. t The first memristor array stores the N*M emitter matrix in the forward algorithm in the form of a conductance matrix.

[0021] At time t=1, the initial state probability will be determined. The converted voltage vector components are sequentially input to the first to N bit lines of the first memristor array; at times t=2,3,...,T, the parallel-to-serial converter and data distributor are controlled to process the received digital signal at each time t. The first memristor array is sequentially input to rows 1-N, converted to voltage by the first digital-to-analog converter, and then sequentially input to bit lines 1-N; at each time, the Oth bit... t The memristors in the column are calculated sequentially and the serial current I is output sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The signal is converted into a voltage by the first transimpedance amplifier and then into a serial digital signal by the first analog-to-digital converter. ;

[0022] Control the serial-to-parallel converter to output the result at each time t. Input rows 1 to N of the second memristor array simultaneously in parallel. After being converted to voltage by the second digital-to-analog converter, the voltage is simultaneously input to the first to Nth bit lines of the second memristor array, causing the memristors in columns 1 to N to perform calculations simultaneously and output parallel current I on the selection lines of columns 1 to N. p1 ~I pN ;I p1 ~IpN The signal is converted to voltage by the second transimpedance amplifier and then converted into a parallel digital signal by the second analog-to-digital converter. And input the parallel-to-serial converter at the next time t+1;

[0023] Sum the N voltages output serially from the first transimpedance amplifier at time T to output the observation sequence O=(O1,O2,...,O2). T The probability of it appearing in a Hidden Markov Model.

[0024] Optionally, it further includes: mapping the transpose of the state transition matrix into the second memristor array in the form of a conductance state matrix, and mapping the emitter matrix B into the first memristor array in the form of a conductance state matrix.

[0025] Optionally, the process of mapping any element of the matrix to a selected memristor in the form of conductance states includes:

[0026] First, a reset operation is performed on the selected memristor. The reset operation includes: applying a fixed high level to the select line terminal of the selected memristor, applying a fixed low level to the bit line terminal, and applying a stepped square wave voltage pulse with gradually increasing amplitude to the word line terminal until the memristor is completely reset.

[0027] Next, a setting operation is performed on the selected memristor to make it reach the preset conductance value. The setting operation includes: applying a fixed high level to the bit line terminal of the selected memristor, applying a fixed low level to the select line terminal, applying a stepped square wave pulse with gradually increasing amplitude to the word line terminal, and applying a read pulse after each pulse to check whether the memristor has reached the preset conductance value. If the memristor conductance reaches the preset value, the pulse application is stopped.

[0028] In summary, compared with the prior art, the technical solutions conceived in this invention have the following main advantages:

[0029] 1. In this invention, the parallel-to-serial converter, data distributor, first digital-to-analog converter, first memristor array, and first analog-to-digital converter constitute the first part; the serial-to-parallel converter, second digital-to-analog converter, second memristor array, second transimpedance amplifier, and second analog-to-digital converter constitute the second part. These two parts actually implement the iterative calculation of the signal flow. This iterative design is compatible with the iterative calculation in the Hidden Markov Model (HMM) forward algorithm. Therefore, when the HMM forward algorithm needs to be executed, it is only necessary to transpose the state transition matrix A of the HMM. T By mapping the conductance state matrix to the second memristor array, mapping the emission matrix B of the Hidden Markov Model to the first memristor array in the form of a conductance state matrix, and controlling the word line gating of the first memristor array based on the observation sequence, the forward algorithm of the Hidden Markov Model can be implemented in hardware.

[0030] 2. This invention fully utilizes the parallel computing capabilities of the memristor array by implementing the forward algorithm of the Hidden Markov Model on the memristor array. Based on the non-volatile nature of the memristor, the state transition matrix and emission matrix are directly stored in the memristor array in the form of conductance values, without the need for additional storage units. The calculation results can be read directly in the form of current, avoiding the data transfer overhead in the traditional architecture. Compared with the traditional digital circuit-based calculation method, the computational complexity is reduced to O(N), making the classifier more efficient when processing large-scale sequence data.

[0031] 3. Traditional Hidden Markov Models (HMMs) rely on software computing platforms, which are limited by memory and computing resources. This invention innovatively maps the core parameters of the HMM (such as the state transition matrix and emission matrix) to the conductance weight matrix of a memristor array, and implements the recursive operation of the forward probability vector through hardware circuitry. This design significantly reduces the hardware footprint of the model, providing an efficient and compact implementation method for embedded devices and edge computing scenarios. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a Hidden Markov Model forward algorithm classifier based on a memristor array in one embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the structure of a memristor array in one embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the structure of an array basic unit in one embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the simulated conductance transition of a 1T1R memristor under gate voltage regulation in one embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of the conductance weighting matrix of a memristor array according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the Hidden Markov Model forward algorithm performing calculations in a memristor array;

[0038] Figure 7 This is a comparison chart of the probability of observation sequences calculated by software and a memristor array according to one embodiment;

[0039] Figure 8 This is a comparison diagram of memristor array calculation and software calculation in one embodiment. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0041] For a Hidden Markov Model (HMM), given N hidden states and M observables, the state transition matrix A is an N*N matrix where each value represents the probability of transitioning from one state to another. Its emission matrix B is an N*M matrix where each value represents the probability of a given observation in a given state, and the initial state probability... Let O = (O1, O2, ..., O2) be a vector of length N. T T is the length of the observation sequence. The forward algorithm of the Hidden Markov Model is used to compute the given model parameters A, B, and T. The probability of a given time t in the observation sequence and the total probability.

[0042] The forward algorithm for Hidden Markov Models requires the following steps to complete a full computation: first, perform an initial forward probability calculation (one Hadamard product); then, perform T-1 forward probability iterations (one matrix-vector multiplication and one Hadamard product); and finally, perform a summation calculation.

[0043] First, the initial forward probability calculation is performed at t=1, using the following formula: ;

[0044] In the formula, Let be the initial probability vector input. The index in matrix B is column vectors, for and Hadamard product, Let be the initial forward probability vector for t=1.

[0045] Then perform T-1 forward probability iterations for t=2,3,…,T, with the formula: ;

[0046] In the formula, A T Let α be the transpose of the state transition matrix A. t-1 The forward probability vector of the previous time step is the α calculated in the previous step. t-1 , The index in matrix B is column vectors, transpose matrix The forward probability vector obtained at time t-1 The vector obtained after matrix multiplication is then multiplied by the column vector. Multiplying them gives the Hadamard product, which yields the forward probability vector at time t. .

[0047] Finally, summing the components of the forward probability vectors of all hidden states at time T yields the observation sequence O = (O1, O2, ..., O2). T The probability of occurrence under a Hidden Markov Model is given by the formula: .

[0048] In the formula, for The i-th component.

[0049] The purpose of this invention is to implement the above-mentioned Hidden Markov Model forward algorithm through hardware structure, so as to improve the computation speed.

[0050] like Figure 1 The diagram shows a schematic of a Hidden Markov Model (HMM) forward algorithm classifier based on a memristor array according to an embodiment of the present invention. It includes first and second memristor arrays, first and second transimpedance amplifiers, first and second analog-to-digital converters (ADCs), first and second digital-to-analog converters (DACs), a data distributor, a serial-to-parallel converter, and a parallel-to-serial converter. The first and second ADCs are used to perform analog-to-digital conversion and are abbreviated as ADCs in the diagram. The first and second DACs are used to perform digital-to-analog conversion and are abbreviated as DACs in the diagram. The first and second transimpedance amplifiers are used to convert current to voltage and are abbreviated as TIAs in the diagram.

[0051] like Figure 2 The diagram shown is a schematic representation of a memristor array according to an embodiment of the present invention. Figure 3 The diagram shown is a structural schematic of an array basic unit in one embodiment of the present invention.

[0052] The basic array unit can adopt a 1T1R structure, which consists of a non-volatile memristor connected in series with a switch, which can be a transistor. In the array, the upper electrode of the memristor is connected to the bit line BL for row selection, the lower electrode of the memristor is connected to the drain of the transistor, the gate of the transistor is connected to the word line WL for column selection, and the source of the transistor is connected to the select line SL. Furthermore, the upper electrodes of 1T1R memristor units in the same row are connected to the same bit line BL, the gates of 1T1R memristor units in the same column are connected to the same sub-line WL, and the sources of 1T1R memristor units in the same column are connected to the same select line SL.

[0053] The conductance of the memristor is adjustable and can be controlled (written) by adjusting the gate voltage. Specifically: apply a fixed positive voltage to BL, a fixed voltage of 0V to SL, and apply a pulsed square wave voltage with gradually increasing amplitude to WL to gradually set the memristor to a low-resistance state; apply a fixed positive voltage to SL, a fixed voltage of 0V to BL, and apply a pulsed square wave voltage with gradually increasing amplitude to WL to gradually reset the memristor to a high-resistance state. Figure 4 The diagram shown is a schematic of the simulated conductance transition of a 1T1R memristor under gate voltage regulation in one embodiment. The simulated conductance state transition is relatively linear and symmetrical in the 1T1R memristor by the gate voltage regulation method, achieving more than 100 stable conductance states. Moreover, the conductance state of the memristor remains unchanged after continuous reading for 10^5s at room temperature, indicating that it has good stability.

[0054] In the Hidden Markov Model (HMM) forward classifier, the transimpedance amplifier, analog-to-digital converter (ADC), and digital-to-analog converter (DAC) can be considered as signal processing modules peripheral to the array. The transimpedance amplifier converts the current output from the memristor array into a suitable voltage and then converts it into a digital signal via the ADC. The DAC converts the digital signal back into a voltage signal and re-inputs it into the memristor array for matrix calculations. The serial-to-parallel converter, parallel-to-serial converter, and data distributor can be considered as data distribution and selection modules. The serial-to-parallel converter converts serial data into parallel data and outputs it, while the parallel-to-serial converter converts parallel data into serial data and outputs it. The data distributor selects the rows of the memristor array. In specific embodiments, both the serial-to-parallel converter and the parallel-to-serial converter can be implemented using shift registers.

[0055] In this invention, a Hidden Markov Model (HMM) forward algorithm classifier is constructed using a memristor array, a signal processing module, and a data allocation and selection module to implement the HMM forward algorithm. This classifier actually comprises the following two structural parts:

[0056] Part 1: Parallel-to-serial converters are used to convert newly received parallel digital signals. The data is sequentially input to the data distributor; the data distributor is used to select only one row of the first memristor array at a time to enable the digital signal. The digital signals of each input row are successively input to the selected row of the array. After being converted into voltage by the first digital-to-analog converter, the voltage is input to the bit line of the corresponding row and then processed by the memristors of the selected column. The selection lines of the selected column output a serial current I sequentially. s1 ~I sN ;I s1 ~I sN The signal is converted to voltage by the first transimpedance amplifier and then converted into a serial digital signal by the first analog-to-digital converter. ;

[0057] Part Two: Serial-to-Parallel Converters are used to convert serial digital signals The digital signals of the N rows of the second memristor array are simultaneously input in parallel. After being converted into voltages by the second digital-to-analog converter, the signals are input to the bit lines of the corresponding rows and then processed by the memristors in the gating column for calculation. The selection lines of the gating column simultaneously output parallel current I. p1 ~I pN ;I p1 ~I pN The signal is converted to voltage by the second transimpedance amplifier and then converted into a parallel digital signal by the second analog-to-digital converter. And input the parallel-to-serial converter at the next moment.

[0058] This shows that the above two parts actually implement the iterative calculation of the signal flow. This iterative design is compatible with the iterative calculation in the Hidden Markov Model forward algorithm. Therefore, when it is necessary to execute the Hidden Markov Model forward algorithm, it is only necessary to convert the transpose A of the state transition matrix of the Hidden Markov Model. T By mapping the conductance state matrix to a second memristor array and the emission matrix B of the Hidden Markov Model (HMM) to a first memristor array in the form of a conductance state matrix, and controlling the word line gating of the first memristor array based on the observation sequence, the forward algorithm of the HMM can be implemented in hardware. Compared with traditional digital circuit-based computation methods, the computational complexity is reduced to O(N), making the classifier more efficient when processing large-scale sequence data, and the recursive operation of the forward probability vector is implemented through hardware circuits. This design greatly reduces the hardware footprint of the model, providing an efficient and compact implementation method for embedded devices and edge computing scenarios.

[0059] In one embodiment, the classifier further includes a data selector located between the first analog-to-digital converter and the serial-to-parallel converter. The data selector is used to select only the selection line corresponding to the selected column of the first memristor array at a time. Thus, by adding the data selector, it is ensured that only the output of the selected column of the first memristor array is transmitted to the serial-to-parallel converter, guaranteeing the accuracy of data transmission.

[0060] In one embodiment, the classifier further includes a writing module for mapping the transpose of the state transition matrix in the forward algorithm to a second memristor array in the form of a conductance state matrix, and mapping the emittance matrix B in the forward algorithm to a first memristor array in the form of a conductance state matrix. Based on this writing module, the parameters in the memristor array can be updated as needed to adapt to different hidden Markov models.

[0061] In one embodiment, a memristor with a TiN / Ti / HfOx / TiN structure is selected, and the transistor width can be 6um~70um and the length can be 300nm~400nm.

[0062] This invention also provides a method for manipulating a Hidden Markov Model (HMM) forward algorithm classifier based on a memristor array, so as to implement the HMM forward algorithm based on the classifier. The manipulation method includes:

[0063] Simultaneously, columns 1 to N of the second memristor array are selected; the second memristor array stores the transpose of the N*N state transition matrix in the forward algorithm in the form of a conductance matrix;

[0064] Based on the observation sequence O=(O1,O2,...,O T ) Perform column gating on the first memristor array, O t Let t be the t-th observation component, and T be the total number of time points. The 0th observation component is selected at time t. t The first memristor array stores the N*M emitter matrix in the forward algorithm in the form of a conductance matrix.

[0065] At time t=1, the initial state probability will be determined. The converted voltage vector components are sequentially input to the first to N bit lines of the first memristor array; at times t=2,3,...,T, the parallel-to-serial converter and data distributor are controlled to process the received digital signal at each time t. The first memristor array is sequentially input to rows 1-N, converted to voltage by the first digital-to-analog converter, and then sequentially input to bit lines 1-N; at each time, the Oth bit... t The memristors in the column are calculated sequentially and the serial current I is output sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The signal is converted into a voltage by the first transimpedance amplifier and then into a serial digital signal by the first analog-to-digital converter. ;

[0066] Control the serial-to-parallel converter to output the result at each time t. Input rows 1 to N of the second memristor array simultaneously in parallel. After being converted to voltage by the second digital-to-analog converter, the voltage is simultaneously input to the first to Nth bit lines of the second memristor array, causing the memristors in columns 1 to N to perform calculations simultaneously and output parallel current I on the selection lines of columns 1 to N. p1 ~I pN ;I p1 ~I pN The signal is converted to voltage by the second transimpedance amplifier and then converted into a parallel digital signal by the second analog-to-digital converter. And input the parallel-to-serial converter at the next time t+1;

[0067] Sum the N voltages output serially from the first transimpedance amplifier at time T to output the observation sequence O=(O1,O2,...,O2). T The probability of it appearing in a Hidden Markov Model.

[0068] The following is a detailed explanation of the operation process.

[0069] Preparation: Transpose A of the N*N state transition matrix A of the Hidden Markov Model. T The N*M emission matrix B of the hidden Markov model is mapped to the second memristor array in the form of a conductance state matrix, and the N*M emission matrix B of the hidden Markov model is mapped to the first memristor array in the form of a conductance state matrix.

[0070] In this invention, matrices A and B are model parameters determined through training. The classifier designed in this invention determines the model parameters through training during the training phase, and then maps the model parameters to the classifier designed in this invention, using the classifier to predict the probability of the input observation sequence.

[0071] Specifically, the operations performed during the training phase include: first, preparing training data to ensure that the observations of the sequence come from a fixed set; then, initializing the model parameters, including the initial state distribution. The model is prepared with state transition matrix A and emission matrix B. Then, the Baum-Welch algorithm is used to train the model, calculating the expected value using a forward-backward algorithm and iteratively updating the parameters until convergence. Finally, the model performance is verified, and the trained model parameters (i.e., the final matrices A and B) are saved for subsequent applications.

[0072] During matrix writing, matrix parameters can be mapped to a memristor array using gate voltage regulation. Taking mapping one element of the matrix to a selected memristor in the array as an example, the matrix gate voltage regulation method includes the following steps S01~S02.

[0073] Step S01: Reset the selected memristor.

[0074] The reset operation includes: applying a fixed high level to the SL terminal of the selected memristor, applying a fixed low level to the BL terminal, and applying a stepped square wave voltage pulse with gradually increasing amplitude to the WL terminal until the memristor is fully reset.

[0075] Specifically, a fixed voltage of 1.4V is applied to the SL terminal of the selected memristor, a fixed voltage of 0V is applied to the BL terminal, and a stepped square wave voltage pulse with gradually increasing amplitude is applied to the WL terminal. The initial amplitude of the voltage signal is 0.4V, and it gradually increases in steps of 0.01V until it reaches 3.3V. The pulse width is 100ns. 290 consecutive stepped pulses are applied to completely reset the memristor.

[0076] Step S02: Set the selected memristor to achieve the preset conductance value.

[0077] The setting operation includes: applying a fixed high level to the BL terminal of the selected memristor, applying a fixed low level to the SL terminal, and applying a stepped square wave pulse with gradually increasing amplitude to the WL terminal. After each pulse is applied, a reading pulse is applied to check whether the memristor has reached the preset conductance value. If the memristor conductance reaches the preset value, the pulse application is stopped.

[0078] Specifically, a fixed voltage of 1.0V is applied to the BL terminal of the selected memristor, a fixed voltage of 0V is applied to the SL terminal, and a stepped square wave pulse with gradually increasing amplitude is applied to the WL terminal. The initial pulse of this voltage signal is 0.7V, and it gradually increases in steps of 0.001V until it reaches 1.5V. The pulse width is 100ns. A reading pulse is applied after each pulse to check whether the memristor has reached the preset conductance value. If the memristor conductance reaches the preset value, the pulse application is stopped.

[0079] If the memristor is being used for the first time, an activation operation must be performed before step S01.

[0080] The activation operation includes: applying a fixed high level to the BL terminal of the selected memristor, a fixed low level to the SL terminal, and a square wave pulse to the WL terminal to activate the memristor. After each activation pulse is applied, a read pulse is applied to check whether the memristor is successfully activated. The maximum number of activation pulses is set to 40. For unselected memristor units, SL and BL are left floating.

[0081] Specifically, a fixed voltage of 2.8V is applied to the BL terminal of the selected memristor, a fixed voltage of 0V is applied to the SL terminal, and a square wave pulse with an amplitude of 1.5V and a pulse width of 100ns is applied to the WL terminal to perform forming on the memristor. A read pulse is applied after each forming pulse to check whether the memristor has been successfully forged. The upper limit of the forming pulse is set to 40. For unselected memristor cells, both the SL and BL terminals are forging.

[0082] During the read operation, a fixed voltage of 0.1V can be applied to the SL terminal of the selected memristor, a fixed voltage of 0V can be applied to the BL terminal, and a square wave voltage pulse with an amplitude of 3.3V and a pulse width of 100NS can be applied to the WL terminal. The conductance of the memristor can be calculated by detecting the current of SL.

[0083] Furthermore, after performing conductance mapping on memristors at all locations, post-verification can be performed by applying read pulses to memristors at all locations to determine the accuracy of the conductance mapping.

[0084] The transpose matrix A of the state transition matrix of the trained Hidden Markov Model is... TAfter the emitter matrix B is written into the memristor array in the form of a conductance weight matrix, its conductance weight matrix is ​​as follows: Figure 5 As shown, the normalized mean square error (NMSE) of the target model matrix is ​​4.73%, indicating that the writing accuracy is very high.

[0085] After mapping the matrix parameters of the model to the memristor array in the classifier using the above method, the classifier can be started to perform forward operations. The operations include word line control of the second memristor array, word line control of the first memristor array, initial bit line control of the first memristor array, data distributor, serial-to-parallel converter, and parallel-to-serial converter control.

[0086] Word line control of the second memristor array includes: simultaneously selecting columns 1 to N of the second memristor array throughout the entire operation, thereby implementing the Hidden Markov Forward Algorithm through the second memristor array. Matrix multiplication.

[0087] Word line control of the first memristor array includes: based on the observation sequence O=(O1,O2,...,O2) T ) Perform column gating on the first memristor array, and gating the Oth column at time t. t List.

[0088] The initial bit line control of the first memristor array includes: at time t=1, the initial state probability... The converted voltage vector components are sequentially input to the first to N bit lines of the first memristor array.

[0089] Control of the parallel-to-serial converter and data distributor includes controlling the parallel-to-serial converter and data distributor to process the received digital signal at each time t, at times t=2,3,...,T. The first memristor array is sequentially input to rows 1 to N, and after being converted into voltage by the first digital-to-analog converter, it is sequentially input to the first to N bit lines.

[0090] At each time t, after the bit line of the first memristor array receives a voltage, the Oth... t The memristors in the column are calculated sequentially and the serial current I is output sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The signal is converted into a voltage by the first transimpedance amplifier and then into a serial digital signal by the first analog-to-digital converter. .

[0091] Control of the serial-to-parallel converter includes: at each time t, converting the output at that time... Input rows 1 to N of the second memristor array simultaneously in parallel. After being converted into voltage by the second digital-to-analog converter, the voltage is simultaneously input to the first to Nth bit lines of the second memristor array. At each time t, after the bit lines of the second memristor array receive the voltage, the memristors in columns 1 to N simultaneously perform calculations and output parallel current I on the selection lines of columns 1 to N. p1 ~I pN ;I p1 ~I pN The signal is converted to voltage by the second transimpedance amplifier and then converted into a parallel digital signal by the second analog-to-digital converter. And input the parallel-to-serial converter at the next time t+1.

[0092] Through the above operations, the initial forward probability calculation and forward probability iterative calculation in the Hidden Markov Forward Algorithm can be realized. Finally, by summing the N voltages serially output by the first transimpedance amplifier at time T, the observation sequence O=(O1,O2,...,O2) can be obtained. T The total probability of ).

[0093] like Figure 6 The diagram illustrates the execution of the Hidden Markov Model forward algorithm in a memristor array. Figure 6 Further explanation of the operation and function of the classifier:

[0094] (1) At time t=1, the initial state probability of the Hidden Markov Model is... This is converted into a voltage vector, and then input one by one to the BL terminals of the first memristor array mapped by the emitter matrix B. When the component is applied to the corresponding BL terminal, the first observation O1 corresponds to WL O1 Apply a square wave pulse with an amplitude of 3.3V and a pulse width of 100NS to gating the column indexed by observation O1, the selection line of which is SL. O1 The current is gradually output from the terminal, by gradually... The component is applied to the corresponding BL end and in Apply a synchronization pulse, The memristor performs calculations sequentially and outputs a serial current I sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The voltage is converted to serial voltage via TIA, and the serial voltage is... The Hadamard product is used to calculate the initial forward probability in the forward algorithm of the Hidden Markov Model. ;

[0095] (2) Serial voltage output by TIA The serial digital signal is obtained after ADC processing. The serial data is then converted into parallel data by a serial-to-parallel converter, and after being converted by a DAC, it is input in parallel to the transpose matrix A of the state transition matrix. T The corresponding BL terminal of the mapped second memristor array, for all A T A square wave pulse with an amplitude of 3.3V and a pulse width of 100ns is applied to the WL terminal of the corresponding memristor array to select all A. T The corresponding column of the memristor array, with all SL terminals outputting parallel current I. p1 ~I pN I s1 ~I sN The voltage is converted to parallel voltage via TIA, and the parallel voltage is... Matrix product;

[0096] (3) Parallel output Parallel digital signals are obtained through ADC processing. At time t=2, a parallel-to-serial converter is input to convert the parallel data into serial data. The data is then distributed step-by-step by a data distributor to the BL terminals of the second memristor array mapped by the emitter matrix B. Each voltage value applied to the corresponding BL terminal corresponds to the second observation value O2. Apply a square wave pulse with an amplitude of 3.3V and a pulse width of 100NS to gating the observation value in the O2 index column. Terminal output serial current I s1 ~I sN By gradually putting The component is applied to the corresponding BL end and in Apply a synchronization pulse, The memristor performs calculations sequentially and outputs a serial current I sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The voltage is converted to serial voltage via TIA, and the serial voltage is... The Hadamard product is used to perform the second forward probability calculation in the forward algorithm of the Hidden Markov Model. .

[0097] (4) Iterate in the same way as steps (2) and (3) for the observation sequence O=(O1,O2,...,O T ), and thus calculate through the above process. The value is calculated until all observations O1, O2, ..., O T Corresponding forward probability Until all probabilities have been calculated, in each operation, the forward probability output from the previous step is used. In the transpose matrix A of the state transition matrixT A matrix-vector multiplication operation is performed in the mapped memristor array, and a column vector Hadamard product operation is performed in the memristor array mapped by the emission matrix B based on the current observation.

[0098] (5) Based on step (4), the forward probability vector at time T is obtained recursively. ,Will Summing all components yields the observation sequence O = (O1, O2, ..., O2). T The probability of occurrence given a Hidden Markov Model .

[0099] The effects of the present invention will be verified below.

[0100] Five sets of observation sequence data were obtained from five sets of speech data through feature extraction and vector quantization. Five Hidden Markov Models were then trained using these five sets of observation sequence data. The training process involved initializing the model parameters, including the initial state distribution. The model is trained using the state transition matrix A and the emission matrix B. The expected value is calculated using the forward-backward algorithm, and the parameters are iteratively updated until convergence.

[0101] Five Hidden Markov Models were mapped to memristor arrays. The calculation process of steps (1) to (5) was performed on the 150 observation sequences in the test set in the memristor arrays corresponding to the five Hidden Markov Models. For each observation sequence, the maximum probability calculated in the five models was selected as the classification result of the sequence. The classification result was compared with the true label of the test set, and the classification accuracy was calculated. The accuracy was 94%.

[0102] The same forward algorithm is executed via the CPU and via a memristor array, respectively, and the two methods are compared.

[0103] like Figure 7 The figure shown is a comparison of the probability of the observation sequence calculated by the software with that of the memristor array in one embodiment. It can be seen that the probability of the speech signal from the test set of the first group under Model 1 obtained by the forward algorithm of the memristor array is much greater than the probability of other models, and the speech signal is successfully recognized.

[0104] like Figure 8 The figure shown is a comparison between computation using a memristor array and computation using software. It can be seen that executing the forward algorithm on a memristor array reduces the time complexity from O(NT) to O(1). 2 The power consumption is reduced from 0 to NT, the computing power consumption is reduced by 6 orders of magnitude, and the computing time is reduced by about 20 times.

[0105] In summary, this invention maps the transpose (Aᵀ) of the state transition matrix and the emission matrix (B) of a Hidden Markov Model (HMM) onto a memristor array as conductance weight matrices. By applying a voltage signal in the form of an input vector and combining it with the conductance characteristics of the memristor array, matrix-vector multiplication is performed to generate intermediate hidden state probability vectors. In the memristor array mapped by the emission matrix, the intermediate hidden state probability vector is element-wise multiplied with the observation probability vector (Hadamard product) to achieve weighted updates of the observations, completing the forward probability calculation. Each iteration result is normalized by a transimpedance amplifier to avoid numerical overflow and precision loss. Based on the forward probability vector obtained from the final iteration of the forward algorithm, the most likely HMM state category corresponding to the observed sequence is determined by probability comparison, achieving the classification function. This invention implements the forward algorithm of the HMM on a memristor array, fully utilizing the parallel computing capabilities of the memristor array. Compared to traditional digital circuit-based calculation methods, the computational complexity is reduced by O(N), making the classifier more efficient when processing large-scale sequence data. This invention innovatively maps the core parameters of a Hidden Markov Model (such as the state transition matrix and emitter matrix) to the conductance weight matrix of a memristor array, and implements the recursive operation of the forward probability vector through hardware circuitry. This design significantly reduces the hardware footprint of the model, providing an efficient and compact implementation method for embedded devices and edge computing scenarios.

[0106] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" in this invention are intended to illustrate the invention and are not intended to limit the invention.

[0107] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A Hidden Markov Model forward algorithm classifier based on memristor arrays, characterized in that, include: A first memristor array and a second memristor array, a first transimpedance amplifier and a second transimpedance amplifier, a first analog-to-digital converter and a second analog-to-digital converter, a first digital-to-analog converter and a second digital-to-analog converter, a data distributor, a serial-to-parallel converter and a parallel-to-serial converter; Each memristor array's basic unit includes a series-connected non-volatile memristor and a switch. The conductance of the memristor is adjustable. The switch control terminals of basic units in the same column are connected to the same word line, the input terminals of basic units in the same row are connected to the same bit line, and the output terminals of basic units in the same column are connected to the same select line. The parallel-to-serial converter is used to convert the newly received parallel digital signal into a parallel digital signal. The data is input sequentially to the data distributor; the data distributor is used to select only one row of the first memristor array at a time to enable the digital signal. The digital signals of each input row are successively input to the selected row of the array. After being converted into voltage by the first digital-to-analog converter, the voltage is input to the bit line of the corresponding row and then processed by the memristors of the selected column. The selection lines of the selected column output a serial current I sequentially. s1 ~I sN ;I s1 ~I sN The signal is converted to voltage by the first transimpedance amplifier and then converted into a serial digital signal by the first analog-to-digital converter. ; The serial-to-parallel converter is used to convert serial digital signals. The digital signals of the second memristor array are simultaneously input in parallel to each other. After being converted into voltage by the second digital-to-analog converter, the digital signals of the input rows are input to the bit lines of the corresponding rows and then processed by the memristors in the gating column for calculation. The selection lines of the gating column simultaneously output parallel current I. p1 ~I pN ;I p1 ~I pN The signal is converted into a voltage by the second transimpedance amplifier, then converted into a new parallel digital signal by the second analog-to-digital converter, and then input into the parallel-to-serial converter.

2. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, The classifier also includes a data selector located between the first analog-to-digital converter and the serial-to-parallel converter, the data selector being used to select only the selection line corresponding to the selected column of the first memristor array at a time.

3. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, Both the serial-to-parallel converter and the parallel-to-serial converter are shift registers.

4. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, The classifier also includes a writing module, which maps the transpose of the state transition matrix in the forward algorithm to the second memristor array in the form of a conductance state matrix, and maps the emitter matrix B in the forward algorithm to the first memristor array in the form of a conductance state matrix.

5. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, The classifier also includes a first timing control module, a second timing control module, and a first address control module; The first timing control module is used to control the parallel-to-serial converter to process the newly received parallel digital signal. The data is input sequentially into the data distributor. The first address control module is used to control the data distributor to successively select N rows of the first memristor array so that Input is sequentially sent to the array to be selected for passage; The second timing control module is used to control the serial-to-parallel converter to convert the serial digital signal into a serial digital signal. The N rows of the second memristor array are input simultaneously in parallel.

6. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, The memristor used is a TiN / Ti / HfOx / TiN stacked memristor.

7. The Hidden Markov Model Forward Algorithm Classifier based on Memristor Array as described in claim 1, characterized in that, The switch used is a transistor.

8. A method for manipulating a Hidden Markov Model forward algorithm classifier based on a memristor array as described in any one of claims 1 to 7, characterized in that, include: Simultaneously, columns 1 to N of the second memristor array are selected; the second memristor array stores the transpose of the N*N state transition matrix in the forward algorithm in the form of a conductance matrix; Based on the observation sequence O=(O1,O2,...,O T ) Perform column gating on the first memristor array, O t Let t be the t-th observation component, and T be the total number of times. The 0th observation component is selected at time t. t The first memristor array stores the N*M emission matrix in the forward algorithm in the form of a conductance matrix, where M is the number of observables in the hidden Markov model. At time t=1, the initial state probability will be determined. The converted voltage vector components are sequentially input to the first to N bit lines of the first memristor array; at times t=2,3,...,T, the parallel-to-serial converter and data distributor are controlled to process the received digital signal at each time t. The first memristor array is sequentially input into rows 1 to N, and after being converted into voltage by the first digital-to-analog converter, it is sequentially input into the first to N bit lines. At each moment, the Oth t The memristors in the column are calculated sequentially and the serial current I is output sequentially on the select line of that column. s1 ~I sN I s1 ~I sN The signal is converted into a voltage by the first transimpedance amplifier and then into a serial digital signal by the first analog-to-digital converter. ; Control the serial-to-parallel converter to output the result at each time t. Input rows 1 to N of the second memristor array simultaneously in parallel. After being converted to voltage by the second digital-to-analog converter, the voltage is simultaneously input to the first to Nth bit lines of the second memristor array, causing the memristors in columns 1 to N to perform calculations simultaneously and output parallel current I on the selection lines of columns 1 to N. p1 ~I pN ;I p1 ~I pN The signal is converted into a voltage by the second transimpedance amplifier, then converted into a parallel digital signal by the second analog-to-digital converter, and input into the parallel-to-serial converter at the next time t+1. Sum the N voltages output serially from the first transimpedance amplifier at time T to output the observation sequence O=(O1,O2,...,O2). T The probability of it appearing in a Hidden Markov Model.

9. The control method as described in claim 8, characterized in that, Also includes: The transpose of the state transition matrix is ​​mapped to the second memristor array in the form of a conductance state matrix, and the emitter matrix B is mapped to the first memristor array in the form of a conductance state matrix.

10. The control method as described in claim 9, characterized in that, The process of mapping any element of a matrix to a selected memristor in terms of conductance states includes: First, a reset operation is performed on the selected memristor. The reset operation includes: applying a fixed high level to the select line terminal of the selected memristor, applying a fixed low level to the bit line terminal, and applying a stepped square wave voltage pulse with gradually increasing amplitude to the word line terminal until the memristor is completely reset. Next, a setting operation is performed on the selected memristor to make it reach the preset conductance value. The setting operation includes: applying a fixed high level to the bit line terminal of the selected memristor, applying a fixed low level to the select line terminal, applying a stepped square wave pulse with gradually increasing amplitude to the word line terminal, and applying a read pulse after each pulse to check whether the memristor has reached the preset conductance value. If the memristor conductance reaches the preset value, the pulse application is stopped.

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