Memory device and noise suppression method thereof

Abstract

The invention provides a memory device and a noise suppression method thereof. An input receiving circuit of the memory circuit receives a data strobe differential signal pair. The noise suppression circuit provides a noise suppression resistor connected between an input terminal of the input receiving circuit and a ground voltage during a write data strobe off period before a write ordinal period.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a memory device and a method for suppressing noise thereof. Background Art

[0002] In a low power DDR4 (low power DDR4, LPDDR4) dynamic random access memory (DRAM), there may sometimes be a situation where the control signal output from the controller to the memory circuit violates the timing definition before the preamble of the data strobe signal (Data Strobe Signal, DQS) of the Solid State Technology Association (JEDEC) standard (standard). For example, during the period before the write preamble, during the period when the write data strobe signal is off, both the data strobe signals DQS_t and DQS_c are at a low logic level.

[0003] Since the data strobe signals DQS_c and DQS_t are a differential signal pair, any small signal may be amplified and then generate a noise signal that causes the circuit to malfunction. Especially when the on-die termination (ODT) of the dynamic random access memory is maintained in the off state, it is more likely to generate a noise signal sufficient to cause the circuit to malfunction. Summary of the Invention

[0004] The present invention provides a method for suppressing noise in a memory device, which can effectively prevent a noise signal from being amplified into a noise signal sufficient to cause the circuit to malfunction when the data strobe signal pair is at a low logic level during the period when the write data strobe signal is off.

[0005] The memory device of the present invention includes a memory circuit and a noise suppression circuit. The memory circuit receives data according to a data strobe differential signal pair, and the memory circuit includes an input receiving circuit for receiving the data strobe differential signal pair. The noise suppression circuit is coupled to the input end of the input receiving circuit, and provides a noise suppression resistor connected between the input end of the input receiving circuit and the ground voltage during the period when the write data strobe signal is off before the write preamble.

[0006] In an embodiment of the present invention, the above input receiving circuit is a differential amplifier, and the noise suppression circuit includes a first switch circuit, a first resistor, a second switch circuit, and a second resistor. The first resistor and the first switch circuit are connected in series between the first input terminal of the differential amplifier and the ground voltage. The second resistor and the second switch circuit are connected in series between the second input terminal of the differential amplifier and the ground voltage. The first switch circuit and the second switch circuit provide the first resistor connected between the first input terminal of the differential amplifier and the ground voltage and the second resistor connected between the second input terminal of the differential amplifier and the ground voltage during the period when the write data strobe signal is off.

[0007] In an embodiment of the present invention, the above data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at its first output terminal and second output terminal. The first switch circuit includes a first switch and a second switch. The second switch is connected in series with the first switch between the first input terminal of the differential amplifier and the first resistor. The conduction state of the first switch is controlled by the first data strobe signal or the first output signal, and the conduction state of the second switch is controlled by the second data strobe signal or the second output signal.

[0008] In an embodiment of the present invention, the above first switch and second switch are transistors.

[0009] In an embodiment of the present invention, the above data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at its first output terminal and second output terminal. The second switch circuit includes a third switch and a fourth switch. The fourth switch is connected in series with the third switch between the second input terminal of the differential amplifier and the second resistor. The conduction state of the third switch is controlled by the first data strobe signal or the first output signal, and the conduction state of the fourth switch is controlled by the second data strobe signal or the second output signal.

[0010] In an embodiment of the present invention, the above third switch and fourth switch are transistors.

[0011] In an embodiment of the present invention, the above memory device further includes a control circuit that provides a data strobe differential signal pair, and the memory circuit receives data from the control circuit according to the data strobe differential signal pair.

[0012] The present invention also provides a noise suppression method for a memory device. The memory device includes an input receiving circuit for receiving a data strobe differential signal pair. The noise suppression method for the memory device includes the following steps. Determine whether the memory device enters the write data strobe signal off period before the write preamble period. When the memory device enters the write data strobe signal off period, provide a noise suppression resistor connected between the input end of the input receiving circuit and the ground voltage.

[0013] In an embodiment of the present invention, the above input receiving circuit is a differential amplifier. The noise suppression method for the memory device includes the following steps. Provide a first switch circuit, a second switch circuit, a first resistor, and a second resistor. The first resistor and the first switch circuit are connected in series between the first input end of the differential amplifier and the ground voltage. The second resistor and the second switch circuit are connected in series between the second input end of the differential amplifier and the ground voltage. During the write data strobe signal off period, control the first switch circuit and the second switch circuit to respectively provide the first resistor connected between the first input end of the differential amplifier and the ground voltage and the second resistor connected between the second input end of the differential amplifier and the ground voltage.

[0014] In an embodiment of the present invention, the above data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at its first output end and second output end. The first switch circuit includes a first switch and a second switch. The second switch is connected in series with the first switch between the first input end of the differential amplifier and the first resistor. The conduction state of the first switch is controlled by the first data strobe signal or the first output signal. The conduction state of the second switch is controlled by the second data strobe signal or the second output signal.

[0015] In an embodiment of the present invention, the above first switch and second switch are transistors.

[0016] In an embodiment of the present invention, the above data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at its first output end and second output end. The second switch circuit includes a third switch and a fourth switch. The fourth switch is connected in series with the third switch between the second input end of the differential amplifier and the second resistor. The conduction state of the third switch is controlled by the first data strobe signal or the first output signal. The conduction state of the fourth switch is controlled by the second data strobe signal or the second output signal.

[0017] In an embodiment of the present invention, the above third switch and fourth switch are transistors.

[0018] Based on the above, during the period when the write data strobe signal is turned off before the preamble writing period, the noise suppression circuit according to an embodiment of the present invention can provide a noise suppression resistor connected between the input terminal of the input receiving circuit and the ground voltage. In this way, when the data strobe signal is at a low logic level during the period when the write data strobe signal is turned off, noise signals can be effectively prevented from being amplified into noise signals sufficient to cause misoperation of the circuit.

[0019] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0020] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention;

[0021] Figure 2 is a waveform schematic diagram of data strobe signals DQS_c and DQS_t according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of an input receiving circuit and a noise suppression circuit according to an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of an input receiving circuit and a noise suppression circuit according to another embodiment of the present invention;

[0024] Figure 5 is a schematic diagram of a noise suppression resistor and an output resistor of a control circuit according to an embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of a noise suppression resistor, an on-chip terminator resistor, and an output resistor of a control circuit according to an embodiment of the present invention;

[0026] Figure 7 is a flowchart of a noise suppression method for a memory device according to an embodiment of the present invention. Detailed Embodiments

[0027] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Please refer to Figure 1. The memory device 100 includes a memory circuit 104 and a noise control circuit 106. The memory circuit 104 has an input receiving circuit 108. The memory circuit 104 is coupled to a control circuit 102 and the input receiving circuit 108, and the noise control circuit 106 is coupled to the input terminal of the input receiving circuit 108. The control circuit 102 can output an instruction control signal SC1 and a data strobe differential signal pair (including a data strobe signal DQS_c and a data strobe signal DQS_t) to the memory circuit 104. The output instruction control signal SC1 is used to control the data access operation of the memory circuit 104 to transmit a data signal D1 between the control circuit 102 and the memory circuit 104. The data strobe signals DQS_c and DQS_t are used to trigger the access operation of the memory circuit 104. The control circuit 102 can be, for example, a processor or a central processing unit, and the memory device 100 can be, for example, a low-power DDR4 dynamic random access memory, but is not limited thereto. In addition, in some embodiments, the control circuit 102 can also be integrated into the memory device 100, but is not limited to this embodiment.

[0028] As Figure 2 shown, since the data strobe signals DQS_c and DQS_t are a differential signal pair, when the data strobe signals DQS_c and DQS_t are both set to a low voltage logic level during the write data strobe signal off period WDQS_OFF before the write preamble period tWPRE, since the input terminal of the input receiving circuit 108 is a differential input terminal, if a noise signal appears at the input terminal of the input receiving circuit 108, the noise signal may be amplified enough to cause a malfunction of the memory circuit 104, and incorrect data may be accessed during the data transmission period TD. To avoid this situation, the noise suppression circuit 106 can provide a noise suppression resistor connected between the input terminal of the input receiving circuit 108 and the ground voltage during the write data strobe signal off period WDQS_OFF. In this way, the noise signal can be divided by the noise suppression resistor (for example, by a voltage dividing circuit formed with the output resistor CR of the control circuit 102), and the noise signal can be prevented from being amplified into a noise signal that can cause a malfunction of the memory circuit 104.

[0029] Furthermore, the implementation manners of the input receiving circuit 108 and the noise suppression circuit 106 can be as Figure 3 shown. In Figure 3In an embodiment, the input receiving circuit 108 is implemented by a differential amplifier 306, and the noise suppression circuit 106 may include switch circuits 302, 304 and resistors R1, R2. The differential amplifier 306 has a first input terminal and a second input terminal. The switch circuit 302 and the resistor R1 are connected in series between the first input terminal of the differential amplifier 306 and the ground voltage GND. The switch circuit 302 and the resistor R1 are connected in series between the first input terminal of the differential amplifier 306 and the ground voltage GND. The switch circuits 302 and 304 can provide the resistor R1 connected between the first input terminal of the differential amplifier 306 and the ground voltage GND and the resistor R2 connected between the second input terminal of the differential amplifier 306 and the ground voltage GND during the period when the write data strobe signal is off (WDQS_OFF).

[0030] In this embodiment, the switch circuit 302 is implemented by series-connected switches SW1, SW2, and the switch circuit 304 is implemented by series-connected switches SW3, SW4. The conduction states of the switches SW1, SW3 can be controlled by the data strobe signal DQS_c, and the conduction states of the switches SW2, SW4 can be controlled by the data strobe signal DQS_t. Thus, when both the data strobe signals DQS_c and DQS_t are at a low voltage level, the switch circuits 302 and 304 can be in a conducting state to provide the resistor R1 connected between the first input terminal of the differential amplifier 306 and the ground voltage GND and the resistor R2 connected between the second input terminal of the differential amplifier 306 and the ground voltage GND. The switches SW1 to SW4 can be implemented, for example, Figure 4 as shown, by P-type transistors P1 to P4. In other embodiments, the switches SW1 to SW4 can also be implemented by, for example, N-type transistors. In addition, the conduction states of the switches SW1, SW3 can be controlled, for example, by the output signal *DQS_c output from the first output terminal of the differential amplifier 306 according to the data strobe signal DQS_c, and the conduction states of the switches SW2, SW4 can be controlled, for example, by the output signal *DQS_t output from the second output terminal of the differential amplifier 306 according to the data strobe signal DQS_t, and this is not limited to this embodiment.

[0031] When the resistance of the on-die terminator of the memory device 100 is turned off (i.e., Figure 3 、 Figure 4 when the switches SW5, SW6 in Figure 5As shown. Since the switch SW6 is open, the resistance ODTR2 of the on-chip terminator can be ignored. The voltage-dividing circuit formed by the output resistance CR of the control circuit 102 and the resistance R2 of the noise suppression circuit 106 can divide the voltage of the noise signal appearing on the second input terminal of the differential amplifier, and thus achieve the effect of suppressing the noise signal, preventing the noise signal from being amplified into a noise signal that may cause misoperation of the memory circuit 104. Similarly, a voltage-dividing circuit formed by the output resistance CR of the control circuit 102 and the resistance R1 of the noise suppression circuit 106 can also be formed at the first input terminal of the differential amplifier 306 to suppress the noise signal appearing on the first input terminal of the differential amplifier. For example, when the voltage value VN of the noise signal appearing on the second input terminal of the differential amplifier 306 is equal to 134 mV, if the output resistance CR of the control circuit 102 is 50 ohm and the resistance R1 of the noise suppression circuit 106 is 40 ohm, the voltage value of the noise signal at the second input terminal of the differential amplifier 306 will be suppressed to 59 mV.

[0032] In addition, when the resistance of the on-chip terminator of the memory device 100 is turned on (that is, Figure 3 , Figure 4 when the switches SW5 and SW6 in are turned on), the resistances R1 and R2 provided by the switch circuits 302 and 304 can further suppress the noise signal at the second input terminal of the differential amplifier 306. As Figure 6 shown, taking the second input terminal of the differential amplifier 306 as an example, compared with Figure 5 the embodiment, the equivalent resistance circuit of the second input terminal of the differential amplifier 306 can further include the resistance ODTR2 of the on-chip terminator. The output resistance CR of the control circuit 102 is connected in series with the parallel resistances R2 and ODTR2 to further suppress the noise signal at the second input terminal of the differential amplifier 306. For example, when the voltage value VN of the noise signal appearing on the second input terminal of the differential amplifier 306 is equal to 134 mV, if the output resistance CR of the control circuit 102 is 50 ohm, and the resistances R1 and ODTR2 of the noise suppression circuit 106 are both 40 ohm, the voltage value of the noise signal at the second input terminal of the differential amplifier 306 will be suppressed to 38 mV.

[0033] Figure 7FIG. 0 is a flowchart of a noise suppression method for a memory device according to an embodiment of the present invention. The memory device includes an input receiving circuit that receives a data strobe differential signal pair (which includes a first data strobe signal and a second data strobe signal). As can be seen from the above embodiment, the noise suppression method for the memory device may at least include the following steps. First, it is determined whether the memory device enters the write data strobe signal off period before the write preamble period (step S702). Then, when the memory device enters the write data strobe signal off period, a noise suppression resistor connected between the input end of the input receiving circuit and the ground voltage is provided (step S704), so as to divide the noise signal through a voltage dividing circuit formed by the noise suppression resistor and the output resistor of the control circuit, and prevent the noise signal from being amplified into a noise signal that may cause misoperation of the memory circuit.

[0034] Furthermore, the input receiving circuit may be, for example, a differential amplifier. The way of providing the noise suppression resistor may be, for example, to provide a first switch circuit, a second switch circuit, a first resistor, and a second resistor. The first resistor and the first switch circuit are connected in series between the first input end of the differential amplifier and the ground voltage, and the second resistor and the second switch circuit are connected in series between the second input end of the differential amplifier and the ground voltage. During the write data strobe signal off period, the first resistor connected between the first input end of the differential amplifier and the ground voltage and the second resistor connected between the second input end of the differential amplifier and the ground voltage can be respectively provided by turning on the first switch circuit and the second switch circuit. The first switch circuit may include, for example, a first switch and a second switch, and the second switch circuit may include, for example, a third switch and a fourth switch. The first switch and the second switch are connected in series between the first input end of the differential amplifier and the first resistor, and the third switch and the fourth switch are connected in series between the second input end of the differential amplifier and the second resistor. The conduction states of the first switch and the third switch may be controlled by, for example, the first data strobe signal or a first output signal output from the first output end of the differential amplifier, and the conduction states of the second switch and the fourth switch may be controlled by, for example, the second data strobe signal or a second output signal output from the second output end of the differential amplifier. In this way, the first switch to the fourth switch can be turned on when the first data strobe signal and the second data strobe signal are at a low logic level, so as to provide the first resistor and the second resistor as the noise suppression resistors. The first switch to the fourth switch may be implemented by transistors, for example.

[0035] In summary, the noise suppression circuit according to the embodiment of the present invention can provide a noise suppression resistor connected between the input end of the input receiving circuit and the ground voltage during the write data strobe signal off period before the write preamble period. In this way, when the data strobe signal pair is at a low logic level during the write data strobe signal off period, the noise signal can be effectively prevented from being amplified into a noise signal sufficient to cause misoperation of the circuit.

[0036] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to what is defined by the claims.

Claims

1. A memory device, characterized in that: include: A memory circuit receives data according to a data selection differential signal pair, the memory circuit comprising: An input receiving circuit receives the data selection differential signal pair; as well as The noise suppression circuit is coupled to the input terminal of the input receiving circuit and provides a noise suppression resistor connected between the input terminal of the input receiving circuit and the ground voltage during a write data strobe signal OFF period before a write preamble period.

2. The memory device according to claim 1, wherein: The input receiving circuit is a differential amplifier, and the noise suppression circuit includes: a first switching circuit; A first resistor connected in series with the first switch circuit between the first input terminal of the differential amplifier and the ground voltage; a second switching circuit; and A second resistor is connected in series with the second switch circuit between the second input terminal of the differential amplifier and the ground voltage. The first switch circuit and the second switch circuit provide the first resistor connected between the first input terminal of the differential amplifier and the ground voltage and the second resistor connected between the second input terminal of the differential amplifier and the ground voltage during the period when the write data strobe is turned off.

3. The memory device according to claim 2, wherein: The data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at a first output terminal and a second output terminal thereof. The first switch circuit includes: a first switch; and The second switch is connected in series with the first switch between the first input terminal of the differential amplifier and the first resistor, the conduction state of the first switch is controlled by the first data selection signal or the first output signal, and the conduction state of the second switch is controlled by the second data selection signal or the second output signal.

4. The memory device according to claim 3, wherein: The first switch and the second switch are transistors.

5. The memory device according to claim 2, wherein: The data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at a first output terminal and a second output terminal thereof. The second switch circuit includes: a third switch; and A fourth switch is connected in series with the third switch between the second input terminal of the differential amplifier and the second resistor, the conduction state of the third switch is controlled by the first data selection signal or the first output signal, and the conduction state of the fourth switch is controlled by the second data selection signal or the second output signal.

6. The memory device according to claim 5, wherein: The third switch and the fourth switch are transistors.

7. The memory device according to claim 1, wherein: Also includes: The control circuit provides a data strobe differential signal pair, and the memory circuit receives data from the control circuit according to the data strobe differential signal pair.

8. A noise suppression method for a memory device, characterized in that: The memory device includes an input receiving circuit, the input receiving circuit is used to receive a data selection differential signal pair, and the noise suppression method of the memory device includes: determining whether the memory device enters a write data strobe off period before a write preamble period; and When the memory device enters the write data strobe off period, a noise suppression resistor is provided between the input terminal of the input receiving circuit and the ground voltage.

9. The noise suppression method of a memory device according to claim 8, characterized in that: The input receiving circuit is a differential amplifier, and the noise suppression method of the memory device includes: providing a first switch circuit, a second switch circuit, a first resistor and a second resistor, wherein the first resistor and the first switch circuit are connected in series between the first input terminal of the differential amplifier and the ground voltage, and the second resistor and the second switch circuit are connected in series between the second input terminal of the differential amplifier and the ground voltage; and During the write data strobe closure period, the first switch circuit and the second switch circuit are controlled to respectively provide the first resistor connected between the first input terminal of the differential amplifier and the ground voltage and the second resistor connected between the second input terminal of the differential amplifier and the ground voltage.

10. The noise suppression method of a memory device according to claim 9, wherein: The data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at a first output terminal and a second output terminal thereof. The first switch circuit includes: a first switch; and The second switch is connected in series with the first switch between the first input terminal of the differential amplifier and the first resistor, the conduction state of the first switch is controlled by the first data selection signal or the first output signal, and the conduction state of the second switch is controlled by the second data selection signal or the second output signal.

11. The noise suppression method of a memory device according to claim 10, wherein: The first switch and the second switch are transistors.

12. The noise suppression method of a memory device according to claim 9, wherein: The data strobe differential signal pair includes a first data strobe signal and a second data strobe signal. The differential amplifier amplifies the first data strobe signal and the second data strobe signal and outputs a first output signal and a second output signal at a first output terminal and a second output terminal thereof. The second switch circuit includes: a third switch; and A fourth switch is connected in series with the third switch between the second input terminal of the differential amplifier and the second resistor, the conduction state of the third switch is controlled by the first data selection signal or the first output signal, and the conduction state of the fourth switch is controlled by the second data selection signal or the second output signal.

13. The noise suppression method of a memory device according to claim 12, wherein: The third switch and the fourth switch are transistors.

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