Display device
By adopting a connecting electrode containing aluminum alloy and an optimized pad structure in the display device, the problem of increasing dead space when the substrate is bent is solved, the display quality is improved, and problems such as abnormal grain growth and surface roughness are prevented.
Patent Information
- Application Number
- CN202411778066.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-07
- Filing Date
- 2024-12-05
- Publication Date
- 2025-06-10
AI Technical Summary
When the existing display device is bent in the substrate, the position of the driving chip is set to increase the dead space, affecting the display quality.
Using a connecting electrode containing an aluminum alloy, the structure of the pad area is optimized and the dead space is reduced by the intermediate metal layer and the chip on the film provided on the second base substrate.
Effectively prevent abnormal growth of grains in the connecting electrodes, avoid surface roughness and visual black spots, and improve the quality of the display device.
Smart Images
Figure CN120129418A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a display device, and more particularly to a display device with improved quality. Background Art
[0002] In general, a display device is a device that displays an image for providing visual information to a user. Among display devices, an organic light emitting diode display has recently attracted attention.
[0003] The display device may include a display panel and a driving chip that transmits a signal to the display panel. When the substrate is bent in the thickness direction in the bending area, the driving chip may be disposed below the display panel. In this case, the dead space of the display device may be increased. Summary of the invention
[0004] Embodiments provide a display device with improved quality.
[0005] According to an embodiment, a display device includes: a first base substrate including a display area in which pixels are arranged and a pad area separated from the display area, an intermediate metal layer arranged on the first base substrate, a second base substrate arranged on the intermediate metal layer, a chip on film in contact with the intermediate metal layer in the pad area, and a connecting electrode arranged on the second base substrate, in contact with the intermediate metal layer in the pad area and including a first layer including an aluminum alloy and a second layer arranged on the first layer and including aluminum.
[0006] In an embodiment, the aluminum alloy included in the first layer of the connection electrode may include nickel ("Ni").
[0007] In an embodiment, the aluminum alloy included in the first layer of the connection electrode may further include neodymium ("Nd").
[0008] In an embodiment, the aluminum alloy included in the first layer of the connection electrode may further include lanthanum ("La").
[0009] In an embodiment, a ratio of nickel in the aluminum alloy included in the first layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0010] In an embodiment, a ratio of neodymium in the aluminum alloy included in the first layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0011] In an embodiment, a ratio of lanthanum in the aluminum alloy included in the first layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0012] In an embodiment, the thickness of the first layer of the connection electrode may be equal to or greater than about 3000 angstroms and equal to or less than about 4000 angstroms.
[0013] In an embodiment, the connection electrode may further include a third layer disposed on the second layer and including an aluminum alloy.
[0014] In an embodiment, the aluminum alloy included in the third layer of the connection electrode may include at least one of nickel, neodymium, and lanthanum.
[0015] In an embodiment, a ratio of nickel in the aluminum alloy included in the third layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0016] In an embodiment, a ratio of neodymium in the aluminum alloy included in the third layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0017] In an embodiment, a ratio of lanthanum in the aluminum alloy included in the third layer of the connection electrode may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent.
[0018] In an embodiment, a thickness of each of the first layer of the connection electrode and the third layer of the connection electrode may be equal to or greater than about 2000 angstroms and equal to or less than about 3000 angstroms.
[0019] In an embodiment, the connection electrode may further include a fourth layer disposed under the first layer and including titanium.
[0020] In an embodiment, the connection electrode may further include a fifth layer disposed on the second layer and including titanium.
[0021] In an implementation, the first base substrate may define a first opening in a partial region of the pad region.
[0022] In an embodiment, the chip on film may contact a lower surface of the intermediate metal layer in the first opening.
[0023] In an embodiment, each of the pixels may include an active layer disposed on the second base substrate, a gate electrode disposed on the active layer, a source electrode disposed on the gate electrode, and a drain electrode disposed on the gate electrode and spaced apart from the source electrode.
[0024] In an embodiment, the connection electrode, the source electrode, and the drain electrode may be provided on the same layer.
[0025] In an embodiment, the connection electrode may contact an upper surface of the intermediate metal layer.
[0026] In an implementation, the second base substrate may include polyimide.
[0027] In an implementation, the first base substrate and the second base substrate may include the same material.
[0028] In an implementation, the second base substrate may define a second opening.
[0029] In an implementation, the connection electrode may contact the intermediate metal layer in the second opening.
[0030] According to an embodiment, a display device may include: a first base substrate including a display area in which pixels are arranged and a pad area separated from the display area, an intermediate metal layer arranged on the first base substrate, a second base substrate arranged on the intermediate metal layer, a chip on film contacting the intermediate metal layer in the pad area, and a connecting electrode arranged on the second base substrate, contacting the intermediate metal layer in the pad area and including a first layer including an aluminum alloy and a second layer arranged on the first layer and including aluminum.
[0031] Accordingly, a phenomenon in which the crystal grains in the connection electrode grow abnormally can be prevented. Accordingly, a phenomenon in which the surface of the connection electrode becomes rough can be prevented, and a phenomenon in which black spots are visually recognized in a partial area of the connection electrode can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
[0033] Figure 1 A plan view for explaining a display device according to an embodiment.
[0034] Figure 2 According to the implementation mode Figure 1 A cross-sectional view of the display device taken along line XY.
[0035] Figure 3 According to the implementation mode Figure 2 An enlarged cross-sectional view of region A.
[0036] Figure 4 According to the implementation mode Figure 3 An enlarged cross-sectional view of an example of region B.
[0037] Figure 5 To explain the embodiment according to Figure 1 A cross-sectional view of a pixel included in a display device.
[0038] Figure 6 According to the implementation mode Figure 3 An enlarged cross-sectional view of another example of region B. DETAILED DESCRIPTION
[0039] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.
[0040] It will be understood that when an element (or region, layer or portion, etc.) is referred to as being associated with another element (or region, layer or portion, etc.), such as "on" another element (or region, layer or portion, etc.), "connected to" or "coupled to" another element (or region, layer or portion, etc.), it can be directly disposed on the other element (or region, layer or portion, etc.), directly connected to or directly coupled to the other element (or region, layer or portion, etc.), or intervening elements may be disposed between them.
[0041] The same reference numerals or symbols refer to the same elements throughout the text. In the accompanying drawings, for the effective description of the technical content, the proportions and sizes (such as thickness) of the elements are magnified. As used in this article, the term "and / or" includes any and all combinations of one or more related listed items.
[0042] The term "and / or" may include all combinations that may be defined by one or more configurations associated therewith.
[0043] It will be understood that although the terms first, second, etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the scope of the present invention, the first element, component, area, layer or part discussed below may be referred to as the second element, component, area, layer or part. Similarly, the second element, component, area, layer or part may be referred to as the first element, component, area, layer or part. As used in this article, the singular "one (a)", "one (an)" and "described" are intended to also include plural forms, unless the context clearly indicates otherwise.
[0044] Also, terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.
[0045] It will be further understood that when the terms "comprise", "includes" and / or "have" are used in this specification, it indicates the presence of the recited features, integers, steps, operations, elements, components and / or groups thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, "directly disposed on" ... "on" may mean that there are no additional layers, films, regions or plates, etc. between a component (such as a layer, film, region or plate, etc.) and another component (such as a layer, film, region or plate, etc.). For example, "directly disposed on" ... "on" may mean that two layers or two components are disposed without using an additional component such as a bonding component therebetween.
[0046] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.
[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this article have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense unless explicitly so defined in this article.
[0048] Figure 1 A plan view for explaining a display device according to an embodiment.
[0049] In the embodiments and with reference to Figure 1 , the display device DD may include a display area DA and a non-display area NDA. The display area DA may be defined as an area where light is emitted, and the non-display area NDA may be defined as an area in which components for transmitting signals to the display area DA are disposed.
[0050] In an embodiment, the pixels PX may be disposed in the display area DA. Each of the pixels PX may emit light based on a signal applied from the non-display area NDA. The pixels PX may generally be disposed in the display area DA and oriented along a first direction DR1 and a second direction DR2 crossing the first direction DR1. Accordingly, the display area DA may emit light and display an image throughout the entire display area DA.
[0051] In an embodiment, the non-display area NDA may be disposed adjacent to the display area DA. For example, the non-display area NDA may be disposed around the display area DA. For example, the non-display area NDA may surround at least a part of the display area DA. The non-display area NDA may include a pad area PA. The pad area PA may be spaced apart from the display area DA. For example, the pad area PA may be spaced apart from one side of the display area DA in the second direction DR2.
[0052] In an embodiment, the non-display area NDA may include a plurality of drivers for driving the pixels PX. For example, the plurality of drivers may include a gate driver, a light-emitting driver, a power voltage generator, a timing controller, and the like.
[0053] For example, in an embodiment, the second direction DR2 may be oriented perpendicular to the first direction DR1. However, the present invention is not limited thereto, and the second direction DR2 may form an acute angle or an obtuse angle with the first direction DR1. Additionally, a third direction DR3 intersecting the plane formed by the first direction DR1 and the second direction DR2 may be defined. For example, the third direction DR3 may be oriented perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, the present invention is not limited thereto, and the third direction DR3 may form an acute angle or an obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.
[0054] Figure 2 A cross-sectional view taken along the X-Y line of a display device according to an embodiment Figure 1 is shown.
[0055] In an embodiment and with reference to Figure 1 and Figure 2 , the display device DD may include a first substrate SUB1, a second substrate SUB2, a display layer PL, a polarizing plate POL, a cover window WD, a chip-on-film COF, a driving chip DC, and a circuit board PCB.
[0056] In an embodiment, the first substrate SUB1 may include a transparent material or an opaque material. For example, the first substrate SUB1 may be formed of a transparent resin substrate. For example, the first substrate SUB1 may include polyimide.
[0057] However, the present invention is not limited thereto, and in another embodiment, the first substrate SUB1 may include a quartz substrate (e.g., a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, or a non-alkali glass substrate, etc. The materials in these substrates may be used alone or in combination with each other.
[0058] For example, in an embodiment, the first substrate SUB1 may include a display area DA in which pixels PX are disposed and a non-display area NDA including a pad area PA.
[0059] In an embodiment, the second substrate SUB2 may be disposed on the first substrate SUB1. The second substrate SUB2 may include a transparent material or an opaque material. For example, in an embodiment, the second substrate SUB2 may be formed of a transparent resin substrate. For example, in an embodiment, the second substrate SUB2 may include polyimide.
[0060] However, the present invention is not limited thereto, and in an embodiment, the second substrate SUB2 may include a quartz substrate (e.g., synthetic quartz substrate, fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, or an alkali-free glass substrate, etc. The materials in these substrates may be used alone or in combination with each other.
[0061] In an embodiment, the second substrate SUB2 and the first substrate SUB1 may include substantially the same material. However, the present invention is not limited thereto, and in another embodiment, the second substrate SUB2 and the first substrate SUB1 may include different materials.
[0062] In an embodiment, the display layer PL may be disposed on the second substrate SUB2. The display layer PL may be disposed in at least a part of the display area DA. A reference will be made to Figure 5 Describe the display layer PL in more detail.
[0063] In an embodiment, the polarizing plate POL may be disposed on the display layer PL. The polarizing plate POL may prevent external light from being reflected. For example, external light may pass through the polarizing plate POL and be reflected from the upper surface of the common electrode (e.g., Figure 5 the common electrode CE). Thereafter, the external light may pass through the polarizing plate POL again, and in this case, the phase of the external light may change. As a result, the phase of the light reflected from the common electrode is different from the phase of the external light incident on the polarizing plate POL, and extinction interference may occur between the reflected light (e.g., the light reflected from the common electrode) and the external light incident on the polarizing plate POL.
[0064] In an embodiment, the cover window WD may be disposed on the polarizing plate POL. The cover window WD may protect the display layer PL, the polarizing plate POL, etc. from the influence of external impacts. For example, the cover window WD may be attached to the polarizing plate POL through a separate adhesive layer. For example, the cover window WD may be attached to the polarizing plate POL through an optically clear adhesive ("OCA"), an optically clear resin ("OCR"), or a pressure-sensitive adhesive ("PSA"), etc.
[0065] In an embodiment, the chip-on-film COF may be disposed under the second substrate SUB2. For example, the chip-on-film COF may be disposed in the pad area PA. Signal lines for applying an electric signal to the pixel PX may be disposed on the chip-on-film COF.
[0066] For example, in an embodiment, the chip - on - film COF may include a flexible material (such as a film or a tape, etc.). Accordingly, the chip - on - film COF can be bent in various shapes under the second substrate SUB2.
[0067] In an embodiment, the driving chip DC may be disposed on the chip - on - film COF. The driving chip DC can convert the digital data signal in the driving signal into an analog data signal. In addition, the driving chip DC can provide the analog data signal to the pixel PX. That is, the driving chip DC can provide the analog data signal to the pixel PX through the signal line disposed on the chip - on - film COF.
[0068] In an embodiment, the driving chip DC can be attached to the second substrate SUB2 in a chip - on - film (“COF”) scheme. However, the present invention is not limited thereto, and in another embodiment, the driving chip DC can be directly attached to the second substrate SUB2 in a chip - on - plastic (“COP”) scheme or a chip - on - glass (“COG”) scheme.
[0069] In an embodiment, the circuit board PCB may be disposed on the chip - on - film COF. The circuit board PCB can be spaced apart from the driving chip DC. For example, the circuit board PCB can be spaced apart from the driving chip DC on the chip - on - film COF in a direction opposite to the second direction DR2. The circuit board PCB can apply driving signals, driving voltages, etc. to the driving chip DC and the pixel PX.
[0070] In an embodiment, each of the first substrate SUB1 and the second substrate SUB2 may not be bent. In addition, the chip - on - film COF can be attached to the lower surface of the second substrate SUB2. In addition, the driving chip DC and the circuit board PCB can be disposed on the chip - on - film COF. Accordingly, the dead space of the display device DD can be reduced.
[0071] Figure 3 For the Figure 2 magnified cross - sectional view of region A according to an embodiment.
[0072] In an embodiment and with reference to Figure 2 and Figure 3 , the first substrate SUB1 may define a first opening OP1. For example, the first substrate SUB1 may define the first opening OP1 in a partial area of the pad region PA. For example, the first opening OP1 can be a structure obtained by removing a part from the lower surface to the upper surface of the first substrate SUB1.
[0073] In an embodiment, the chip - on - film COF may contact the lower surface of the intermediate metal layer MTL in the first opening OP1, which will be described later. That is, since the first base substrate SUB1 defines the first opening OP1, a space can be formed in which the intermediate metal layer MTL and the chip - on - film COF contact each other.
[0074] In an embodiment, the first insulating layer IL1 may be disposed on the first base substrate SUB1. The first insulating layer IL1 may define an opening. In a plan view, the opening of the first insulating layer IL1 may overlap with the first opening OP1. The intermediate metal layer MTL may fill the opening of the first insulating layer IL1. Accordingly, the intermediate metal layer MTL may be connected to the chip - on - film COF.
[0075] For example, in an embodiment, the first insulating layer IL1 may include an inorganic material. For example, the first insulating layer IL1 may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. These materials may be used alone or in combination with each other.
[0076] In an embodiment, the second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may include an inorganic material. For example, the second insulating layer IL2 may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. These materials may be used alone or in combination with each other.
[0077] In an embodiment, the second base substrate SUB2 may be disposed on the second insulating layer IL2. The second insulating layer IL2 and the second base substrate SUB2 may define a second opening OP2. The upper surface of the intermediate metal layer MTL may be exposed through the second opening OP2.
[0078] In an embodiment, the intermediate metal layer MTL may be disposed on the first base substrate SUB1. Additionally, the second base substrate SUB2 may be disposed on the intermediate metal layer MTL. That is, the intermediate metal layer MTL may be disposed between the first base substrate SUB1 and the second base substrate SUB2. For example, the intermediate metal layer MTL may be disposed between the first insulating layer IL1 and the second insulating layer IL2. As described above, the intermediate metal layer MTL may fill the opening of the first insulating layer IL1. Additionally, the lower surface of the intermediate metal layer MTL may contact the chip - on - film COF in the first opening OP1.
[0079] For example, in an embodiment, the intermediate metal layer MTL may include a metal, a conductive metal oxide, or a metal nitride, etc. These materials may be used alone or in combination with each other.
[0080] In an embodiment, examples of the metal may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), or scandium ("Sc"), etc. These materials may be used alone or in combination with each other.
[0081] In an embodiment, examples of the conductive metal oxide may include indium tin oxide or indium zinc oxide, etc. These materials may be used alone or in combination with each other.
[0082] In addition, in an embodiment, examples of the metal nitride may include aluminum nitride ("AlN x "), tungsten nitride ("WN x "), or chromium nitride ("CrN x "), etc. These materials may be used alone or in combination with each other.
[0083] In an embodiment, the buffer layer BUF may be disposed on the second substrate SUB2. The buffer layer BUF may cover the upper surface of the intermediate metal layer MTL exposed through the second opening OP2. In addition, the buffer layer BUF may define a fourth opening OP4. In a plan view, the fourth opening OP4 may overlap with the second opening OP2. A part of the upper surface of the intermediate metal layer MTL may be exposed through the fourth opening OP4. In an embodiment, the width of the fourth opening OP4 oriented in the second direction DR2 may be smaller than the width of the second opening OP2 oriented in the second direction DR2.
[0084] For example, in an embodiment, the buffer layer BUF may include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other.
[0085] In an embodiment, the gate insulating layer GI may be disposed on the buffer layer BUF. For example, the gate insulating layer GI may include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other.
[0086] In an embodiment, the interlayer insulating layer ILD may be disposed on the gate insulating layer GI. For example, the interlayer insulating layer ILD may include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other.
[0087] In an embodiment, the gate insulating layer GI and the interlayer insulating layer ILD may define a third opening OP3. In a plan view, the third opening OP3 may overlap with the second opening OP2. A part of the upper surface of the intermediate metal layer MTL may be exposed through the third opening OP3. For example, the width of the third opening OP3 oriented in the second direction DR2 may be smaller than the width of the second opening OP2 oriented in the second direction DR2, and may be larger than the width of the fourth opening OP4 oriented in the second direction DR2.
[0088] In an embodiment, the connection electrode LS may be disposed on the interlayer insulating layer ILD. The connection electrode LS may contact the intermediate metal layer MTL in the pad region PA. For example, the connection electrode LS may contact the intermediate metal layer MTL in the second opening OP2. For example, the connection electrode LS may contact the upper surface of the intermediate metal layer MTL exposed through the fourth opening OP4.
[0089] In an embodiment, the driving chip DC and the circuit board PCB may transmit driving signals to the pixels (e.g., Figure 1 the pixels PX) through the chip on film COF, the intermediate metal layer MTL, and the connection electrode LS.
[0090] In an embodiment, the connection electrode LS, the source electrode (e.g., Figure 5 the source electrode SE) to be described later, and the drain electrode (e.g., Figure 5 the drain electrode DE) may be formed on the same layer. In an embodiment, the connection electrode LS, the source electrode, and the drain electrode may include the same material. However, the present invention is not limited thereto, and the connection electrode LS, the source electrode, and the drain electrode may include different materials.
[0091] Figure 4 An enlarged cross-sectional view of an example of region B for Figure 3 an embodiment.
[0092] In an embodiment and with reference to Figure 4 , the connection electrode LS may include a first layer T1, a second layer A1, a third layer A2, and a fourth layer T2. The second layer A1 may be disposed on the first layer T1. The third layer A2 may be disposed on the second layer A1. The fourth layer T2 may be disposed on the third layer A2.
[0093] In an embodiment, the first layer T1 may contain a metal. In an embodiment, the first layer T1 may contain titanium. However, the present invention is not limited thereto, and in another embodiment, the first layer T1 may contain other types of metals, such as tungsten, copper, nickel, or chromium, etc.
[0094] In an embodiment, the second layer A1 may include a metal. In an embodiment, the second layer A1 may include an aluminum alloy. In an embodiment, the aluminum alloy included in the second layer A1 may include aluminum ("Al") and nickel ("Ni"). In an embodiment, the aluminum alloy included in the second layer A1 may further include neodymium ("Nd"). In an embodiment, the aluminum alloy included in the second layer A1 may further include lanthanum ("La"). However, the present invention is not limited thereto, and the aluminum alloy included in the second layer A1 may further include other types of metal elements.
[0095] In an embodiment, the third layer A2 may include a metal. In an embodiment, the third layer A2 may include aluminum. For example, the third layer A2 may include pure aluminum. In this specification, "pure aluminum" may mean that the aluminum is substantially 100%. That is, the third layer A2 may substantially include 100% aluminum. However, the present invention is not limited thereto, and in another embodiment, the third layer A2 may include other types of metals, such as tungsten, copper, nickel, or chromium.
[0096] In an embodiment, the fourth layer T2 may include a metal. In an embodiment, the fourth layer T2 may include titanium. However, the present invention is not limited thereto, and in another embodiment, the fourth layer T2 may include other types of metals, such as tungsten, copper, nickel, or chromium.
[0097] In an embodiment, the fourth layer T2 and the first layer T1 may include the same material. However, the present invention is not limited thereto, and in another embodiment, the fourth layer T2 and the first layer T1 may include different materials.
[0098] In an embodiment, the size of the grains of the aluminum alloy may be smaller than the size of the grains of pure aluminum. Accordingly, the grains of the aluminum alloy may not grow abnormally. In another embodiment, the possibility of abnormal growth of the grains of the aluminum alloy may be lower than the possibility of abnormal growth of the grains of pure aluminum.
[0099] In an embodiment and as described above, the second layer A1 may include an aluminum alloy. Accordingly, the grains of the second layer A1 may not grow abnormally. In another embodiment, because the second layer A1 contains an aluminum alloy, the possibility that the grains of the second layer A1 do not grow abnormally may be higher than the possibility that the grains of the second layer A1 do not grow abnormally when the second layer A1 contains pure aluminum. That is, because the second layer A1 includes an aluminum alloy, the phenomenon of abnormal growth of grains in the connecting electrode LS can be prevented. Accordingly, the phenomenon in which the surface of the connecting electrode LS becomes rough can be prevented, and the phenomenon in which black spots are visually recognized in some regions of the connecting electrode LS can be prevented.
[0100] In an embodiment and as described above, the second base substrate (e.g., Figure 3The second base substrate (SUB2) may include polyimide. That is, the second base substrate may include an organic material. In this case, the discharge of oxygen and / or moisture may occur in the second base substrate. Since the second layer A1 contains aluminum alloy, the phenomenon that the oxygen and / or moisture discharged from the second base substrate penetrates into the third layer A2 containing aluminum can be prevented. That is, the second layer A1 can protect the third layer A2 from the oxygen and / or moisture discharged from the second base substrate. Accordingly, the aluminum contained in the third layer A2 may not be oxidized to aluminum oxide or the like. Therefore, the phenomenon of visually recognizing black dots due to the difference in reflectivity between aluminum and aluminum oxide in the third layer A2 can be prevented.
[0101] However, the present invention is not limited thereto, and the phenomenon of recognizing black dots can have various causes, and since the second layer A1 contains aluminum alloy, the phenomenon of recognizing black dots in the connection electrode LS can be prevented.
[0102] In an embodiment, the proportion of nickel in the aluminum alloy contained in the second layer A1 of the connection electrode LS may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. When the proportion of nickel in the aluminum alloy contained in the second layer A1 is less than about 0.02 atomic percentage, the grains of the second layer A1 may grow abnormally, or the possibility of abnormal grain growth of the second layer A1 may increase. When the proportion of nickel in the aluminum alloy contained in the second layer A1 exceeds about 0.05 atomic percentage, when forming the connection electrode LS including the second layer A1 on the gate insulating layer (e.g., Figure 3 the gate insulating layer GI), the etching process may not proceed smoothly.
[0103] In an embodiment, the proportion of neodymium in the aluminum alloy contained in the second layer A1 of the connection electrode LS may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. When the proportion of neodymium in the aluminum alloy contained in the second layer A1 is less than about 0.02 atomic percentage, the grains of the second layer A1 may grow abnormally, or the possibility of abnormal grain growth of the second layer A1 may increase. When the proportion of neodymium in the aluminum alloy contained in the second layer A1 exceeds about 0.05 atomic percentage, when forming the connection electrode LS including the second layer A1 on the gate insulating layer (e.g., Figure 3 the gate insulating layer GI), the etching process may not proceed smoothly.
[0104] In an embodiment, the proportion of lanthanum in the aluminum alloy contained in the second layer A1 connected to the electrode LS may be equal to or greater than about 0.02 atomic percent and equal to or less than about 0.05 atomic percent. When the proportion of lanthanum in the aluminum alloy contained in the second layer A1 is less than about 0.02 atomic percent, the grains of the second layer A1 may grow abnormally, or the possibility of abnormal grain growth of the second layer A1 may increase. When the proportion of lanthanum in the aluminum alloy contained in the second layer A1 exceeds about 0.05 atomic percent, when forming the connection electrode LS including the second layer A1 on the gate insulating layer (e.g., Figure 3 of the gate insulating layer GI), the etching process may not proceed smoothly.
[0105] In an embodiment, the thickness W1 of the second layer A1 of the connection electrode LS may be equal to or greater than about 3000 angstroms and equal to or less than about 4000 angstroms. When the thickness W1 of the second layer A1 is less than about 3000 angstroms, the second layer A1 may not sufficiently protect the third layer A2 from the oxygen and / or moisture discharged from the second substrate. When the thickness W1 of the second layer A1 exceeds about 4000 angstroms, the resistance of the connection electrode LS may increase, or the conductivity of the connection electrode LS may decrease.
[0106] Figure 5 To illustrate the Figure 1 cross-sectional view of a pixel included in a display device according to an embodiment.
[0107] In an embodiment and referring to Figure 5 , the pixel PX may include a first substrate SUB1, a second substrate SUB2, a first insulating layer IL1, a second insulating layer IL2, a display insulating layer PI, an active layer ACT, a source electrode SE, a gate electrode GE, a drain electrode DE, a pixel electrode PE, a light-emitting layer EML, and a common electrode CE.
[0108] In an embodiment, the light-emitting element LED may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE. The transistor TR may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The display layer PL may include the light-emitting element LED, the transistor TR, and the display insulating layer PI.
[0109] In an embodiment, the display insulating layer PI may include a buffer layer BUF, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, and a packaging layer TFE.
[0110] In an embodiment, the active layer ACT may be disposed on the buffer layer BUF. The active layer ACT may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon, metal oxide semiconductor) or an organic semiconductor, etc. These materials may be used alone or in combination with each other. The active layer ACT may include a source region, a drain region, and a channel region disposed between the source region and the drain region.
[0111] In an embodiment, the metal oxide semiconductor may include binary compounds (“AB x ”) containing indium (“In”), zinc (“Zn”), gallium (“Ga”), tin (“Sn”), titanium (“Ti”), aluminum (“Al”), hafnium (“Hf”), zirconium (“Zr”), and / or magnesium (“Mg”), etc. and oxygen, ternary compounds (“AB x C y ”), and quaternary compounds (“AB x C y D z ”), etc. These materials may be used alone or in combination with each other.
[0112] For example, in an embodiment, the metal oxide semiconductor may include zinc oxide (“ZnO x ”), gallium oxide (“GaO x ”), tin oxide (“SnO x ”), indium oxide (“InO x ”), indium gallium oxide (“IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), indium zinc tin oxide (“IZTO”), and indium gallium zinc oxide (“IGZO”). These materials may be used alone or in combination with each other.
[0113] In an embodiment, the gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may sufficiently cover the active layer ACT. For example, the gate insulating layer GI may cover the active layer ACT and may be disposed along the contour of the active layer ACT.
[0114] In an embodiment, the gate electrode GE may be disposed on the gate insulating layer GI. In a plan view, the gate electrode GE may overlap with the channel region of the active layer ACT.
[0115] In an embodiment, the gate electrode GE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. Examples of the metal may include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), or scandium (“Sc”), etc. These materials may be used alone or in combination with each other.
[0116] In an embodiment, examples of the conductive metal oxide may include indium tin oxide or indium zinc oxide, etc. Additionally, examples of the metal nitride may include aluminum nitride (“AlN x ”), tungsten nitride (“WN x ”), or chromium nitride (“CrN x ”), etc. These materials may be used alone or in combination with each other.
[0117] In an embodiment, an interlayer insulating layer ILD may be disposed on the gate insulating layer GI. The interlayer insulating layer ILD may sufficiently cover the gate electrode GE. For example, the interlayer insulating layer ILD may cover the gate electrode GE and may be disposed along the contour of the gate electrode GE.
[0118] In an embodiment, a source electrode SE may be disposed on the interlayer insulating layer ILD. The source electrode SE may be connected to the source region of the active layer ACT through a first contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.
[0119] In an embodiment, a drain electrode DE may be disposed on the interlayer insulating layer ILD. The drain electrode DE may be connected to the drain region of the active layer ACT through a second contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.
[0120] For example, in an embodiment, each of the source electrode SE and the drain electrode DE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These materials may be used alone or in combination with each other. In an embodiment, the source electrode SE, the drain electrode DE, and the connection electrode (e.g., Figure 4 the connection electrode LS) may include the same material and have the same structure.
[0121] However, the present invention is not limited thereto, and in another embodiment, each of the source electrode SE and the drain electrode DE may have a material different from that of the connection electrode and a structure different from that of the connection electrode. For example, in an embodiment, each of the source electrode SE and the drain electrode DE may have a single-layer structure made of one material.
[0122] In an embodiment, a via insulating layer VIA may be disposed on the interlayer insulating layer ILD. The via insulating layer VIA may sufficiently cover the source electrode SE and the drain electrode DE. The via insulating layer VIA may include an organic material. For example, the via insulating layer VIA may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, or epoxy resin, etc. These materials may be used alone or in combination with each other.
[0123] In an embodiment, a pixel electrode PE may be disposed on the via insulating layer VIA. The pixel electrode PE may be connected to the drain electrode DE through a contact hole passing through the via insulating layer VIA.
[0124] In an embodiment, the pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These materials may be used alone or in combination with each other. In an embodiment, the pixel electrode PE may have a stacked structure including ITO / Ag / ITO. For example, in an embodiment, the pixel electrode PE may operate as an anode.
[0125] In an embodiment, the pixel defining layer PDL may be disposed on the via insulating layer VIA. The pixel defining layer PDL may cover the side portions of the pixel electrode PE. Additionally, an opening may be defined in the pixel defining layer PDL to expose a part of the upper surface of the pixel electrode PE.
[0126] For example, in an embodiment, the pixel defining layer PDL may include an inorganic material or an organic material. In an embodiment, the pixel defining layer PDL may include an organic material such as an epoxy resin or a silicone resin. These materials may be used alone or in combination with each other. In another embodiment, the pixel defining layer PDL may further include a light-blocking material containing a black pigment or a black dye, etc.
[0127] In an embodiment, the emission layer EML may be disposed on the pixel electrode PE. The emission layer EML may include an organic material that emits light of a predetermined color. For example, the emission layer EML may include an organic material that emits red light. However, the present invention is not limited thereto, and the emission layer EML may emit light of a color different from red light.
[0128] In an embodiment, the common electrode CE may be disposed on the emission layer EML and the pixel defining layer PDL. The common electrode CE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These materials may be used alone or in combination with each other. The common electrode CE may operate as a cathode.
[0129] In an embodiment, the encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may prevent impurities and moisture from penetrating from the outside into the pixel electrode PE, the emission layer EML, and the common electrode CE. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer.
[0130] For example, in an embodiment, the inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic layer may include a polymer cured product such as polyacrylate.
[0131] Although embodiments of the pixel PX have been described with reference to Figure 5 the pixel PX is not limited to Figure 5The structure shown. That is, in other embodiments, the pixel PX may include all structures that receive an electrical signal and emit light having a luminance corresponding to the intensity of the electrical signal.
[0132] Figure 6 is an enlarged cross-sectional view of another example of region B according to an embodiment. Figure 3 of region B according to an embodiment.
[0133] In another embodiment and with reference to Figure 6 , the connection electrode LS' may include a first layer T1, a second layer A1', a third layer A2, a fourth layer A3, and a fifth layer T2'.
[0134] In an embodiment, the second layer A1' may be disposed on the first layer T1. The third layer A2 may be disposed on the second layer A1'. The fourth layer A3 may be disposed on the third layer A2. The fifth layer T2' may be disposed on the fourth layer A3.
[0135] In an embodiment, the first layer T1 may contain a metal. In an embodiment, the first layer T1 may contain titanium. However, the present invention is not limited thereto, and in another embodiment, the first layer T1 may contain other types of metals, such as tungsten, copper, nickel, or chromium, etc.
[0136] In an embodiment, the second layer A1' may contain a metal. In an embodiment, the second layer A1' may contain an aluminum alloy. In an embodiment, the aluminum alloy contained in the second layer A1' may contain nickel, neodymium, or lanthanum, etc. These elements may be used alone or in combination with each other.
[0137] For example, in an embodiment, the second layer A1' may contain aluminum and nickel. In an embodiment, the aluminum alloy contained in the second layer A1' may further contain neodymium. In an embodiment, the aluminum alloy contained in the second layer A1' may further contain lanthanum. However, the present invention is not limited thereto, and the aluminum alloy contained in the second layer A1' may further contain other types of metal elements.
[0138] In an embodiment, the third layer A2 may contain a metal. In an embodiment, the third layer A2 may contain aluminum. For example, the third layer A2 may contain pure aluminum. However, the present invention is not limited thereto, and in another embodiment, the third layer A2 may contain other types of metals, such as tungsten, copper, nickel, or chromium, etc.
[0139] In an embodiment, the fourth layer A3 may contain a metal. In an embodiment, the fourth layer A3 may contain an aluminum alloy. In an embodiment, the aluminum alloy contained in the fourth layer A3 may contain nickel, neodymium, or lanthanum, etc. These elements may be used alone or in combination with each other.
[0140] For example, in an embodiment, the fourth layer A3 may include aluminum and nickel. In an embodiment, the aluminum alloy included in the fourth layer A3 may further include neodymium. In an embodiment, the aluminum alloy included in the fourth layer A3 may further include lanthanum. However, the present invention is not limited thereto, and the aluminum alloy included in the fourth layer A3 may further include other types of metal elements.
[0141] In an embodiment, the fourth layer A3 and the second layer A1' may include substantially the same material. However, the present invention is not limited thereto, and in another embodiment, the fourth layer A3 and the second layer A1' may include different materials.
[0142] In an embodiment, the fifth layer T2' may include a metal. In an embodiment, the fifth layer T2' may include titanium. However, the present invention is not limited thereto, and in another embodiment, the fifth layer T2' may include other types of metals, such as tungsten, copper, nickel, or chromium, etc.
[0143] In an embodiment, the proportion of nickel in the aluminum alloy included in the second layer A1' of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. In an embodiment, the proportion of neodymium in the aluminum alloy included in the second layer A1' of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. In an embodiment, the proportion of lanthanum in the aluminum alloy included in the second layer A1' of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage.
[0144] In an embodiment, the proportion of nickel in the aluminum alloy included in the fourth layer A3 of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. In an embodiment, the proportion of neodymium in the aluminum alloy included in the fourth layer A3 of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage. In an embodiment, the proportion of lanthanum in the aluminum alloy included in the fourth layer A3 of the connecting electrode LS' may be equal to or greater than about 0.02 atomic percentage and equal to or less than about 0.05 atomic percentage.
[0145] In an embodiment, the thickness W2 of the second layer A1' of the connecting electrode LS' may be equal to or greater than about 2000 angstroms and equal to or less than about 3000 angstroms. In an embodiment, the thickness W3 of the fourth layer A3 of the connecting electrode LS' may be equal to or greater than about 2000 angstroms and equal to or less than about 3000 angstroms.
[0146] In an embodiment, the thickness W3 of the fourth layer A3 and the thickness W2 of the second layer A1' may be substantially the same. However, the present invention is not limited thereto, and in another embodiment, the thickness W3 of the fourth layer A3 and the thickness W2 of the second layer A1' may be different.
[0147] The present invention can be applied to various display devices. For example, the present invention is suitable for various display devices, such as display devices for vehicles, ships, and aircraft, display devices for portable communication devices, display devices for exhibitions or information transmission, and medical display devices, etc.
[0148] The foregoing is an illustration of embodiments of the present invention and is not to be construed as a limitation of the present invention. Although several embodiments have been described, those skilled in the art will readily recognize that many modifications can be made to the present invention without departing from the new teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention. Therefore, it should be understood that the foregoing is an illustration of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the present invention. Moreover, without departing from the scope of the present invention, embodiments or parts of embodiments can be combined in whole or in part.
Claims
1. A display device, comprising: a first base substrate including a display area in which pixels are disposed and a pad area spaced apart from the display area; an intermediate metal layer, disposed on the first base substrate; a second base substrate, disposed on the intermediate metal layer; a chip on film in contact with the intermediate metal layer in the pad region; as well as A connection electrode is provided on the second base substrate, contacts the intermediate metal layer in the pad region, and includes a first layer including an aluminum alloy and a second layer provided on the first layer and including aluminum. 2 . The display device according to claim 1 , wherein the aluminum alloy contained in the first layer contains nickel. 3 . The display device according to claim 2 , wherein the aluminum alloy contained in the first layer further contains neodymium. The display device according to claim 3 , wherein the aluminum alloy contained in the first layer further contains lanthanum. 5 . The display device according to claim 4 , wherein a ratio of the nickel in the aluminum alloy included in the first layer is equal to or greater than 0.02 atomic % and equal to or less than 0.05 atomic %. 6 . The display device according to claim 4 , wherein a ratio of the neodymium in the aluminum alloy contained in the first layer is equal to or greater than 0.02 atomic % and equal to or less than 0.05 atomic %. 7 . The display device according to claim 4 , wherein a ratio of the lanthanum in the aluminum alloy contained in the first layer is equal to or greater than 0.02 atomic % and equal to or less than 0.05 atomic %. 8 . The display device according to claim 1 , wherein a thickness of the first layer is equal to or greater than 3000 angstroms and equal to or less than 4000 angstroms.
9. The display device according to claim 1, wherein the connecting electrode further comprises: The third layer is disposed on the second layer and comprises an aluminum alloy. 10 . The display device according to claim 9 , wherein the aluminum alloy contained in the third layer of the connection electrode contains at least one of nickel, neodymium, and lanthanum.
11. The display device according to claim 10, wherein The proportion of the nickel in the aluminum alloy contained in the third layer of the connection electrode is equal to or greater than 0.02 atomic percent and equal to or less than 0.05 atomic percent, The ratio of the neodymium in the aluminum alloy contained in the third layer of the connection electrode is equal to or greater than 0.02 atomic percent and equal to or less than 0.05 atomic percent, and The ratio of the lanthanum in the aluminum alloy contained in the third layer of the connection electrode is equal to or greater than 0.02 atomic percent and equal to or less than 0.05 atomic percent. 12 . The display device according to claim 9 , wherein a thickness of each of the first layer and the third layer is equal to or greater than 2000 angstroms and equal to or less than 3000 angstroms.
13. The display device according to claim 1, wherein the connecting electrode further comprises: The fourth layer is disposed below the first layer and includes titanium.
14. The display device according to claim 13, wherein the connecting electrode further comprises: The fifth layer is disposed on the second layer and includes titanium.
15. The display device according to claim 1, wherein the first base substrate defines a first opening in a partial region of the pad region, and The chip-on-film contacts a lower surface of the intermediate metal layer in the first opening.
16. The display device according to claim 1, wherein each of the pixels comprises: an active layer, disposed on the second base substrate; A gate electrode, disposed on the active layer; A source electrode, disposed on the gate electrode; and a drain electrode disposed on the gate electrode and spaced apart from the source electrode, wherein The connection electrode, the source electrode and the drain electrode are arranged on the same layer. 17 . The display device according to claim 1 , wherein the connection electrode contacts an upper surface of the intermediate metal layer.
18. The display device of claim 1, wherein the second base substrate comprises polyimide. 19 . The display device of claim 18 , wherein the first base substrate and the second base substrate include the same material.
20. The display device according to claim 1, wherein the second base substrate defines a second opening, and The connection electrode contacts the intermediate metal layer in the second opening.