A local layout routing method based on sequential value correction and history-guided search

Abstract

The application relates to the technical field of electronic design automation, in particular to a local layout wiring method based on sequential value correction and historical guidance search, which comprises the following steps: calling a multi-source dynamic sequential value wave diffusion path search sub-algorithm, generating initial paths for all line networks, and initializing a historical solution set and a current solution sequence; performing random disturbance based on the current solution sequence, and generating a candidate solution; judging whether the candidate solution meets design rule constraints; checking whether a maximum iteration number or an improvement number limit is reached, if yes, entering the step of outputting an optimal solution, otherwise returning to the step of generating the candidate solution; selecting a wiring path with an optimal target function value and meeting all constraints from the historical solution set, and outputting a final result; the local layout wiring method based on sequential value correction and historical guidance search can solve problems such as high-density area wiring feasibility, complex design rule meeting, multi-target optimization and calculation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a local layout routing method based on sequential value correction and historical guidance search. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, the integration and complexity of chips grow exponentially, making chip routing one of the most challenging key problems in the field of modern electronic design automation (EDA). Routing is not only a core step in the physical design process, but also directly determines the functionality, performance, power consumption and manufacturability of the chip. However, current routing techniques still face many technical difficulties in dealing with high integration, high complexity and strict design rules of chip design.

[0003] The chip routing process needs to meet the interconnection requirements of a large number of line networks, which increases dramatically with the shrinking of process nodes and the expansion of chip size. The rapid increase in the number of line networks brings great challenges to the allocation and optimization of routing resources. Specifically, in the core area of the chip, the line network density continues to rise, resulting in reduced routing feasibility and increasingly significant resource congestion problems. Existing routing algorithms are difficult to effectively avoid conflicts and resource waste between line networks in high-density areas, and are prone to open circuits with incomplete interconnections or short circuit problems due to congestion, thereby affecting the feasibility of the design and circuit performance. In addition, the complexity of design rules brought about by advanced manufacturing processes further increases the difficulty of routing. Modern chip manufacturing processes require routing to strictly follow a series of design rules, including minimum line width, minimum spacing, minimum area and other constraint conditions, to ensure high yield and high reliability of the chip in the manufacturing process. However, existing routing tools often struggle to balance between solving efficiency and rule constraint satisfaction when faced with complex design rules. Especially in high-density areas, routing tools may experience a significant increase in computational complexity, further slowing down the design cycle.

[0004] In addition, as the demand for EDA tools in actual chip design continues to increase, the computational efficiency of routing algorithms has become one of the key factors affecting the practicality of the tool. Under the premise of meeting design rules and optimization objectives, routing tools need to complete the layout and interconnection of a large number of line networks within a limited time. In particular, in modern chip design, the running efficiency of routing tools needs to keep pace with the increase in chip complexity. However, many current routing tools have insufficient running efficiency in actual design, especially in high-density and high-complexity scenarios, where routing time often exceeds acceptable limits, greatly limiting the practical application value of EDA tools.

[0005] In summary, the technical problems faced by the current chip routing field can be summarized as follows:

[0006] 1. High-density area routing feasibility problem: how to effectively solve the congestion of the line network, ensure the interconnection demand of the line network to be realized in the high-density area, and avoid the occurrence of open circuit and short circuit problems.

[0007] 2. Complex design rule satisfaction problem: how to reduce the computational complexity of routing while satisfying a large number of design rule constraints (such as minimum line width, minimum spacing, etc.), and improve the efficiency of routing solution.

[0008] 3. Multi-objective optimization problem: how to find a reasonable balance point among the optimization objectives such as total line length, signal delay, etc., to meet the needs of high-performance chip design.

[0009] 4. Computational efficiency problem: how to improve the running efficiency of the routing tool in chip design, so that it can complete the routing task within a limited time to adapt to the rapid iteration demand of modern chip design.

[0010] In summary, the problems faced by chip routing are essentially the multiple contradictions between high-density interconnection demand, complex design rules and optimization objectives. These problems are intertwined with each other, making it difficult for existing local routing algorithms to balance between precision, efficiency and adaptability. Especially in the high-density local routing scene, the algorithm needs to complete dynamic resource allocation, multi-objective trade-off and comprehensive optimization under strict rule constraints within a limited computing time, while the traditional method shows obvious limitations in handling high-complexity scenarios. Therefore, an innovative algorithm and system are urgently needed to efficiently solve the above technical problems and provide strong technical support for modern integrated circuit design. SUMMARY

[0011] The purpose of the present application is to propose a local layout routing method based on sequential value correction and historical guidance search, which can solve the problems of high-density area routing feasibility, complex design rule satisfaction, multi-objective optimization and computational efficiency, etc.

[0012] To achieve this purpose, the present application adopts the following technical solutions:

[0013] A local layout routing method based on sequential value correction and historical guidance search, comprising the following steps:

[0014] Initial solution generation: calling a multi-source dynamic sequential value wave diffusion path search sub-algorithm to generate initial paths for all line networks, and initializing a historical solution set and a current solution sequence;

[0015] Candidate solution generation: based on the current solution sequence, a random disturbance is generated to generate a disturbed solution sequence, and a multi-source dynamic sequential value wave diffusion path search sub-algorithm is called to re-plan the path to generate a candidate solution;

[0016] Candidate solution evaluation and historical solution update: Determine whether the candidate solution meets the design rule constraints. If it is valid, calculate its objective function value and compare it with the solutions in the historical solution set. Update the historical solution set and the current solution sequence according to the preset acceptance rules.

[0017] Termination condition judgment: Check whether the maximum number of iterations has been reached or there is no limit to the number of improvements. If the conditions are met, proceed to the step of outputting the optimal solution; otherwise, return to the step of generating candidate solutions.

[0018] Output the optimal solution: Select the wiring path with the optimal objective function value from the historical solution set that satisfies all constraints, and output the final result.

[0019] Preferably, the initial solution generation step specifically includes:

[0020] The multi-source dynamic sequential value wave diffusion path search sub-algorithm is used to plan the initial path for each wire network in turn, ensuring that the path meets the design rule constraints.

[0021] The historical solution set is initialized based on the objective function value of the initial solution. The historical solution set is a fixed-length historical window used to record the objective values ​​of candidate solutions during the iteration process.

[0022] Preferably, in the candidate solution generation step, the random perturbation strategy includes:

[0023] Adjust the routing priority of the network;

[0024] Randomly swap the connection order of the source or target points;

[0025] The current path is locally heuristically optimized and adjusted to generate diverse candidate solutions.

[0026] Preferably, in the steps of candidate solution evaluation and historical solution update, the candidate solution acceptance rule is as follows:

[0027] If the objective function value of a candidate solution is better than that of the current solution, then accept the current solution and update it.

[0028] If the objective function value of a candidate solution is worse than the current solution but better than the worst value in the historical solution set, then accept it and replace the oldest value in the historical solution set.

[0029] In other cases, candidate solutions are rejected, and the current solution is retained.

[0030] Preferably, the multi-source dynamic sequential value wave diffusion path search sub-algorithm includes the following sub-steps:

[0031] Initialize the order value matrix: dynamically adjust the order values ​​based on the grid point occupancy status, path diffusion effect, and layout diffusion effect;

[0032] The wave propagation process is simulated by a priority queue, and the optimal path is searched starting from multiple source points, with path backtracking information dynamically updated.

[0033] If the path reaches the target point, then backtrack to generate the complete path and update the set of wire connection requirements.

[0034] Preferably, the update rule for the ordered value matrix includes:

[0035] Occupied grid points are marked with the Occupied order value;

[0036] The regions affected by path diffusion are tagged with Path Influence order values;

[0037] The areas affected by the layout diffusion are marked with the Layout Influence order value.

[0038] Preferably, the design rule constraints include:

[0039] Minimum spacing and minimum line width constraints between paths;

[0040] Path continuity and no-crossing short-circuit constraints;

[0041] Uniqueness constraint for resource usage.

[0042] Preferably, the objective function value is a weighted sum of the total path length and wiring congestion, used to quantify the global optimization effect of path planning.

[0043] Preferably, the wave propagation path search process is accelerated by parallel computing, and dynamic resource allocation is implemented to avoid local congestion in real time.

[0044] Preferably, the output of the optimal solution needs to pass design rule checks and electrical rule checks to ensure the manufacturing feasibility and electrical performance of the wiring result.

[0045] The technical solution provided by this invention may include the following beneficial effects:

[0046] This invention systematically solves the congestion, rule conflicts, and efficiency problems in high-density wiring through dynamic order value correction, a history-guided search framework, and a multi-objective optimization mechanism. It improves the quality of the global solution, covering multiple dimensions such as wiring quality, computational efficiency, manufacturing feasibility, and electrical performance, while shortening wiring time to meet the rapid iteration requirements of modern chip design. Multi-source wave diffusion search quickly generates initial paths that satisfy design rules, reducing the computational burden of subsequent iterations. The history-guided search framework avoids getting trapped in local optima by perturbing and evaluating candidate solutions, thus improving the quality of the global solution. Termination condition judgment mechanisms, such as the maximum number of iterations, ensure that the algorithm outputs a feasible solution within a reasonable time, adapting to the needs of rapid iteration. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the overall algorithm flow of one embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the multi-source dynamic sequential value wave diffusion path search sub-algorithm of one embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram showing the layout information and port display of a layout with a number of 5 layouts according to an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram showing part of the running results of an embodiment of the present invention, connect_5.

[0051] Figure 5 This is a schematic diagram showing the partial running results of an embodiment of the present invention, case connect_10. Detailed Implementation

[0052] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In this specification, a wire network refers to a circuit network to be connected, and a path refers to a specific wiring trajectory.

[0053] The following is combined with Figures 1 to 5 This describes a local layout routing method based on sequence value correction and history guidance search according to an embodiment of the present invention.

[0054] A local layout routing method based on sequence value correction and history-guided search includes the following steps:

[0055] Initial solution generation: Invoke the multi-source dynamic sequential value wave diffusion path search sub-algorithm to generate initial paths for all wire meshes and initialize the historical solution set and the current solution sequence;

[0056] Candidate solution generation: Based on the current solution sequence, random perturbation is performed to generate a perturbed solution sequence, and the multi-source dynamic sequential value wave diffusion path search sub-algorithm is called to replan the path and generate candidate solutions;

[0057] Candidate solution evaluation and historical solution update: Determine whether the candidate solution meets the design rule constraints. If it is valid, calculate its objective function value and compare it with the solutions in the historical solution set. Update the historical solution set and the current solution sequence according to the preset acceptance rules.

[0058] Termination condition judgment: Check whether the maximum number of iterations has been reached or there is no limit to the number of improvements. If the conditions are met, proceed to the step of outputting the optimal solution; otherwise, return to the step of generating candidate solutions.

[0059] Output the optimal solution: Select the wiring path with the optimal objective function value from the historical solution set that satisfies all constraints, and output the final result.

[0060] This invention, through core steps such as initial solution generation, candidate solution generation, candidate solution evaluation and historical solution updating, termination condition judgment and optimal solution output, realizes dynamic order value correction, historical guidance search framework and multi-objective optimization mechanism, systematically solves the problems of congestion, rule conflict and efficiency in high-density wiring, improves the global solution quality, and can cover multiple dimensions such as wiring quality, computing efficiency, manufacturing feasibility and electrical performance, shorten wiring time and meet the rapid iteration requirements of modern chip design.

[0061] Efficient initial solution generation: Initial paths that meet design rules are quickly generated through multi-source wave diffusion search, reducing the computational burden of subsequent iterations.

[0062] Dynamic optimization capability: The history-guided search framework avoids getting stuck in local optima and improves the quality of the global solution by perturbing and evaluating candidate solutions.

[0063] High convergence efficiency: Termination condition judgment mechanism, such as maximum number of iterations, ensures that the algorithm outputs a feasible solution within a reasonable time and adapts to the needs of rapid iteration.

[0064] This invention achieves efficient wiring in constrained environments through several key technologies, with the following beneficial effects:

[0065] Dynamic Sequence Value Update and Resource Utilization Optimization: The algorithm of this invention implements a dynamic sequence value update mechanism. By adjusting the sequence value matrix of the grid in real time, it effectively avoids resource conflicts and local congestion problems in path planning. Whenever a path occupies certain grids, the algorithm can dynamically expand its influence range and update the sequence value, thereby providing reasonable guidance for subsequent path planning. This dynamic adjustment strategy based on sequence value correction significantly improves resource utilization efficiency.

[0066] Multi-source, multi-objective path planning capability: The algorithm of this invention employs a multi-source, multi-objective path search strategy, enabling it to quickly find the optimal path that satisfies the constraints within a local grid. By introducing various strategies (such as dynamically adjusting the path order and wave exploration), the algorithm can efficiently explore the global solution space, avoiding getting trapped in local optima. Especially in high-complexity connectivity scenarios, this invention demonstrates superior path planning capabilities.

[0067] Combining local perturbation with heuristic optimization: The algorithm implements an optimization strategy based on local perturbation. Through randomized perturbation operations and heuristic adjustments, it can continuously improve the routing quality based on the initial solution.

[0068] Comprehensive optimization based on design rules: This invention comprehensively considers multiple design rules such as line length and minimum spacing during the path planning process, and balances the conflicts between different objectives through an adaptive optimization method.

[0069] High Implementation and Operation Efficiency: This invention combines search efficiency with path planning capabilities through an optimization framework based on History Guided Search (HGS), enabling the rapid generation of high-quality routing results within a limited runtime. Experimental results demonstrate that the algorithm outperforms traditional methods in both solution speed and solution quality.

[0070] In summary, this invention, through its innovative locally detailed routing algorithm, effectively improves routing efficiency and quality, significantly reducing routing resource consumption and computational costs while meeting stringent design rules. This not only helps optimize chip design processes and shorten development cycles but also reduces failure rates and resource waste in chip manufacturing, providing strong support for the sustainable development of EDA tools. The technical solution of this invention possesses good versatility and flexibility.

[0071] Specifically, the initial solution generation step includes:

[0072] The multi-source dynamic sequential value wave diffusion path search sub-algorithm is used to plan the initial path for each wire network in turn, ensuring that the path meets the design rule constraints.

[0073] The historical solution set is initialized based on the objective function value of the initial solution. The historical solution set is a fixed-length historical window used to record the objective values ​​of candidate solutions during the iteration process.

[0074] By calling the sub-algorithm to plan the initial path and initialize the historical solution set, and limiting the specific implementation method of generating the initial solution, the historical solution set of fixed length can retain the recent optimization trend, avoid interference from outdated solutions, make the initial solution legal and reliable, reduce the invalid search in subsequent iterations, and at the same time improve the historical window to enhance the stability of the algorithm and avoid drastic fluctuations in the optimization process.

[0075] This step first calls the multi-source dynamic sequential value wave diffusion path search sub-algorithm to provide an initial solution for the history-guided search algorithm, and at the same time prepares the initial set of historical solutions and the current solution sequence for the history-guided search algorithm.

[0076] Using the path search sub-algorithm, an initial path is generated for each net that needs to be connected; a fixed-length history window is created to record previous objective function values, and the window is initially filled with the objective function values ​​of the initial solution; the generated initial solution is used as the current solution, and the current objective function value is recorded.

[0077] Preferably, in the candidate solution generation step, the random perturbation strategy includes:

[0078] Adjust the routing priority of the network;

[0079] Randomly swap the connection order of the source or target points;

[0080] The current path is locally heuristically optimized and adjusted to generate diverse candidate solutions.

[0081] Based on the current solution, the random perturbation strategy in generating constrained candidate solutions is optimized by adjusting the wiring order, changing the starting and ending point sets of each connection, and exchanging the connection order. For the solution sequence after perturbation, a path search sub-algorithm is used to replan the path. The path search sub-algorithm dynamically adjusts the order values, such as the path diffusion order value and the layout diffusion order value, to ensure that the new path avoids high order value regions as much as possible. The perturbation strategy generates diverse candidate solutions by changing the net priority or adjusting local paths, which can take into account the diversity of solutions and the potential for local optimization, thereby breaking local optima, expanding the solution space, and improving the robustness of the algorithm in high-complexity scenarios. The evaluation of candidate solutions first determines whether they are valid, such as whether there are any missing paths and whether they meet the various constraints in the mathematical model. If they are not valid, they are discarded in the next step. If they are valid, the objective function value of the candidate solution is calculated, such as the total path length, and the next step considers whether to update the historical solution set.

[0082] Specifically, in the steps of candidate solution evaluation and historical solution update, the candidate solution acceptance rule is as follows:

[0083] If the objective function value of a candidate solution is better than that of the current solution, then accept the current solution and update it.

[0084] If the objective function value of a candidate solution is worse than the current solution but better than the worst value in the historical solution set, then accept it and replace the oldest value in the historical solution set.

[0085] In other cases, candidate solutions are rejected, and the current solution is retained.

[0086] Based on the candidate solution acceptance rules of the history-guided search algorithm, it is determined whether to accept a candidate solution and update the historical solution set and the current solution sequence. The current solution is updated based on the comparison between the objective function value and the historical solution set. This process determines the candidate solution acceptance rules, enabling dynamic acceptance thresholds. It allows some suboptimal solutions to enter the historical set, preserving potential optimization directions, accelerating convergence, avoiding stagnation, and improving the algorithm's adaptability to complex constraints.

[0087] The pseudocode for the history-guided search algorithm is as follows:

[0088] Generate an initial solution s;

[0089] Calculate the objective function value C(s) of the initial solution;

[0090] Specify the historical length \(L_h\);

[0091] Initialize the historical array \(f_k\), and set the values of all \(k\in\{0,\cdots,L_h - 1\}\) to \(C(s)\);

[0092] Set the iteration counter to \(I = 0\);

[0093] When the termination condition is not met, repeat the following steps:

[0094] Construct a candidate solution \(s^*\);

[0095] Calculate the objective function value \(C(s^*)\) of the candidate solution;

[0096] If \(C(s^*)<f[I\bmod L_h]\) or \(C(s^*)<C(s)\): Accept the candidate solution: \(s = s^*\);

[0097] Otherwise: 12. Reject the candidate solution: \(s = s\);

[0098] Update the historical array: \(f[I\bmod L_h]:=C(s)\);

[0099] Increment the iteration counter by 1: \(I = I + 1\);

[0100] Return the optimal solution found.

[0101] Preferably, the multi-source dynamic sequential value wave diffusion path search sub-algorithm includes the following sub-steps:

[0102] Initialize the sequential value matrix: Dynamically adjust the sequential value according to the occupancy status of grid points, path diffusion influence, and layout diffusion influence;

[0103] Simulate the wave diffusion process through a priority queue, search for the optimal path starting from multiple source points, and dynamically update the path backtracking information;

[0104] If the path reaches the target point, backtrack to generate the complete path and update the net connection requirement set.

[0105] Implement the multi-source dynamic sequential value wave diffusion path search sub-algorithm through sequential value initialization, wave diffusion search, and path backtracking. Achieve efficient path exploration through a priority queue, simulate the wavefront propagation process, quickly generate feasible paths, reduce the computational overhead, and the dynamic sequential value can guide the path to avoid conflict areas and reduce the congestion risk.

[0106] In the loop, the head element is continuously popped from the queue, and adjacent network points are processed; this step is the wave diffusion process. The diffused neighboring nodes are pushed to the tail of the queue, and this process is repeated continuously. The entire path search process resembles wave diffusion, simulating the process of a wave spreading outward from the starting point, while dynamically adjusting the order values ​​of the grid points to gradually explore and find the optimal path from multiple starting points to the target point. The specific implementation process is as follows:

[0107] Initialize the net connection requirement set: Initialize all net pairs to be connected, i.e., the source point set and the end point set, and store these net requirements as a set for subsequent processing.

[0108] Update source and destination sets: If this is the first update of source and destination sets, initialize the source and destination sets and use the corresponding ports of the layout as source and destination sets according to routing requirements and the current solution sequence after perturbation. If this is a subsequent iterative process, add the path point set found in each search to the destination set so that other source points can achieve multi-source connection routing in this iterative search process, instead of each source point having to connect only to the initial destination. If the source point connects to the original path during wave propagation, multi-source routing connection can be achieved.

[0109] Check if the set is empty: If the set of net connection requirements is empty, it means that all nets have been successfully connected, the algorithm ends, and the final path set is output. If the set is not empty, proceed to the next step and continue processing the currently incomplete net connection requirements.

[0110] Initialize the order value matrix and priority queue:

[0111] Initialize the point weight map: Set the order value of each point in the grid, including: marking occupied grid points as Occupied, setting the influence area of ​​path diffusion as Path Influence, and setting the influence area of ​​layout diffusion as Layout Influence. Ensure that the state of each point in the grid is correct for the search algorithm to process.

[0112] Initialize priority queue: Add all source nodes in the current wire connection requirement to the priority queue. The initial element of the priority queue is (total source node cost, source node coordinates).

[0113] Check if the queue is empty: If the priority queue is empty and there are unmet nets, it means that no feasible path can be found for the current net requirement. In this case, output an error message indicating that no valid connection path was found for the current path, return to the error status to end the sub-algorithm, and hand it over to the main algorithm for evaluating candidate solutions.

[0114] If the priority queue is not empty, pop the head element from the queue and proceed to the next step.

[0115] Determine if the target point is the endpoint: Check if the current point (x, y) belongs to the target point set. If it is the endpoint, perform path backtracking, construct a complete path from the source point to the endpoint, add the path to the final path set, update the net connection requirement set, delete the nets that have been connected, return to the main loop, and process the next net requirement. If it is not the endpoint, proceed to the next step and process the adjacent nets of the current point, that is, explore the adjacent net points.

[0116] Processing adjacent network points: Traverse all adjacent grid points (nx, ny) of the current point (x, y). Point (nx, ny) is the point explored one grid in each direction (up, down, left, right) from point (x, y). If (nx, ny) is a valid point (not out of bounds, not an obstacle, not occupied), calculate the new total cost: new_dist = dist[x][y] * order_values[nx][ny]. If new_dist is better than the currently recorded optimal total cost, update dist[nx][ny] = new_dist, and record the current point (x, y) as the parent node of the adjacent point (nx, ny): parent[nx][ny] = (x, y). The parent node represents the path direction from the current point (x, y) to the adjacent point (nx, ny). This step of recording the parent node is convenient for finding the parent node during subsequent path backtracking until a complete path is found. Add (new_dist, nx, ny) to the priority queue for subsequent processing.

[0117] Store at the tail of the queue: Store the processed adjacent points at the tail of the priority queue according to the calculated cost, so that other grid points can be searched. Return to the priority queue and repeat the process for the next grid point until the corresponding conditions are met.

[0118] Path backtracking: When the target point is successfully found, the path is constructed by backtracking from the endpoint to the starting point according to the parent matrix, and each point of the path is stored in the final path set.

[0119] Specifically, the update rules for the ordered value matrix include:

[0120] Occupied grid points are marked with the Occupied order value;

[0121] The regions affected by path diffusion are tagged with Path Influence order values;

[0122] The areas affected by the layout diffusion are marked with the Layout Influence order value.

[0123] By differentiating between direct occupation, path diffusion impact, and map diffusion impact, dynamic order values ​​are layered, path selection is precisely controlled, minimum spacing and line width constraints are strictly met, resource occupancy status is perceived in real time, and short-circuit and open-circuit problems are avoided.

[0124] The update rules for the order value matrix include three types of order values. Setting these three types of order values ​​will cause the path search direction to differ under different circumstances. Occupied grid points should obviously be avoided during path search; setting a maximum order value will have a penalty-like effect. If a path traverses an occupied grid point, the total cost will become particularly high, and the searched path will tend to avoid occupied grid points. Similarly, the setting of the Path Influence order value is similar to that of the Layout Influence order value. If a path traverses a point, its total order value will be relatively low compared to the total order values ​​for traversing other points, and it will not be prioritized for that path point. This will cause the path to avoid the influence areas of other path diffusion and the influence areas of layout diffusion as much as possible, in order to meet the minimum spacing requirements between paths and between paths and layout obstacles.

[0125] Preferably, the design rule constraints include:

[0126] Minimum spacing and minimum line width constraints between paths;

[0127] Path continuity and no-crossing short-circuit constraints;

[0128] Uniqueness constraint for resource usage.

[0129] By controlling the spacing and linewidth between paths, process constraints are achieved, short circuits between wires or devices at different potentials are avoided, and overlap between routing paths and the layout or other parts of the layout (such as devices, wells, isolation areas, etc.) is prevented. All these factors are incorporated into the optimization objectives, and multi-dimensional rules are integrated to ensure that the routing results meet manufacturing process requirements. This also reduces signal delay and power consumption, and improves chip performance.

[0130] Specifically, the objective function value is a weighted sum of the total path length and wiring congestion, used to quantify the global optimization effect of path planning.

[0131] The algorithm employs a weighted and multi-objective approach to optimize the total path length and cabling congestion. Under the premise of satisfying design rule constraints, cabling resource constraints, and path feasibility constraints, the algorithm achieves the optimization objectives of minimizing the total path length and cabling congestion, balances the conflicting demands of line length and congestion rate, avoids resource allocation imbalance caused by single optimization, provides clear evaluation criteria, and enhances the controllability of the algorithm.

[0132] Preferably, the wave propagation path search process is accelerated by parallel computing, and dynamic resource allocation is implemented to avoid local congestion in real time.

[0133] Parallel optimization is used to improve search efficiency, multi-threaded processing of grid point exploration shortens path planning time, which can significantly improve the computational efficiency of large-scale cabling scenarios, and dynamic resource allocation can alleviate local congestion in real time.

[0134] Specifically, the output of the optimal solution needs to pass the Design Rule Check (DRC) and Electrical Rule Check (ERC) to ensure the manufacturing feasibility and electrical performance of the wiring result.

[0135] Embedding rule checks into the algorithm output steps ensures the practical feasibility of the solution, reduces the risk of chip manufacturing failure, and improves the electrical reliability and signal integrity of the wiring results.

[0136] Connection information (Connect) input example description:

[0137] The connectivity information describes the multiple source and destination points that need to be interconnected in the cabling task. To comprehensively demonstrate the algorithm's performance under different connectivity scales, several representative connectivity information cases were selected, including cases with 5, 10, 20, 30, 40, and 50 connections.

[0138] (1) Overview of Connection Files: For ease of understanding and presentation, the basic structure and characteristics of all connection files (connect_5 to connect_50) are summarized in the table below.

[0139]

[0140] Table 1 Overview of Link File Information

[0141] (2) Example of a specific connection file: In order to show the connection information more intuitively, the following shows the specific connection information for a connection with a number of 5 (connect_5).

[0142]

[0143] Table 2 connect_5 Detailed Connection Information

[0144] Placement Information (Placement_Info) Input Example Description: The placement information details the overall scope of the routing area, design rules, and the specific location and structure of each module. Examples include placement information for layouts ranging from 5 to 45. The following is an example of placement information for layout 5.

[0145]

[0146] Table 3: Placement information for a layout of 5 pieces.

[0147] In the description of this specification, references to terms such as "embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0148] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A local layout routing method based on sequence value correction and history-guided search, characterized in that, Includes the following steps: Initial solution generation: Invoke the multi-source dynamic sequential value wave diffusion path search sub-algorithm to generate initial paths for all wire meshes and initialize the historical solution set and the current solution sequence; The multi-source dynamic sequential value wave diffusion path search sub-algorithm includes the following sub-steps: Initialize the order value matrix: dynamically adjust the order values ​​based on the grid point occupancy status, path diffusion effect, and layout diffusion effect; Initialize point weight map: Set the order value of each point in the grid, including: marked occupied grid points as Occupied order value, set the influence area of ​​path diffusion as Path Influence order value, and set the influence area of ​​layout diffusion as Layout Influence order value; The wave propagation process is simulated by a priority queue, and the optimal path is searched starting from multiple source points, with path backtracking information dynamically updated. If the path reaches the target point, backtrack to generate the complete path and update the set of wire connection requirements; Candidate solution generation: Based on the current solution sequence, random perturbation is performed to generate a perturbed solution sequence, and the multi-source dynamic sequential value wave diffusion path search sub-algorithm is called to replan the path and generate candidate solutions; Candidate solution evaluation and historical solution update: Determine whether the candidate solution meets the design rule constraints. If it is valid, calculate its objective function value and compare it with the solutions in the historical solution set. Update the historical solution set and the current solution sequence according to the preset acceptance rules. Termination condition judgment: Check whether the maximum number of iterations has been reached or there is no limit to the number of improvements. If the conditions are met, proceed to the step of outputting the optimal solution; otherwise, return to the step of generating candidate solutions. Output the optimal solution: Select the wiring path with the optimal objective function value from the historical solution set that satisfies all constraints, and output the final result.

2. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The steps for generating the initial solution specifically include: The multi-source dynamic sequential value wave diffusion path search sub-algorithm is used to plan the initial path for each wire network in turn, ensuring that the path meets the design rule constraints. The historical solution set is initialized based on the objective function value of the initial solution. The historical solution set is a fixed-length historical window used to record the objective values ​​of candidate solutions during the iteration process.

3. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, In the candidate solution generation step, the random perturbation strategy includes: Adjust the routing priority of the network; Randomly swap the connection order of the source or target points; The current path is locally heuristically optimized and adjusted to generate diverse candidate solutions.

4. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, In the steps of candidate solution evaluation and historical solution update, the candidate solution acceptance rule is as follows: If the objective function value of a candidate solution is better than that of the current solution, then accept the current solution and update it. If the objective function value of a candidate solution is worse than the current solution but better than the worst value in the historical solution set, then accept it and replace the oldest value in the historical solution set. In other cases, candidate solutions are rejected, and the current solution is retained.

5. A local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The update rules for the ordered value matrix include: Occupied grid points are marked with the Occupied order value; The regions affected by path diffusion are tagged with Path Influence order values; The areas affected by the layout diffusion are marked with the Layout Influence order value.

6. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The design rule constraints include: Minimum spacing and minimum line width constraints between paths; Path continuity and no-crossing short-circuit constraints; Uniqueness constraint for resource usage.

7. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The objective function value is a weighted sum of the total path length and wiring congestion, used to quantify the global optimization effect of path planning.

8. The local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The process of accelerating the wave propagation path search is accelerated by parallel computing, and dynamic resource allocation is implemented to avoid local congestion in real time.

9. A local layout routing method based on sequence value correction and history-guided search according to claim 1, characterized in that, The optimal solution must be checked by design rules and electrical rules to ensure the manufacturing feasibility and electrical performance of the wiring result.

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