Current equalization circuitry for folded branches of rail-to-rail input OTA with class AB output stages

Abstract

The invention relates to current equalization circuitry for folded branches of rail-to-rail input OTA with class AB output stages. Described herein is an operational transconductance amplifier (OTA) having a constant current source that provides a constant current to a node. The OTA includes two input pairs of transistors: a first pair provides a variable current based on a feedback voltage and an input voltage, and a second pair also absorbs the variable current based on the feedback voltage and the input voltage. The folded cascode arrangement includes two branches, one of which includes a Monicelli cell. A class AB output stage exists, and the input of the class AB output stage is connected to the two ends of the Monicheri unit. Further, the bias stage mirrors and scales the constant current to generate the control voltage. Within the folded cascode branches, the compensation transistors are controlled by these control voltages to ensure that the magnitudes of various variable currents provided and absorbed are equal, making the OTA independent of the input voltage.

Description

Technical Field

[0001] The present disclosure generally relates to operational transconductance amplifiers (OTAs), and more particularly to circuitry designed to achieve current equalization in a folded cascode branch of a rail-to-rail input OTA having a class-AB output stage. Background Art

[0002] Operational transconductance amplifiers (OTAs) are fundamental building blocks in analog integrated circuit design. Their ability to convert a differential voltage input into a current output makes them play important roles in various applications such as filters, oscillators, and analog signal processing chains. The rail-to-rail input capability in an OTA ensures that the amplifier can handle input signals spanning the entire power supply range (e.g., 0 to VDD), thereby providing greater design flexibility and broader applicability.

[0003] One of the popular topologies employed to achieve rail-to-rail input capability in OTA design is the folded cascode configuration. Compared to the basic OTA structure, the folded cascode OTA offers advantages such as improved linearity, increased output resistance, and better swing capability. However, when the input voltage approaches the rail limits, the current distribution within the folded cascode branch may vary. These variations can lead to non-linearity, offset voltage, and other undesirable anomalies in the behavior of the amplifier.

[0004] The known OTA 10 is now described with reference to FIG. 1. The OTA 10 includes a p-channel transistor M1, the source of the p-channel transistor M1 is connected to the supply node VDD, its drain is connected to the node N1, and its gate is coupled to the control signal ppol. In the OTA 10 described below, it is noted that the voltages ppol, npol, ncasc, and pcasc are generated outside the OTA 10 and are generally available in a system integrating such an OTA.

[0005] The first input pair 13 is formed by the following elements: a p-channel transistor MP0, the source of which is connected to the node N1, its drain is connected to the node C, and its gate is coupled to the feedback voltage VFB; and a p-channel transistor MP1, the source of which is connected to the node N1, its drain is connected to the node D, and its gate is coupled to the input voltage VIN. For simplicity, the condition that VIN is almost equal to VFB will be applied from now on, since this OTA is typically used in a closed-loop system.

[0006] The second input pair 14 is formed by the following elements: an n-channel transistor MN0, the drain of which is connected to the node A, its source is connected to the node N2, and its gate is coupled to the feedback voltage VFB; and an n-channel transistor MN1, the drain of which is connected to the node B, its source is connected to the node N2, and its gate is coupled to the input voltage VIN.

[0007] The current mirror is formed by the following components: an n-channel transistor M5, whose drain is connected to node N2, whose source is connected to ground, and whose gate is connected to node N3 and receives the tail voltage ntail; and an n-channel transistor M4, whose drain and gate are connected to node N3, and whose source is connected to ground.

[0008] The current splitting structure 12 is formed by the following components: a p-channel transistor M3, whose source is connected to node N1, whose drain is connected to node N3, and whose gate is connected to node N4; a p-channel transistor M2, whose source is connected to the power supply node VDD, whose drain is connected to node N4, and whose gate is connected to node N4; and an n-channel transistor MC0, whose drain is connected to node N4, whose source is connected to ground, and whose gate is connected to the control signal npol.

[0009] The folded cascode 17 is formed by the following components: a p-channel transistor M6, whose source is connected to the power supply node VDD, whose drain is connected to node A, and whose gate is coupled to the control signal ppol; a p-channel transistor M8, whose source is connected to node A, whose drain is connected to node N5, and whose gate is connected to the gate of p-channel transistor M9 and the control signal pcasc; an n-channel transistor M13, whose drain is connected to node N5, whose source is connected to node C, and whose gate is connected to the gate of n-channel transistor M12 and the control signal ncasc; an n-channel transistor M14, whose drain is connected to node C, whose source is connected to ground, and whose gate is connected to node N5; a p-channel transistor M7, whose source is connected to the power supply node VDD, whose drain is connected to node B, and whose gate is connected to the control signal ppol; a p-channel transistor M9, whose source is connected to node B, whose drain is connected to node N6, and whose gate is connected to the control signal pcasc; an n-channel transistor M12, whose drain is connected to node N6, whose source is connected to node D, and whose gate is connected to the gate of n-channel transistor M13 and the control signal ncasc; and an n-channel transistor M15, whose drain is connected to node D, whose source is connected to ground, and whose gate is connected to node N5.

[0010] The class-AB output stage 19 is formed by the following components: a p-channel transistor M16, whose source is connected to the power supply node VDD, whose drain is connected to the source of a p-channel transistor M17, and whose gate is connected to the gate of the p-channel transistor M7 and the control signal ppol; a p-channel transistor M17, whose source is connected to the drain of the p-channel transistor M16, whose drain is connected to the node N7, and whose gate is coupled to the control signal pcasc; and a Monticelli cell 18. The Monticelli cell 18 is formed by the following components: an n-channel transistor M11, whose drain is connected to the node N7, whose source is connected to the node N6, and whose gate is coupled to the node H; and a p-channel transistor M10, whose source is connected to the node N7, whose drain is connected to the node N6, and whose gate is coupled to the node J.

[0011] The class-AB output stage 19 further includes: an n-channel transistor M18, whose drain is connected to the node N6, whose source is connected to the drain of an n-channel transistor M19, and whose gate is coupled to the control signal ncasc; an n-channel transistor M19, whose drain is connected to the source of the n-channel transistor M18, whose source is connected to ground, and whose gate is coupled to the control signal npol; a p-channel transistor M21, whose source is connected to the power supply node VDD, whose drain is connected to the node NO, and whose gate is connected to the node N7; an n-channel transistor M20, whose drain is connected to the node NO, whose source is connected to ground, and whose gate is connected to the node N6; a p-channel transistor M34, whose source is connected to VDD, whose drain is connected to the node H, and whose gate is coupled to the control signal ppol; an n-channel transistor M32, whose drain and gate are connected to the node H, and whose source is connected to the gate and drain of an n-channel transistor M31; an n-channel transistor M31, whose drain and gate are connected to the source of the n-channel transistor M32, and whose source is connected to ground; a p-channel transistor M35 in a diode-coupled configuration, whose source is connected to VDD, and whose gate and drain are connected to the source of a p-channel transistor M36; a p-channel transistor M36 in a diode-coupled configuration, whose source is connected to the gate and drain of the p-channel transistor M35, and whose drain and gate are connected to the node J; and an n-channel transistor M33, whose drain is connected to the node J, whose source is connected to ground, and whose gate of M33 is coupled to the control signal npol.

[0012] A capacitor C2 is connected between the node NO and ground, and the output voltage Vout is formed across the capacitor C2. A resistor R0 and a capacitor C0 are connected in series between the node N7 and the node NO. A resistor R1 and a capacitor C1 are connected in series between the node N6 and the node NO.

[0013] In operation, the voltage VIN is the non-inverting input of the OTA 10 (e.g., the gates of transistors MP1 and MN1), and the feedback voltage VFB is the inverting input of the OTA 10 (e.g., the gates of transistors MP0 and MN0). The P-channel transistor M1 is controlled via the control signal ppol such that a constant current of magnitude 2I TI is supplied to node N1.

[0014] The control signal npol causes a constant current to be absorbed from N4 by MC0 and supplied by M2, thereby defining the voltage at node N4. M3 splits the current 2I supplied by M1 from node N1 TI into 2(I TI -x) and 2x. The portion 2(I TI -x) is further split into two equal-magnitude portions, namely, I TI -x flowing through MP0 and I TI -x flowing through MP1. The current portion 2x flows through M3 and is mirrored by M4 to M5 until it flows through MN0 and MN1. More specifically, the transistor MC0 is a tail current generator that absorbs the current read by the transistor M2. This arrangement generates a voltage at node N4 for controlling the gate of the transistor M3. Consider the case where VIN is close to ground; in this case, 2I TI will flow into transistors MP0 and MP1, so node N1 will follow VIN, and the voltage at node N1 will be low enough to force the transistor M3 to turn off, such that 2x = 0, and transistors MN0 and MN1 are also off under this condition. Now consider the case where VIN is close to VDD; in this case, 2I TI will flow into transistor M1, node N1 will follow the voltage at node N4, and the voltage at node N1 will be low enough to force transistors MP0 and MP1 to turn off, such that 2I TI will flow through transistor M3 and be mirrored by M4:M5 to MN0:MN1, such that 2x = 2I TI , and transistors MN0 and MN1 are on under this condition. The sizes of transistors MC0 and M2 are designed such that if VIN is close to VDD, then transistor M3 can absorb the current generated by transistor M1, such that this current essentially bypasses transistors MP0 and MP1.

[0015] Keeping this in mind, the arrangement of the n-channel transistor MC0, the structure M2:M3, and the current mirror M4:M5 allows differentiating where the current of magnitude 2I TI supplied to node N1 by the P-channel transistor M1 will flow. If VIN is low enough, then this current flows into input pair 13, and if VIN is high enough, then this current flows into input pair 14. If VIN is at some intermediate position between the low and high values, then the current 2ITI is split into two parts (2I TI -2x and 2x), where 2x can be larger or smaller depending on VIN.

[0016] For example, when VIN decreases and approaches 0, the value of x approaches 0, which is mathematically expressed as:

[0017]

[0018] When VIN is 0, a current of magnitude I TI thus flows into each of p-channel transistor MP0 and p-channel transistor MP1, while substantially no current flows through M3 and current mirror M4:M5.

[0019] Conversely, when VIN increases and approaches VDD, the value of x approaches I TI , which is mathematically expressed as:

[0020]

[0021] For VIN being VDD, a current of magnitude I TI thus flows into each of n-channel transistor MN0 and n-channel transistor MN1, while substantially no current flows into p-channel transistor MP0 and MP1.

[0022] Due to this current steering arrangement, the transconductance of OTA 10 is independent of the input voltage in the first order.

[0023] In the folded cascode 17, p-channel transistor M6 controlled via control signal ppol supplies a current of magnitude I TF to node A, but recalling that n-channel transistor MN0 draws a current of magnitude x from node A, such that the current supplied by p-channel transistor M8 to node N5 has a magnitude of I TF -x. Similarly, p-channel transistor M7 controlled via control signal ppol supplies a current of magnitude I TF to node B, but recalling that n-channel transistor MN1 draws a current of magnitude x from node B, such that the current supplied by p-channel transistor M9 to node N6 has a magnitude of I TF -x. N-channel transistor M13 controlled via control signal ncasc then supplies a current of magnitude I TF -x to node C, and similarly, n-channel transistor M12 controlled via control signal ncasc supplies a current of magnitude I TF -x to node D.

[0024] Since n-channel transistor M13 supplies a current of magnitude I TFa current of -x and since the p-channel transistor MP0 supplies a current of magnitude I to node C TI a current of -x, the magnitude of the current through the n-channel transistor M14 is I TF +I TI -2x. Similarly, since the n-channel transistor M12 supplies a current of magnitude I TF -x to node D and since the p-channel transistor MP1 supplies a current of magnitude I TI -x to node D, the magnitude of the current through the n-channel transistor M15 is I TF +I TI -2x.

[0025] Regarding the operation of the folded cascode 17, first consider the case where VIN has a value of 0. At this time, the n-channel transistor M13 supplies a current of magnitude I TF to node C, the n-channel transistor M12 supplies a current of magnitude I TF to node D, the p-channel transistor MP0 supplies a current of magnitude I TI to node C, and the p-channel transistor MP1 supplies a current of magnitude I TI to node D. Therefore, the current absorbed by the n-channel transistor M14 from node C is I TF +I TI , and the current absorbed by the n-channel transistor M15 from node D is I TF +I TI .

[0026] However, now consider the case where VIN has a value of VDD. At this time, the n-channel transistor M13 supplies a current of magnitude I TF -I TI to node C, the n-channel transistor M12 supplies a current of magnitude I TF -I TI to node D, the p-channel transistor MP0 does not supply current to node C and the p-channel transistor MP1 does not supply current to node D. Therefore, the current absorbed by the n-channel transistor M14 from node C is I TF -I TI and the current absorbed by the n-channel transistor M15 from node D is I TF -I TI .

[0027] Therefore, the bias current of the folded cascode 17 is input-dependent, which is undesirable because there may be some poles and zeros (in general, some singularities) at high frequencies that shift undesirably with the input, making the dynamic response of the OTA input-dependent. Additionally, the transconductance of the current mirror M14:M15 is input-dependent, resulting in an input-dependent input-referred M14:M15 mirror noise contribution. In other words, in terms of noise and singularities (e.g., poles and zeros), the OTA 10 behaves like three different OTAs depending on whether the input voltage is close to VDD, close to ground, or somewhere between VDD and ground.

[0028] In the output stage 19, the Monticelli cell 18 dynamically generates a static bias voltage at nodes N7 and N6 to control the bias currents of M21 and M20, thereby achieving low crossover distortion by keeping the output transistors M21 and M20 slightly on in the absence of an input signal. As the amplitude of the input signal rises, the Monticelli cell 18 modulates the gate voltages of these output transistors M21 and M20, thereby providing an adaptive driving capability. This provides a balanced operation between the push transistor M21 and the pull transistor M20, thereby equalizing their contributions during the transition. The Monticelli cell 18 provides thermal stability, dynamically adjusting the bias according to temperature changes. This results in a class-AB output that balances efficiency and linearity at the output node NO.

[0029] Note that here, the Monticelli cell 18 is located within a separate branch separate from the folded cascode 17 because the Monticelli cell operates using a constant current, and as explained, the folded cascode 17 does not provide a constant current. The use of such a separate branch consumes space and increases the complexity of the OTA 10 design.

[0030] Given the above disadvantages of the folded cascode 17 and the resulting disadvantages in biasing the Monticelli cell 18, further development in the field of OTAs is needed. Summary of the Invention

[0031] Disclosed herein is an operational transconductance amplifier (OTA) that includes a constant current source configured to provide a first constant current to a first node and a first input pair of transistors. The first input pair of transistors includes: a first input transistor coupled between the first node and a third folded branch node, the first input transistor being configured to provide a first variable current to the third folded branch node based on a feedback voltage; and a second input transistor coupled between the first node and a fourth folded branch node, the second input transistor being configured to provide a second variable current to the fourth folded branch node based on an input voltage. A tail current source absorbs a tail current from a second node.

[0032] The second input pair of the transistor includes: a third input transistor coupled between a first folded branch node and a second node, the third input transistor being configured to absorb a third variable current from the first folded branch node based on a feedback voltage; and a fourth input transistor coupled between a second folded branch node and the second node, the fourth input transistor being configured to absorb a fourth variable current from the second folded branch node based on an input voltage.

[0033] The folded cascode arrangement includes a first folded cascode branch coupled to the first folded branch node and the third folded branch node and a second folded cascode branch coupled to the second folded branch node and the fourth folded branch node, wherein the second folded cascode branch includes a Monticelli cell coupled between the second folded branch node and the fourth folded branch node. The class-AB output stage has an input coupled across the Monticelli cell.

[0034] The bias stage is configured to mirror and scale a first constant current and a tail current to generate first and second control voltages.

[0035] The folded cascode arrangement includes, within the first folded cascode branch: a first tail generator transistor controlled by the first control voltage for providing a fifth variable current to the first folded branch node, the magnitude of the fifth variable current being equal to the third variable current; and a second tail generator transistor controlled by the second control voltage for absorbing a sixth variable current from the third folded branch node, the magnitude of the sixth variable current being equal to the first variable current.

[0036] The folded cascode arrangement includes, within the second folded cascode branch: a third tail generator transistor controlled by the first control voltage for providing a seventh variable current to the second folded branch node, the magnitude of the seventh variable current being equal to the fourth variable current; and a fourth tail generator transistor controlled by the second control voltage for absorbing an eighth variable current from the fourth folded branch node, the magnitude of the eighth variable current being equal to the second variable current.

[0037] The tail current source can be a current mirror having a control node receiving a first control signal. The constant current source can have a control terminal receiving a second control signal.

[0038] The bias stage may include: a first bias transistor connected between a supply voltage node and a first compensation node in a diode-coupled arrangement; a second bias transistor connected between the first compensation node and ground, with the control terminal of the second bias transistor connected to the control node of a current mirror; a third bias transistor connected between the supply voltage node and a second compensation node, with the control terminal of the third bias transistor coupled to a second control signal; a fourth bias transistor connected between the second compensation node and ground, with the control terminal of the fourth bias transistor coupled to a first control signal; and a fifth bias transistor connected between the second compensation node and ground in a diode-coupled arrangement.

[0039] The constant current source may have a control terminal that receives the second control signal.

[0040] The folded cascode arrangement may further include, within a first folded cascode branch: a fifth tail generator transistor connected between the supply voltage node and a first folded branch node, the fifth tail generator transistor having a control terminal coupled to the second control signal; a first cascode transistor connected between the first folded branch node and a third cascode transistor, the first cascode transistor having a control terminal coupled to a first cascode control signal; a second cascode transistor connected between the first cascode transistor and the third cascode transistor, the second cascode transistor having a control terminal coupled to a third cascode control signal; a third cascode transistor connected between the second cascode transistor and a third folded branch node, the third cascode transistor having a control terminal coupled to a second cascode control signal; and a sixth tail generator transistor connected between the third folded branch node and ground, the sixth tail generator transistor having a control terminal coupled to the node between the second cascode transistor and the third cascode transistor.

[0041] The folded cascode arrangement may further include, within a second folded cascode branch: a seventh tail generator transistor connected between the supply voltage node and a second folded branch node, the seventh tail generator transistor having a control terminal coupled to the second control signal; a fourth cascode transistor connected between the second folded branch node and a Monticelli cell, the fourth cascode transistor having a control terminal coupled to the first cascode control signal; a fifth cascode transistor connected between the Monticelli cell and a fourth folded branch node, the fifth cascode transistor having a control terminal coupled to the second cascode control signal; and an eighth tail generator transistor connected between the fourth folded branch node and ground, the eighth tail generator transistor having a control terminal coupled to the node between the second cascode transistor and the third cascode transistor.

[0042] The first folded branch node can be connected to the source of the first cascode transistor, and the second folded branch node can be connected to the source of the fourth cascode transistor.

[0043] The folded cascode arrangement may further include a first chopper having first and second inputs and first and second outputs, the first chopper being configured to chop the voltages at the first and second inputs of the first chopper, a first output of the first chopper being connected to the drain of the first cascode transistor, and a second output of the first chopper being connected to the drain of the fourth cascode transistor.

[0044] The fifth tail generator transistor may have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The first tail generator transistor may have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper. The seventh tail generator transistor may have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper. The third tail generator transistor may have a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper.

[0045] The third folded branch node can be connected to the source of the third cascode transistor, and the fourth folded branch node can be connected to the source of the fifth cascode transistor.

[0046] The folded cascode arrangement may further include a second chopper having first and second inputs and first and second outputs, the second chopper being configured to chop the voltages at the first and second inputs of the second chopper, a first output of the second chopper being connected to the drains of the sixth and second tail generator transistors, and a second output of the second chopper being connected to the drains of the eighth and fourth tail generator transistors.

[0047] The third cascode transistor may have a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper. The fifth cascode transistor may have a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper.

[0048] The folded cascode arrangement may further include a first chopper having first and second inputs and first and second outputs, the first chopper being configured to chop the voltages at the first and second inputs of the first chopper, a first output of the first chopper being connected to the drain of the first cascode transistor, and a second output of the first chopper being connected to the fourth cascode transistor.

[0049] The fifth tail generator transistor may have a first conductive terminal connected to a supply voltage node and a second conductive terminal connected to a first input of the first chopper. The first tail generator transistor may have a first conductive terminal connected to a supply voltage node and a second conductive terminal connected to a first input of the first chopper. The seventh tail generator transistor may have a first conductive terminal connected to a supply voltage node and a second conductive terminal connected to a second input of the first chopper.

[0050] The third tail generator transistor may have a first conductive terminal connected to a supply voltage node and a second conductive terminal connected to a second input of the first chopper. The folded cascode arrangement may further include a second chopper having first and second inputs and first and second outputs, the second chopper being configured to chop the voltages at the first and second inputs of the second chopper, a first output of the second chopper being connected to the drains of the sixth tail generator transistor and the second tail generator transistor, and a second output of the second chopper being connected to the drains of the eighth tail generator transistor and the fourth tail generator transistor.

[0051] The third cascode transistor may have a first conductive terminal connected to the first cascode transistor and a second conductive terminal connected to a first input of the second chopper. The fifth cascode transistor may have a first conductive terminal connected to the Monticelli cell and a second conductive terminal connected to a second input of the second chopper.

[0052] The third chopper may be configured to chop the feedback voltage and the input voltage, provide the chopped feedback voltage to the control terminals of the first input transistor and the third input transistor, and provide the chopped input voltage to the control terminals of the second input transistor and the fourth input transistor.

[0053] A constant current source may have a control terminal that receives a second control signal. The class-AB output stage may include: a first input coupled to a first output terminal of a Monticelli cell; a second input coupled to a second output terminal of the Monticelli cell; a first output transistor connected between a power supply node and an output node, the first output transistor having a control terminal connected to the first input; a second output transistor connected between the output node and ground, the second output transistor having a control terminal connected to the second input; a third output transistor connected between the power supply node and a fourth output transistor, the third output transistor having a control terminal connected to the second control signal; a fourth output transistor connected in a diode-coupled configuration between the third output transistor and the first input of the Monticelli cell; a fifth output transistor connected in a diode-coupled configuration between the fourth output transistor and ground; a sixth output transistor connected in a diode-coupled configuration between the power supply node and a seventh output transistor; a seventh output transistor connected in a diode-coupled configuration between the sixth output transistor and the second input of the Monticelli cell; and an eighth output transistor connected between the second input of the Monticelli cell and ground.

[0054] The Monticelli cell may include: a first transistor connected between the first output terminal and the second output terminal, wherein the first transistor has a control terminal connected to the control terminal of the fourth output transistor; and a second transistor connected between the first output terminal and the second output terminal, wherein the second transistor has a control terminal connected to the control terminal of the seventh output transistor.

[0055] The class-AB output stage may include: a first resistor and a first capacitor connected in series between the first output terminal of the Monticelli cell and the output node; and a second resistor and a second capacitor connected in series between the second output terminal of the Monticelli cell and the output node.

[0056] The class-AB output stage may include: a first capacitor connected in series between a second folded branch node and the output node; and a second capacitor connected in series between a fourth folded branch node and the output node. Description of the Drawings

[0057] FIG. 1 is a schematic diagram of a prior art operational transconductance amplifier (OTA).

[0058] Figure 2 is a schematic diagram of a first embodiment of the OTA disclosed herein.

[0059] Figure 3 is a schematic diagram of a second embodiment of the OTA disclosed herein.

[0060] Figure 4 It is a schematic diagram of the third embodiment of the OTA disclosed in this article.

[0061] Figure 5 It is a schematic diagram of the fourth embodiment of the OTA disclosed in this article. Detailed implementation manners

[0062] The following disclosure enables those skilled in the art to manufacture and use the subject matter described herein. Without departing from the spirit and scope of this disclosure, the general principles outlined in this disclosure can be applied to embodiments and applications other than those detailed above. It is not intended to limit this disclosure to the embodiments shown, but rather to give it the broadest scope consistent with the principles and features disclosed or suggested herein.

[0063] Note that in the following description, unless otherwise stated, any resistor or resistance mentioned is a discrete device, not just an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between these two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitance mentioned is a discrete device, not a parasitic element, unless otherwise stated. In addition, unless otherwise stated, any inductor or inductance mentioned is a discrete device, not a parasitic element, unless otherwise stated.

[0064] Now refer to Figure 2 Describe an improved OTA 20 with a folded cascode configuration. The OTA 20 includes a p-channel transistor M1, the source of the p-channel transistor M1 is connected to the power supply node VDD, its drain is connected to the node N1, and its gate is coupled to the control signal ppol.

[0065] The first input pair 13 is formed by the following elements: a p-channel transistor MP0, the source of which is connected to the node N1, its drain is connected to the node C, and its gate is coupled to the feedback voltage VFB; and a p-channel transistor MP1, the source of which is connected to the node N1, its drain is connected to the node D, and its gate is coupled to the input voltage VIN. For simplicity, from now on, the condition that VIN is almost equal to VFB will be applied, because this OTA is usually used in a closed-loop system.

[0066] The second input pair 14 is formed by the following elements: an n-channel transistor MN0, the drain of which is connected to the node A, its source is connected to the node N2, and its gate is coupled to the feedback voltage VFB; and an n-channel transistor MN1, the drain of which is connected to the node B, its source is connected to the node N2, and its gate is coupled to the input voltage VIN.

[0067] The current mirror is formed by the following components: an n-channel transistor M5, whose drain is connected to node N2, whose source is connected to ground, and whose gate is connected to node N3 and receives the tail voltage ntail; and an n-channel transistor M4, whose drain and gate are connected to node ntail, and whose source is connected to ground.

[0068] The current splitting structure 12 is formed by the following components: a p-channel transistor M3, whose source is connected to node N1, whose drain is connected to node N3, and whose gate is connected to node N4; a p-channel transistor M2, whose source is connected to the supply node VDD, whose drain is connected to node N4, and whose gate is connected to node N4; and an n-channel transistor MC0, whose drain is connected to node N4, whose source is connected to ground, and whose gate is connected to the control signal npol.

[0069] The bias stage 21 includes: a p-channel transistor M30, whose source is connected to the supply node VDD, and whose drain and gate are connected to node F; an n-channel transistor M29, whose drain is connected to node F, whose source is connected to ground, and whose gate is coupled to the control voltage ntail; a p-channel transistor M27, whose source is connected to the supply node VDD, whose drain is connected to node E, and whose gate is coupled to the control voltage ppol; an n-channel transistor M28, whose drain is connected to node E, whose source is connected to ground, and whose gate is coupled to the control voltage ntail; and an n-channel transistor M26 with a diode coupling between node E and ground, whose drain and gate are connected to node E and whose source is connected to ground.

[0070] The folded cascode 17 is formed by the following components: a p-channel transistor M6, whose source is connected to the power supply node VDD, whose drain is connected to the node A, and whose gate is coupled to the control signal ppol; a p-channel transistor M24, whose source is connected to the power supply node VDD, whose drain is connected to the node A, and whose gate is coupled to the node F; a p-channel transistor M8, whose source is connected to the node A, whose drain is connected to the source of the p-channel transistor M37, and whose gate is connected to the gate of the p-channel transistor M9 and the control signal pcasc; a p-channel transistor M37, whose source is connected to the drain of the p-channel transistor M8, whose drain is connected to the node N5, and whose gate is connected to the node J; an n-channel transistor M13, whose drain is connected to the node N5, whose source is connected to the node C, and whose gate is connected to the gate of the n-channel transistor M12 and the control signal ncasc; an n-channel transistor M14, whose drain is connected to the node C, whose source is connected to the ground, and whose gate is connected to the node N5; an n-channel transistor M23, whose drain is connected to the node C, whose source is connected to the ground, and whose gate is coupled to the node E; a p-channel transistor M7, whose source is connected to the power supply node VDD, whose drain is connected to the node B, and whose gate is connected to the control signal ppol; a p-channel transistor M25, whose source is connected to the power supply node VDD, whose drain is connected to the node B, and whose gate is coupled to the node F; and a p-channel transistor M9, whose source is connected to the node B, whose drain is connected to the node N7, and whose gate is connected to the gate of the p-channel transistor M8 and the control signal pcasc.

[0071] The folded cascode 17 further includes a Monticelli cell 18, which is formed by the following components: an n-channel transistor M11, whose drain is connected to the node N7, whose source is connected to the node N6, and whose gate is coupled to the node H; and a p-channel transistor M10, whose source is connected to the node N7, whose drain is connected to the node N6, and whose gate is coupled to the node J.

[0072] The folded cascode 17 further includes: an n-channel transistor M12, whose drain is connected to the node N6, whose source is connected to the node D, and whose gate is connected to the gate of the n-channel transistor M13 and the control signal ncasc; an n-channel transistor M15, whose drain is connected to the node D, whose source is connected to the ground, and whose gate is connected to the node N5; and an n-channel transistor M22, whose drain is connected to the node D, whose source is connected to the ground, and whose gate is coupled to the node E.

[0073] The AB - class output stage 19 includes: a p - channel transistor M21, whose source is connected to the supply node VDD, whose drain is connected to the node NO, and whose gate is connected to the node N7; an n - channel transistor M20, whose drain is connected to the node NO, whose source is connected to ground, and whose gate is connected to the node N6; a p - channel transistor M34, whose source is connected to the supply voltage VDD, whose drain is connected to the node H, and whose gate is coupled to the control signal ppol; a diode - coupled n - channel transistor M32, whose drain and gate are connected to the node H, and whose source is connected to the drain and gate of an n - channel transistor M31; a diode - coupled n - channel transistor M31, whose drain and gate are connected to the source of the n - channel transistor M32, and whose source is connected to ground; a diode - coupled p - channel transistor M35, whose source is connected to the supply voltage VDD, and whose drain and gate are connected to the source of a p - channel transistor M36; a diode - coupled p - channel transistor M36, whose source is connected to the drain and gate of the transistor M35, and whose drain and gate are connected to the node J; and an n - channel transistor M33, whose drain is connected to the node J, whose source is connected to ground, and whose gate is coupled to the control voltage npol.

[0074] The resistor R0 and the capacitor C0 are connected in series between the node N7 and the node NO. The resistor R1 and the capacitor C1 are connected in series between the node N6 and the node NO.

[0075] The operation is now described. In operation, the voltage VIN is at the non - inverting input of the OTA 20 (e.g., the gates of the transistors MP1 and MN1), and the feedback voltage VFB is at the inverting input of the OTA 20 (e.g., the gates of the transistors MP0 and MN0). The p - channel transistor M1 is controlled via the control signal ppol such that a constant current of magnitude 2I TI is supplied to the node N1.

[0076] The control signal npol causes a constant current to be absorbed from N4 and provided by M2, thereby defining the voltage at the node N4. M3 splits the current provided by M1 from the node N1 into a portion of magnitude 2(I TI - x), where I TI - x flows through MP0 and I TI - x flows through MP1, and another portion 2x flows through M3 and is mirrored by M4 to M5 until it flows through MN0 and MN1.

[0077] In the bias stage 21, a current of magnitude 2I TI provided by the p - channel transistor M1 is copied to the p - channel transistor M27 with a scaling factor of 1 / N, such that the p - channel transistor M27 supplies a current of magnitude 2I TIThe current of / N. Similarly, the control signal ntail causes a current of magnitude 2x to be absorbed from N2, and this current is replicated to the n-channel transistor M28 with a scaling factor of 1 / N, such that the n-channel transistor M28 absorbs a current of magnitude 2x / N from node E. Thus, since the p-channel transistor M27 supplies a current of magnitude 2I TI / N to node E and the n-channel transistor M28 absorbs a current of magnitude 2x / N from node E, the difference between the two currents equal to 2I TI / N - 2x / N is forced to flow through M26, thereby setting the voltage at node E. Additionally, the current of magnitude 2x absorbed from node N2 by the n-channel transistor M5 is replicated to the n-channel transistor M29 and scaled by a factor of 1 / N, such that the n-channel transistor M29 absorbs a current of magnitude 2x / N from node F. Additionally, the diode-coupled transistor M30 supplies a current of magnitude 2x / N to node F, thereby setting the voltage at node F.

[0078] In the folded cascode 17, the p-channel transistor M6 controlled via the control signal ppol supplies a current of magnitude I TF to node A, and the p-channel transistor M24 under the control of the voltage at node F mirrors the current supplied by the p-channel transistor M30 to node F with a scaling factor of N / 2, supplying a current of magnitude x to node A. The n-channel transistor MN0 absorbs a current of magnitude x from node A, and the p-channel transistors M8 and M37 controlled by the voltages at nodes pcasc and J respectively cause a constant current of magnitude I TF and supply it to node N5. The n-channel transistor M13 controlled via the control signal ncasc then supplies a current of magnitude I TF to node C. The p-channel transistor MP0 supplies a current of magnitude I TI -x to node C. The n-channel transistor M23 under the control of the voltage at node E mirrors the current absorbed by the n-channel transistor M26 from node E with a scaling factor of N / 2, absorbing a current of magnitude I TI -x from node C. Thus, the n-channel transistor M14 absorbs a current of magnitude I TF from node C.

[0079] Similarly, the p-channel transistor M7 controlled via the control signal ppol supplies a current of magnitude I TF to node B, and the p-channel transistor M25 under the control of the voltage at node F mirrors the current supplied by the p-channel transistor M30 to node F with a scaling factor of N / 2, supplying a current of magnitude x to node B. The n-channel transistor MN1 absorbs a current of magnitude x from node B, such that the current supplied by the p-channel transistor M9 to node N7 has a magnitude ITF . The Monticelli cell 18 then supplies a current of magnitude I to node N6 under the control of the voltages at nodes H and J. TF . The N-channel transistor M12, which is controlled via the control signal ncasc, then supplies a current of magnitude I to node D. TF . The P-channel transistor MP1 supplies a current of magnitude I TI -x to node D. The N-channel transistor M22, under the control of the voltage at node E, mirrors the current absorbed by the n-channel transistor M26 from node E with a scaling factor of N / 2, absorbing a current of magnitude I TI -x from node D. Thus, the n-channel transistor M15 absorbs a current of magnitude I TF from node D.

[0080] Considering the case where the value of VIN is 0, the result is that x is 0. At this time, the n-channel transistor M13 supplies a current of magnitude I TF to node C. Since the n-channel transistor M23 absorbs a current of magnitude I TI from node C to match the current of magnitude I TI supplied by the p-channel transistor MP0 to node C, the current absorbed by the n-channel M14 from node C when x is 0 has a magnitude of I TF , rather than I TF +I TI in the prior art design of FIG. 1. Similarly, the n-channel transistor M12 supplies a current of magnitude I TF to node D. Since the n-channel transistor M22 absorbs a current of magnitude I TI from node D to match the current of magnitude I TI supplied by the p-channel transistor MP1 to node D, the current absorbed by the n-channel M15 from node D when VIN is 0 has a magnitude of I TF , rather than I TF +I TI in the prior art design of FIG. 1. The same current balance considerations apply to nodes A and B. At this time, the p-channel transistor M6 supplies a current of magnitude I TF to node A. Since the p-channel transistor M24 supplies a current of magnitude equal to 0 to match the current of magnitude 0 absorbed by the n-channel transistor MN0, the current absorbed by the p-channel M8 from node A when x is 0 has a magnitude of I TF , the same as in the prior art design of FIG. 1. Similarly, the p-channel transistor M7 supplies a current of magnitude I TFcurrent. Since the p-channel transistor M25 provides a current with a magnitude equal to 0 to match the current absorbed by the n-channel transistor MN1 with a magnitude of 0, the current absorbed by the p-channel M9 from node B when x is 0 has a magnitude of I TF , the same as in the prior art design of FIG. 1.

[0081] Now consider the case where the value of VIN is VDD. As a result, x is I TI . At this time, finally, the n-channel transistor M13 provides a current with a magnitude of I TF to node C, and finally, M12 provides a current with a magnitude of I TF to node D. The p-channel transistor MP0 does not provide current to node C, the p-channel transistor MP1 does not provide current to node D, the n-channel transistor M23 does not absorb current from node C, and the n-channel transistor M22 does not absorb current from node D. Therefore, the current absorbed by the n-channel transistor M14 from node C is I TF , and the current absorbed by the n-channel transistor M15 from node D is I TF . Similarly, finally, the p-channel transistor M6 provides a current with a magnitude of I TF to node A, and finally, M7 provides a current with a magnitude of I TF to node B. The p-channel transistor M24 provides a current of I TI to node A, the p-channel transistor M25 provides a current of I TI to node B, the n-channel transistor MN0 absorbs a current of I TI from node A, and the n-channel transistor MN1 absorbs a current of I TI from node B. Therefore, the current absorbed by the p-channel transistor M8 from node A is I TF , and the current absorbed by the p-channel transistor M9 from node B is I TF , different from the I TF -I TI in the prior art design of FIG. 1.

[0082] Therefore, when VIN is VDD, the current absorbed by M14 from node C is I TF and the current flowing through the n-channel transistor M13 and the p-channel transistor M8 is I TF , the same as when VIN is 0. Similarly, when VIN is VDD, the current absorbed by M15 from node D and the current flowing through the n-channel transistor M12 and the p-channel transistor M9 are I TF, which is the same as when VIN is 0. Therefore, the bias current of the folded cascode 17 and the bias current of the M14:M15 mirror are independent of the input, different from the input-dependence in the prior art design of FIG. 1. The high-frequency poles and zeros generated from the cascode transistors M8, M9, M13, M12, M37 and by the Monticelli cell 18 do not shift with the input. In addition, the transconductance of the current mirror M14:M15 is independent of the input, different from the input-dependence in the prior art design of FIG. 1. This aspect makes the input-referred noise contribution of the M14:M15 mirror independent of the input. Moreover, the additional branch used to provide a constant bias current to the Monticelli cell 18 in the prior art design of FIG. 1 is now eliminated. Moreover, the additional current consumption of the OTA 20 given by the bias stage 21 is 2(I TI +x) / N. Since the scaling factor 1 / N used herein can be set to a desired number, this means that N can be increased to reduce the current consumption.

[0083] Variants of the OTA 20 are within the scope of the present disclosure. For example, Figure 3 the variant 20' of the OTA shown in includes a chopper 25 that is connected between the drains of the p-channel transistors M24, M6 and node A and between the drains of the p-channel transistors M25, M7 and node B. In addition, there is a chopper 26 that is connected between the drains of the n-channel transistors M23, M14 and node C and between the drains of the n-channel transistors M15, M22 and node D. These choppers 25 and 26 are used to modulate the contributions of the transistors M24, M6, M7, M25, M23, M14, M15 and M22 to the flicker noise and offset.

[0084] Another variant is Figure 4 the OTA 20” shown in, which includes a chopper 27 that chops the feedback voltage VFB and the input voltage VIN. The OTA 20” also includes a chopper 25 that is connected between the sources of the p-channel transistors M8 and node A and between the sources of the p-channel transistors M9 and node B. The OTA 20” further includes a chopper 26 that is connected between the sources of the n-channel transistors M13 and node C and between the sources of the n-channel transistors M12 and node D. As explained, these choppers 25 and 26 are used to modulate the contributions of the transistors MP0, MP1, MN0, MN1, M24, M6, M7, M25, M23, M14, M15 and M22 to the flicker noise and offset.

[0085] Still another variant is Figure 5The OTA 20”' shown in [figure] removes resistors R0 and R1, connects capacitor C0 between node B and node NO, and connects capacitor C1 between node D and node NO, thereby providing compatibility with Ahuja compensation.

[0086] The OTAs 20, 20', 20”, 20”' described herein can be used in a variety of applications. For example, OTA 20 can be configured as a buffer, where the output node NO is connected to the inverting input (the gates of MP1 and MN1). As a buffer or as a voltage-to-current converter, the OTAs 20, 20', 20”, 20”' described herein can be used in a variety of microelectromechanical systems (MEMS) applications, particularly those in which a consistent noise level and dynamic response are desired over the entire input and output dynamic range. In particular, the OTAs 20, 20', 20”, 20”' described herein can be used to drive the electrodes of a gyroscope resonator or a MEMS micromirror.

[0087] Finally, it is clear that modifications and changes can be made to the content described and illustrated herein without departing from the scope of the disclosure.

[0088] Although the disclosure has been described by way of a limited number of embodiments, those skilled in the art who benefit from the disclosure can envision other embodiments that do not deviate from the disclosed scope. In addition, those skilled in the art can envision embodiments that represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. An operational transconductance amplifier OTA, comprising: a constant current source configured to provide a first constant current to the first node; a first input pair of transistors, comprising: a first input transistor coupled between the first node and a third folded branch node, the first input transistor configured to provide a first variable current to the third folded branch node based on a feedback voltage; and a second input transistor coupled between the first node and a fourth folded branch node, the second input transistor configured to provide a second variable current to the fourth folded branch node based on an input voltage; a tail current source configured to sink a tail current from the second node; a second input pair of transistors, comprising: a third input transistor coupled between the first folded branch node and the second node, the third input transistor configured to sink a third variable current from the first folded branch node based on a feedback voltage; and a fourth input transistor coupled between the second folded branch node and the second node, the fourth input transistor configured to sink a fourth variable current from the second folded branch node based on an input voltage; A folded cascode arrangement comprising: a first folded cascode branch coupled to a first folded branch node and a third folded branch node; a second folded cascode branch coupled to a second folded branch node and a fourth folded branch node; wherein the second folded cascode branch comprises a Monticelli cell coupled between the second folded branch node and the fourth folded branch node; A class AB output stage having an input coupled across a Monticelli cell; a bias stage configured to: mirror and scale the first constant current and the tail current to generate a first control voltage and a second control voltage; Wherein, the folded cascode arrangement in the first folded cascode branch comprises: a first tail generator transistor controlled by a first control voltage for providing a fifth variable current to the first folded branch node, the fifth variable current having a magnitude equal to the third variable current; a second tail generator transistor controlled by a second control voltage for sinking a sixth variable current from the third folded branch node, the sixth variable current having a magnitude equal to the first variable current; Wherein, the folded cascode is arranged in the second folded cascode branch and comprises: a third tail generator transistor controlled by the first control voltage for providing a seventh variable current to the second folded branch node, the seventh variable current having a magnitude equal to the fourth variable current; and A fourth tail generator transistor, controlled by the second control voltage, is configured to sink an eighth variable current from the fourth folded branch node, the eighth variable current having a magnitude equal to the second variable current.

2. The operational transconductance amplifier OTA according to claim 1, in, The tail current source includes a current mirror having a control node receiving a first control signal; Wherein, the constant current source has a control terminal for receiving a second control signal; Among them, the bias stage includes: a first biasing transistor connected in a diode-coupled arrangement between a supply voltage node and a first compensation node; a second bias transistor connected between the first compensation node and ground, a control terminal of the second bias transistor connected to a control node of the current mirror; a third bias transistor connected between the supply voltage node and the second compensation node, a control terminal of the third bias transistor coupled to the second control signal; a fourth bias transistor connected between the second compensation node and ground, a control terminal of the fourth bias transistor being coupled to the first control signal; and A fifth biasing transistor is connected in a diode-coupled arrangement between the second compensation node and ground.

3. The operational transconductance amplifier OTA according to claim 1, in, The constant current source has a control terminal receiving a second control signal; Wherein, the folded cascode arrangement further comprises, within the first folded cascode branch: a fifth tail generator transistor connected between the supply voltage node and the first folded branch node, the fifth tail generator transistor having a control terminal coupled to a second control signal; a first cascode transistor connected between the first folded branch node and the third cascode transistor, the first cascode transistor having a control terminal coupled to a first cascode control signal; a second cascode transistor connected between the first cascode transistor and the third cascode transistor, the second cascode transistor having a control terminal coupled to a third cascode control signal; a third cascode transistor connected between the second cascode transistor and the third folded branch node, the third cascode transistor having a control terminal coupled to a second cascode control signal; and a sixth tail generator transistor connected between the third folded branch node and ground, the sixth tail generator transistor having a control terminal coupled to a node between the second cascode transistor and the third cascode transistor; wherein the folded cascode arrangement within the second folded cascode branch further comprises: a seventh tail generator transistor connected between the supply voltage node and the second folded branch node, the seventh tail generator transistor having a control terminal coupled to the second control signal; a fourth cascode transistor connected between the second folded branch node and the Monticelli cell, the fourth cascode transistor having a control terminal coupled to the first cascode control signal; a fifth cascode transistor connected between the Monticelli cell and the fourth folded branch node, the fifth cascode transistor having a control terminal coupled to the second cascode control signal; and An eighth tail generator transistor is connected between the fourth folded branch node and ground, the eighth tail generator transistor having a control terminal coupled to a node between the second cascode transistor and the third cascode transistor.

4. The operational transconductance amplifier OTA according to claim 1, in, The first folded branch node is connected to a source of the first cascode transistor, and wherein the second folded branch node is connected to a source of the fourth cascode transistor; wherein the folded cascode arrangement further comprises a first chopper having a first input and a second input and a first output and a second output, the first chopper being configured to chop a voltage at the first input and the second input of the first chopper, the first output of the first chopper being connected to a drain of the first cascode transistor, the second output of the first chopper being connected to a drain of the fourth cascode transistor; wherein the fifth tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper; wherein the first tail generator transistor has a first conduction terminal connected to a supply voltage node and a second conduction terminal connected to a first input of the first chopper; wherein the seventh tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper; and Therein, the third tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper.

5. The operational transconductance amplifier OTA as claimed in claim 4, in, The third folded branch node is connected to the source of the third cascode transistor, and wherein the fourth folded branch node is connected to the source of the fifth cascode transistor; wherein the folded cascode arrangement further comprises a second chopper having a first input and a second input and a first output and a second output, the second chopper being configured to chop a voltage at the first input and the second input of the second chopper, the first output of the second chopper being connected to drains of the sixth tail generator transistor and the second tail generator transistor, the second output of the second chopper being connected to drains of the eighth tail generator transistor and the fourth tail generator transistor; wherein the third cascode transistor has a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper; Therein, the fifth cascode transistor has a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper.

6. The operational transconductance amplifier OTA according to claim 1, in, The folded cascode arrangement further includes a first chopper having first and second inputs and first and second outputs, the first chopper being configured to chop voltages at the first and second inputs of the first chopper, the first output of the first chopper being connected to a drain of the first cascode transistor, the second output of the first chopper being connected to a fourth cascode transistor; wherein the fifth tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the first input of the first chopper; wherein the first tail generator transistor has a first conduction terminal connected to a supply voltage node and a second conduction terminal connected to a first input of the first chopper; wherein the seventh tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper; wherein the third tail generator transistor has a first conduction terminal connected to the supply voltage node and a second conduction terminal connected to the second input of the first chopper; wherein the folded cascode arrangement further comprises a second chopper having a first input and a second input and a first output and a second output, the second chopper being configured to chop a voltage at the first input and the second input of the second chopper, the first output of the second chopper being connected to drains of the sixth tail generator transistor and the second tail generator transistor, the second output of the second chopper being connected to drains of the eighth tail generator transistor and the fourth tail generator transistor; wherein the third cascode transistor has a first conduction terminal connected to the second cascode transistor and a second conduction terminal connected to the first input of the second chopper; wherein a fifth cascode transistor has a first conduction terminal connected to the Monticelli cell and a second conduction terminal connected to the second input of the second chopper; and It also includes a third chopper configured to chop the feedback voltage and the input voltage, provide the chopped feedback voltage to the control terminals of the first input transistor and the third input transistor, and provide the chopped input voltage to the control terminals of the second input transistor and the fourth input transistor.

7. The operational transconductance amplifier OTA according to claim 1, in, The constant current source has a control terminal receiving a second control signal; Among them, the class AB output stage includes: a first input coupled to a first output terminal of a Monticelli cell; a second input coupled to a second output terminal of the Monticelli cell; a first output transistor connected between the supply node and the output node, the first output transistor having a control terminal connected to the first input; a second output transistor connected between the output node and ground, the second output transistor having a control terminal connected to the second input; a third output transistor connected between the supply node and the fourth output transistor, the third output transistor having a control terminal connected to a second control signal; a fourth output transistor connected in a diode-coupled configuration between the third output transistor and the first input of the Monticelli cell; a fifth output transistor connected between the fourth output transistor and ground in a diode-coupled configuration; a sixth output transistor connected in a diode-coupled configuration between the supply node and the seventh output transistor; a seventh output transistor connected in a diode-coupled configuration between the sixth output transistor and the second input of the Monticelli cell; and An eighth output transistor is connected between the second input of the Monticelli cell and ground.

8. The operational transconductance amplifier OTA as claimed in claim 7, wherein: The Monticelli cell comprises a first transistor connected between a first output terminal and a second output terminal, wherein the first transistor has a control terminal connected to a control terminal of a fourth output transistor, and a second transistor connected between the first output terminal and the second output terminal, wherein the second transistor has a control terminal connected to a control terminal of a seventh output transistor.

9. The operational transconductance amplifier OTA as claimed in claim 7, wherein: The class AB output stage includes: a first resistor and a first capacitor connected in series between a first output terminal of the Monticelli cell and an output node; and a second resistor and a second capacitor connected in series between a second output terminal of the Monticelli cell and the output node.

10. The operational transconductance amplifier OTA as claimed in claim 7, wherein: The class AB output stage includes: a first capacitor connected in series between a second folded branch node and an output node; and a second capacitor connected in series between a fourth folded branch node and the output node.

11. An operational transconductance amplifier (OTA), comprising: a constant current source p-channel transistor having a source connected to the supply voltage node, a drain connected to the first node, and a gate coupled to the first control voltage; A first input pair of transistors comprises: a first input p-channel transistor having a source connected to the first node, a drain connected to the third folded branch node, and a gate coupled to the feedback voltage; and a second input p-channel transistor having a source connected to the first node, a drain connected to the fourth folded branch node, and a gate coupled to the input voltage; a tail current source n-channel transistor having a drain connected to the second node, a source connected to ground, and a gate connected to a third node; A second input pair of transistors includes: a first input n-channel transistor having a drain connected to the first folded branch node, a source connected to the second node, and a gate coupled to a feedback voltage; and a second input n-channel transistor having a drain connected to the second folded branch node, a source connected to the second node, and a gate coupled to the input voltage; a first mirror n-channel transistor having a drain and a gate connected to the third node and a source connected to ground; a second mirror p-channel transistor having a source connected to the first node, a drain connected to the third node, and a gate connected to the fourth node; a third mirror p-channel transistor having a source connected to the supply voltage node and a drain and a gate connected to the fourth node; a tail n-channel transistor having a drain connected to the fourth node, a source connected to ground, and a gate coupled to a second control voltage; Bias stage, including: a first bias p-channel transistor having a source connected to the supply voltage node, a drain connected to the first bias node, and a gate coupled to the first control voltage; a first bias n-channel transistor having a drain connected to a first bias node, a source connected to ground, and a gate coupled to the first bias node; a second bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to a second control voltage; a second bias p-channel transistor having a source connected to the supply voltage node and a drain and a gate connected to a second bias node; and a third bias n-channel transistor having a drain connected to the second bias node, a source connected to ground, and a gate coupled to the third node; A folded cascode arrangement, comprising within a first folded cascode branch: a first tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the first folded branch node, and a gate connected to the second bias node; and a first tail generator n-channel transistor having a drain connected to the third folded branch node, a source connected to ground, and a gate connected to the first bias node; The folded cascode arrangement in the second folded cascode branch comprises: a second tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the second folded branch node, and a gate connected to the first bias node; a second tail generator n-channel transistor having a drain connected to the fourth folded branch node, a source connected to ground, and a gate connected to the first bias node; and a Monticelli cell coupled between a drain of the second tail generator p-channel transistor and a drain of the second tail generator n-channel transistor; A class AB output stage having an input coupled across the Monticelli cell and an output connected to an output node.

12. The operational transconductance amplifier OTA as claimed in claim 11, wherein: The folded cascode arrangement further comprises within the first folded cascode branch: a third tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the first folded branch node, and a gate coupled to the first control voltage; a first cascode p-channel transistor having a source connected to the first folded branch node, a drain, and a gate coupled to a first cascode control signal; a second cascode p-channel transistor having a source connected to the drain of the first cascode p-channel transistor, a drain, and a gate connected to the first cascode control node; a first cascode n-channel transistor having a drain connected to the drain of the second cascode p-channel transistor, a source connected to the third folded branch node, and a gate coupled to the second cascode control signal; and A second cascode n-channel transistor has a drain connected to the third folded branch node, a source connected to ground, and a gate connected to the drain of the second cascode p-channel transistor.

13. The operational transconductance amplifier OTA as claimed in claim 12, wherein: The folded cascode arrangement further comprises within the second folded cascode branch: a third cascode p-channel transistor having a source connected to the supply voltage node, a drain connected to the second folded branch node, and a gate coupled to the first control voltage; a fourth cascode p-channel transistor having a source connected to the second folded branch node, a drain, and a gate connected to the first cascode control signal; a third cascode n-channel transistor having a drain, a source connected to the fourth folded branch node, and a gate coupled to the second cascode control signal; a fourth cascode n-channel transistor having a drain connected to the fourth folded branch node, a source connected to ground, and a gate connected to the drain of the second cascode p-channel transistor; and A Monticelli cell having a first output connected to the drain of the fourth cascode p-channel transistor, a second output connected to the drain of the second cascode n-channel transistor, a first input connected to the first cascode control node, and a second input connected to the second cascode control node.

14. The operational transconductance amplifier OTA as claimed in claim 13, further comprising: a first chopper having a first input connected to the drain of the third tail generator p-channel transistor, a second input connected to the drain of the first tail generator p-channel transistor, a first output connected to the first folded branch node, and a second output connected to the second folded branch node; as well as A second chopper has a first input connected to the source of the first cascode n-channel transistor, a second input connected to the source of the third cascode n-channel transistor, a first output connected to the third folded branch node, and a second output connected to the fourth folded branch node. 15 . The operational transconductance amplifier OTA of claim 14 , further comprising a third chopper configured to chop the feedback voltage and the input voltage.

16. The operational transconductance amplifier OTA as claimed in claim 11, wherein: The Class AB output stage consists of: a first input node connected to a first output of the Monticelli cell; a second input node connected to a second output of the Monticelli cell; a first output p-channel transistor having a source connected to the supply voltage node, a drain connected to the output node, and a gate connected to the first input node; a first output n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second input node; a second output p-channel transistor having a source connected to the supply voltage node, a drain connected to the second cascode control node, and a gate coupled to the first control voltage; a second output n-channel transistor having a drain and a gate connected to the second cascode control node and a source; a third output n-channel transistor having a drain and a gate connected to the source of the second output n-channel transistor and a source connected to ground; a third output p-channel transistor having a source connected to the supply voltage node and a gate and a drain; a fourth output p-channel transistor having a source connected to the gate and drain of the third output p-channel transistor and a gate and drain connected to the first cascode control node; and A fourth output n-channel transistor has a drain connected to the first cascode control node, a source connected to ground, and a gate coupled to the second control voltage.

17. The operational transconductance amplifier OTA as claimed in claim 16, wherein: The class AB output stage further includes: a first resistor and a first capacitor connected in series between the first output of the Monticelli cell and the output node; and a second resistor and a second capacitor connected in series between the second output of the Monticelli cell and the output node.

18. The operational transconductance amplifier OTA as claimed in claim 16, wherein: The class AB output stage further includes: a first capacitor connected in series between the second folded branch node and the output node; and a second capacitor connected in series between the fourth folded branch node and the output node.

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