Embedded power modules and smart devices

Abstract

This application provides an embedded power module and a smart device, belonging to the field of embedded packaging. A first DC path is provided on a first circuit board layer, an AC path and either the first or second DC path are provided on a second circuit board layer, and a second DC path and an AC path are provided on a third circuit board layer. The AC path on the third circuit board layer is interleaved with the AC path on the second circuit board layer. The direction of the first DC path is opposite to the direction of the AC and second DC paths. The first DC path, AC path, and second DC path on different layers are stacked parallel to each other and generate magnetic fields in opposite directions, allowing these magnetic fields to superimpose and cancel each other out. After the magnetic fields in opposite directions superimpose and cancel each other out, the parasitic inductance of the embedded power module is reduced, solving the problem of large parasitic inductance in traditional power modules.

Description

Technical Field

[0001] This application belongs to the field of embedded packaging technology, and in particular relates to an embedded power module and a smart device. Background Technology

[0002] Third-generation wide-bandgap semiconductor silicon carbide (SiC) power devices and gallium nitride (GaN) power devices have the advantage of high switching speed. However, the high switching speed of power devices leads to a high rate of current change, resulting in large parasitic inductance and voltage spikes, creating voltage stress. If the voltage stress generated during operation exceeds the device's blocking voltage, it will cause serious damage to the device, leading to breakdown, and may even damage the downstream application load.

[0003] To prevent voltage stress from exceeding the blocking voltage of power devices during operation, it is necessary to reduce the parasitic inductance (also known as stray inductance) of power devices. Printed Circuit Board (PCB) embedded packaging is one of the technical approaches for low stray inductance power devices and has received widespread attention. However, parasitic inductance is ubiquitous in the PCB structure of traditional power modules, originating from wiring, connection lines, and other components, resulting in relatively high parasitic inductance. Summary of the Invention

[0004] The purpose of this application is to provide an embedded power module and a smart device, which aims to solve the problem of large parasitic inductance in traditional power modules.

[0005] This application provides an embedded power module, comprising: a first circuit board layer, a second circuit board layer, and a third circuit board layer stacked sequentially, wherein...

[0006] The first circuit board layer is provided with a first DC path;

[0007] The second circuit board layer is provided with an AC path and either the first DC path or the second DC path;

[0008] The third circuit board layer is provided with the second DC path and the AC path, and the AC path located on the third circuit board layer and the AC path located on the second circuit board layer are arranged alternately;

[0009] The current direction of the first DC path is opposite to the current direction of the AC path and the current direction of the second DC path, respectively; the first DC path, the AC path and the second DC path are connected.

[0010] In one embodiment, the embedded power module further includes a chip mounting layer disposed between the second circuit board layer and the third circuit board layer, wherein a first power chip and a second power chip are disposed at intervals within the chip mounting layer;

[0011] The first power chip is connected to the second DC path located on the third circuit board layer and the AC path located on the second circuit board layer;

[0012] The second power chip is connected to the AC path located on the third circuit board layer and the first DC path located on the second circuit board layer or the second DC path located on the second circuit board layer;

[0013] The chip mounting layer includes a fourth circuit board layer, a first insulating layer, and a fifth circuit board layer stacked together.

[0014] In one embodiment, a first conductive recess and a second conductive recess are provided at intervals within the chip mounting layer;

[0015] The first power chip is disposed in the first conductive recess, and the second power chip is disposed in the second conductive recess;

[0016] The first conductive recess is connected to the second DC path located on the third circuit board layer, the first power chip is connected to the AC path located on the second circuit board layer, the second conductive recess is connected to the AC path located on the third circuit board layer, and the second power chip is connected to the first DC path located on the second circuit board layer or the second DC path located on the second circuit board layer.

[0017] In one embodiment, the DC current signal flows from the second DC path to the first DC path.

[0018] In one embodiment, the drain of the first power chip is connected to the second DC path, and the source of the first power chip is connected to the AC path located on the second circuit board layer.

[0019] The drain of the second power chip is connected to the AC path located on the third circuit board layer, and the source of the second power chip is connected to the first DC path or the second DC path located on the second circuit board layer.

[0020] In one embodiment, the DC current signal flows from the first DC path to the second DC path.

[0021] In one embodiment, the first DC path located on the first circuit board layer extends to the second circuit board layer through at least one first via.

[0022] The AC path located on the second circuit board layer extends to the third circuit board layer through at least one second via.

[0023] In one embodiment, the first DC path is positioned opposite to the second DC path, and the first DC path is positioned opposite to the AC path.

[0024] In one embodiment, the sum of the paths of the second DC path and the AC path is the same as that of the first DC path.

[0025] In one embodiment, the first circuit board layer is provided with a first drive signal path and a second drive signal path, and the first drive signal path, the second drive signal path and the first DC path are spaced apart.

[0026] In one embodiment, the embedded power module further includes:

[0027] The sixth circuit board layer is stacked on the side of the third circuit board layer away from the second circuit board layer.

[0028] This application provides an embedded power module, including: a first circuit board layer, a second circuit board layer and a fourth circuit board layer stacked sequentially;

[0029] The first circuit board layer is provided with a first DC path;

[0030] The second circuit board layer has an AC path;

[0031] The fourth circuit board layer is provided with a second DC path, which is located on the fourth circuit board layer;

[0032] The second DC path located on the fourth circuit board layer is alternately arranged with the AC path located on the second circuit board layer.

[0033] The current direction of the first DC path is opposite to the current direction of the AC path and the current direction of the second DC path, respectively; the first DC path, the AC path and the second DC path are connected.

[0034] In one embodiment, the second circuit board layer is provided with the AC path and the second DC path spaced apart;

[0035] The second DC path located on the fourth circuit board layer, the AC path located on the second circuit board layer, and the second DC path located on the second circuit board layer are arranged alternately.

[0036] In one embodiment, a third conductive recess and a fourth conductive recess are spaced apart in the fourth circuit board layer, a first power chip is disposed in the third conductive recess, and a second power chip is disposed in the fourth conductive recess.

[0037] The third conductive recess is connected to the second DC path located on the fourth circuit board layer, the first power chip is connected to the AC path located on the second circuit board layer, the fourth conductive recess is connected to the AC path located on the second circuit board layer, and the second power chip is connected to the first DC path located on the first circuit board layer.

[0038] In one embodiment, the embedded power module further includes a first insulating layer and a fifth circuit board layer stacked together, wherein the first insulating layer and the fifth circuit board layer are disposed on the side of the fourth circuit board layer away from the second circuit board layer;

[0039] The first insulating layer is provided with a first insulating heat-conducting part and a second insulating heat-conducting part spaced apart;

[0040] The fifth circuit board layer is provided with a first conductive part and a second conductive part spaced apart.

[0041] The third conductive recess, the first insulating and heat-conducting portion, and the first conductive portion are disposed opposite to each other, and the fourth conductive recess, the second insulating and heat-conducting portion, and the second conductive portion are disposed opposite to each other.

[0042] This application provides a smart device including at least one embedded power module as described in any of the above embodiments.

[0043] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0044] In the embedded power module provided in this application, a first DC path located on a first circuit board layer, an AC path located on a second circuit board layer and either the first DC path or the second DC path, and a second DC path located on a third circuit board layer and the AC path form stacked parallel current paths. The first DC path on the first circuit board layer and the AC path on the second circuit board layer are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path on the first circuit board layer and the second DC path on the second circuit board layer are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path on the first circuit board layer and the second DC path and AC path on the third circuit board layer are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path on the second circuit board layer and the AC path on the third circuit board layer are current paths in opposite directions, capable of generating magnetic fields in opposite directions.

[0045] Furthermore, the first DC path, AC path, and second DC path, located on different circuit board layers, are connected to provide the required current signals to each power chip in the embedded power module. These three paths, stacked parallel to each other on different circuit board layers, generate magnetic fields in opposite directions, allowing them to cancel each other out. This cancellation of opposite magnetic fields reduces the total magnetic field strength, lowering the parasitic inductance (also known as stray inductance) of the embedded power module and ensuring its safe operation.

[0046] Therefore, the parasitic inductance of the embedded power module provided in this application is reduced, which reduces the voltage spikes during switching, thereby reducing the switching losses of the embedded power module, reducing the risk of overvoltage, and further improving the voltage platform of the entire vehicle. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of the stacked structure of the second DC path to the first DC path of the embedded power module in some embodiments provided in this application.

[0049] Figure 2 A schematic diagram of the stacked structure of the second DC path to the first DC path of the embedded power module in some embodiments provided in this application.

[0050] Figure 3 A schematic diagram of the stacked structure of the first DC path to the second DC path of the embedded power module in some embodiments provided in this application.

[0051] Figure 4 A schematic diagram of the overall stacked structure of the embedded power module in some embodiments provided in this application.

[0052] Figure 5 The diagram shows the structure of the power chip of the embedded power module in some embodiments provided in this application.

[0053] Figure 6 The diagram shows the structure of the power chip of the embedded power module in some embodiments provided in this application.

[0054] Figure 7The first conductive recess and the second conductive recess are schematic diagrams of the structure of the first power chip and the second power chip, respectively, in some embodiments provided in this application.

[0055] Figure 8 A schematic diagram of the structure of the half-bridge inverter circuit formed by the embedded power module provided in this application.

[0056] Figure 9 A schematic diagram of the structure of the full-bridge inverter circuit formed by the embedded power module provided in this application.

[0057] Figure 10 A cross-sectional schematic diagram of the vias and drive signal paths of the embedded power module in some embodiments provided in this application.

[0058] Figure 11 A top view of the first circuit board layer in some embodiments provided in this application.

[0059] Figure 12 A schematic diagram of the stacked structure of the second DC path to the first DC path of the embedded power module in some embodiments provided in this application.

[0060] Figure 13 A schematic diagram of the stacked structure of conductive recesses, insulating and thermally conductive portions, and conductive portions in some embodiments provided in this application.

[0061] Figure 14 A schematic diagram of the stacked structure of the second DC path to the first DC path of the embedded power module in some embodiments provided in this application. Detailed Implementation

[0062] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0063] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0064] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] Please see Figure 1 This application provides an embedded power module 100. The embedded power module 100 includes a first circuit board layer 10, a second circuit board layer 20, and a third circuit board layer 30. The first circuit board layer 10 is provided with a first DC path 410. The second circuit board layer 20 is provided with an AC path 420 and either the first DC path 410 or the second DC path 430. Figure 2 As shown, the second circuit board layer 20 is provided with an AC path 420 and a second DC path 430. The second circuit board layer 20 is stacked with the first circuit board layer 10.

[0067] The third circuit board layer 30 is provided with a second DC path 430 and an AC path 420. The second circuit board layer 20 is stacked between the first circuit board layer 10 and the third circuit board layer 30. The AC path 420 located on the third circuit board layer 30 and the AC path 420 located on the second circuit board layer 20 are staggered.

[0068] The current direction of the first DC path 410 is opposite to that of the current direction of the AC path 420 and the current direction of the second DC path 430. The first DC path 410, the AC path 420 and the second DC path 430 are connected.

[0069] In this embodiment, the first circuit board layer 10, the second circuit board layer 20, and the third circuit board layer 30 can be metal layers or alloy layers, such as copper layers, silver layers, or copper alloy layers. The first circuit board layer 10 and the second circuit board layer 20 are stacked as insulating layers, meaning that the first circuit board layer 10 and the second circuit board layer 20 are stacked together and insulated from each other. Similarly, the third circuit board layer 30 and the second circuit board layer 20 are stacked as insulating layers, meaning that the third circuit board layer 30 and the second circuit board layer 20 are stacked together and insulated from each other.

[0070] The first circuit board layer 10 forms the first DC path 410 through a series of processing techniques (such as photolithography and etching). The first DC path 410 can be understood as the path through which the DC signal flows in the direction of the signal, or as a metal line through which the DC signal flows in the direction of the signal, serving as a transmission channel for the DC signal. Figure 1 As shown, the direction can be the direction of current flow towards the negative terminal of the power supply, DC-. Figure 3 As shown, the direction can also be the direction of current flow from the positive DC+ terminal of the power supply, which can be set according to the actual situation.

[0071] The second circuit board layer 20 is provided with an AC path 420 and either a first DC path 410 or a second DC path 430. This can be understood as the AC path 420 and the first DC path 410 located on the second circuit board layer 20 being spaced apart on the same circuit board layer, being independent paths, isolated from each other, and not connected. Alternatively, the AC path 420 and the second DC path 430 located on the second circuit board layer 20 are spaced apart on the same circuit board layer, being two independent paths, isolated from each other, and not connected.

[0072] The second circuit board layer 20 forms an AC path 420 and either a first DC path 410 or a second DC path 430 through a series of processing techniques (such as photolithography and etching). The first DC path 410 on the second circuit board layer 20 and the first DC path 410 on the first circuit board layer 10 both carry DC signals flowing in a first direction, which is the same flow direction. The AC path 420 on the second circuit board layer 20 and the AC path 420 on the third circuit board layer 30 both carry AC signals flowing in the same direction. The second DC path 430 on the second circuit board layer 20 and the second DC path 430 on the third circuit board layer 30 both carry DC signals flowing in a second direction, which is the same flow direction. In this application, the first direction and the second direction refer to the directions of current flow.

[0073] The second DC path 430, located on the second circuit board layer 20, can be understood as the path through which the DC signal flows in a second direction, or as a metal line through which the DC signal flows in a second direction, serving as a transmission channel for the DC signal. The second direction can be the direction of current flow towards the negative terminal DC- of the power supply, or the direction of current flow out of the positive terminal DC+ of the power supply, and can be set according to actual conditions. The directions can be completely opposite, and the relationship between the two directions can be set according to actual conditions. For example: the first direction is the direction of current flow towards the negative terminal DC- of the power supply, and the second direction is the direction of current flow out of the positive terminal DC+ of the power supply; or, the first direction is the direction of current flow out of the positive terminal DC+ of the power supply, and the second direction is the direction of current flow towards the negative terminal DC- of the power supply. The flow direction of the second DC path 430 and the flow direction of the AC path 420 are both the second direction, the same flow direction, and opposite to the first direction.

[0074] The AC path 420 located on the second circuit board layer 20 can be understood as the path through which the alternating current (AC) signal flows in the second direction, or as a metal line through which the AC signal flows in the second direction, serving as a transmission channel for the AC signal. The AC signal is formed by alternately controlling the on or off states of multiple power chips in the embedded power module 100.

[0075] The third circuit board layer 30 is provided with a second DC path 430 and an AC path 420. It can be understood that the second DC path 430 and the AC path 420 located on the third circuit board layer 30 are arranged at intervals on the same circuit board layer, and are two independent paths that are isolated from each other and not connected. The second DC path 430 and the AC path 420 are formed on the third circuit board layer 30 through a series of processing techniques (such as photolithography and etching).

[0076] The AC path 420 located on the third circuit board layer 30 is staggered with the AC path 420 located on the second circuit board layer 20. This can be understood as the AC path 420 on the third circuit board layer 30 and the AC path 420 on the second circuit board layer 20 being located at different positions. Furthermore, this staggered arrangement of the AC path 420 on the third circuit board layer 30 and the AC path 420 on the second circuit board layer 20 can cancel out the magnetic field generated by the first DC path 410, thereby reducing the parasitic inductance of the embedded power module 100. Moreover, because the AC path 420 on the third circuit board layer 30 and the AC path 420 on the second circuit board layer 20 are staggered, the second DC paths 430 distributed on the third circuit board layer 30 and the second DC paths 430 on the second circuit board layer 20 are also staggered, jointly canceling out the magnetic field generated by the first DC path 410, thus reducing the parasitic inductance of the embedded power module 100.

[0077] In the embedded power module 100 provided in this application, a first DC path 410 located on the first circuit board layer 10, an AC path 420 located on the second circuit board layer 20, and either the first DC path 410 or the second DC path 430, as well as a second DC path 430 located on the third circuit board layer 30, form stacked parallel current paths. The first DC path 410 on the first circuit board layer 10 and the AC path 420 on the second circuit board layer 20 are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path 410 on the first circuit board layer 10 and the second DC path 430 on the second circuit board layer 20 are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path 410 on the first circuit board layer 10, the second DC path 430 on the third circuit board layer 30, and the AC path 420 are current paths in opposite directions, capable of generating magnetic fields in opposite directions. The first DC path 410 on the second circuit board layer 20 and the AC path 420 on the third circuit board layer 30 are current paths in opposite directions, capable of generating magnetic fields in opposite directions.

[0078] Furthermore, the first DC path 410, AC path 420, and second DC path 430, located on different circuit board layers, are connected to provide the required current signals to each power chip in the embedded power module 100. The first DC path 410, AC path 420, and second DC path 430, located on different circuit board layers, are stacked parallel to each other and generate magnetic fields in opposite directions, allowing these magnetic fields to superimpose and cancel each other out. After the opposing magnetic fields superimpose and cancel each other out, the total magnetic field strength is reduced, lowering the parasitic inductance (also known as stray inductance) of the embedded power module 100 and ensuring the safe operation of the embedded power module 100.

[0079] Therefore, the parasitic inductance of the embedded power module 100 provided in this application is reduced, which reduces the voltage spikes during switching, thereby reducing the switching losses of the embedded power module 100, reducing the risk of overvoltage, and further improving the voltage platform of the whole vehicle.

[0080] Please see Figure 4 In one embodiment, the embedded power module 100 further includes a chip mounting layer. The chip mounting layer includes a fourth circuit board layer 70, a first insulating layer 510, and a fifth circuit board layer 80 stacked together. The chip mounting layer is disposed between the second circuit board layer 20 and the third circuit board layer 30. A first power chip 610 and a second power chip 620 are spaced apart within the chip mounting layer.

[0081] The first power chip 610 is connected to the second DC path 430 located on the third circuit board layer 30 and the AC path 420 located on the second circuit board layer 20. The second power chip 620 is connected to the AC path 420 located on the third circuit board layer 30 and the first DC path 410 located on the second circuit board layer 20 (e.g., ...). Figure 1 (as shown) or connected via the second DC path 430 located on the second circuit board layer 20 (e.g.) Figure 2 (As shown).

[0082] In this embodiment, the fourth circuit board layer 70 is stacked between the second circuit board layer 20 and the first insulating layer 510. The fifth circuit board layer 80 is stacked between the first insulating layer 510 and the third circuit board layer 30. The fourth circuit board layer 70, the first insulating layer 510, and the fifth circuit board layer 80 together form a chip mounting layer for placing the first power chip 610 and the second power chip 620.

[0083] The first insulating layer 510 can be made of insulating materials such as aluminum oxide, aluminum oxide, or silicon nitride. The fourth circuit board layer 70 and the fifth circuit board layer 80 can be metal layers or alloy layers, such as copper layers, silver layers, or copper alloy layers. The first power chip 610 and the second power chip 620 are insulated from each other. The first power chip 610 and the second power chip 620 can be insulated-gate bipolar transistor (IGBT) chips, fast recovery diode (FRD) chips, silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOS) chips, gallium-nitride metal-oxide-semiconductor field-effect transistor (GaN MOS) chips, gallium nitride high electron mobility transistor (GaN HEMT) chips, etc.

[0084] The first power chip 610 enables conduction between the second DC path 430 located on the third circuit board layer 30 and the AC path 420 located on the second circuit board layer 20. The second power chip 620 also enables connection between the AC path 420 on the third circuit board layer 30 and the first DC path 410 on the second circuit board layer 20. Alternatively, the second power chip 620 enables connection between the AC path 420 on the third circuit board layer 30 and the second DC path 430 on the second circuit board layer 20.

[0085] The first power chip 610 and the second power chip 620 are respectively disposed at intervals on the chip mounting layer. The first power chip 610 and the second power chip 620 are distributed at different positions on the chip mounting layer. Furthermore, by distributing the second DC path 430, AC path 420, and the first DC path 410 between different circuit board layers at different stacking positions of the first circuit board layer 10, the second circuit board layer 20, and the third circuit board layer 30, the first DC path 410 can overlap with the second DC path 420 and the second DC path 430, respectively, so that the generated magnetic fields can be superimposed and canceled. After the magnetic fields in opposite directions are superimposed and canceled, the parasitic inductance of the embedded power module 100 is reduced, which can ensure the safe operation of the embedded power module 100.

[0086] Please see Figure 5 and Figure 6 In one embodiment, a first conductive recess 611 and a second conductive recess 621 are spaced apart within the chip mounting layer. A first power chip 610 is disposed within the first conductive recess 611. A second power chip 620 is disposed within the second conductive recess 621.

[0087] The first conductive recess 611 is connected to the second DC path 430 located on the third circuit board layer 30. The first power chip 610 is connected to the AC path 420 located on the second circuit board layer 20. The second conductive recess 621 is connected to the AC path 420 located on the third circuit board layer 30. The second power chip 620 is connected to the first DC path 410 located on the second circuit board layer 20 (e.g., ...). Figure 5 (as shown) or the second DC path 430 located on the second circuit board layer 20 (e.g.) Figure 6 (As shown) connection.

[0088] In this embodiment, the first conductive recess 611 and the second conductive recess 621 are conductive and can be made of metallic conductive materials, such as copper, aluminum-copper alloys, etc. The structures of the first conductive recess 611 and the second conductive recess 621 are as follows: Figure 7As shown. A first conductive recess 611 has a first groove 612. A first power chip 610 is disposed within the first conductive recess 611, or alternatively, within the first groove 612. A second conductive recess 621 has a second groove 622. A second power chip 620 is disposed within the second conductive recess 621, or alternatively, within the second groove 622. The first conductive recess 611 enables the connection between the second DC path 430 located on the third circuit board layer 30 and the first power chip 610. The second conductive recess 621 enables the connection between the AC path 420 located on the third circuit board layer 30 and the second power chip 620.

[0089] The first conductive recess 611 and the second conductive recess 621 not only transmit the required current signal to the first power chip 610 and the second power chip 620, but also dissipate heat from the first power chip 610 and the second power chip 620. The first conductive recess 611 surrounds the first power chip 610, dissipating the heat generated by the first power chip 610. The second conductive recess 621 surrounds the second power chip 620, dissipating the heat generated by the second power chip 620.

[0090] In one embodiment, the DC current signal flows to the first DC path 410 via the second DC path 430, such as... Figure 1 and Figure 2 As shown.

[0091] In this embodiment, the current flowing from the positive terminal DC+ of the power supply flows into the second DC path 430 located on the third circuit board layer 30, and then through the first power chip 610 into the AC path 420 located on the second circuit board layer 20. The AC path 420 is connected to an external AC load (e.g., a motor in a vehicle inverter system or other load requiring an AC signal). After passing through the external AC load, the current flows into the second power chip 620, and then through the second power chip 620 into either the first DC path 410 or the second DC path 430 located on the second circuit board layer 20. The DC current flows through either the first DC path 410 or the second DC path 430 located on the second circuit board layer 20 into the first DC path 410 located on the first circuit board layer 10, and then flows out through the first DC path 410 to the negative terminal DC- of the power supply.

[0092] The DC current in the second DC path 430 located on the third circuit board layer 30 is the current flowing out of the positive DC+ terminal of the power supply. The DC current in the first DC path 410 located on the first circuit board layer 10 is the current flowing to the negative DC- terminal of the power supply. The second DC path 430 and the AC path 420 form opposite loop current paths with the first DC path 410, so that the first DC path 410 forms an anti-directional stacked current path with the AC path 420 and the second DC path 430, generating magnetic fields in opposite directions. The generated magnetic fields can be superimposed and canceled out, reducing the parasitic inductance of the embedded power module 100.

[0093] In one embodiment, the DC current signal flows from the first DC path 410 to the second DC path 430, such as... Figure 3 As shown. In this embodiment, the current flowing from the positive terminal DC+ of the power supply flows into the first DC path 410 located on the first circuit board layer 10, and then through the first DC path 410 or the second DC path 430 located on the second circuit board layer 20, flowing into the second power chip 620. After passing through the second power chip 620, it flows into the AC path 420 located on the third circuit board layer 30. The AC path 420 is connected to an external AC load (e.g., a motor in a vehicle inverter system or other load that requires an AC signal). After passing through the external AC load, the current flows into the first power chip 610, and then through the second DC path 430 located on the third circuit board layer 30 to the negative terminal DC- of the power supply.

[0094] The DC current in the first DC path 410 located on the first circuit board layer 10 is the current flowing out of the positive DC+ terminal of the power supply. The second DC path 430 located on the third circuit board layer 30 is the current flowing to the negative DC- terminal of the power supply. The first DC path 410 forms opposite loop current paths with the second DC path 430 and the AC path 420, respectively. This results in the first DC path 410 forming opposite-direction stacked current paths with the AC path 420 and the second DC path 430, generating magnetic fields in opposite directions. These magnetic fields can be superimposed and cancel each other out, reducing the parasitic inductance of the embedded power module 100.

[0095] In one embodiment, the drain of the first power chip 610 is connected to the second DC path 430. The source of the first power chip 610 is connected to the AC path 420 located on the second circuit board layer 20, such as... Figure 1 As shown. The drain of the second power chip 620 is connected to the AC path 420 located on the third circuit board layer 30. The source of the second power chip 620 is connected to either the first DC path 410 or the second DC path 430 located on the second circuit board layer 20.

[0096] In this embodiment, the first power chip 610, the second DC path 430, the AC path 420, the second power chip 620, and the first DC path 410 form a half-bridge inverter circuit, such as... Figure 8 As shown. The first power chip 610 corresponds to the upper half-bridge. The second power chip 620 corresponds to the lower half-bridge. Both the first power chip 610 and the second power chip 620 are MOSFETs. The source of the first power chip 610 and the drain of the second power chip 620 are connected and connected to the AC path 420 for connection to an external load. The DC power supply is converted to AC power supply by the alternating on and off of the first power chip 610 and the second power chip 620 in the half-bridge inverter circuit. With the alternating on and off of the first power chip 610 and the second power chip 620, an AC voltage is formed on the load connected to the AC path 420.

[0097] The first power chip 610 and the second power chip 620 are connected to the paths of different circuit board layers respectively, forming opposite loop current paths. The current paths in different directions are distributed to different positions of different circuit board layers, so that the current paths can be stacked in opposite directions. The magnetic fields generated can be superimposed and canceled out, thereby reducing the parasitic inductance of the embedded power module 100.

[0098] In one embodiment, the three embedded power modules 100 can also be used to form a three-phase full-bridge power module, such as Figure 9 As shown, in a motor control system, the DC power supply is converted into a three-phase AC power supply by turning the power chips in the three-phase full-bridge power module on and off, thus powering the three-phase AC load and controlling the motor speed. The three-phase full-bridge power module integrates multiple power chips and their drive circuits into a single module, improving integration and reducing the number of external connection lines and components, thereby enhancing reliability and stability.

[0099] Please see Figure 10 In one embodiment, a first DC path 410 located on the first circuit board layer 10 extends to the second circuit board layer 20 through at least one first via 110.

[0100] In this embodiment, at least one first via 110 enables the connection of the first DC path 410 in the first circuit board layer 10 to other circuit board layers, distributing the current in the first DC path 410 to various components and circuit parts that require power, thus forming a transmission channel for the first DC path 410. The first DC path 410 located in the first circuit board layer 10 extends to the second circuit board layer 20 through at least one first via 110, connecting the first DC path 410 located in the second circuit board layer 20 with the first DC path 410 located in the first circuit board layer 10, thereby realizing the flow and transmission of DC current in the first direction. Thus, the first DC path 410 located in the second circuit board layer 20 and the first DC path 410 located in the first circuit board layer 10 are distributed at different relative positions in different circuit board layers, which can better form a reverse stacked current path with the second DC path 430 and the AC path 420, thereby reducing the parasitic inductance of the embedded power module 100.

[0101] In one embodiment, the AC path 420 located on the second circuit board layer 20 extends to the third circuit board layer 30 through at least one second via 210.

[0102] In this embodiment, at least one second via 210 enables the connection of the AC path 420 in the second circuit board layer 20 to other circuit board layers, distributing the current in the AC path 420 to the required components and circuit sections, thus forming a transmission channel for the AC path 420. The AC path 420 located in the second circuit board layer 20 extends to the third circuit board layer 30 through at least one second via 210, connecting the AC path 420 in the second circuit board layer 20 with the AC path 420 in the third circuit board layer 30, thereby enabling the flow and transmission of AC current along the second direction. Thus, the AC path 420 in the second circuit board layer 20 and the AC path 420 in the third circuit board layer 30 are distributed at different relative positions on different circuit board layers, which can better form a reverse stacked current path with the first DC path 410, thereby reducing the parasitic inductance of the embedded power module 100.

[0103] By using at least one first via 110 and at least one second via 210, the circuit paths between different stacked circuit board layers are connected, thus completing the circuit wiring of the entire embedded power module 100 and forming a complete multi-layer structure, which is more conducive to the integration of multiple power chips.

[0104] In one embodiment, when the first power chip 610 and the second power chip 620 are connected to the first DC path 410, the AC path 420 and the second DC path 430, the connection is also achieved through multiple vias.

[0105] In one embodiment, the first DC path 410 and the second DC path 430 are positioned opposite each other. Furthermore, the first DC path 410 and the AC path 420 are positioned opposite each other.

[0106] In this embodiment, the current directions of the first DC path 410 and the second DC path 430 are opposite, and the directions of the magnetic fields they generate are also opposite. The first DC path 410 and the second DC path 430 are arranged facing each other, so that the magnetic fields they generate are exactly opposite in the region between the first DC path 410 and the second DC path 430, and can be superimposed and canceled out, effectively reducing the parasitic inductance of the embedded power module 100.

[0107] The current directions of the first DC path 410 and the AC path 420 are also opposite, and the directions of the magnetic fields they generate are also opposite. The first DC path 410 and the AC path 420 are arranged facing each other, so that the magnetic fields they generate are exactly opposite to each other in the region between the first DC path 410 and the AC path 420, and can be superimposed and canceled out, effectively reducing the parasitic inductance of the embedded power module 100.

[0108] In one embodiment, the sum of the paths of the second DC path 430 and the AC path 420 is the same as that of the first DC path 410.

[0109] In this embodiment, the sum of the paths of the second DC path 430 and the AC path 420 may include the sum of the lengths of the second DC path 430 and the sum of the areas of the second DC path 430 and the AC path 420. The sum of the paths of the second DC path 430 and the AC path 420 is the same as that of the first DC path 410, which can be understood as the sum of the lengths and the sum of the areas of the second DC path 430 and the AC path 420 being the same as the length and area of ​​the first DC path 410, respectively.

[0110] Both the second DC path 430 and the AC path 420 are current transmission channels flowing in the second direction, opposite to the current direction of the first DC path 410. When the sum of the paths of the second DC path 430 and the AC path 420 is the same as that of the first DC path 410, the magnetic fields generated by the circuit paths on the first circuit board layer 10, the second circuit board layer 20, and the third circuit board layer 30 can be completely superimposed and canceled out, significantly reducing the parasitic inductance of the embedded power module 100.

[0111] Please see Figure 10 and Figure 11 In one embodiment, the first circuit board layer 10 is provided with a first drive signal path 440 and a second drive signal path 450, and the first drive signal path 440, the second drive signal path 450 and the first DC path 410 are spaced apart.

[0112] In this embodiment, the first circuit board layer 10 is provided with a first driving signal path 440, a second driving signal path 450, and a first DC path 410 spaced apart. The area of ​​the first DC path 410 is larger than the areas of the driving signal path 440 and the second driving signal path 450, such as... Figure 11 As shown. In one embodiment, the area of ​​the first DC path 410 is in the range of 85% to 95% of the area of ​​the first circuit board layer 10. In one embodiment, the first drive signal path 440 is the path of the gate drive signal of the power chip. The second drive signal path 450 is the path of the source drive signal of the power chip.

[0113] The first circuit board layer 10 has a first drive signal path 440, which is connected to the gate of the first power chip 610. The first circuit board layer 10 also has a second drive signal path 450, which is connected to the source of the first power chip 610, and is used to control the conduction or cutoff of the first power chip 610, thereby realizing the function of the half-bridge inverter circuit of the first power chip 610 and the second power chip 620.

[0114] In one embodiment, the embedded power module 100 further includes a sixth circuit board layer 90, such as Figure 6 As shown. The sixth circuit board layer 90 is stacked on the side of the third circuit board layer 30 away from the second circuit board layer 20. It can also be understood that the sixth circuit board layer 90 is stacked on the side of the third circuit board layer 30 away from the fifth circuit board layer 80.

[0115] In this embodiment, the sixth circuit board layer 90 can be a metal layer or an alloy layer, such as a copper layer, a silver layer, or a copper alloy layer. The first circuit board layer 10 and the second circuit board layer 20 are stacked together and insulated from each other. In one embodiment, a second insulating layer 520 is stacked between the first circuit board layer 10 and the second circuit board layer 20. The material of the second insulating layer 520 can be an insulating material such as alumina, aluminum oxide, or silicon nitride.

[0116] The fourth circuit board layer 70 is stacked with the second circuit board layer 20 and is insulated from each other. In one embodiment, a third insulating layer 530 is stacked between the fourth circuit board layer 70 and the second circuit board layer 20. The material of the third insulating layer 530 can be an insulating material such as alumina, aluminum oxide, or silicon nitride.

[0117] The fifth circuit board layer 80 is stacked with the third circuit board layer 30 and is insulated from each other. In one embodiment, a fourth insulating layer 540 is stacked between the fifth circuit board layer 80 and the third circuit board layer 30. The material of the fourth insulating layer 540 can be an insulating material such as alumina, aluminum oxide, or silicon nitride. The sixth circuit board layer 90 is stacked with the third circuit board layer 30 and is insulated from each other.

[0118] In one embodiment, a fifth insulating layer 550 is stacked between the sixth circuit board layer 90 and the third circuit board layer 30. The fifth insulating layer 550 serves both thermal conductivity and insulation purposes. The material of the fifth insulating layer 550 can be ceramic or epoxy resin-based composite material, etc.

[0119] The first circuit board layer 10, the second circuit board layer 20, the fourth circuit board layer 70, the fifth circuit board layer 80, the third circuit board layer 30, and the sixth circuit board layer 90 are all stacked together, and an insulating layer is provided between them. The fourth circuit board layer 70 and the fifth circuit board layer 80 dissipate heat from the first power chip 610 and the second power chip 620. When the first power chip 610 and the second power chip 620 generate heat during operation, the heat can be dissipated to a larger area through the fourth circuit board layer 70 and the fifth circuit board layer 80, thereby assisting in heat dissipation.

[0120] The fifth circuit board layer 80 transfers the heat generated by the first power chip 610 and the second power chip 620 during operation to the heat sink via the third circuit board layer 30, the fifth insulating layer 550, and the sixth circuit board layer 90, thus achieving heat dissipation for the embedded power module 100. Both the fifth insulating layer 550 and the sixth circuit board layer 90 serve as links in the heat conduction path, dispersing heat and preventing excessive heat concentration near the first power chip 610 and the second power chip 620. This results in a more uniform heat distribution and further enhances the heat dissipation effect.

[0121] Therefore, the embedded power module 100 provided in this application can achieve heat dissipation and reduce parasitic inductance simultaneously with 6 circuit board layers without sacrificing heat dissipation capacity, without the need to increase the number of circuit board layers.

[0122] Please see Figure 12 This application provides an embedded power module 100. The embedded power module 100 includes a first circuit board layer 10, a second circuit board layer 20, and a fourth circuit board layer 70 stacked sequentially. The first circuit board layer 10 is provided with a first DC path 410. The second circuit board layer 20 is provided with an AC path 420. The fourth circuit board layer 70 is provided with a second DC path 430.

[0123] The second DC path 430 located on the fourth circuit board layer 70 is alternately arranged with the AC path 420 located on the second circuit board layer 20. The current direction of the first DC path 410 is opposite to the current direction of the AC path 420 and the current direction of the second DC path 430. The first DC path 410, the AC path 420 and the second DC path 430 are connected.

[0124] In this embodiment, the descriptions of the first circuit board layer 10 and the second circuit board layer 20 can be found in the descriptions of the above embodiments. The descriptions of the first DC path 410, the AC path 420, and the second DC path 430 can also be found in the descriptions of the above embodiments.

[0125] The fourth circuit board layer 70 can be a metal layer or an alloy layer, such as a copper layer, a silver layer, or a copper alloy layer. The fourth circuit board layer 70 and the second circuit board layer 20 are stacked together through a third insulating layer 530. The fourth circuit board layer 70 forms the second DC path 430 through a series of processing techniques (such as photolithography and etching).

[0126] The second DC path 430 located on the fourth circuit board layer 70 and the AC path 420 located on the second circuit board layer 20 are staggered, which can be understood as the second DC path 430 on the fourth circuit board layer 70 and the AC path 420 on the second circuit board layer 20 being in different positions. Furthermore, the staggered arrangement of the second DC path 430 on the fourth circuit board layer 70 and the AC path 420 on the second circuit board layer 20 can cancel out the magnetic field generated by the first DC path 410, thereby reducing the parasitic inductance of the embedded power module 100.

[0127] In the embedded power module 100 provided in this application, a first DC path 410 located on the first circuit board layer 10, an AC path 420 located on the second circuit board layer 20, and a second DC path 430 located on the fourth circuit board layer 70 form stacked parallel current paths. The first DC path 410 on the first circuit board layer 10 and the AC path 420 on the second circuit board layer 20 are current paths in opposite directions, capable of generating magnetic fields in opposite directions. Similarly, the first DC path 410 on the first circuit board layer 10 and the second DC path 430 on the fourth circuit board layer 70 are current paths in opposite directions, capable of generating magnetic fields in opposite directions.

[0128] The first DC path 410, AC path 420, and second DC path 430, located on different circuit board layers, are stacked parallel to each other and generate magnetic fields in opposite directions, allowing the generated magnetic fields to superimpose and cancel each other out. After the magnetic fields in opposite directions superimpose and cancel each other out, the total magnetic field strength is reduced, which reduces the parasitic inductance (also known as stray inductance) of the embedded power module 100 and ensures the safe operation of the embedded power module 100.

[0129] Therefore, the parasitic inductance of the embedded power module 100 provided in this application is reduced, which reduces the voltage spikes during switching, thereby reducing the switching losses of the embedded power module 100, reducing the risk of overvoltage, and further improving the voltage platform of the whole vehicle.

[0130] Please see Figure 12 and Figure 13 In one embodiment, a third conductive recess 615 and a fourth conductive recess 625 are spaced apart within the fourth circuit board layer 70. A first power chip 610 is disposed within the third conductive recess 615. A second power chip 620 is disposed within the fourth conductive recess 625.

[0131] The third conductive recess 615 is connected to the second DC path 430 located on the fourth circuit board layer 70. The first power chip 610 is connected to the AC path 420 located on the second circuit board layer 20. The fourth conductive recess 625 is connected to the AC path 420 located on the second circuit board layer 20. The second power chip 620 is connected to the first DC path 410 located on the first circuit board layer 10.

[0132] In this embodiment, the third conductive recess 615 is provided with a third groove 616, such as Figure 13 As shown. The first power chip 610 is disposed within the third recess 616. The fourth conductive recess 625 has a fourth recess 626. The second power chip 620 is disposed within the fourth recess 626. The third conductive recess 615 and the fourth conductive recess 625 are conductive and can be made of a metallic conductive material, such as copper, aluminum-copper alloy, etc. The third conductive recess 615 enables the connection between the second DC path 430 located on the fourth circuit board layer 70 and the first power chip 610. The fourth conductive recess 625 enables the connection between the AC path 420 located on the second circuit board layer 20 and the second power chip 620.

[0133] The third conductive recess 615 and the fourth conductive recess 625 not only enable the transmission of the required current signal to the first power chip 610 and the second power chip 620, but also facilitate heat dissipation for the first power chip 610 and the second power chip 620. The third conductive recess 615 surrounds the first power chip 610, dissipating the heat generated by the first power chip 610. The fourth conductive recess 625 surrounds the second power chip 620, dissipating the heat generated by the second power chip 620.

[0134] In one embodiment, the embedded power module 100 further includes a first insulating layer 510 and a fifth circuit board layer 80 stacked together. The first insulating layer 510 and the fifth circuit board layer 80 are disposed on the side of the fourth circuit board layer 70 away from the second circuit board layer 20. A first insulating thermally conductive portion 614 and a second insulating thermally conductive portion 624 are disposed at a distance from each other within the first insulating layer 510. A first conductive portion 613 and a second conductive portion 623 are disposed at a distance from each other within the fifth circuit board layer 80.

[0135] The third conductive recess 615, the first insulating and heat-conducting portion 614, and the first conductive portion 613 are disposed opposite to each other. The fourth conductive recess 625, the second insulating and heat-conducting portion 624, and the second conductive portion 623 are disposed opposite to each other.

[0136] In this embodiment, the first insulating layer 510 is disposed between the fourth circuit board layer 70 and the fifth circuit board layer 80, providing insulation between the two layers. A first insulating and heat-conducting portion 614 and a second insulating and heat-conducting portion 624 are spaced apart within the first insulating layer 510. The materials of the first insulating and heat-conducting portion 614 and the second insulating and heat-conducting portion 624 can be ceramic or other materials that can provide both insulation and heat conduction. The materials of the first conductive portion 613 and the second conductive portion 623 can be metallic conductive materials, such as copper or aluminum-copper alloys. In one embodiment, the materials of the first conductive portion 613 and the second conductive portion 623 are the same as the materials of the third conductive recess 615 and the fourth conductive recess 625.

[0137] The third conductive recess 615 and the fourth conductive recess 625 are conductive, allowing signals to be transmitted to the first power chip 610 and the second power chip 620. Furthermore, the heat generated by the first power chip 610 and the second power chip 620 can be transferred to the first insulating heat-conducting part 614 and the second insulating heat-conducting part 624 respectively through the third conductive recess 615 and the fourth conductive recess 625. The first insulating heat-conducting part 614 is positioned opposite to the first conductive part 613, allowing heat to be transferred from the first insulating heat-conducting part 614 to the first conductive part 613. The second insulating heat-conducting part 624 is positioned opposite to the second conductive part 623, allowing heat to be transferred from the second insulating heat-conducting part 624 to the second conductive part 623, thus achieving heat dissipation.

[0138] Furthermore, the third conductive recess 615, the first insulating and thermally conductive portion 614, and the first conductive portion 613 are arranged opposite to each other, serving as a heat conduction path for the first power chip 610 to diffuse heat and prevent excessive heat concentration around the first power chip 610. Similarly, the fourth conductive recess 625, the second insulating and thermally conductive portion 624, and the second conductive portion 623 are arranged opposite to each other, serving as a heat conduction path for the second power chip 620 to diffuse heat and prevent excessive heat concentration around the second power chip 620. The embedded power module 100 provided in this application enables heat dissipation, further enhancing the heat dissipation effect.

[0139] Please see Figure 14 In one embodiment, the second circuit board layer 20 is provided with an AC path 420 and a second DC path 430 spaced apart. The second DC path 430 located on the fourth circuit board layer 70, the AC path 420 located on the second circuit board layer 20, and the second DC path 430 located on the second circuit board layer 20 are arranged alternately.

[0140] In this embodiment, the second circuit board layer 20 is provided with an AC path 420 and a second DC path 430 at intervals. For a related description, please refer to the relevant description in the above embodiment.

[0141] The second DC path 430 located on the fourth circuit board layer 70, the AC path 420 located on the second circuit board layer 20, and the second DC path 430 located on the second circuit board layer 20 are staggered, which can jointly cancel the magnetic field generated by the first DC path 410, thereby reducing the parasitic inductance of the embedded power module 100.

[0142] Therefore, the parasitic inductance of the embedded power module 100 provided in this application is reduced, which reduces the voltage spikes during switching, thereby reducing the switching losses of the embedded power module 100, reducing the risk of overvoltage, and further improving the voltage platform of the whole vehicle.

[0143] This application provides a smart device, including at least one embedded power module 100 as described in any of the above embodiments.

[0144] In this embodiment, multiple embedded power modules 100 can be integrated to form a three-phase full-bridge power module. In electric vehicles and hybrid vehicles, the three-phase full-bridge power module can be applied to the motor control of the inverter system of intelligent devices. As a key component of the drive motor, it can convert the DC power supplied by the battery into three-phase AC power to provide power to the drive motor. Intelligent devices can be vehicles, driving equipment, robots, flying cars, electric aircraft, and other similar devices.

[0145] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. In the above embodiments, the descriptions of each embodiment have different focuses; parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0146] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0147] The division of modules or units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections through interfaces, devices, or units, and may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate; the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Additionally, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0148] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An embedded power module, characterized in that, include: The first circuit board layer (10), the second circuit board layer (20), and the third circuit board layer (30) are stacked in sequence. The first circuit board layer (10) is provided with a first DC path (410); The second circuit board layer (20) is provided with an AC path (420) and the first DC path (410) or the second DC path (430) at intervals. The third circuit board layer (30) is provided with the second DC path (430) and the AC path (420) spaced apart, and the AC path (420) located on the third circuit board layer (30) and the AC path (420) located on the second circuit board layer (20) are arranged alternately. The current direction of the first DC path (410) is opposite to the current direction of the AC path (420) and the current direction of the second DC path (430); the first DC path (410), the AC path (420) and the second DC path (430) are connected. The embedded power module further includes a chip mounting layer, which is disposed between the second circuit board layer (20) and the third circuit board layer (30). A first power chip (610) and a second power chip (620) are disposed at intervals in the chip mounting layer. The first DC path (410) located on the first circuit board layer (10) is connected to the first DC path (410) or the second DC path (430) located on the second circuit board layer (20) through a first via; the first DC path (410) or the second DC path (430) is connected to the AC path (420) located on the third circuit board layer (30) through the second power chip (620); the AC path (420) is connected to the AC path (420) located on the second circuit board layer (20) through a second via; the AC path (420) located on the second circuit board layer (20) is connected to the second DC path (430) located on the third circuit board layer (30) through the first power chip (610).

2. The embedded power module as described in claim 1, characterized in that, The chip mounting layer includes a fourth circuit board layer (70), a first insulating layer (510), and a fifth circuit board layer (80) stacked together.

3. The embedded power module as described in claim 2, characterized in that, The chip mounting layer is provided with a first conductive recess (611) and a second conductive recess (621) spaced apart. The first power chip (610) is disposed in the first conductive recess (611), and the second power chip (620) is disposed in the second conductive recess (621); The first conductive recess (611) is connected to the second DC path (430) located on the third circuit board layer (30), the first power chip (610) is connected to the AC path (420) located on the second circuit board layer (20), the second conductive recess (621) is connected to the AC path (420) located on the third circuit board layer (30), and the second power chip (620) is connected to the first DC path (410) located on the second circuit board layer (20) or the second DC path (430) located on the second circuit board layer (20).

4. The embedded power module as described in claim 2, characterized in that, The DC current signal flows from the second DC path (430) to the first DC path (410).

5. The embedded power module as described in claim 4, characterized in that, The drain of the first power chip (610) is connected to the second DC path (430), and the source of the first power chip (610) is connected to the AC path (420) located on the second circuit board layer (20). The drain of the second power chip (620) is connected to the AC path (420) located on the third circuit board layer (30), and the source of the second power chip (620) is connected to the first DC path (410) or the second DC path (430) located on the second circuit board layer (20).

6. The embedded power module as described in claim 2, characterized in that, The DC current signal flows from the first DC path (410) to the second DC path (430).

7. The embedded power module as described in any one of claims 1 to 6, characterized in that, The first DC path (410) is positioned opposite the second DC path (430), and the first DC path (410) is positioned opposite the AC path (420).

8. The embedded power module as described in any one of claims 1 to 6, characterized in that, The sum of the paths of the second DC path (430) and the AC path (420) is the same as that of the first DC path (410).

9. The embedded power module as described in any one of claims 1 to 6, characterized in that, The first circuit board layer (10) is provided with a first drive signal path (440) and a second drive signal path (450), and the first drive signal path (440), the second drive signal path (450) and the first DC path (410) are arranged at intervals.

10. The embedded power module as described in claim 1, characterized in that, The embedded power module further includes: The sixth circuit board layer (90) is stacked on the side of the third circuit board layer (30) away from the second circuit board layer (20).

11. An embedded power module, characterized in that, include: The first circuit board layer (10), the second circuit board layer (20), and the fourth circuit board layer (70) are stacked in sequence. The first circuit board layer (10) is provided with a first DC path (410); The second circuit board layer (20) is provided with an AC path (420); The fourth circuit board layer (70) is provided with a second DC path (430), located on the fourth circuit board layer (70). The second DC path (430) located on the fourth circuit board layer (70) is interleaved with the AC path (420) located on the second circuit board layer (20). The current direction of the first DC path (410) is opposite to the current direction of the AC path (420) and the current direction of the second DC path (430); the first DC path (410), the AC path (420) and the second DC path (430) are connected. The fourth circuit board layer (70) is provided with a third conductive recess (615) and a fourth conductive recess (625) spaced apart. The third conductive recess (615) is provided with a first power chip (610) and the fourth conductive recess (625) is provided with a second power chip (620). The third conductive recess (615) is connected to the second DC path (430) located on the fourth circuit board layer (70), the first power chip (610) is connected to the AC path (420) located on the second circuit board layer (20), the fourth conductive recess (625) is connected to the AC path (420) located on the second circuit board layer (20), and the second power chip (620) is connected to the first DC path (410) located on the first circuit board layer (10).

12. The embedded power module as described in claim 11, characterized in that, The second circuit board layer (20) is provided with the AC path (420) and the second DC path (430) spaced apart. The second DC path (430) located on the fourth circuit board layer (70), the AC path (420) located on the second circuit board layer (20), and the second DC path (430) located on the second circuit board layer (20) are arranged alternately.

13. The embedded power module as described in claim 11, characterized in that, The embedded power module further includes a first insulating layer (510) and a fifth circuit board layer (80) stacked together, wherein the first insulating layer (510) and the fifth circuit board layer (80) are disposed on the side of the fourth circuit board layer (70) away from the second circuit board layer (20); The first insulating layer (510) is provided with a first insulating heat-conducting part (614) and a second insulating heat-conducting part (624) spaced apart. The fifth circuit board layer (80) is provided with a first conductive part (613) and a second conductive part (623) spaced apart. The third conductive recess (615), the first insulating and heat-conducting portion (614), and the first conductive portion (613) are arranged opposite to each other, and the fourth conductive recess (625), the second insulating and heat-conducting portion (624), and the second conductive portion (623) are arranged opposite to each other.

14. A smart device, characterized in that, It includes at least one embedded power module as described in any one of claims 1 to 13.

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