Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device including highly integrated memory cells and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes: a memory cell array; a dummy region including a dummy stack horizontally spaced apart from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and the dummy region; a stack stage plug passing through the dummy stack; and a stack stage spacer formed on a sidewall of the stack stage plug.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application Nos. 10 - 2023 - 0178842 and 10 - 2024 - 0169960, filed on December 11, 2023, and November 25, 2024, respectively, which are incorporated herein by reference in their entirety. Technical field

[0003] Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including three - dimensional (3D) memory cells and a method of manufacturing the semiconductor device. Background art

[0004] To meet the requirements of large capacity and miniaturization of memory devices, a technology for providing a three - dimensional (3D) memory device in which a plurality of memory cells are stacked has been recently disclosed. Summary of the invention

[0005] Embodiments of the present disclosure relate to a semiconductor device including highly integrated memory cells and a method of manufacturing the semiconductor device.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a memory cell array; a dummy region including a dummy stack horizontally spaced apart from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and the dummy region; a stack - level plug passing through the dummy stack; and a stack - level spacer formed on a sidewall of the stack - level plug.

[0007] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a memory cell array and a dummy stack on a first substrate, the memory cell array and the dummy stack being horizontally spaced apart from each other; forming a stack - level contact hole to penetrate the dummy stack; forming a stack - level spacer on a sidewall of the stack - level contact hole; and forming a stack - level plug on the stack - level spacer to fill the stack - level contact hole.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a memory cell array disposed on a first substrate; a second substrate including a front surface and a back surface, and being flipped to face the memory cell array; a peripheral circuit formed on the front surface of the second substrate; and a back - side interconnect structure passing through the second substrate from the back surface of the second substrate and coupled to the peripheral circuit.

[0009] According to another embodiment of the present disclosure, a semiconductor device includes: a peripheral circuit region; a memory cell array including vertical wires disposed over the peripheral circuit region, a plurality of data storage elements, and a common plate line commonly coupled to the data storage elements. The semiconductor device further includes: a substrate formed over an upper portion of the common plate line; a nano via configured to penetrate the substrate to expose the upper portion of the common plate line; a nano spacer formed on sidewalls of the nano via; a nano silicon via configured to fill the nano via over the nano spacer; an upper layer interconnect located over the nano silicon via; a lower layer interconnect coupled to a lower portion of the vertical wire; a first bonding pad coupled to the lower layer interconnect; and a second bonding pad coupled to the first bonding pad and coupled to the peripheral circuit region. The semiconductor device may include: a dummy region including a dummy stack horizontally spaced apart from the memory cell array; a stack level plug configured to penetrate the dummy stack; and a stack level spacer formed on sidewalls of the stack level plug.

[0010] According to another embodiment of the present disclosure, a semiconductor device includes: a memory cell array disposed over a front surface of a first substrate; a backside interconnect structure disposed at a level higher than the memory cell array; a second substrate having a front surface facing the memory cell array and a back surface facing the backside interconnect structure; a control circuit including one or more transistors, the control circuit disposed over the front surface of the second substrate; and a multi-layer metal wire including one or more metal wires coupled to the control circuit. The backside interconnect structure may include: a power supply interconnect embedded inside one side of the front surface of the second substrate; a power supply via configured to penetrate the back surface of the second substrate to be coupled to the power supply interconnect; a power supply contact plug coupled to the power supply interconnect and the control circuit; and a power supply level spacer formed on sidewalls of the power supply interconnect and the power supply via.

[0011] According to an embodiment of the present invention, a semiconductor device may include: a first substrate; a memory cell array including memory cells vertically stacked over the first substrate; a second substrate including a front surface facing the memory cell array and a back surface located at a level higher than the front surface, and including a plurality of control circuits for controlling the memory cells; a backside power distribution network passing through the second substrate and supplying power from the back surface of the second substrate to the control circuits, wherein the backside power distribution network may include: an embedded power rail embedded in the front surface of the second substrate; a nano silicon via passing through the back surface of the second substrate and coupled to the embedded power rail; a power supply level spacer formed on sidewalls of the nano silicon via and the embedded power rail; and an embedded power rail via disposed on the front surface of the second substrate and coupled to the embedded power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1Ais a schematic perspective view showing a storage cell according to an embodiment of the present disclosure.

[0013] Figure 1B is a schematic sectional view showing Figure 1A the storage cell shown in

[0014] Figure 1C is a plan view showing Figure 1A the switching element shown in

[0015] Figure 1D is a schematic sectional view showing a storage cell according to another embodiment of the present disclosure.

[0016] Figure 2A is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 2B is a schematic perspective view showing Figure 2A the storage cell array MCA shown in

[0018] Figure 2C is a schematic sectional view taken along line A - A' shown in Figure 2A

[0019] Figure 2D is a schematic sectional view taken along line B - B' shown in Figure 2A

[0020] Figure 3 is a schematic sectional view showing a semiconductor device 200 according to another embodiment of the present disclosure.

[0021] Figures 4 to 22 shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0022] Figures 23 to 27 shows a method for manufacturing a pad portion according to an embodiment of the present disclosure.

[0023] Figures 28 to 33 shows Figure 3 the method for manufacturing a semiconductor device shown in

[0024] Figures 34 to 36 shows a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0025] Figures 37 to 39 is a perspective view showing a semiconductor device according to another embodiment of the present disclosure.

[0026] Figure 40 is a sectional view showing a storage cell array according to another embodiment of the present disclosure. ​​

[0027] Figures 41 to 45 A semiconductor device according to another embodiment of the present disclosure is shown. Detailed Description of Specific Embodiments

[0028] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same components in the multiple drawings and embodiments of the present disclosure.

[0029] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0030] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments of the present disclosure. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer is present between the first layer and the second layer or between the first layer and the substrate.

[0031] The following embodiments of the present disclosure relate to three-dimensional memory cells, which can increase the memory cell density and reduce the parasitic capacitance by vertically stacking the memory cells.

[0032] Figure 1A is a schematic perspective view showing a memory cell MC according to an embodiment of the present disclosure. Figure 1B is showing Figure 1A a schematic cross-sectional view of the memory cell MC. Figure 1C is showing Figure 1A a plan view of the switching element.

[0033] Referring to Figures 1A to 1C , the memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0034] The first wire BL may be vertically oriented along a first direction D1. The first wire BL may include bit lines. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. For example, the first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0035] The switching element TR may have a function of controlling the voltage (or current) supplied to the data storage element CAP during a data writing operation and a data reading operation for the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line. The horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0036] The horizontal layer HL may extend in a second direction D2 that intersects a first direction D1. The second wire DWL may extend in a third direction D3 that intersects the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), while the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0037] The horizontal layer HL may be horizontally oriented in the second direction D2 starting from a first wire BL. The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 that face each other, with the horizontal layer HL therebetween. The interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL, and the lower horizontal line G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of the upper horizontal line G1 and the lower horizontal line G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 may form a pair coupled to a single memory cell MC. According to another embodiment of the present disclosure, different driving voltages may be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 may be used as a back gate or a shielding gate.

[0038] Return reference Figure 1C, the width of each of the upper horizontal line G1 and the lower horizontal line G2 in the second direction D2 (e.g., the width of the overlapping portion overlapping with the horizontal layer HL) can be greater than the width of the non-overlapping portion that does not overlap with the horizontal layer HL. Due to this width difference, the second wire DWL can have a notched sidewall. The second wire DWL can include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP can refer to the portion overlapping with the channel CH of the horizontal layer HL. The channel non-overlapping portion NOL can refer to the portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP can have a cross shape or a rhombus shape.

[0039] Viewed from a top-down perspective, the horizontal layer HL can have a cross shape or a rhombus shape. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL can have a curved shape or a circular shape.

[0040] The horizontal layer HL can include a semiconductor material. For example, the horizontal layer HL can include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present disclosure, the horizontal layer HL can include an oxide semiconductor material. For example, the oxide semiconductor material can include indium gallium zinc oxide (IGZO). According to another embodiment of the present disclosure, the horizontal layer HL can include a conductive metal oxide.

[0041] The upper surface and the lower surface of the horizontal layer HL can have flat surfaces. The upper surface and the lower surface of the horizontal layer HL can be parallel to each other in the second direction D2.

[0042] The horizontal layer HL can include a channel CH, a first doped region SR located between the channel CH and the first wire BL, and a second doped region DR located between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH can be formed of an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The horizontal layer HL can also be referred to as an active layer or a thin body. The channel CH and the channel overlapping portion WLP of the second wire DWL can overlap with each other. The channel CH can have a cross shape or a rhombus shape. The size of the channel overlapping portion WLP of the second wire DWL can be larger than the size of the channel CH. The channel overlapping portion WLP of the second wire DWL can completely overlap with the channel CH.

[0043] The first doped region SR and the second doped region DR can be doped with impurities of the same conduction type. The first doped region SR and the second doped region DR can be doped with N-type conductive impurities or P-type conductive impurities. The first doped region SR and the second doped region DR can include at least one impurity selected from the group consisting of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR can be coupled to the first wire BL, and the second doped region DR can be coupled to the data storage element CAP. The first doped region SR and the second doped region DR can be respectively referred to as the first source / drain region and the second source / drain region.

[0044] The interlayer dielectric layer GD can be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD can also be referred to as the gate dielectric layer. The interlayer dielectric layer GD can also be referred to as the horizontal layer side dielectric layer. The interlayer dielectric layer GD can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or combinations thereof. The interlayer dielectric layer GD can include SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZrO 2 , AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The interlayer dielectric layer GD can be formed by a thermal oxidation process of a semiconductor material.

[0045] The second wire DWL can include a metal-based material, a semiconductor material, or combinations thereof. The second wire DWL can include titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the second wire DWL can include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The second wire DWL can include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or less. The P-type work function material can have a high work function of about 4.5 eV or greater. The second wire DWL can include a stack of a low work function material and a high work function material.

[0046] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed in a second direction D2 starting from the switching element TR. The data storage element CAP may include a first electrode SN that horizontally extends in the second direction D2 starting from a horizontal layer HL. The data storage element CAP may further include a second electrode PN located above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed in the second direction D2. The first electrode SN may include an internal space and a plurality of outer surfaces. The internal space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN may vertically extend in a first direction D1, and the horizontal outer surfaces of the first electrode SN may horizontally extend in the second direction D2 or a third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN above the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to a second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to a common plate PL.

[0047] The data storage element CAP may be a three-dimensional structure. The first electrode SN may have a three-dimensional structure that may be a horizontally oriented three-dimensional structure in the second direction D2. In an example of the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0048] According to another embodiment of the present disclosure, the first electrode SN may have a columnar or columnar-cylindrical shape. The columnar-cylindrical shape may refer to a structure in which a columnar shape and a cylindrical shape are combined.

[0049] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 )), iridium (Ir), iridium oxide (IrO 2)), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / titanium silicon nitride (TiSiN) stack, titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0050] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, high-k materials, or a combination thereof. High-k materials may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0051] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO 2 ). The dielectric layer DE may include a ZA (ZrO 2 / Al 2 O 3 ) stack or a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack may have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on zirconium oxide (ZrO 2 ). The ZAZ stack may have a structure in which zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide (ZrO 2 ) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as zirconium oxide (ZrO 2)Base layer. According to another embodiment of the present disclosure, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can be a stacked structure including hafnium oxide (HfO 2 ). The dielectric layer DE can include a HA (HfO 2 / Al 2 O 3 ) stack or a HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack can have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on hafnium oxide (HfO 2 ). The HAH stack can have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and hafnium oxide (HfO 2 ) are stacked in sequence. The HA stack and the HAH stack can be referred to as hafnium oxide (HfO 2 ) base layers. Among the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, aluminum oxide (Al 2 O 3 ) can have a bandgap energy larger than that of zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Aluminum oxide (Al 2 O 3 ) can have a dielectric constant lower than that of zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a bandgap energy larger than that of the high-k material. In addition to aluminum oxide (Al 2 O 3 ), the dielectric layer DE can also include silicon oxide (SiO 2 ) as another high-bandgap material. By including the high-bandgap material, the dielectric layer DE can suppress leakage current. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present disclosure, the dielectric layer DE can include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, a ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al2 O 2 / ZrO 2 ) stacked, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stacked, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stacked, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) stacked, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) stacked, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) stacked or AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / Al 2 O 3 ) stacked. In the above stacking structure, aluminum oxide (Al 2 O 3 ) can be thinner than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ).

[0052] According to another embodiment of the present disclosure, the dielectric layer DE may include a high-k material and a high bandgap material. The dielectric layer DE may have a stacked structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a hybrid structure in which the high-k material and the high bandgap material are mixed with each other.

[0053] According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0054] According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material. According to another embodiment of the present disclosure, the dielectric layer DE may include a perovskite dielectric material. The perovskite dielectric material may include SrTiO 3 , (Ba,Sr)TiO 3 , BaTiO 3 , PbTiO 3 , PZT, PLZT or PbTiO 3 .

[0055] According to another embodiment of the present disclosure, an interface control layer for reducing leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0056] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0057] For example, the storage unit MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced with an anode wire. The horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode connected in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high-conductance state with a large current flowing or a low-conductance state with a small current flowing or no current flowing. The storage unit MC according to an embodiment of the present disclosure may have a "1" state and a "0" state respectively according to the high-conductance state and the low-conductance state of the thyristor.

[0058] Return reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first wire BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0059] Figure 1D is a schematic cross-sectional view showing a memory cell MC1 according to another embodiment of the present disclosure. Figure 1D The memory cell MC1 may be similar to Figures 1A to 1C The memory cell MC. Herein, a detailed description of the constituent elements that also appear in Figures 1A to 1C may be omitted.

[0060] The memory cell MC1 may include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0061] The memory cell MC1 may further include a first contact node BLC between the first wire BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0062] The second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be horizontally arranged in the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first wire BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The thickness of the horizontal layer HL may be less than the thickness of each of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0063] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of different work function materials. The first work function electrode G11 may have a work function higher than that of the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function greater than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include low work function materials. The second work function electrode G12 and the third work function electrode G13 may have a work function less than the mid-gap work function of silicon. Specifically, the high work function material may have a work function greater than about 4.5 eV, while the low work function material may have a work function less than about 4.5 eV. The first work function electrode G11 may include a metal-based material, while the second work function electrode G12 and the third work function electrode G13 may include semiconductor materials.

[0064] The second work function electrode G12 and the third work function electrode G13 may include polysilicon doped with an N-type dopant, i.e., N-type dopant-doped polysilicon. The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may be further formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0065] According to an embodiment of the present disclosure, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a second work function electrode G12, a first work function electrode G11, and a third work function electrode G13 that are sequentially and horizontally arranged in the second direction D2. The first work function electrode G11 may include a metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0066] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a polysilicon-metal-polysilicon (PMP) structure in which polysilicon, metal, and polysilicon are horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may be polysilicon doped with an N-type dopant. The N-type dopant may include phosphorus or arsenic.

[0067] A first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. A second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface, and one side surface of the first work function electrode G11.

[0068] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13. Therefore, the second wire DWL may have a low resistance. The first work function electrodes G11 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The second work function electrodes G12 and the third work function electrodes G13 of the upper horizontal line G1 and the lower horizontal line G2 may also vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The overlapping portion of the first work function electrode G11 and the horizontal layer HL may be larger than the overlapping portions of the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrode G13 may have an independent structure overlapping with the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlapping portion WLP and a channel non-overlapping portion NOL, and the second work function electrode G12 and the third work function electrode G13 may be a part of the channel overlapping portion WLP. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may be in direct contact with each other.

[0069] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a triple work function electrode structure including the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13, which extend in the third direction D3 intersecting with the horizontal layer HL, and the horizontal layer HL is interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap with the channel CH.

[0070] As shown Figure 1C each second conductor DWL may include a channel overlap portion WLP and a channel non - overlap portion NOL. The channel overlap portion WLP may have a cross - shaped or diamond - shaped form. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may have a notch - shaped sidewall caused by the channel overlap portion WLP and the channel non - overlap portion NOL. From a top - down perspective, the notch - shaped sidewall may be provided by a protruding portion formed by the channel overlap portion WLP and a recessed portion formed by the channel non - overlap portion NOL. The channel overlap portion WLP may include a first work - function electrode G11, a second work - function electrode G12, and a third work - function electrode G13. The first work - function electrode G11, the second work - function electrode G12, and the third work - function electrode G13 may vertically overlap with the channel CH.

[0071] In the second direction D2, the first work - function electrode G11 having a high work function may be disposed at the center of the second conductor DWL, while the second work - function electrode G12 and the third work - function electrode G13 having low work functions may be disposed at both end portions of the second conductor DWL, thereby reducing leakage current, such as gate - induced drain leakage (GIDL).

[0072] By disposing the first work - function electrode G11 having a high work function at the center of the second conductor DWL, the threshold voltage of the switching element TR can be increased. Since the second work - function electrode G12 of the second conductor DWL has a low work function, a low electric field can be formed between the first conductor BL and the second conductor DWL. Since the third work - function electrode G13 of the second conductor DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second conductor DWL.

[0073] As described above, the memory cell MC1 may include a second wire DWL having a triple work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap with the channel CH. The second work function electrode G12 may be disposed adjacent to the first wire BL and the first doped region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, which may reduce the leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, which may reduce the leakage current. Due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR may be increased. In addition, due to the high work function of the first work function electrode G11, the height of the memory cell MC1 may be reduced, which is advantageous in terms of integration.

[0074] Figure 2A is a schematic plan view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2B is shown Figure 2A of the memory cell array MCA. Figure 2C is along Figure 2A The schematic cross-sectional view taken along the line A-A' shown in. Figure 2D is along Figure 2A The schematic cross-sectional view taken along the line B-B' shown in.

[0075] Reference Figure 2A , Figure 2B , Figure 2C and Figure 2D , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. Each memory cell MC may be described with reference to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP. According to another embodiment of the present disclosure, each memory cell MC may be the same as the memory cell MC1 of Figure 1D . The switching element TR may include a second wire DWL and a horizontal layer HL.

[0076] The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may be a region where the memory cell MC is formed, and the second region CTA may be a region where a unit contact plug WC coupled to the second wire DWL of the memory cell MC is formed.

[0077] The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. For example, the memory cell array MCA may include a plurality of column arrays. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1. The row array of memory cells MC may include a plurality of memory cells MC horizontally arranged in a second direction D2 and a third direction D3.

[0078] The memory cell array MCA may include a plurality of first mirror-type sub-cell arrays and a plurality of second mirror-type sub-cell arrays. The first mirror-type sub-cell array may include a mirror structure in which two adjacent memory cells MC in the second direction D2 share a first wire BL. The second mirror-type sub-cell array may include a mirror structure in which two memory cells MC share a second electrode PN of a data storage element CAP in the second direction D2.

[0079] The inter-cell dielectric layer IL may be disposed between memory cells MC stacked in the first direction D1. The cell isolation layers ISOA and ISOB may be disposed between memory cells MC adjacent to each other in the third direction D3. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The cell isolation layer may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly arranged in the second direction D2. The first cell isolation layer ISOA may be disposed between data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between first wires BL in the third direction D3. The second wire DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2.

[0080] The memory cell array MCA may be disposed on a first substrate W1.

[0081] The memory cell array MCA may include a plurality of first wires BL extending vertically in the first direction D1. The memory cell array MCA may include a plurality of second wires DWL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include an alternating stack of second wires DWL and inter-cell dielectric layers IL stacked in the first direction D1.

[0082] Each second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with a horizontal layer HL therebetween. An interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL, and the lower horizontal line G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal line G1 and lower horizontal line G2. Each second wire DWL may include a channel overlap portion WLP as Figure 1C shown. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second wire DWL extending along the third direction D3 may include a plurality of channel overlap portions WLP. The second wire DWL may have a notch-shaped sidewall due to the channel overlap portion WLP.

[0083] A plurality of first passivation layers BF1 may be disposed between the lowermost second wire DWL in the second wire DWL and the first substrate W1. A second passivation layer BF2 may be disposed between the first wire BL and the first substrate W1. A third passivation layer BF3 may be disposed between the data storage element CAP and the first substrate W1. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first wire BL, the second wire DWL, and the data storage element CAP from the first substrate W1.

[0084] The first wire BL may vertically extend from the upper portion of the first substrate W1 along the first direction D1. The horizontal layer HL may extend along a second direction D2 intersecting the first direction D1. The second wire DWL may extend along a third direction D3 intersecting the first direction D1 and the second direction D2.

[0085] The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP. Viewed from above, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL may have a curved shape or a circular shape. As Figure 1B and Figure 2C shown, the horizontal layer HL may include a channel CH.

[0086] The first capping layer BC can be disposed between the second wire DWL and the first wire BL. The second capping layer CC can be disposed between the second wire DWL and the first electrode SN of the data storage element CAP. The first capping layer BC can be disposed between the upper horizontal line G1 and the first wire BL. In addition, the first capping layer BC can also be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC can be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP. In addition, the second capping layer CC can also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP.

[0087] The first capping layer BC and the second capping layer CC can include a dielectric material. The first capping layer BC and the second capping layer CC can include silicon oxide, silicon nitride, silicon carbon oxide, air gap, or a combination thereof. The first capping layer BC and the second capping layer CC can include a stack of silicon oxide and silicon nitride.

[0088] The horizontal layer HL of the switching element TR disposed horizontally along the third direction D3 can share a second wire DWL. The horizontal layer HL of the switching element TR disposed horizontally along the third direction D3 can be coupled to different first wires BL. The switching elements TR stacked along the first direction D1 can share a first wire BL. The switching elements TR disposed horizontally along the third direction D3 can share a second wire DWL.

[0089] The first unit isolation layer ISOA can be disposed in the third direction D3 between the first electrodes SN of the data storage elements CAP. The first electrodes SN can be separated from each other by the first unit isolation layer ISOA. The second electrode PN of the data storage element CAP can be coupled to a common plate PL. The second electrodes PN of the data storage elements CAP can be combined into a common plate PL.

[0090] The first unit isolation layer ISOA can be disposed in the third direction D3 between the data storage elements CAP. The second unit isolation layer ISOB can be disposed in the third direction D3 between the vertical wires BL. The second wire DWL can be disposed in the second direction D2 between the first unit isolation layer ISOA and the second unit isolation layer ISOB.

[0091] The first substrate W1 can be a material suitable for semiconductor processing. The first substrate W1 can include one or more of a conductive material, a dielectric material, and a semiconductor material. A variety of materials can be formed on the first substrate W1. The first substrate W1 can include a semiconductor substrate. The first substrate W1 can be formed of a silicon-containing material. The first substrate W1 can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. The first substrate W1 can include other semiconductor materials, such as germanium. The first substrate W1 can include a group III-V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). The first substrate W1 can include a silicon-on-insulator (SOI) substrate.

[0092] According to another embodiment of the present disclosure, the memory cell array MCA can include a dynamic random access memory (DRAM), an embedded DRAM, NAND, a ferroelectric random access memory (FeRAM), a spin transfer torque random access memory (STT-RAM), a phase change RAM (PCRAM), or a resistive RAM (ReRAM).

[0093] Reference Figure 2D , the second wire DWL can be disposed in the first region CA, and a portion of the second wire DWL can extend to the second region CTA. The portion of the second wire DWL disposed in the second region CTA can be referred to as a pad portion WLE, an edge portion, or a pad stack. The stack of the second wire DWL can include a first stack and a second stack. The first stack can be the portion formed in the first region CA, and the second stack can be the portion formed in the second region CTA. Figure 2A One side of the pad portion WLE of can be covered by an interlayer dielectric layer ILD.

[0094] The pad portion WLE of the second wire DWL can include multiple layers L1, L2, L3, and L4. In the pad portion WLE, each horizontal wire DWL of the layers L1 to L4 can include a pair of upper horizontal lines G1 and lower horizontal lines G2. In the pad portion WLE, the layers L1 to L4 can further include pad GPs. The pad GPs can be disposed between the upper horizontal line G1 and the lower horizontal line G2. Each pad GP can be electrically connected to the upper horizontal line G1 and the lower horizontal line G2.

[0095] The lateral lengths of the pad GPs in the third direction D3 can be different from each other. For example, the lateral length of the pad GP can gradually decrease as it goes from the fourth layer L4 to the first layer L1 in the first direction D1.

[0096] The pad GPs and the horizontal layer HL can be spaced apart from each other. The pad GPs can not be disposed in the first region CA.

[0097] The pad GP, the upper horizontal line G1, and the lower horizontal line G2 may include the same material. The pad GP, the upper horizontal line G1, and the lower horizontal line G2 may include a metal-based material. For example, the pad GP, the upper horizontal line G1, and the lower horizontal line G2 may include titanium nitride, tungsten, or a combination thereof.

[0098] The second region CTA may include contact plugs WC1, WC2, WC3, and WC4 respectively coupled to the second wire DWL of the pad portion WLE.

[0099] The second region CTA may include a pad portion WLE in which the first wire DWL and the inter-cell dielectric layer IL are alternately stacked. The second region CTA may include an array of contact plugs WC1, WC2, WC3, and WC4 disposed in the pad portion WLE, which are laterally spaced apart from each other in the second horizontal direction (i.e., the third direction D3) and have different heights. The top surfaces of the contact plugs WC1, WC2, WC3, and WC4 may be disposed on the same horizontal plane, and the bottoms of the contact plugs WC1, WC2, WC3, and WC4 may be adjacent to the second wire DWL respectively.

[0100] The first contact plug WC1 may be electrically connected to the second wire DWL of the first layer L1. The first contact plug WC1 may be electrically connected to the upper horizontal line G1 of the first layer L1. The second contact plug WC2 may be electrically connected to the second wire DWL of the second layer L2. The second contact plug WC2 may be electrically connected to the upper horizontal line G1 of the second layer L2 through the cell insulation layer IL. The third contact plug WC3 may be electrically connected to the second wire DWL of the third layer L3. The third contact plug WC3 may be electrically connected to the upper horizontal line G1 of the third layer L3 through the cell insulation layer IL. The fourth contact plug WC4 may be electrically connected to the second wire DWL of the fourth layer L4. The fourth contact plug WC4 may be electrically connected to the upper horizontal line G1 of the fourth layer L4 through the cell insulation layer IL.

[0101] The vertical height of the fourth contact plug WC4 may be greater than the vertical height of the third contact plug WC3, and the vertical height of the third contact plug WC3 may be greater than the vertical height of the second contact plug WC2. The vertical height of the second contact plug WC2 may be greater than the vertical height of the first contact plug WC1. Here, the vertical height may refer to the height in the first direction D1.

[0102] As described above, the pad portion WLE of the second wire DWL may have a stepped structure.

[0103] Figure 3 is a schematic cross-sectional view showing a semiconductor device 200 according to another embodiment of the present disclosure.

[0104] Reference Figure 3, the semiconductor device 200 may include a memory cell array MCA, a peripheral circuit region PA1, and a dummy region PA2. The memory cell array MCA may be disposed at a level higher than that of the peripheral circuit region PA1. The dummy region PA2 may be horizontally spaced apart from the memory cell array MCA. For a detailed description of the Figure 3 memory cell array MCA, reference may be made to Figures 2A to 2D .

[0105] The memory cell array MCA and the dummy region PA2 may be formed on a first substrate W1. The peripheral circuit region PA1 may be formed on a second substrate W2. The memory cell array MCA may include a three-dimensional array of memory cells MC, and the three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. For a detailed description of the memory cells MC, reference may be made to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP. According to another embodiment of the present disclosure, each memory cell MC may be the same as the Figure 1D memory cell MC1. The memory cell array MCA may include a plurality of first wires BL vertically extending along a first direction D1. The memory cell array MCA may include a plurality of second wires DWL vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked along the first direction D1. The memory cell array MCA may include an alternating stack of second wires DWL and inter-cell dielectric layers IL stacked along the first direction D1.

[0106] The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may have memory cells MC formed therein, and the second region CTA may have cell contact plugs WC formed therein. In the second region CTA, a pad portion WLE of the second wire DWL may be provided, and the second wire DWL of the pad portion WLE may be coupled to the cell contact plug WC. The second wire DWL of the pad portion WLE may have a stepped structure. An interlayer dielectric layer ILD may be formed over the pad portion WLE, and the cell contact plug WC passes through the interlayer dielectric layer ILD.

[0107] The peripheral circuit region PA1 may include a semiconductor substrate, a metal interconnect structure, an insulating structure, a conductive structure, another memory, or a peripheral circuit portion.

[0108] Reference Figure 3, the peripheral circuit region PA1 can be set at a level lower than the memory cell array MCA. This can be referred to as a Cell-over-PERI (COP) structure. The first substrate W1 is flipped to bond the memory cell array MCA to the peripheral circuit region PA1.

[0109] The peripheral circuit region PA1 can be coupled to the memory cell array MCA. The peripheral circuit region PA1 can include one or more control circuits for driving the memory cell array MCA. One or more control circuits of the peripheral circuit portion can include N-channel transistors, P-channel transistors, CMOS circuits, or combinations thereof. One or more control circuits of the peripheral circuit portion can include an address decoder circuit, a read circuit, a write circuit, etc. One or more control circuits of the peripheral circuit portion can include planar channel transistors, recessed channel transistors, buried gate transistors, fin channel transistors (FinFETs), etc.

[0110] For example, the peripheral circuit region PA1 can include a plurality of control circuits formed on the second substrate W2. For example, the peripheral circuit region PA1 can include a sub-word line driver SWD and a sense amplifier SA. The second wire DWL of the memory cell array MCA can be coupled to the sub-word line driver SWD. The first wire BL of the memory cell array MCA can be coupled to the sense amplifier SA. The peripheral circuit region PA1 can also include a peripheral control circuit CL.

[0111] The peripheral circuit region PA1 and the memory cell array MCA can be coupled to each other through a bonding structure WBD. The peripheral circuit region PA1 and the dummy region PA2 can be coupled to each other through the bonding structure WBD and the first multi-level interconnect LML. The bonding structure WBD can include a plurality of bonding pads CBD and PBD. The peripheral circuit region PA1 and the memory cell array MCA can be coupled to each other through the bonding structure WBD and the first multi-level interconnect LML.

[0112] The bonding pads CBD and PBD can include a first bonding pad CBD and a second bonding pad PBD. The first bonding pad CBD and the second bonding pad PBD can be coupled to each other through wafer bonding. The first bonding contact plug CBC can be coupled to the first bonding pad CBD. The second bonding contact plug PBC can be coupled to the second bonding pad PBD.

[0113] The first wire BL of the memory cell array MCA can be coupled to the first bonding pad CBD and the first bonding contact plug CBC through a front-layer interconnect FM1. A front-layer plug F1B can be disposed between the first wire BL and the front-layer interconnect FM1.

[0114] The cell contact plug WC of the memory cell array MCA can be coupled to the first bonding pad CBD and the first bonding contact plug CBC through the front-layer interconnect FM1.

[0115] The common plate PL of the data storage element CAP of the memory cell array MCA can be coupled to the second multi-level interconnect UML through the nano-silicon via PC and the back-layer interconnect PM. The nano-silicon via PC can penetrate the back surface of the first substrate W1. The nano-scale spacer SP2 can be formed on the sidewall of the nano-silicon via PC. The nano-scale spacer SP2 can be disposed between the nano-silicon via PC and the first substrate W1. The nano-silicon via PC can be coupled to the common plate line PL passing through the first substrate W1 from the back surface of the first substrate W1. The nano-silicon via PC is embedded in the first substrate W1, and the sidewall of the nano-silicon via PC is completely surrounded by the nano-scale spacer SP2 and isolated from the first substrate W1 by the nano-scale spacer SP2.

[0116] The dummy region PA2 can be disposed at a level higher than the peripheral circuit region PA1. The dummy region PA2 can include a dummy stack SG, a stack-level plug FC passing through the dummy stack SG, and a stack-level spacer SP1 formed on the sidewall of the stack-level plug FC. The stack-level spacer SP1 can include a dielectric material. The dummy stack SG can include silicon layers S1 and S3 and silicon-germanium layers S2 and S4.

[0117] The stack-level spacer SP1 can be disposed between the stack-level plug FC and the dummy stack SG. The stacks of the silicon layers S1 and S3 and the silicon-germanium layers S2 and S4 can be disposed around the stack-level plug FC and the stack-level spacer SP1.

[0118] The vertical height of the stack-level plug FC can be greater than the vertical height of the nano-silicon via PC.

[0119] The second multi-level interconnect UML and the back-layer interconnect PM can be coupled to the upper part of the stack-level plug FC. The front-layer interconnect FM1 can be coupled to the lower part of the stack-level plug FC. The stack-level plug FC can be coupled to the second multi-level interconnect UML through the nano-silicon via PC and the back-layer interconnect PM. The front-layer interconnect FM1 can be coupled to the first bonding contact plug CBC and the first bonding pad CBD. The peripheral control circuit CL can be coupled to the second bonding contact plug PBC and the second bonding pad PBD through the first multi-level interconnect LML. The nano-silicon via PC is embedded in the first substrate W1, and the sidewall of the nano-silicon via PC is completely surrounded by the nano-scale spacer SP2 and isolated from the first substrate W1 by the nano-scale spacer SP2.

[0120] The sub-word line driver SWD and the sense amplifier SA can be coupled to the second bonding contact plug PBC and the second bonding pad PBD through the first multi-level interconnect LML.

[0121] The through-silicon via nano PC, the post-level interconnect PM, and the second multi-level interconnect UML may be a backside interconnect structure. The peripheral control circuit CL may be electrically coupled to the backside interconnect structure through a vertical path of the first multi-level interconnect LML, the bonding structure WBD, and the stacked-level plug FC.

[0122] Figure 3 The semiconductor device 200 may include a COP structure, and the memory cell array MCA and the dummy region PA2 may be disposed at a level higher than the peripheral circuit region PA1. As described above, since the spacers SP1 and SP2 are formed on the sidewalls of the stacked-level plug FC and the through-silicon via nano PC, short circuits between the stacked-level plug FC and the through-silicon via nano PC and the first substrate W1 can be prevented. In addition, short circuits between the stacked-level plug FC and the through-silicon via nano PC can be prevented.

[0123] Figures 4 to 22 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0124] Reference Figure 4 , a stack body SB may be formed on the first substrate 11. The first substrate 11 may include a semiconductor substrate. The stack body SB may have a plurality of sub-stacks stacked alternately. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a preliminary horizontal layer 14 stacked in the mentioned order. The first layer 12A and the third layer 12B may be formed of the same material and may contain silicon germanium. The second layer 13 may include single-crystalline silicon. The preliminary horizontal layer 14 may include single-crystalline silicon. The second layer 13 and the preliminary horizontal layer 14 may be formed of the same material. The first layer 12A, the second layer 13, the third layer 12B, and the preliminary horizontal layer 14 may be formed by an epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the preliminary horizontal layer 14 may be thicker than the second layer 13.

[0125] The stack body SB may include a plurality of preliminary horizontal layers 14, a first sacrificial layer stack SB1, a second sacrificial layer stack SB2, a third sacrificial layer stack SB3, a fourth sacrificial layer stack SB4, and a fifth sacrificial layer stack SB5. The stack body SB may include the first sacrificial layer stack SB1, the preliminary horizontal layer 14, the second sacrificial layer stack SB2, the preliminary horizontal layer 14, the third sacrificial layer stack SB3, the preliminary horizontal layer 14, the fourth sacrificial layer stack SB4, the preliminary horizontal layer 14, and the fifth sacrificial layer stack SB5 stacked in the mentioned order. The uppermost layer of the stack body SB may be the second layer 13. Each of the first to fifth sacrificial layer stacks SB1 to SB5 may be a three-layer stack of a first layer 12A, a second layer 13, and a third layer 12B. For example, when the first layer 12A and the third layer 12B include silicon germanium layers and the second layer 13 includes a single-crystalline silicon layer, the first to fifth sacrificial layer stacks SB1 to SB5 may include a stack of a first silicon germanium layer, a single-crystalline silicon layer, and a second silicon germanium layer (SiGe / Si / SiGe). The fifth sacrificial layer stack SB5 may be a four-layer stack of a first layer 12A / a second layer 13 / a third layer 12B / a second layer 13. The fifth sacrificial layer stack SB5 may be used as a hard mask.

[0126] The second layer 13 may include a first single-crystalline silicon layer, and the preliminary horizontal layer 14 may include a second single-crystalline silicon layer. Thus, the stack body SB may have the first sacrificial layer stack SB1 disposed below the second single-crystalline silicon layer and the second sacrificial layer stack SB2 disposed above the second single-crystalline silicon layer. Each of the first sacrificial layer stack SB1 and the second sacrificial layer stack SB2 may include a stack of a first silicon germanium layer, a first single-crystalline silicon layer, and a second silicon germanium layer. The second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer.

[0127] As described above with reference to the embodiments of the present disclosure, when stacking storage units, the first sacrificial layer stack SB1, the preliminary horizontal layer 14, the second sacrificial layer stack SB2, the preliminary horizontal layer 14, the third sacrificial layer stack SB3, the preliminary horizontal layer 14, the fourth sacrificial layer stack SB4, the preliminary horizontal layer 14, and the fifth sacrificial layer stack SB5 may be alternately stacked multiple times.

[0128] According to another embodiment of the present disclosure, the preliminary horizontal layer 14 may include amorphous silicon or polycrystalline silicon.

[0129] Reference Figure 5 , a part of the stack body SB may be etched. As a result, a plurality of vertical openings 15 and 16 may be formed in the stack body SB. The vertical openings 15 and 16 may include a first vertical opening 15 and a second vertical opening 16. From a top-down perspective, the first vertical opening 15 and the second vertical opening 16 may be hole-shaped vertical openings. According to another embodiment of the present disclosure, the first vertical opening 15 and the second vertical opening 16 may be linear vertical openings.

[0130] As described above, the hard mask layer pattern HM1 can be formed to form the vertical openings 15 and 16, and the hard mask layer pattern HM1 can be formed by adopting a double patterning process.

[0131] Reference Figure 6 , a portion HT of the hard mask layer pattern HM1 can be trimmed.

[0132] Subsequently, the first layer 12A and the third layer 12B can be selectively removed through the vertical openings 15 and 16. Figure 5 of the first layer 12A and the third layer 12B.

[0133] In order to selectively remove the first layer 12A and the third layer 12B, the difference between the etching selectivity of the second layer 13 and the preliminary horizontal layer 14 and the etching selectivity of the first layer 12A and the third layer 12B can be utilized. The first layer 12A and the third layer 12B can be removed by a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 and the preliminary horizontal layer 14 include a silicon layer, the silicon germanium layer can be etched by using an etchant or etching gas having selectivity with respect to the silicon layer.

[0134] Subsequently, the second layer 13 can be removed. The second layer 13 can be removed by a wet etching process or a dry etching process. According to an embodiment of the present disclosure, the preliminary horizontal layer 14 can be partially removed while removing the second layer 13. As a result, the second layer 13 can be removed, and the preliminary horizontal layer 14 can be thinned (as indicated by the reference numeral "14A"). The recess process for forming the thin preliminary horizontal layer 14A (i.e., the preliminary horizontal layer pattern 14A) can be referred to as a thinning process or a trimming process of the preliminary horizontal layer 14. The preliminary horizontal layer pattern 14A can be referred to as a thin body active layer. The preliminary horizontal layer pattern 14A can include a single crystal silicon layer. While forming the preliminary horizontal layer pattern 14A, the surface of the first substrate 11 can be recessed to a predetermined depth. The recess process for forming the preliminary horizontal layer pattern 14A can use Hot SC-1 (HSC1). HSC1 can include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) are mixed in a ratio of approximately 1:4:20. The second layer 13 and the preliminary horizontal layer 14 can be selectively etched by using HSC1.

[0135] As a result of the above recess process, the preliminary horizontal layer pattern 14A and the wide recess 17 can be formed. Each of the upper surface and the lower surface of the preliminary horizontal layer pattern 14A can include a flat surface.

[0136] From a top-down perspective, the preliminary horizontal layer pattern 14A may have a cross shape. The side surface of the preliminary horizontal layer pattern 14A may have a curved shape or a circular shape.

[0137] After the preliminary horizontal layer pattern 14A is formed, the vertical openings 15 and 16 may be enlarged.

[0138] Reference Figure 7 , the first dielectric layer 18 may be formed to completely cover the preliminary horizontal layer pattern 14A. The first dielectric layer 18 may include silicon nitride.

[0139] While the first dielectric layer 18 is being formed, a dummy dielectric layer 18D may be formed on the surface of the first substrate 11.

[0140] Subsequently, a second dielectric layer 19 may be formed on top of the first dielectric layer 18. The second dielectric layer 19 may be filled between vertically adjacent first dielectric layers 18. The second dielectric layer 19 may include silicon oxide. A portion of the second dielectric layer 19 may be conformally formed on the surfaces of the vertical openings 15 and 16. Figure 6 Each wide recess 17 of may be filled with the first dielectric layer 18 and the second dielectric layer 19.

[0141] The first dielectric layer 18 may surround the preliminary horizontal layer pattern 14A, and the second dielectric layer 19 may surround the first dielectric layer 18.

[0142] Subsequently, a sacrificial pillar 20 may be formed on top of the second dielectric layer 19 located in the vertical openings 15 and 16. The sacrificial pillar 20 may include amorphous carbon. According to another embodiment of the present disclosure, a pillar capping layer may be further formed on top of the sacrificial pillar 20. The pillar capping layer may include a metal-based material. The pillar capping layer may include titanium nitride.

[0143] The second dielectric layer 19 and the sacrificial pillar 20 may form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2 that fill the vertical openings 15 and 16. The first sacrificial pillar structure SV1 may fill the first vertical opening 15, and the second sacrificial pillar structure SV2 may fill the second vertical opening 16. The sacrificial pillar 20 may not be formed between the vertically stacked first dielectric layers 18. According to another embodiment of the present disclosure, each of the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. Each of the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may contain silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0144] As the preliminary horizontal layer pattern 14A, the first dielectric layer 18, and the second dielectric layer 19 are formed, the unit mode structure MD can be formed. The unit mode structure MD can include a plurality of unit modes. Each unit mode can include a plurality of mode layers. For example, each unit mode can include a first mode layer, a second mode layer, a third mode layer, a fourth mode layer, and a fifth mode layer that are sequentially stacked. The first mode layer and the fifth mode layer can correspond to the second dielectric layer 19. The second mode layer and the fourth mode layer can correspond to the first dielectric layer 18. The third mode layer can correspond to the preliminary horizontal layer pattern 14A. Each unit mode can include an ONSNO stack. Here, the ONSNO stack can refer to a structure in which a first oxide, a first nitride, a single crystal silicon layer, a second nitride, and a second oxide are sequentially stacked. The first silicon oxide and the second silicon oxide can correspond to the second dielectric layer 19, and the first silicon nitride and the second silicon nitride can correspond to the first dielectric layer 18. The single crystal silicon layer can correspond to the preliminary horizontal layer pattern 14A.

[0145] Through the above Figures 4 to 7 shown series of processes, the sub-stacks SB1 to SB5 of the stack SB can be replaced with unit modes. The first layer 12A, the second layer 13, and the third layer 12B of each sub-stack SB1 to SB5 can be replaced with the first dielectric layer 18 and the second dielectric layer 19. The preliminary horizontal layer 14 can become the preliminary horizontal layer pattern 14A.

[0146] Reference Figure 8 , Figure 7 The hard mask layer pattern HM1 of

[0147] Reference Figure 9 ,the top dielectric layer HM can fill Figure 8 the hard mask layer level opening HM’. The top dielectric layer HM can include silicon oxide.

[0148] Reference Figure 10 , Figure 9 the second sacrificial pillar structure SV2 of

[0149] Subsequently, the second dielectric layer 19 can be horizontally recessed. Subsequently, the first dielectric layer 18 can be horizontally recessed. The recess amount of the first dielectric layer 18 can be greater than the recess amount of the second dielectric layer 19. A part of the first dielectric layer 18 can be recessed to form a dummy dielectric layer 18D on the substrate 11.

[0150] Due to the recess process of the first dielectric layer 18, a first dielectric layer level recess 22 can be formed. A part of the preliminary horizontal layer pattern 14A can be exposed through the first dielectric layer level recess 22.

[0151] Reference Figure 11 , the first vertical sacrificial structure 23 can be formed to fill Figure 10 the first dielectric layer-level depression 22 and the first hole-shaped vertical opening 21 of . The first vertical sacrificial structure 23 can include a dielectric material. The first vertical sacrificial structure 23 can include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. Each first vertical sacrificial structure 23 can include a main body portion filling the first hole-shaped vertical opening 21 and an extended portion 23A filling the first dielectric layer-level depression 22.

[0152] Reference Figure 12 , Figure 11 the sacrificial pillar 20 of the first sacrificial pillar structure SV1 of can be removed to form a vertical-level path 24.

[0153] Subsequently, in order to form a lower-level gap 25, Figure 11 the dummy dielectric layer 18D below the vertical-level path 24 of can be removed.

[0154] Reference Figure 13 , a part of the second dielectric layer 19 can be cut to form a second hole-shaped vertical opening 26.

[0155] Subsequently, the first passivation layer BF1 can be formed to fill Figure 12 the lower-level gap 25 of . The first passivation layer BF1 can include silicon oxide. Forming the first passivation layer BF1 can include depositing silicon oxide to fill the lower-level gap 25 and etching the silicon oxide. Subsequently, the second passivation layer BF2 can be formed by oxidizing the surface of the first substrate 11.

[0156] Reference Figure 14 , Figure 13 the first dielectric layer 18 of can be removed to form a horizontal-level depression 27. A part of the preliminary horizontal layer pattern 14A can be exposed by the horizontal-level depression 27. A part of one preliminary horizontal layer pattern 14A can be exposed by a pair of horizontal-level depressions 27.

[0157] Reference Figure 15 , an interlayer dielectric layer 28 can be formed over the exposed portion of the preliminary horizontal layer pattern 14A. The interlayer dielectric layer 28 can be formed by oxidizing the surface of the preliminary horizontal layer pattern 14A. According to another embodiment of the present disclosure, the interlayer dielectric layer 28 can be formed by a deposition process of silicon oxide.

[0158] The interlayer dielectric layer 28 can include silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 28 can include SiO 2 , Si 3 N 4 , HfO2 、 Al 2 O 3 、 ZrO 2 、 AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0159] Reference Figure 16 , a horizontal wire 29 can be formed on the interlayer dielectric layer 28 to fill the horizontal-level recess 27. Forming the horizontal wire 29 can include depositing a conductive material on the interlayer dielectric layer 28 to fill the horizontal-level recess 27 and performing an etch-back process on the conductive material. The horizontal wire 29 can include a pair of first horizontal wires 29A and second horizontal wires 29B that face each other with the semiconductor layer pattern 14A therebetween. The first horizontal wire 29A and the second horizontal wire 29B can include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal wire 29A and the second horizontal wire 29B can include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal wire 29A and the second horizontal wire 29B can include a titanium nitride and tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal wire 29A and the second horizontal wire 29B can include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or lower. The P-type work function material can have a high work function of about 4.5 eV or greater. As Figures 1A to 1C shown, each of the first horizontal wire 29A and the second horizontal wire 29B can have a cross shape and can include a channel overlap portion WLP. The horizontal wire 29 can correspond to the second wire DWL as Figures 1A to 3 shown. The first horizontal wire 29A and the second horizontal wire 29B can correspond to the upper horizontal line G1 and the lower horizontal line G2 as Figures 1A to 2D shown.

[0160] Reference Figure 17 , a vertical wire 33 can be formed to be commonly coupled with the preliminary horizontal layer pattern 14A. The vertical wire 33 can fill the Figure 16 second hole-shaped vertical opening 26. The vertical wire 33 can include titanium nitride, tungsten, or a combination thereof. The vertical wire 33 can include a bit line. The vertical wire 33 can correspond to the Figures 1A to 3 first wire BL as

[0161] Before forming the vertical wire 33, a first contact node 31 can be formed. The first contact node 31 can include a metal-based material or a semiconductor material. The first contact node 31 can include doped polysilicon. Impurities can diffuse from the first contact node 31, thereby forming a first doped region 32 on one side of the preliminary horizontal layer pattern 14A.

[0162] Before forming the first contact node 31, a first capping layer 30 may be formed. The first capping layer 30 may be formed on one side of the horizontal wire 29. The first capping layer 30 may include silicon oxide, silicon nitride, or a combination thereof.

[0163] Reference Figure 18 , Figure 17 The main body portion of the first vertical sacrificial structure 23 may be removed to form an enlarged hole-shaped opening 34'. Subsequently, a third passivation layer BF3 may be formed on the surface of the first substrate 11. The third passivation layer BF3 may include silicon oxide.

[0164] Subsequently, in order to form the storage opening 35, the extended portion of the first vertical sacrificial structure 23 and the preliminary horizontal layer pattern 14A may be trimmed horizontally from the enlarged hole-shaped opening 34'. The extended portion of the first vertical sacrificial structure 23 remaining after forming the storage opening 35 may be simply referred to as the first capping layer 34, and the remaining preliminary horizontal layer pattern 14A may be simply referred to as the horizontal layer HL. From a top-down perspective, the horizontal layer HL may have a cross shape.

[0165] Reference Figure 19 , a second contact node 36 may be formed above the second edge of the horizontal layer HL. The second contact node 36 may include doped polysilicon. Impurities may diffuse from the second contact node 36, thereby forming a second doped region 37 on the second side of the horizontal layer HL. The second contact node 36 may be referred to as an inner contact node.

[0166] The horizontal layer HL may include a first doped region 32, a second doped region 37, and a channel 38. The channel 38 may be defined between the first doped region 32 and the second doped region 37. The channel 38 may vertically overlap with the horizontal wire 29. The channel 38 may correspond to the channel CH as Figures 1A to 2D shown.

[0167] Reference Figure 20 , a first electrode 39 of the data storage element may be formed above the second contact node 36. The first electrode 39 may have a horizontally oriented cylindrical shape.

[0168] Reference Figure 21 , the second dielectric layer 19 may be horizontally recessed (see reference numeral '40'). As a result, the outer wall of the first electrode 39 may be exposed.

[0169] Reference Figure 22 , a dielectric layer 41 and a second electrode 42 may be sequentially formed above the first electrode 39. The first electrode 39, the dielectric layer 41, and the second electrode 42 may form the data storage element CAP.

[0170] The first electrode 39 may include an internal space and a plurality of outer surfaces. The internal space of the first electrode 39 may include a plurality of inner surfaces. The outer surfaces of the first electrode 39 may include vertical outer surfaces and a plurality of horizontal outer surfaces. The internal space of the first electrode 39 may be a three-dimensional space. The dielectric layer 41 may conformally cover the inner and outer surfaces of the first electrode 39. The second electrode 42 may be disposed in the internal space of the first electrode 39 above the dielectric layer 41. Some of the outer surfaces of the first electrode 39 may be coupled to the horizontal layer HL.

[0171] The first electrode 39 may have a cylindrical shape. The cylindrical shape of the first electrode 39 may include a cylindrical inner surface and a cylindrical outer surface. The dielectric layer 41 and the second electrode 42 may be disposed on the cylindrical inner surface of the first electrode 39.

[0172] Each of the first electrode 39 and the second electrode 42 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, each of the first electrode 39 and the second electrode 42 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a titanium nitride / titanium silicon nitride (TiN / TiSiN) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 42 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 42 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material that fills the internal space of the first electrode 39, titanium nitride (TiN) may serve as the second electrode 42 of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0173] The dielectric layer 41 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 41 may include silicon oxide, silicon nitride, a high-k material, a perovskite material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 41 may include a high-k material, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O5 ), niobium oxide (Nb2O5) or strontium titanate (SrTiO 3 ). The dielectric layer 41 may include ZA (ZrO 2 / Al 2 O 3 ) stack, ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, HA (HfO 2 / Al 2 O 3 ) stack, HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stack, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) stack, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2)Stack, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 )Stack, or AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / Al 2 O 3 )Stack.

[0174] According to another embodiment of the present disclosure, an interface control layer may be further formed between the first electrode 39 and the dielectric layer 41 to reduce leakage current. The interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 42 and the dielectric layer 41.

[0175] Figures 23 to 27 Shows a method for forming a pad portion according to an embodiment of the present disclosure. Figures 23 to 27 Shows according to Figure 2A The method of forming the pad portion along the line B - B' shown therein. The pad portion forming process may be performed after forming Figure 17 The vertical wire 33 shown therein.

[0176] Referring to Figures 4 to 17 , after forming the horizontal wire 29 and the vertical wire 33, a pad portion may be formed at the edge on one side of the horizontal wire 29.

[0177] Referring to Figure 23 , the horizontal wire 29 may include a pair of first horizontal wires 29A and second horizontal wires 29B. Multiple horizontal wires 29 may be stacked in the first direction D1. The preliminary horizontal layer pattern 14A and the interlayer dielectric layer 28 may be formed in the first region CA and the second region CTA, respectively. The second dielectric layer 19 may be formed between the horizontal wires 29.

[0178] Referring to Figure 24 , the horizontal wire 29 and the second dielectric layer 19 may be etched to form a pad isolation gap WSM in the second region CTA.

[0179] Figure 23The interlayer dielectric layer 28 and the preliminary horizontal layer pattern 14A can be removed through the pad isolation gap WSM. As a result, a pad-shaped recess PD’ can be formed between the first horizontal wire 29A and the second horizontal wire 29B.

[0180] Reference Figure 25 , a pad GP for filling the pad-shaped recess PD’ can be formed. Figure 24

[0181] Each horizontal wire 29 can include a pair of the first horizontal wire 29A and the second horizontal wire 29B. Each pad GP can be electrically connected to the first horizontal wire 29A and the second horizontal wire 29B.

[0182] The pad GP, the first horizontal wire 29A, and the second horizontal wire 29B can include the same material. The pad GP, the first horizontal wire 29A, and the second horizontal wire 29B can include a metal-based material. For example, the pad GP, the first horizontal wire 29A, and the second horizontal wire 29B can include titanium nitride, tungsten, or a combination thereof. The pad GP, the first horizontal wire 29A, and the second horizontal wire 29B can include a metal-based material.

[0183] After forming the pad GP, a gap WSL for filling the pad isolation gap WSM can be formed. The gap WSL can include a dielectric material.

[0184] Reference Figure 26 , the pad GP, the first horizontal wire 29A, and the second horizontal wire 29B can be etched to form a stepped structure STP.

[0185] Reference Figure 27 , after forming an interlayer dielectric layer ILD covering the stepped structure STP, unit contact plugs WC coupled to the horizontal wires 29 of each level can be formed. The unit contact plugs WC can include a metal-based material.

[0186] The memory cell array can be formed in the first substrate 11 through a series of processes as Figures 4 to 27 shown. Hereinafter, for a detailed description of the constituent elements of the memory cell array, reference can be made to Figures 1A to 27 .

[0187] Figures 28 to 33 Shows a method for manufacturing the Figure 3 semiconductor device shown in

[0188] Reference Figure 28 , a first substrate W1 including a memory cell array MCA and a dummy stack SG can be prepared. The dummy stack SG can include a silicon layer and a silicon germanium layer. The dummy stack SG can correspond to as Figure 4The stacked body SB shown below. In the following, for a detailed description of the constituent elements of the memory cell array MCA and the dummy stack SG, reference can be made to Figures 1A to 27 . The memory cell array MCA may include a first region CA and a second region CTA.

[0189] A plurality of contact holes C1 and C2 may be formed. The contact holes may include a first contact hole C1 and a second contact hole C2. The first contact hole C1 may be formed in the first region CA of the memory cell array MCA, and the second contact hole C2 may be formed in the second region CTA of the memory cell array MCA. The first contact hole C1 may expose the upper portion of the first wire BL of the memory cell array MCA. The second contact hole C2 may expose the step of the second wire DWL of the pad portion.

[0190] The front layer plug F1B may be formed in the first contact hole C1, and the cell contact plug WC may be formed in the second contact hole C2.

[0191] After forming the front layer plug F1B and the cell contact plug WC, a third contact hole C3 may be formed in the dummy region PA2. The third contact hole C3 may pass through the dummy stack SG of the dummy region PA2 and may extend into the interior of the first substrate W1. The third contact hole C3 may be referred to as a stack-level contact hole.

[0192] Reference Figure 29 , the stack-level plug FC may be formed in the third contact hole C3. Before forming the stack-level plug FC, a stack-level spacer SP1 may be formed on Figure 28 the sidewall of the third contact hole C3.

[0193] Reference Figure 30 , the front layer interconnect FM1 may be formed above the front layer plug F1B and the cell contact plug WC. The front layer interconnect FM1 may be formed above the stack-level plug FC. The front layer interconnect FM1 may be formed above the memory cell array MCA and the dummy region PA2.

[0194] The first bonding contact plug CBC and the first bonding pad CBD may be sequentially formed above the front layer interconnect FM1.

[0195] Reference Figure 31 , the peripheral circuit region PA1 may be prepared. The peripheral circuit region PA1 may be formed with a peripheral control circuit CL, a sub-word line driver SWD, and a sense amplifier SA above the second substrate W2. The peripheral control circuit CL, the sub-word line driver SWD, and the sense amplifier SA may include transistors.

[0196] The first multi-level interconnect LML may be formed above the peripheral control circuit CL, the sub-word line driver SWD, and the sense amplifier SA.

[0197] The second bonding contact plug PBC and the second bonding pad PBD can be sequentially formed on the first multi-level interconnect LML.

[0198] Reference Figure 32 , a wafer bonding process can be performed to bond the memory cell array MCA and the peripheral circuit region PA1. For example, the first substrate W1 can be flipped to bond the memory cell array MCA and the peripheral circuit region PA1 to each other. In addition, the first substrate W1 can be flipped to bond the dummy region PA2 and the peripheral circuit region PA1. The memory cell array MCA and the peripheral circuit region PA1 can be bonded through the bonding structure WBD of the first bonding pad CBD and the second bonding pad PBD. The dummy region PA2 and the peripheral circuit region PA1 can be bonded through the bonding structure WBD of the first bonding pad CBD and the second bonding pad PBD.

[0199] Subsequently, a plurality of nano-vias NT can be formed on the back surface of the first substrate W1. The nano-vias NT can be formed by partially etching the back surface of the first substrate W1.

[0200] The nano-vias NT can expose the back surfaces of the stacked vias FC and the common plate PL.

[0201] Reference Figure 33 , a nano-silicon via PC and a post-layer interconnect PM can be formed. The nano-silicon via PC can fill the nano-vias NT. Before forming the nano-silicon via PC, nano-scale spacers SP2 can be formed on the sidewalls of the nano-vias NT.

[0202] The second multi-level interconnect UML can be formed on the post-layer interconnect PM.

[0203] The common plate PL of the data storage element CAP of the memory cell array MCA can be coupled to the second multi-level interconnect UML through the nano-silicon via PC and the post-layer interconnect PM. The nano-silicon via PC can penetrate the back surface of the first substrate W1. Nano-scale spacers SP2 can be formed on the sidewalls of the nano-silicon via PC.

[0204] The stacked via FC can be coupled to the second multi-level interconnect UML through the nano-silicon via PC and the post-layer interconnect PM.

[0205] Figures 34 to 36 is a cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0206] Reference Figure 34, a stack SB10 can be formed on a first substrate 11. The stack SB10 can include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack can include a plurality of silicon-germanium layers 12 and a plurality of single-crystalline silicon layers 14' alternately stacked by an epitaxial growth process. The silicon-germanium layer 12 can be a sacrificial layer, and the single-crystalline silicon layer 14' can be a recess target layer. The silicon-germanium layer 12 can correspond to Figure 4 the first layer 12A or the third layer 12B, while the single-crystalline silicon layer 14' can correspond to Figure 4 the fourth layer 14. Different from the stack SB Figure 4 , the stack SB10 can have an alternating stack of the silicon-germanium layer 12 and the single-crystalline silicon layer 14'.

[0207] Referring to Figure 35 , a hard mask layer pattern HM1 can be formed on the stack SB10.

[0208] Subsequently, the stack SB10 can be etched by using the hard mask layer pattern HM1 as an etch stop. As a result, a plurality of first sacrificial vertical openings 15 and second sacrificial vertical openings 16 can be formed in the stack SB10.

[0209] Referring to Figure 36 , a preliminary horizontal layer 14A' and a horizontal recess 17 can be formed. The preliminary horizontal layer 14A' and the horizontal recess 17 can be formed by Figure 35 a recess process of the silicon-germanium layer 12 and the single-crystalline silicon layer 14'. After removing the silicon-germanium layer 12, a recess process of the single-crystalline silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 6 the preliminary horizontal layer 14A.

[0210] The silicon-germanium layer 12 can be recessed by a wet etching process or a dry etching process. The silicon-germanium layer 12 can be etched by using an etchant or an etching gas that is selective with respect to the single-crystalline silicon layer 14'.

[0211] The recess process of the single-crystalline silicon layer 14' for forming the preliminary horizontal layer 14A' can use, for example, Hot SC-1 (HSC1). HSC1 can include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) are mixed in a ratio of about 1:4:20. The single-crystalline silicon layer 14' can be selectively etched by using HSC1.

[0212] While forming the preliminary horizontal layer 14A', the surface of the first substrate 11 can be recessed to a predetermined depth (see reference numeral '11A'). As a result, the depths of the first sacrificial vertical openings 15 and the second sacrificial vertical openings 16 can be increased.

[0213] Subsequently, a series of processes shown in Figures 8 to 22 can be executed.

[0214] Figures 37 to 39 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. The memory cell arrays MCA100, MCA200, and MCA300 may be similar to Figure 2C the memory cell array MCA. Hereinafter, for a detailed description of the constituent elements that also appear in Figure 2C reference may be made to the above embodiments of the present disclosure.

[0215] Referring to Figure 37 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0216] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may have a plurality of memory cells MC10 stacked in a first direction D1. The row array of memory cells MC10 may have a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0217] Each memory cell MC10 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0218] The switching element TR may include a horizontal layer HL and a second wire DWL. The horizontal layer HL may extend along the second direction D2. The second wire DWL may extend along the third direction D3.

[0219] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL therebetween. As Figure 1B shown, an interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL.

[0220] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FSW extending along the third direction D3. The flat sidewalls FSW may refer to vertical sidewalls. The flat sidewalls FSW may have a linear shape extending along the third direction D3.

[0221] Referring to Figure 38 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0222] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked along a first direction D1. The row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged along a second direction D2 and a third direction D3.

[0223] Each memory cell MC20 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0224] The switching element TR may include a horizontal layer HL and a second wire SWL. The horizontal layer HL may extend along the second direction D2. The second wire SWL may extend along the third direction D3.

[0225] The second wire SWL may be of a single structure. For example, the second wire SWL may be disposed above the horizontal layer HL. As Figure 3 shown, an interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second wire SWL. According to another embodiment of the present disclosure, the second wire SWL may be disposed below the horizontal layer HL.

[0226] The second wire SWL may include a pair of flat sidewalls FSW extending along the third direction D3. The flat sidewalls FSW may refer to vertical sidewalls.

[0227] According to another embodiment of the present disclosure, the second wire SWL may include a channel overlap portion WLP and a channel non-overlap portion NOL, as Figure 1C shown.

[0228] Refer to Figure 39 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0229] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in the first direction D1. The row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in the second direction D2 and the third direction D3.

[0230] Each memory cell MC30 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0231] The switching element TR may include a horizontal layer HL and a second wire GAA-WL. The horizontal layer HL may extend along a second direction D2. The second wire GAA-WL may extend along a third direction D3.

[0232] The second wire GAA-WL may be a gate-all-around structure GAA. For example, the second wire GAA-WL may extend along the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second wire GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0233] The second wire GAA-WL may include a pair of flat sidewalls FSW extending in the third direction D3. The flat sidewalls FSW may refer to vertical sidewalls.

[0234] According to another embodiment of the present disclosure, each memory cell may have a first wire BL horizontally extending in the third direction D3, a second wire DWL vertically extending in the first direction D1, and a horizontal layer HL horizontally extending in the second direction D2. The second wire DWL may have a dual structure and may be replaced with a single structure or a gate-all-around structure.

[0235] Figure 40 is a cross-sectional view showing a memory cell array MCA400 according to another embodiment of the present disclosure.

[0236] Figure 40 The memory cell array MCA400 may be similar to Figures 2A to 2D The memory cell array MCA. Hereinafter, a detailed description of the constituent elements of the memory cell array MCA400 that also appear in Figures 2A to 2D The memory cell array MCA may be omitted.

[0237] Reference Figure 40 , the buried buffer layer BBF may completely cover the upper surface of the first substrate W1. The buried buffer layer BBF may include an oxide, such as silicon oxide. The first substrate W1 and the buried buffer layer BBF may have a silicon-on-insulator (SOI) structure.

[0238] Figures 41 to 44 Schematically shows a semiconductor device according to another embodiment of the present disclosure.

[0239] Reference Figures 41 to 44, each of the semiconductor devices 300, 310, 300A, and 310A may include a memory cell array MCA, a peripheral circuit PERI, and a backside interconnect structure BSPDN. The semiconductor devices 300, 310, 300A, and 310A may further include a bonding structure WBD disposed between the memory cell array MCA and the peripheral circuit PERI. Figure 41 The semiconductor device 300 and Figure 42 the semiconductor device 310 may have the same constituent elements except for a buffer layer BF and a buried buffer layer BF10. Figure 43 The semiconductor device 300A and Figure 44 the semiconductor device 310A may have the same constituent elements except for a buffer layer BF and a buried buffer layer BF10. The semiconductor devices 300, 310, 300A, and 310A may not include Figure 3 the dummy stack SG shown in.

[0240] The memory cell array MCA may be similar to Figures 2A to 2D the memory cell array MCA of. Hereinafter, for a detailed description of the constituent elements of the memory cell array MCA, reference may be made to Figures 2A to 2D . The memory cell array MCA may include a first substrate W10, a plurality of memory cells MC, and front multi-layer metal lines FMLM.

[0241] The memory cell array MCA may include a first region R1 and a second region R2. The first region R1 may be a region where the memory cells MC are formed, and the second region R2 may be a region where cell contact plugs coupled to the memory cells MC are formed. The second region R2 of the semiconductor devices 300 and 310 may include a stepped pad portion. The second region R2 of the semiconductor devices 300A and 310A may include a non-stepped pad portion.

[0242] The memory cell MC can be disposed on the first substrate W10. The front multi-layer metal lines FMLM can be disposed on the memory cell MC. The three-dimensional array of the memory cell MC can include a column array of the memory cell MC and a row array of the memory cell MC. The column array of the memory cell MC can include a plurality of memory cells MC stacked along the first direction D1. The row array of the memory cell MC can include a plurality of memory cells MC horizontally disposed in the second direction D2 and the third direction D3. The memory cell array can be vertically stacked along the first direction D1 on the first substrate W10. According to another embodiment of the present disclosure, the memory cell array can be horizontally disposed in the second direction D2 on the first substrate W10. The memory cell array can include a buried-gate based dynamic random access memory (DRAM), a three-dimensional (3D) DRAM, 3D NAND, flash memory, spin transfer torque random access memory (STT-RAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), thyristor, a vertical-gate based DRAM, etc. The front multi-layer metal lines FMLM can include a plurality of metal lines and a plurality of vias. The memory cell array MCA can include a plurality of top dielectric layers TIL1, TIL2, and TIL3. The upper surfaces of the first wire BL and the common plate PL can be disposed at the same level as the upper surface of the top dielectric layer TIL2. The front multi-layer metal lines FMLM of the memory cell array MCA can include a front layer plug F1B, a front layer interconnect FM1, a front layer plug F2C, and a front layer interconnect FM2. The front layer plug F1B can penetrate the top dielectric layer TIL3 to be respectively coupled to the first wire BL and the common plate PL. The front layer interconnect FM2 can be respectively coupled to the first bonding contact plug CBC and the first bonding pad CBD.

[0243] Reference Figure 41 and Figure 42 , in the second region R2 of the memory cell array MCA, each pad portion of the stepped pad portion can include an upper horizontal line G1, a lower horizontal line G2, and a pad GP between the upper horizontal line G1 and the lower horizontal line G2. The pad portions of the stepped pad portion can have different horizontal lengths. The inter-cell dielectric layer IL can be disposed between the pad portions. The inter-cell dielectric layer IL can include silicon oxide. The inter-cell dielectric layer IL can be referred to as a horizontal inter-cell dielectric layer. The upper horizontal line G1 of the stepped pad portion can be respectively coupled to the first front contact plug F1C and the front layer interconnect FM1. The first front contact plug F1C can be referred to as a cell contact. The first front contact plug F1C can penetrate the top dielectric layers TIL1, TIL2, and TIL3 and the inter-layer dielectric layer ILD. The first front contact plug F1C can correspond to Figure 3 the cell contact plug WC.

[0244] Reference Figure 43 and Figure 44, in the second region R2 of the memory cell array MCA, each pad portion of the staircase-free pad portion may include an upper horizontal line G1, a lower horizontal line G2, and a pad GP between the upper horizontal line G1 and the lower horizontal line G2. The pad portions of the staircase-free pad portion may have the same horizontal length. The upper horizontal line G1 of the staircase-free pad portion may be coupled to the first front contact plug F1C and the front layer interconnect FM1, respectively. Sidewall spacers F1S may be formed on the sidewalls of the first front contact plug F1C. The sidewall spacers F1S may include a dielectric material.

[0245] A buffer layer BF may be disposed on the bottom surface of the first wire BL and the bottom surface of the common plate PL. The buffer layer BF may include an oxide, such as silicon oxide. Figure 42 The semiconductor device 310 in may have a buried buffer layer BF10 that completely covers the upper surface of the first substrate W10. The buried buffer layer BF10 may include an oxide, such as silicon oxide. The first substrate W10 and the buried buffer layer BF10 may have a silicon-on-insulator (SOI) structure.

[0246] The peripheral circuit PERI may include a second substrate W20, a plurality of control circuits CL, SA, and SWD disposed on the lower surface of the second substrate W20, and a multilayer metal wire MLM coupled to the control circuits CL, SA, and SWD. The multilayer metal wire MLM may include a plurality of metal wires MT1 to MT5 and a plurality of metal contact plugs M1C to M5C. The multilayer metal wire MLM may include at least a first layer of metal wire MT1 and a first layer of metal contact plug M1C. The first layer of metal wire MT1 and the first layer of metal contact plug M1C may be coupled to the control circuits CL, SA, and SWD.

[0247] The peripheral circuit PERI may include at least one or more control circuits for driving the memory cell array MCA. One or more control circuits of the peripheral circuit PERI may include N-channel transistors, P-channel transistors, CMOS circuits, or combinations thereof. One or more control circuits of the peripheral circuit PERI may include an address decoder circuit, a read circuit, a write circuit, etc. One or more control circuits of the peripheral circuit PERI may include planar channel transistors, recessed channel transistors, buried gate transistors, fin channel transistors (FinFETs), etc.

[0248] For example, the peripheral circuit PERI may include a common plate control circuit CL, a sub-word line driver SWD, and a sense amplifier SA. The first wire BL of the memory cell array MCA may be coupled to the sense amplifier SA. The second wire DWL may be coupled to the sub-word line driver SWD. The common plate PL may be coupled to the common plate control circuit CL. Each transistor for the common plate control circuit CL, the sub-word line driver SWD, and the sense amplifier SA may include a gate, a gate spacer, and a source / drain.

[0249] The backside interconnect structure BSPDN may include a second substrate W20, a power interconnect line PIL embedded in the second substrate W20, a power contact plug PILC coupled to the first surface of the power interconnect line PIL, a power via PM1C coupled to the second surface of the power interconnect line PIL, and a post multi-layer metal line PMLM disposed over the power via PM1C. The post multi-layer metal line PMLM may include a plurality of metal lines PM1, TMT, and RDA and a plurality of vias TMC and RDV. The power interconnect line PIL and the power via PM1C may have an integral structure. The sidewalls of the power interconnect line PIL and the sidewalls of the power via PM1C may be surrounded by a power-level spacer SP. The power interconnect line PIL is embedded in the second substrate W20, and the sidewalls of the power interconnect line PIL are completely surrounded by the power-level spacer SP and isolated from the second substrate W20 by the power-level spacer SP. The second substrate W20 may include a front side FS and a back side BS. The second substrate W20 may be flipped by wafer flipping such that the back side BS is disposed over the front side FS. Thus, the front side FS of the second substrate W20 may refer to the surface facing the multi-layer metal line MLM and the memory cell array MCA, and the back side BS of the second substrate W20 may refer to the surface facing the post multi-layer metal line PMLM.

[0250] A post inter-level dielectric layer PILD may be formed on the back side BS of the second substrate W20. The power via PM1C may extend into the interior of the second substrate W20 by passing through the post inter-level dielectric layer PILD. The power via PM1C may have a low aspect ratio. The power via PM1C may be referred to as a 'nano through-silicon via NTSV'. The power interconnect line PIL may be referred to as a buried power rail BPR. The power contact plug PILC may be referred to as a buried power rail via that lands on the power interconnect line PIL, i.e., 'Via-to-BPR' VBPR. The vertical structure of the power via PM1C, the power interconnect line PIL, and the power contact plug PILC may be a structure that passes through the post inter-level dielectric layer PILD and the second substrate W20. The power contact plug PILC may be coupled to the multi-layer metal line MLM. The power contact plug PILC may be coupled to the first metal line MT1 of the multi-layer metal line MLM. The first metal contact plug M1C and the power contact plug PILC may be disposed at the same level.

[0251] The backside interconnect structure BSPDN can be a backside power distribution network that is directly powered from the backside of the second substrate W20. The backside interconnect structure BSPDN can power the control circuits CL, SA, and SWD of the peripheral circuit PERI. The backside interconnect structure BSPDN and the peripheral circuit PERI can share the second substrate W20. The backside interconnect structure BSPDN can be coupled to the peripheral circuit PERI by passing through the second substrate W20 from the backside BS of the second substrate W20.

[0252] The wafer bonding structure WBD can include a first bonding pad CBD coupled to the memory cell array MCA and a second bonding pad PBD coupled to the peripheral circuit PERI. The wafer bonding structure WBD can further include a first bonding contact plug CBC and a second bonding contact plug PBC. The first bonding contact plug CBC can be coupled to the front multi-layer metal lines FMLM of the memory cell array MCA and the first bonding pad CBD. The second bonding contact plug PBC can be coupled to the multi-layer metal lines MLM of the peripheral circuit PERI and the second bonding pad PBD. A bonding dielectric layer can be disposed between the first bonding pads CBD at the same level, and the bonding dielectric layer can be disposed between the second bonding pads PBD at the same level. The first bonding pad CBD and the second bonding pad PBD can be coupled by direct bonding or hybrid bonding. Direct bonding can mean that the first bonding pad CBD and the second bonding pad PBD are directly bonded. For example, it can mean metal-to-metal bonding. Hybrid bonding can mean a combination of metal-to-metal bonding and dielectric-to-dielectric bonding, which is simply referred to as dielectric-to-dielectric bonding. Dielectric-to-dielectric bonding can mean the bonding of the bonding dielectric layer.

[0253] As described above, the semiconductor devices 300, 310, 300A, and 310A can include: a memory cell array MCA disposed above the front side of the first substrate W10; a backside interconnect structure BSPDN disposed at a level higher than the memory cell array MCA; a second substrate W20 having a front side FS facing the memory cell array MCA and a backside BS facing the backside interconnect structure BSPDN; a control circuit including at least one or more transistors disposed above the front side FS of the second substrate W20; and multi-layer metal lines MLM including at least one or more metal lines coupled to the control circuit. The backside interconnect structure BSPDN includes: a power interconnect line PIL embedded inside one side of the front side FS of the second substrate W20; a power via PM1C passing through the backside BS of the second substrate W20 to be coupled to the power interconnect line PIL; a power contact plug PILC coupled to the power interconnect line PIL and the control circuit; and a power stage spacer SP formed on the sidewalls of the power via and the power interconnect line.

[0254] As described above, the semiconductor devices 300, 310, 300A, and 310A may have a structure in which a memory cell array MCA, a peripheral circuit PERI, and a backside interconnect structure BSPDN are vertically stacked. The memory cell array MCA may be disposed at a level lower than the control circuits CL, SA, and SWD. The post-multilayer metal lines PMLM of the backside interconnect structure BSPDN may be disposed at a level higher than the control circuits CL, SA, and SWD. Power may be supplied directly from the backside interconnect structure BSPDN to the control circuits CL, SA, and SWD. Therefore, the path for supplying power from the backside interconnect structure BSPDN to the control circuits CL, SA, and SWD may be shortened. The power supply path may include the post-multilayer metal lines PMLM, power vias PM1C, power contact plugs PILC, power interconnections PIL, first-layer metal lines MT1, and first-layer metal contact plugs M1C. The method for supplying power to the control circuits CL, SA, and SWD of the peripheral circuit PERI may be top-down power supply.

[0255] The memory cell array MCA and the peripheral circuit PERI may be bonded by a wafer bonding process. The memory cell array MCA and the peripheral circuit PERI may be bonded by a wafer bonding structure WBD. The wafer bonding structure WBD may improve the integration degree, for example, overcome process limitations and maximize the net die.

[0256] When the wafer bonding process is applied, the backside interconnect structure BSPDN may be disposed on the backside BS of the second substrate W20. Therefore, the power consumption and current resistance of the semiconductor devices 300, 310, 300A, and 310A may be reduced.

[0257] Figure 45 A semiconductor device according to another embodiment of the present disclosure is schematically illustrated. Figure 45 The semiconductor device 200A may be similar to Figure 3 The semiconductor device 200. Hereinafter, the repeated description of the components the same as those shown in Figure 3 will be simplified or omitted.

[0258] Refer to Figure 45 , the semiconductor device 200A may include a memory cell array MCA, a peripheral circuit region PA1, and a dummy region PA2. The memory cell array MCA and the dummy region PA2 may be disposed at a level higher than the peripheral circuit region PA1. The dummy region PA2 may be horizontally spaced apart from the memory cell array MCA. For a detailed description of the memory cell array MCA of Figure 3 , reference may be made to Figures 2A to 2D .

[0259] The memory cell array MCA and the dummy region PA2 may be formed on the first substrate W1.

[0260] The peripheral circuit region PA1 may be formed on the second substrate W2. The memory cell array MCA may include a three-dimensional array of memory cells MC. For a detailed description of the memory cells MC, reference may be made to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0261] The memory cell array MCA may include a first region CA and a second region CTA. The first region CA may have memory cells MC formed therein, and the second region CTA may have cell contact plugs WC formed therein. In the second region CTA, a stepped pad portion WLE of a second wire DWL may be provided, and the second wire DWL of the stepped pad portion WLE may be coupled to the cell contact plug WC. The stepped pad portion WLE may include a vertical stack of pad portions, and each pad portion of the stepped pad portion WLE may include an upper horizontal line G1, a lower horizontal line G2, and a pad GP between the upper horizontal line G1 and the lower horizontal line G2. The pad portions of the stepped pad portion WLE may have the same horizontal length. Figure 3 The semiconductor device 200 of Figure 45 may include a stepped pad portion, while the semiconductor device 200A of

[0262] The peripheral circuit region PA1 may be coupled to the memory cell array MCA. The peripheral circuit region PA1 may be disposed at a lower level than the memory cell array MCA. The first substrate W1 is flipped to bond the memory cell array MCA to the peripheral circuit region PA1. The peripheral circuit region PA1 may include one or more control circuits for driving the memory cell array MCA. For example, the peripheral circuit region PA1 may include a sub-word line driver SWD, a sense amplifier SA, and a peripheral control circuit CL. The first wire BL of the memory cell array MCA may be coupled to the sense amplifier SA.

[0263] The peripheral circuit region PA1 and the memory cell array MCA may be coupled to each other through a bonding structure WBD. The peripheral circuit region PA1 and the dummy region PA2 may be coupled to each other through the bonding structure WBD and the first multi-level interconnect LML. The bonding structure WBD may include a plurality of bonding pads CBD and PBD. The peripheral circuit region PA1 and the memory cell array MCA may be coupled to each other through the bonding structure WBD and the first multi-level interconnect LML. The bonding pads CBD and PBD may include a first bonding pad CBD and a second bonding pad PBD. The first bonding pad CBD and the second bonding pad PBD may be coupled to each other through wafer bonding. The first bonding contact plug CBC may be coupled to the first bonding pad CBD. The second bonding contact plug PBC may be coupled to the second bonding pad PBD.

[0264] The first wire BL of the memory cell array MCA can be coupled to the first bonding pad CBD and the first bonding contact plug CBC through the front-layer interconnect FM1. The cell contact plug WC of the memory cell array MCA can be coupled to the first bonding pad CBD and the first bonding contact plug CBC through the front-layer interconnect FM1. Sidewall spacers F1S can be formed on the sidewalls of the first front contact plug F1C. The sidewall spacers F1S can include a dielectric material. The common plate PL of the data storage element CAP of the memory cell array MCA can be coupled to the second multi-level interconnect UML through the nano-silicon via PC and the back-layer interconnect PM. The nano-silicon via PC can penetrate the back surface of the first substrate W1. Nano-scale spacers SP2 can be formed on the sidewalls of the nano-silicon via PC. The nano-scale spacers SP2 can be disposed between the nano-silicon via PC and the first substrate W1.

[0265] The dummy region PA2 can include a dummy stack SG, a stack-level plug FC passing through the dummy stack SG, and stack-level spacers SP1 formed on the sidewalls of the stack-level plug FC. The stack-level spacers SP1 can include a dielectric material. The dummy stack SG can include silicon layers S1 and S3 and silicon-germanium layers S2 and S4.

[0266] The stack-level spacers SP1 can be disposed between the stack-level plug FC and the dummy stack SG. The stack of the silicon layers S1 and S3 and the silicon-germanium layers S2 and S4 can be disposed around the stack-level plug FC and the stack-level spacers SP1. The vertical height of the stack-level plug FC can be greater than the vertical height of the nano-silicon via PC.

[0267] The second multi-level interconnect UML can be coupled to the upper part of the stack-level plug FC. The front-layer interconnect FM1 can be coupled to the lower part of the stack-level plug FC. The front-layer interconnect FM1 can be coupled to the first bonding contact plug CBC and the first bonding pad CBD. The peripheral control circuit CL can be coupled to the second bonding contact plug PBC and the second bonding pad PBD through the first multi-level interconnect LML.

[0268] The sub-word line driver SWD and the sense amplifier SA can be respectively coupled to the second bonding contact plug PBC and the second bonding pad PBD through the first multi-level interconnect LML.

[0269] According to an embodiment of the present disclosure, spacers can be formed on the sidewalls of the stack-level plugs provided in the dummy region, thereby preventing short circuits between adjacent structures.

[0270] While embodiments of the present disclosure have been described with respect to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A memory cell array; a dummy region including a dummy stack horizontally spaced apart from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and the dummy region; a stack-level plug passing through the dummy stack; as well as A stack-level spacer is formed on a sidewall of the stack-level plug.

2. The semiconductor device according to claim 1, wherein The dummy area also includes: a substrate, including a front side and a back side; a nano-through silicon via passing through the substrate and coupled to an upper portion of the stack-level plug; and A nanoscale spacer formed on the sidewall of the nano-through silicon via, wherein the dummy stack is formed on the front side of the substrate, and the substrate is turned over so that the dummy stack and the peripheral circuit region face each other.

3. The semiconductor device according to claim 2, wherein: A vertical height of the stack-level plug is greater than a vertical height of the nano-through silicon via.

4. The semiconductor device according to claim 1, wherein: The dummy stack comprises: A plurality of silicon layers and a plurality of silicon germanium layers are alternately stacked.

5. The semiconductor device according to claim 1, wherein The peripheral circuit area includes: A plurality of control circuits are used to drive the memory cell array.

6. The semiconductor device according to claim 1, wherein The memory cell array includes a plurality of memory cells stacked vertically, and Wherein, each of the storage units comprises: horizontal layers, which are oriented horizontally; a first conductive line vertically oriented and coupled to a first side of the horizontal layer; a second conductive line oriented horizontally and passing through the horizontal layer; and A data storage element is coupled to the second side of the horizontal layer.

7. The semiconductor device according to claim 6, wherein: The second conductive line of the memory cell array comprises: Stepped pad section.

8. The semiconductor device according to claim 7, wherein: The pad portion comprises: upper horizontal line; Lower horizontal line; and A pad is located between the upper horizontal line and the lower horizontal line.

9. The semiconductor device according to claim 6, wherein: The second conductive line of the memory cell array comprises: The pad portion without steps.

10. The semiconductor device according to claim 1, further comprising: A bonding structure disposed at: between the peripheral circuit region and the memory cell array, and between the peripheral circuit region and the dummy region.

11. The semiconductor device according to claim 10, wherein: The bonding structure comprises: first bonding pads respectively coupled to the memory cell array and the stack-level plug; and A second bonding pad is coupled to the peripheral circuit region.

12. A method for manufacturing a semiconductor device, the method comprising: forming a memory cell array and a dummy stack horizontally spaced apart from each other over a first substrate; forming a stack-level contact hole to penetrate the dummy stack; forming a stack-level spacer on a sidewall of the stack-level contact hole; as well as A stack-level plug is formed over the stack-level spacer to fill the stack-level contact hole.

13. The method according to claim 12, wherein: The memory cell array includes a plurality of memory cells stacked vertically, and Wherein, each of the storage units comprises: horizontal layers, which are oriented horizontally; a first conductive line vertically oriented and coupled to a first side of the horizontal layer; a second conductive line oriented horizontally and crossing the horizontal layer; and A data storage element is coupled to the second side of the horizontal layer.

14. The method according to claim 12, wherein: Forming the memory cell array and the dummy stack horizontally spaced apart from each other over the first substrate includes: forming a stack on the first substrate; and replacing the first portion of the stack with a unit mold, and Wherein, the second part of the stack body is reserved as the dummy stack.

15. The method according to claim 12, further comprising: forming a plurality of control circuits on the second substrate; forming first bonding pads respectively coupled to the memory cell array and the stack-level plug; forming a second bonding pad coupled to the control circuit; as well as The first bonding pad and the second bonding pad are wafer-bonded by turning over the first substrate.

16. The method according to claim 15, further comprising: After wafer bonding the first bonding pad and the second bonding pad, forming a nano-via to penetrate the back side of the first substrate and expose the stack-level plug; forming nanoscale spacers on sidewalls of the nano-perforations; forming a nano-through silicon via on the nano-scale spacer to fill the nano-through hole; as well as An upper layer interconnection is formed on the nano-silicon through-via.

17. The method according to claim 15, further comprising: Before forming the first bonding pads respectively coupled to the memory cell array and the stack-level plug, forming a lower level interconnect to be coupled to the stack-level plug; as well as A first bonding contact plug is formed over the lower-level interconnect.

18. A semiconductor device comprising: A memory cell array is disposed on a first substrate; a second substrate including a front side and a back side and turned over to face the memory cell array; a peripheral circuit formed on the front surface of the second substrate; as well as A backside interconnection structure passes through the second substrate from the backside of the second substrate and is coupled to the peripheral circuit.

19. The semiconductor device according to claim 18, wherein: The backside interconnect structure comprises: a power supply interconnection line embedded in the second substrate; a power contact plug coupled to a bottom surface of the power interconnect; a power via coupled to a top surface of the power interconnection line; and A multi-level interconnect is provided, which is coupled to the top surface of the power via.

20. The semiconductor device according to claim 18, further comprising: A power level spacer is formed on the sidewall of the power interconnection line and the sidewall of the power via.

21. The semiconductor device according to claim 20, wherein: The power interconnection line is embedded in the second substrate, and a sidewall of the power interconnection line is completely surrounded by the power level spacer and isolated from the second substrate by the power level spacer.

22. The semiconductor device according to claim 18, further comprising: a first bonding pad coupled to the memory cell array; as well as A second bonding pad is coupled to the peripheral circuit.

23. The semiconductor device according to claim 18, wherein: The peripheral circuit comprises: A plurality of control circuits are used to drive the memory cell array.

24. The semiconductor device according to claim 18, wherein The memory cell array includes a plurality of memory cells stacked vertically, and Wherein, each of the storage units comprises: horizontal layers, which are oriented horizontally; a first conductive line vertically oriented and coupled to a first side of the horizontal layer; a second conductive line oriented horizontally and crossing the horizontal layer; and A data storage element is coupled to the second side of the horizontal layer.

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