Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes forming a stack over a lower structure in which a substrate, a barrier layer, and a support layer are sequentially stacked; forming a plurality of sacrificial vertical openings by etching the stack and the support layer using the barrier layer as an etch stop layer; and forming a three-dimensional memory cell including a vertical conductive line, a horizontal conductive line, and a data storage element in the stack.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0178784, filed on December 11, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including three - dimensional memory cells and a method of manufacturing the semiconductor device. Background art

[0004] To meet the demands for high capacity and miniaturization of storage devices, a technology for providing a three - dimensional (3D) storage device in which a plurality of memory cells are stacked has recently been disclosed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device including highly integrated memory cells and a method of manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a stack on a sub - structure in which a substrate, a barrier layer, and a support layer are sequentially stacked; forming a plurality of sacrificial vertical openings by etching the stack and the support layer using the barrier layer as an etch stop layer; and forming three - dimensional memory cells including vertical wires, horizontal wires, and data storage elements in the stack.

[0007] According to another embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a sub - structure including a substrate, a sacrificial barrier layer, and a support layer stacked in sequence; forming an etch target layer on the sub - structure, in which a first semiconductor layer and a second semiconductor layer are alternately stacked; forming a plurality of sacrificial isolation openings and a stack by etching the etch target layer and the support layer using the sacrificial barrier layer as an etch stop layer; forming sacrificial spacers on sidewalls of the sacrificial isolation openings; forming a lower - layer gap by removing the sacrificial barrier layer; and filling the lower - layer gap with a barrier layer.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a sub - structure including a substrate, a barrier layer, and a support layer stacked in sequence; a memory cell array including a plurality of vertical wires vertically extending from the barrier layer; and a cell isolation layer disposed between the vertical wires.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a lower structure including a substrate, a barrier layer, and a support layer sequentially stacked; a cell isolation layer vertically oriented from the lower structure in a first direction; a horizontal layer horizontally oriented in a second direction intersecting the first direction and vertically stacked in the first direction between the cell isolation layers; a vertical wire vertically oriented in the first direction and coupled to a first edge of the horizontal layer; a horizontal wire intersecting the horizontal layer in a third direction intersecting the first and second directions; and data storage elements respectively coupled to a second edge of the horizontal layer.

[0010] According to another embodiment of the present invention, a semiconductor device includes: a lower structure including a substrate and a barrier layer sequentially stacked; a memory cell array including a plurality of vertical wires vertically extending from the barrier layer; and a cell isolation layer disposed between the vertical wires, wherein the memory cell array includes: a plurality of horizontal layers respectively horizontally extending from the vertical wires; a horizontal wire horizontally extending while surrounding the horizontal layers; and a plurality of data storage elements respectively coupled to the horizontal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a schematic perspective view showing a memory cell according to an embodiment of the present invention.

[0012] Figure 1B is a schematic cross-sectional view showing Figure 1A the memory cell shown in

[0013] Figure 1C is a schematic cross-sectional view showing Figure 1A the switching element shown in

[0014] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention.

[0015] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0016] Figure 3A is a schematic perspective view showing Figure 2 the first memory cell array MCA1 shown in

[0017] Figure 3B is a cross-sectional view taken along line A-A' shown in Figure 2

[0018] Figure 3C is a cross-sectional view taken along line B-B' shown in Figure 2

[0019] Figure 3D ​​is taken along Figure 2 the cross-sectional view taken along line C-C’ shown in

[0020] FIG. 4A to FIG. 27B shows a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0021] FIG. 28A to FIG. 28C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0022] Figure 29 to Figure 31 is a perspective view showing a memory cell array according to other embodiments of the present invention.

[0023] Fig.32 shows a memory cell array according to another embodiment of the present invention.

[0024] Fig.33 shows a memory cell array according to still another embodiment of the present invention. Detailed Description of the Invention

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same components in multiple drawings and embodiments of the present invention.

[0026] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer is present between the first layer and the second layer or between the first layer and the substrate.

[0028] The following embodiments of the present invention relate to three-dimensional memory cells, which can increase the memory cell density and reduce the parasitic capacitance by vertically stacking the memory cells.

[0029] According to the following embodiments of the present invention, a barrier layer of silicon oxide can be formed at the bottom of the bit line to improve the bridging between the bit lines in a three-dimensional dynamic random access memory (DRAM) structure.

[0030] Figure 1A is a schematic perspective view showing a memory cell MC according to an embodiment of the present invention. Figure 1B is showing Figure 1ASchematic cross-sectional view of the memory cell shown in Figure 1C is a diagram showing Figure 1A Planar view of the switching element shown in

[0031] Reference Figures 1A to 1C , the memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0032] The first wire BL may be vertically oriented along a first direction D1. The first wire BL may include a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a cylindrical bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0033] The switching element TR may have a function of controlling the supply of voltage (or current) to the data storage element CAP during a data write operation and a data read operation for the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0034] The horizontal layer HL may extend in a second direction D2 intersecting (perpendicular) to the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), while the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0035] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide. According to another embodiment of the present disclosure, the horizontal layer HL may include a two-dimensional material. For example, the two-dimensional material may include MoS 2, MoSe 2 , MoTe 2 , WS 2 , WSe 2 or WTe 2 .

[0036] The upper and lower surfaces of the horizontal layer HL may have flat surfaces. The upper and lower surfaces of the horizontal layer HL may be parallel to each other in the second direction D2.

[0037] The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is an oxide semiconductor material, the channel CH may be formed of the oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0038] The first doped region SR and the second doped region DR may be doped with impurities of the same conduction type. Each of the first doped region SR and the second doped region DR may be doped with N-type conductive impurities or P-type conductive impurities. Each of the first doped region SR and the second doped region DR may include at least one impurity selected from the group consisting of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first wire BL, while the second doped region DR may be coupled to the data storage element CAP. The first doped region SR and the second doped region DR may be respectively referred to as a first source / drain region and a second source / drain region.

[0039] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first wire BL.

[0040] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL therebetween. An interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL, and the lower horizontal line G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal line G1 and lower horizontal line G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 may form a pair and may be coupled to a memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 may be used as a back gate or a shielding gate.

[0041] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second wire DWL may include a stack of a low work function material and a high work function material.

[0042] Each of the upper horizontal line G1 and the lower horizontal line G2 may have a greater width in the second direction D2 (e.g., the width of the overlapping portion overlapping with the horizontal layer HL) than the width of the non-overlapping portion that does not overlap with the horizontal layer HL. Due to this width difference, the side walls of the second wire DWL extending in the third direction D3 may have notched side walls.

[0043] Return reference Figure 1C , the second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to the portion overlapping with the channel CH of the horizontal layer HL. The channel non-overlapping portion NOL may refer to the portion that does not overlap with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a rhombus shape. According to another embodiment of the present invention, the side surface of the channel overlapping portion WLP may have a curved shape or a circular shape.

[0044] The channel CH and the channel overlapping portion WLP of the second wire DWL may overlap each other. The channel CH may have a cross shape or a rhombus shape. The size of the channel overlapping portion WLP of the second wire DWL may be greater than the size of the channel CH. The channel overlapping portion WLP of the second wire DWL may completely overlap the channel CH.

[0045] Viewed from a top-down perspective, the horizontal layer HL may have a cross shape or a rhombus shape. According to another embodiment of the present invention, the side surface of the horizontal layer HL may have a curved shape or a circular shape.

[0046] An interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3, ZrO 2 , AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD can be formed by a thermal oxidation process of a semiconductor material.

[0047] The data storage element CAP can include a storage element such as a capacitor. The data storage element CAP can be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP can include a first electrode SN that horizontally extends from the horizontal layer HL in the second direction D2. The data storage element CAP can further include a second electrode PN located above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN can be horizontally disposed in the second direction D2. The first electrode SN can include an internal space and a plurality of outer surfaces. The internal space of the first electrode SN can include a plurality of inner surfaces. The outer surfaces of the first electrode SN can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN can vertically extend in the first direction D1. The horizontal outer surfaces of the first electrode SN can horizontally extend in the second direction D2 or the third direction D3. The internal space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN can be disposed in the internal space of the first electrode SN above the dielectric layer DE. Some of the outer surfaces of the first electrode SN can be electrically connected to the second doped region DR of the horizontal layer HL.

[0048] The data storage element CAP can be a three-dimensional structure. The first electrode SN can have a three-dimensional structure, which can be a horizontally oriented three-dimensional structure in the second direction D2. In an example of the three-dimensional structure, the first electrode SN can have a cylindrical shape. The cylindrical shape of the first electrode SN can include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN can be electrically connected to the second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN can be disposed on the cylindrical inner surface of the first electrode SN.

[0049] According to another embodiment of the present invention, the first electrode SN can have a columnar or columnar-cylindrical shape. The columnar-cylindrical shape can refer to a structure in which a columnar shape and a cylindrical shape are combined.

[0050] The first electrode SN and the second electrode PN can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2) Iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0051] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0052] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO 2 ). The dielectric layer DE may include a ZA (ZrO 2 / Al 2 O 3 ) stack or a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack may have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on zirconium oxide (ZrO 2 ). The ZAZ stack may have a structure in which zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide (ZrO 2 ) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as being based on zirconium oxide (ZrO2 ) layer. According to another embodiment of the present invention, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can be a stacked structure including hafnium oxide (HfO 2 ). The dielectric layer DE can include HA (HfO 2 / Al 2 O 3 ) stack or HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack can have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on hafnium oxide (HfO 2 ). The HAH stack can have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) are sequentially stacked. The HA stack and the HAH stack can be referred to as hafnium oxide (HfO 2 )-based layers. Among the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, aluminum oxide (Al 2 O 3 ) can have a larger bandgap energy than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Aluminum oxide (Al 2 O 3 ) can have a lower dielectric constant than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap energy than the high-k material. In addition to aluminum oxide (Al 2 O 3 ), the dielectric layer DE can also include silicon oxide (SiO 2 ) as another high-bandgap material. By including the high-bandgap material, the dielectric layer DE can be capable of suppressing leakage current. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE can include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, a ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO2 / Al 2 O 2 / ZrO 2 ) stacked, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stacked, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stacked, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) stacked, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) stacked, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) stacked or AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / Al 2 O 3 ) stacked. In the above stacking structure, aluminum oxide (Al 2 O 3 ) can be thinner than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ).

[0053] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material. The dielectric layer DE may have a stacked structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0054] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0055] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material. According to another embodiment of the present disclosure, the dielectric layer DE may include a perovskite dielectric material. The perovskite dielectric material may include SrTiO 3 , (Ba,Sr)TiO 3 , BaTiO 3 , PbTiO 3 , PZT, PLZT or PbTiO 3 .

[0056] According to another embodiment of the present invention, an interface control layer may be further formed to improve the leakage current between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0057] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0058] For example, the storage cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced with an anode wire. The horizontal layer HL may include four semiconductor layers horizontally stacked in the second direction D2. The thyristor may include a first diode and a second diode connected in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state with a large amount of current flowing or a low conductance state with a small amount of current flowing or no current flowing. The storage cell MC may have a "1" state and a "0" state respectively according to the high conductance state and the low conductance state of the thyristor.

[0059] Return reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first wire BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0060] Figure 1D is a schematic cross-sectional view showing a memory cell MC1 according to another embodiment of the present invention. Figure 1D The memory cell MC1 may be similar to Figures 1A to 1C the memory cell MC. Hereinafter, the detailed description of the constituent elements that also appear in Figures 1A to 1C will be omitted.

[0061] See Figure 1D , the memory cell MC1 may include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0062] The memory cell MC1 may further include a first contact node BLC between the first wire BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0063] The second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second work function electrode G12, the first work function electrode G11, and the third work function electrode G13 may be horizontally arranged in the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be adjacent to the first conductive line BL, and the third work function electrode G13 may be adjacent to the data storage element CAP. The first work function electrode G11 may be disposed between the second work function electrode G12 and the third work function electrode G13. The horizontal layer HL may have a thickness smaller than that of each of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0064] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of different work function materials. The first work function electrode G11 may have a higher work function than the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include low work function materials. The second work function electrode G12 and the third work function electrode G13 may have a work function less than the mid-gap work function of silicon. Specifically, the high work function material may have a work function greater than about 4.5 eV, while the low work function material may have a work function less than about 4.5 eV. The first work function electrode G11 may include a metal-based material, while each of the second work function electrode G12 and the third work function electrode G13 may include a semiconductor material.

[0065] Each of the second work function electrode G12 and the third work function electrode G13 may include polysilicon doped with an N-type dopant, i.e., N-type dopant-doped polysilicon. The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0066] According to an embodiment of the present invention, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a second work function electrode G12, a first work function electrode G11, and a third work function electrode G13 horizontally arranged in the second direction D2 in this order. The first work function electrode G11 may include a metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0067] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a polysilicon-metal-polysilicon (PMP) structure, in which polysilicon, metal, and polysilicon are horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and each of the second work function electrode G12 and the third work function electrode G13 may be N-type doped polysilicon. The N-type dopant may include phosphorus or arsenic.

[0068] A first barrier layer G12L may be provided between the first work function electrode G11 and the second work function electrode G12. A second barrier layer G13L may be provided between the first work function electrode G11 and the third work function electrode G13. Each of the first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface, and one side surface of the first work function electrode G11.

[0069] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13. Therefore, the second wire DWL may have a low resistance. The first work function electrodes G11 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The second work function electrodes G12 and the third work function electrodes G13 of the upper horizontal line G1 and the lower horizontal line G2 may also vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The overlapping area of the first work function electrode G11 and the horizontal layer HL may be larger than the overlapping areas of the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrode G13 may have an independent structure overlapping with the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlapping portion WLP and a channel non-overlapping portion NOL, and the second work function electrode G12 and the third work function electrode G13 may be a part of the channel overlapping portion WLP. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may be in direct contact with each other.

[0070] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a triple work function electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13, which extend in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0071] As Figure 1C shown, each second wire DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap the channel CH. The second wire DWL extending in the third direction D3 through the channel overlap portion WLP and the channel non-overlap portion NOL may have a notched sidewall. From a top view perspective, the notched sidewall may be provided by a protruding portion formed through the channel overlap portion WLP and a recessed portion formed through the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0072] In the second direction D2, the first work function electrode G11 having a high work function may be disposed at the center of the second wire DWL, while the second work function electrode G12 and the third work function electrode G13 having a low work function may be disposed on both side surfaces of the second wire DWL, thereby improving leakage current (e.g., gate-induced drain leakage (GIDL)).

[0073] By disposing the first work function electrode G11 having a high work function at the center of the second wire DWL, the threshold voltage of the switching element TR can be increased. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field may be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field may be formed between the data storage element CAP and the second wire DWL.

[0074] As described above, the memory cell MC1 may include a second wire DWL having a triple work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap with the channel CH. The second work function electrode G12 may be adjacent to the first wire BL and the first doped region SR. The third work function electrode G13 may be adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, which may improve the leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, which may improve the leakage current. Due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR may be increased. In addition, due to the high work function of the first work function electrode G11, the height of the memory cell MC1 may be reduced, which is advantageous for integration.

[0075] Figure 2 is a schematic plan view showing a semiconductor device 100 according to an embodiment of the present invention. Figure 3A is showing Figure 2 a schematic perspective view of the first memory cell array MCA1 shown in Figure 3B is a cross-sectional view taken along the line A-A' shown in Figure 2 Figure 3C is a cross-sectional view taken along the line B-B' shown in Figure 2 Figure 3D is a cross-sectional view taken along the line C-C' shown in Figure 2

[0076] Referring to Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. Each memory cell MC will be described with reference to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0077] ​​​The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1. The row array of memory cells MC may include a plurality of memory cells MC horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include sub-memory cell arrays MCA1 adjacent to each other in the second direction D2. The sub-memory cell array MCA1 may have a mirror structure in which two memory cells MC share a first wire BL. According to another embodiment of the present invention, the semiconductor device 100 may further include a sub-memory cell array having a mirror structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which the memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 horizontally arranged in the third direction D3.

[0078] According to another embodiment of the present invention, the memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 arranged in the second direction D2. For example, in the second direction D2, the data storage element CAP, the switching element TR, the first wire BL, and the switching element TR may be sequentially arranged.

[0079] The inter-cell dielectric layer IL may be provided between the memory cells MC stacked in the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer. The hard mask layer HM may be provided on the uppermost inter-cell dielectric layer IL.

[0080] The cell isolation layers ISOA and ISOB can be disposed between adjacent memory cells MC in a third direction D3. The cell isolation layers ISOA and ISOB can be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB can include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB can include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB can vertically extend in a first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB can have a column structure that vertically extends along the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB can be alternately and repeatedly disposed in a second direction D2. The first cell isolation layer ISOA can be disposed between data storage elements CAP in the third direction D3. The second cell isolation layer ISOB can be disposed between first wires BL in the third direction D3. A second wire DWL can be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB can include a stack of a cell isolation liner layer ISOL and a cell isolation gap-fill layer ISOG. The cell isolation liner layer ISOL can include silicon oxide, and the cell isolation gap-fill layer ISOG can include silicon carbon oxide.

[0081] A memory cell array MCA can be disposed over a lower structure LS. A first wire BL and a common plate PL of the memory cell array MCA can be supported by a support layer LSP. A barrier layer ESL can be disposed between the lower structure LS and the support layer LSP. The lower structure LS and the support layer LSP can include a silicon-containing material, and the barrier layer ESL can include a dielectric material. The lower structure LS and the support layer LSP can include a single-crystalline silicon layer, and the barrier layer ESL can include silicon oxide. The support layer LSP can support the first wire BL and the data storage element CAP. The barrier layer ESL can be disposed between the lower structure LS and the support layer LSP. The first wire BL and a first contact node BLC can contact the barrier layer ESL.

[0082] The barrier layer ESL can prevent bridging between adjacent first wires BL adjacent to each other in the third direction D3. Additionally, the barrier layer ESL can prevent bridging between the first wire BL and the data storage element CAP.

[0083] The memory cell array MCA may include a plurality of second conductive wires DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of first conductive wires BL spaced apart from each other in a third direction D3.

[0084] Each second conductive wire DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL, as Figure 1C shown. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductive wire DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portions WLP and the channel non-overlap portions NOL are alternately repeated in the third direction D3, the second conductive wire DWL may have a notched sidewall.

[0085] A plurality of first passivation layers BF1 may be disposed between the lower structure LS and the lowermost second conductive wire DWL among the second conductive wires DWL. A second passivation layer BF2 may be disposed between the first conductive wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. Each of the first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. Each of the first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first conductive wire BL, the second conductive wire DWL, and the data storage element CAP from the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The lowermost inter-cell insulating layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0086] The first conductive wire BL may vertically extend in the first direction D1 above the lower structure LS. The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second conductive wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2.

[0087] Viewed from above, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, the side surface of the horizontal layer HL may have a curved shape or a circular shape. As Figure 1B shown, the horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive wire BL, and a second doped region DR between the channel CH and the data storage element CAP. Return reference Figure 3C, a horizontal level spacer HLS may be formed on a side surface of the horizontal level HL. The horizontal level spacer HLS may include a dielectric material (e.g., silicon oxide).

[0088] A first capping layer BC may be disposed between the second wire DWL and the first wire BL. A second capping layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first capping layer BC may be disposed between the upper horizontal line G1 and the first wire BL. In addition, the first capping layer BC may also be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP. In addition, the second capping layer CC may also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. A memory cell MC may include a pair of first capping layers BC and a pair of second capping layers CC.

[0089] The first capping layer BC and the second capping layer CC may include a dielectric material. The first capping layer BC and the second capping layer CC may include silicon oxide, silicon nitride, silicon oxynitride, air gap, or a combination thereof. The first capping layer BC may include silicon oxide, and the second capping layer CC may include a stack of silicon oxide and silicon nitride. According to another embodiment of the present invention, the first capping layer BC may include a stack of silicon oxide and silicon nitride.

[0090] The horizontal levels HL of the switching elements TR horizontally disposed along the third direction D3 may share a second wire DWL. The horizontal levels HL of the switching elements TR horizontally disposed along the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked along the first direction D1 may share a first wire BL. The horizontal levels HL of the switching elements TR horizontally disposed along the third direction D3 may share a second wire DWL.

[0091] A first unit isolation layer ISOA may be disposed between the first electrodes SN of the data storage elements CAP in the third direction D3. The first electrodes SN may be separated from each other by the first unit isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to a common plate PL.

[0092] According to another embodiment of the present invention, the lower structure LS may further include a semiconductor substrate, a metal interconnect structure, an insulating structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit unit.

[0093] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnect structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be bonded by wafer bonding.

[0094] The peripheral circuit unit of the lower structure LS may be disposed at a level lower than that of the memory cell array MCA. This may be referred to as a Cell-over-PERI (COP) structure. The peripheral circuit unit may include one or more control circuits for driving the memory cell array MCA. At least one or more of the control circuits of the peripheral circuit unit may include N-channel transistors, P-channel transistors, CMOS circuits, or combinations thereof. One or more control circuits of the peripheral circuit unit may include an address decoder circuit, a read circuit, a write circuit, etc. One or more control circuits of the peripheral circuit unit may include planar channel transistors, recessed channel transistors, buried gate transistors, fin channel transistors (FinFETs), etc.

[0095] For example, the peripheral circuit unit may include a sub-word line driver and a sense amplifier. A second wire DWL may be coupled to the sub-word line driver. A first wire BL may be coupled to the sense amplifier.

[0096] According to another embodiment of the present invention, the peripheral circuit unit may be disposed at a level higher than that of the memory cell array MCA. This may be referred to as a PERI-over-Cell (POC) structure. In this case, the lower structure LS may include a first semiconductor substrate, and the peripheral circuit unit may include a second semiconductor substrate.

[0097] According to another embodiment of the present invention, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND, a ferroelectric random access memory (FeRAM), a spin transfer torque RAM (STT-RAM), a phase change RAM (PCRAM), or a resistive RAM (ReRAM).

[0098] According to another embodiment of the present invention, each memory cell MC may be replaced with Figure 1D the memory cell MC1 shown therein.

[0099] FIG. 4A to FIG. 26B A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0100] Figure 4A is a plan view showing a method of forming a stack SB and sacrificial isolation openings 15A and 15B at the level of the fourth layer 14. Figure 4B is Figure 4A a cross-sectional view taken along line A-A' shown therein. Figure 4C is Figure 4A a cross-sectional view taken along line B-B' shown therein.

[0101] Refer to FIG. 4A to FIG. 4C, the stack SB can be formed on the lower structure 11L. The lower structure 11L can be a material suitable for semiconductor processing. The lower structure 11L can include one or more of a conductive material, a dielectric material, and a semiconductor material.

[0102] The lower structure 11L can include a substrate 11, a barrier layer ESL, and a support layer 11T. The substrate 11 and the support layer 11T can be of the same material. The substrate 11 and the support layer 11T can be formed of a silicon-containing material. Each of the substrate 11 and the support layer 11T can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. Each of the substrate 11 and the support layer 11T can further include another semiconductor material, such as germanium. Each of the substrate 11 and the support layer 11T can further include a group III-V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). The barrier layer ESL can have an etching selectivity with respect to the substrate 11 and the support layer 11T. The barrier layer ESL can include a dielectric material. The barrier layer ESL can include silicon oxide. The barrier layer ESL can be formed by replacing a semiconductor material with a dielectric material.

[0103] The lower structure 11L can include a silicon-on-insulator (SOI) substrate.

[0104] The stack SB can include a plurality of sub-stacks stacked alternately. Each sub-stack can include a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14 stacked in sequence. The first layer 12A and the third layer 12B can be formed of the same material and can include silicon germanium or single-crystalline silicon germanium. The second layer 13 and the fourth layer 14 can be formed of the same material and can include single-crystalline silicon. Each of the first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 can be formed by an epitaxial growth process. The lowermost first layer 12A can act as a seed layer during the epitaxial growth process. Each first layer 12A can be thinner than each second layer 13, and each fourth layer 14 can be thicker than each second layer 13.

[0105] According to an embodiment of the present invention, the stack body SB may include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, and a third stack SB3. The stack body SB may include the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 stacked in sequence. Each of the first stack SB1, the second stack SB2, and the third stack SB3 may include a three-layer stack of a first layer 12A, a second layer 13, and a third layer 12B. For example, when each of the first layer 12A and the third layer 12B includes a silicon-germanium layer and the second layer 13 includes a single-crystalline silicon layer, the first stack SB1, the second stack SB2, and the third stack SB3 may include a first silicon-germanium / single-crystalline silicon / second silicon-germanium (SiGe / Si / SiGe) stack. The third stack SB3 may further include a second layer 13 on top of the three-layer stack of the first layer 12A, the second layer 13, and the third layer 12B.

[0106] Each second layer 13 may include a first single-crystalline silicon layer, and each fourth layer 14 may include a second single-crystalline silicon layer. Each second single-crystalline silicon layer may be thicker than each first single-crystalline silicon layer. Accordingly, the stack body SB may have the first stack SB1 disposed below the second single-crystalline silicon layer and the second stack SB2 disposed above the second single-crystalline silicon layer. Each of the first stack SB1 and the second stack SB2 may include a three-layer stack of a first silicon-germanium layer, a first single-crystalline silicon layer, and a second silicon-germanium layer. Each second single-crystalline silicon layer may be thicker than each first single-crystalline silicon layer.

[0107] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as "sacrificial layers", and the fourth layer 14 may be referred to as a recess target layer.

[0108] The stack body SB may be referred to as a vertical stack. The stack body SB may be formed by alternately arranging a plurality of sacrificial layers and recess target layers. The sacrificial layers may include the first stack SB1, the second stack SB2, and the third stack SB3. Each of the first stack SB1, the second stack SB2, and the third stack SB3 may include a three-layer stack of a first layer 12A, a second layer 13, and a third layer 12B. The recess target layers may include the fourth layer 14. Each sacrificial layer may include a three-layer stack of a first silicon-germanium layer, a first single-crystalline silicon layer, and a second silicon-germanium layer. Each recess target layer may include a single layer of the second single-crystalline silicon layer. Each second single-crystalline silicon layer may be thicker than each first single-crystalline silicon layer.

[0109] Reference Figures 2 to 4C , when the storage cells MC are vertically stacked, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 may be alternately stacked multiple times.

[0110] Subsequently, the stack SB and the support layer 11T can be etched to form a plurality of sacrificial isolation openings 15A and 15B. The sacrificial isolation openings 15A and 15B can be initial openings for cell isolation and can include large openings 15A and small openings 15B. The size of the large opening 15A can be larger than that of the small opening 15B. From a top-down perspective, the large opening 15A and the small opening 15B can have a rectangular shape. According to another embodiment of the present invention, the large opening 15A and the small opening 15B can have a circular or oval shape. According to another embodiment of the present invention, the sacrificial isolation openings 15A and 15B can be referred to as sacrificial isolation trenches. The large opening 15A and the small opening 15B can extend vertically in the first direction D1. The large opening 15A and the small opening 15B can be alternately arranged in the second direction D2. A plurality of large openings 15A can be arranged in the third direction D3. A plurality of small openings 15B can be arranged in the third direction D3. Each of the large opening 15A and the small opening 15B can penetrate the stack SB and the support layer 11T in the first direction D1.

[0111] The etching process for forming the sacrificial isolation openings 15A and 15B can include an etching process of the stack SB and an etching process of the support layer 11T. The etching process of the support layer 11T can stop at the etch stop layer ESL. The bottom surface of the sacrificial isolation openings 15A and 15B can penetrate the support layer 11T to expose the surface of the etch stop layer ESL. The bottom surface of the sacrificial isolation openings 15A and 15B can include a U-shaped profile. The fourth layer 14 can be patterned into a grid shape through the sacrificial isolation openings 15A and 15B.

[0112] FIG. 5A to FIG. 5D Shows a method for forming FIG. 4A to FIG. 4C the lower structure 11L shown in

[0113] Refer to Figure 5A , a sacrificial barrier layer 11S can be formed on the substrate 11. A support layer 11T can be formed on the sacrificial barrier layer 11S. Each of the substrate 11, the sacrificial barrier layer 11S, and the support layer 11T can include a silicon-containing material. The substrate 11 can be a single-crystalline silicon substrate. The support layer 11T can be a single-crystalline silicon layer. The sacrificial barrier layer 11S can be a silicon-germanium layer. The sacrificial barrier layer 11S and the support layer 11T can be formed on the substrate 11 through an epitaxial growth process.

[0114] A stack SB as shown in Figure 4B and Figure 4C can be formed on the support layer 11T.

[0115] Refer to Figure 5B , the stack SB and the support layer 11T can be etched to form a plurality of sacrificial isolation openings 15A and 15B.

[0116] Refer to Figure 5C , a sacrificial spacer 11P can be formed on the sidewalls of the isolation openings 15A and 15B to be sacrificed. The sacrificial spacer 11P can be formed by depositing a dielectric material and etching the dielectric material.

[0117] To form the lower gap 11G, the sacrificial barrier layer 11S can be removed by using the sacrificial spacer 11P as a mask.

[0118] The sacrificial barrier layer 11S can be selectively removed based on the difference in etching selectivity between the sacrificial barrier layer 11S and the substrate 11. The sacrificial barrier layer 11S can be removed by a wet etching process or a dry etching process. For example, when the sacrificial barrier layer 11S includes a silicon-germanium layer and the substrate 11 and the support layer 11T include single-crystalline silicon layers, the silicon-germanium layer can be etched by using an etchant or etching gas that is selective with respect to the single-crystalline silicon layer.

[0119] Reference Figure 5D , a barrier layer ESL for filling the formed Figure 5C lower gap 11G can be formed. To form the barrier layer ESL, a dielectric material for filling the lower gap 11G can be formed. The barrier layer ESL can include silicon oxide.

[0120] As described in reference FIG. 5A to FIG. 5D , the lower structure 11L can include a substrate 11, a barrier layer ESL, and a support layer 11T stacked in sequence.

[0121] Subsequently, the sacrificial spacer 11P can be removed.

[0122] Fig. 6A is a plan view showing a method of forming the sacrificial isolation layers 16A and 16B at the level of the fourth layer 14, Figure 6B is a cross-sectional view taken along the line B-B' shown in Fig. 6A .

[0123] Reference Fig. 6A and Figure 6B , the sacrificial isolation layers 16A and 16B can be formed to fill the sacrificial isolation openings 15A and 15B of 4A to 5D respectively. The sacrificial isolation layers 16A and 16B can include a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A can fill the large opening 15A, while the second sacrificial isolation layer 16B can fill the small opening 15B.

[0124] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. Each of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include forming a sacrificial isolation material over the stack SB to fill the sacrificial isolation openings 15A and 15B, and planarizing the sacrificial isolation material to expose the top layer of the stack SB. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A may be larger than the size (or volume) of the second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have the same length in the third direction D3, but may have different lengths in the second direction D2. The length of the first sacrificial isolation layer 16A in the second direction D2 may be greater than the length of the second sacrificial isolation layer 16B in the second direction D2.

[0125] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in the second direction D2. A plurality of first sacrificial isolation layers 16A may be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may penetrate the stack SB in the first direction D1.

[0126] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. Each of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. For example, each of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbonitride, or a combination thereof.

[0127] Fig. 7A is a plan view at the level of the fourth layer 14 showing a method of forming the sacrificial vertical openings V1' and V2', while Figure 7B is a cross-sectional view taken along Fig. 7A the line A-A' shown in

[0128] Reference Fig. 7A and Figure 7B , a hard mask layer pattern 17 may be formed over the stack SB, the first sacrificial isolation layer 16A, and the second sacrificial isolation layer 16B. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a mask layer. The hard mask layer pattern 17 may have a plurality of hole-shaped openings defined therein.

[0129] Subsequently, the stack SB and the support layer 11T can be etched by using the hard mask layer pattern 17 as an etch stop. As a result, a plurality of sacrificial vertical openings V1' and V2' can be formed in the stack SB and the support layer 11T. The sacrificial vertical openings V1' and V2' can include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can be hole-shaped openings. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can vertically extend in a first direction D1. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can be formed by etching the stack SB and the support layer 11T between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1' can be formed by etching the stack SB and the support layer 11T between the second sacrificial isolation layer 16B. The second sacrificial vertical opening V2' can be formed by etching the stack SB and the support layer 11T between the first sacrificial isolation layer 16A. The first sacrificial vertical opening V1' can be disposed between the second sacrificial isolation layers 16B in a third direction D3. The second sacrificial vertical opening V2' can be disposed between the first sacrificial isolation layers 16A in a third direction D3. From a top-down perspective, the cross-sections of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can be square, circular, or elliptical.

[0130] The etching process for forming the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can stop at the barrier layer ESL. The barrier layer ESL can be used as an etch stop layer during the etching process for forming the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2'. The depths of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' can be uniformly formed by the barrier layer ESL.

[0131] Fig. 8A is a plan view showing a method of forming the preliminary horizontal layer 14A. Figure 8B is along Fig. 8A the line A-A' shown in Figure 8C is along Fig. 8A the line B-B' shown in

[0132] Reference FIG. 8A to FIG. 8C , a part of the hard mask layer pattern 17 can be trimmed (see reference numeral "17T").

[0133] The first layer 12A and the third layer 12B can be selectively removed through the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2'. The first layer 12A and the third layer 12B can be selectively removed based on the etching selectivity difference between the second layer 13 and the fourth layer 14 and the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B can be removed by a wet etching process or a dry etching process. For example, when each of the first layer 12A and the third layer 12B includes a silicon germanium layer, and each of the second layer 13 and the fourth layer 14 includes a single crystal silicon layer, the silicon germanium layer can be etched by using an etchant or etching gas that is selective to the single crystal silicon layer.

[0134] Subsequently, the second layer 13 and the fourth layer 14 can be recessed. The second layer 13 and the fourth layer 14 can be recessed by a wet etching process or a dry etching process. According to an embodiment of the present invention, when the second layer 13 is removed, the fourth layer 14 can be partially etched. As a result, the second layer 13 can be removed, and the fourth layer 14 can be thinned, as shown by the reference numeral "14A". The recessing process for forming the thin fourth layer 14A (i.e., the preliminary horizontal layer 14A) can be referred to as the thinning process or the trimming process of the fourth layer 14. To form the preliminary horizontal layer 14A, the upper surface, the lower surface, and the side surface of the fourth layer 14 can be recessed. The preliminary horizontal layer 14A can be referred to as a thin body active layer. Each preliminary horizontal layer 14A can include a single crystal silicon layer. The recessing process for forming the preliminary horizontal layer 14A can use, for example, HSC1 (i.e., Hot SC-1). HSC1 can include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) are mixed in a ratio of approximately 1:4:20. The second layer 13 and the fourth layer 14 can be selectively etched by using HSC1 as described above.

[0135] The preliminary horizontal layer 14A can be formed by the recessing process of the fourth layer 14 as described above. Horizontal recesses 18 can be formed between the preliminary horizontal layers 14A. Each of the upper surface and the lower surface of the preliminary horizontal layer 14A can include a flat surface.

[0136] From a top-down perspective, the preliminary horizontal layer 14A can have a cross shape. The side surface of the preliminary horizontal layer 14A can have a curved shape or a circular shape.

[0137] After the preliminary horizontal layer 14A is formed, the first sacrificial vertical opening and the second sacrificial vertical opening can be enlarged as indicated by reference numerals "V1" and "V2". The preliminary horizontal layer 14A can be arranged to be spaced apart from each other in the second direction D2 through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A can have a shape in which a plurality of cross shapes are combined in the third direction D3.

[0138] When the preliminary horizontal layer 14A is formed, the surface of the support layer 11T can be recessed to a predetermined depth (see reference numeral "11A"). Accordingly, the widths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can be increased.

[0139] The first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can be alternately arranged between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical opening V1 can be arranged between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical opening V2 can be arranged between the first sacrificial isolation layers 16A in the third direction D3.

[0140] Fig. 9A is a plan view showing a method of forming the first dielectric layer 19 and the second dielectric layer 20. Fig. 9B is along Fig. 9A the cross-sectional view taken along line A-A' shown in Fig. 9C is along Fig. 9A the cross-sectional view taken along line B-B' shown in

[0141] Reference 9A to 9C , the first dielectric layer 19 covering the preliminary horizontal layer 14A can be formed. Each first dielectric layer 19 can include silicon nitride. The first dielectric layer 19 can completely cover the upper surface, the lower surface, and the side surfaces of the preliminary horizontal layer 14A.

[0142] When the first dielectric layer 19 is formed, a dummy dielectric layer 19D can be formed on the surface of the substrate 11. Some of the first dielectric layers in the first dielectric layer 19 can completely cover the upper surface, the lower surface, and the side surfaces of the hard mask layer pattern 17.

[0143] Subsequently, the second dielectric layer 20 can be formed on the first dielectric layer 19. The second dielectric layer 20 can be filled between the vertically adjacent first dielectric layers 19. The second dielectric layer 20 can include silicon oxide. A part of the second dielectric layer 20 can be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontal recess ( Figure 8B and Figure 8C 18) can be filled with the first dielectric layer 19 and the second dielectric layer 20.

[0144] The sacrificial pillar 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial pillar 21 may include amorphous carbon as a sacrificial material. According to another embodiment of the present invention, a pillar capping layer may also be formed on the sacrificial pillar 21. The pillar capping layer may include a metal-based material. The pillar capping layer may include titanium nitride. Forming the sacrificial pillar 21 may include depositing the sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial pillar 21 may be performed until the uppermost first dielectric layer 19 is exposed. Subsequently, the uppermost second dielectric layer 20 may also be planarized until the uppermost first dielectric layer 19 is exposed. The sacrificial pillar 21 may not be formed between the vertically stacked first dielectric layers 19.

[0145] The second dielectric layer 20 and the sacrificial pillar 21 may form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2 that fill the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The first sacrificial pillar structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial pillar structure SV2 may fill the second sacrificial vertical opening V2. According to another embodiment of the present invention, each of the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, each of the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From a top-down perspective, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may be hole-shaped sacrificial pillars. According to another embodiment of the present invention, a portion of the first dielectric layer 19 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. Therefore, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may also include a portion of the first dielectric layer 19.

[0146] Return to Fig. 9C , the first dielectric layer 19 may be formed between the preliminary horizontal layers 14A, and the second dielectric layer 20 may be disposed within each first dielectric layer 19. Each first dielectric layer 19 may surround each second dielectric layer 20. The first dielectric layer 19 may include a first surrounding portion and a second surrounding portion. The first surrounding portion may surround the preliminary horizontal layer 14A in the A-A' direction, and the second surrounding portion may surround the second dielectric layer 20 in the B-B' direction.

[0147] As described above, a unit mode structure can be formed by forming a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. The unit mode structure can include a plurality of unit modes CM. Each unit mode CM can include a plurality of mode layers. The mode layers can refer to the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20. Each unit mode CM can include an oxide-nitride-silicon-nitride (ONSN) stack. Here, the ONSN stack can refer to a structure in which silicon oxide, first silicon nitride, single-crystalline silicon layer, and second silicon nitride are sequentially stacked. The silicon oxide can correspond to the second dielectric layer 20. The first silicon nitride and the second silicon nitride can correspond to the first dielectric layer 19. The single-crystalline silicon layer can correspond to the preliminary horizontal layer 14A. The unit mode structure including a plurality of unit modes CM can be referred to as a vertical stack. From another perspective, the unit mode structure can include an oxide-nitride-silicon-nitride-oxide (ONSNO) stack. Here, the ONSNO stack can refer to a structure in which first silicon oxide, first silicon nitride, single-crystalline silicon layer, second silicon nitride, and second silicon oxide are sequentially stacked.

[0148] As described above, the sub-stack of the stack body SB can be replaced with the unit mode CM by 4A to 9C a series of processes shown in. The first layer 12A, the second layer 13, and the third layer 12B can be replaced with the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 can be turned into the preliminary horizontal layer 14A through a recess process. The first dielectric layer 19 can be referred to as a trimming target layer.

[0149] Fig. 10A is a plan view showing a method of forming unit isolation openings 22A and 22B and a horizontal layer 14B, Fig. 10B is a cross-sectional view taken along the Fig. 10A line B-B' shown in.

[0150] Referring to Fig. 10A and Fig. 10B , 9A to 9C the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B can be removed to form the unit isolation openings 22A and 22B. When the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B are removed, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be covered by a mask layer. The unit isolation openings 22A and 22B can expose the side surfaces of the preliminary horizontal layer 14A and the first dielectric layer 19 in the B-B' direction.

[0151] Subsequently, 9A to 9CThe side surfaces of the initial horizontal layer 14A can be trimmed in the second direction D2 and the third direction D3 through the cell isolation openings 22A and 22B. As a result, a trimmed horizontal layer 14B can be formed. A horizontal layer gap 14R can be formed on the side surface of the horizontal layer 14B. The horizontal layer gap 14R and the horizontal layer 14B can be disposed between the first dielectric layers 19. The horizontal layer 14B can be referred to as a "trimmed horizontal layer pattern".

[0152] When the horizontal layer 14B is formed, the surface of the substrate 11 (such as the bottom surfaces of the cell isolation openings 22A and 22B) can be enlarged.

[0153] The horizontal layer 14B can be disposed between the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 in the second direction D2. From a top view perspective, the horizontal layer 14B can have a cross shape. The horizontal layer 14B can have a cross shape with dimensions smaller than those of the initial horizontal layer 14A. The initial horizontal layer 14A can have a shape in which multiple cross shapes are combined, and the horizontal layer 14B can have a shape in which the cross shapes are separately separated in the third direction D3. The horizontal layer gap 14R can be formed between the horizontal layers 14B disposed in the third direction D3. The first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be disposed between the horizontal layers 14B in the second direction D2.

[0154] Fig.11A is a plan view showing a method of forming the horizontal layer spacers 23 and the first dielectric layer 19A, Fig. 11B is along Fig.11A the cross-sectional view taken along the line B - B' shown.

[0155] Refer to Fig.11A and Fig. 11B , the horizontal layer spacers 23 can be formed on the side surfaces of the horizontal layer 14B. Forming the horizontal layer spacers 23 can include forming a spacer material on the side surfaces of the horizontal layer 14B and etching the spacer material. Each horizontal layer spacer 23 can include a dielectric material, such as silicon oxide. The horizontal layer spacers 23 can fill the horizontal layer gap 14R. The horizontal layers 14B disposed in the third direction D3 can be separated from each other by the horizontal layer spacers 23.

[0156] Subsequently, a portion of the first dielectric layer 19 can be horizontally trimmed through the cell isolation openings 22A and 22B. After the trimming process, the first dielectric layer 19 can be retained, as indicated by the reference numeral '19A'. Therefore, from the perspective of the line B - B', a pair of first dielectric layers 19A can be disposed between the horizontal layers 14B, and the second dielectric layer 20 can be disposed between the pair of first dielectric layers 19A.

[0157] Refer to FIG. 10A to FIG. 11B, the width of the first dielectric layer 19A between the unit isolation openings 22A and 22B in the third direction D3 can be greater than the width of the horizontal layer 14B. The trimming depth of the first dielectric layer 19 in the third direction D3 can be less than the trimming depth of the preliminary horizontal layer 14A.

[0158] A pair of first dielectric layers 19A can vertically overlap with a horizontal layer 14B. The trimmed first dielectric layer 19A can be referred to as the trimmed first dielectric layer.

[0159] As described above, the first dielectric layer 19 and the preliminary horizontal layer 14A can be FIG. 10A to FIG. 11B horizontally trimmed by the series of processes shown. Thus, the unit die can include the horizontal layer 14B, the first dielectric layer 19A, and the second dielectric layer 20.

[0160] Fig. 12A is a plan view showing a method of forming the unit isolation layers 24A and 24B, Fig. 12B is a cross-sectional view taken along the Fig. 12A line B-B' shown. Fig. 12A can be a plan view showing a method of forming the unit isolation layers 24A and 24B at the level of the first dielectric layer 19A.

[0161] Referring to Fig. 12A and Fig. 12B , the unit isolation layers 24A and 24B can be formed to fill the Fig.11A and Fig. 11B unit isolation openings 22A and 22B. The unit isolation layers 24A and 24B can include a first unit isolation layer 24A and a second unit isolation layer 24B. The first unit isolation layer 24A and the second unit isolation layer 24B can include the same material. Each of the first unit isolation layer 24A and the second unit isolation layer 24B can be formed of a dielectric material. For example, the first unit isolation layer 24A and the second unit isolation layer 24B can include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbonitride, or a combination thereof. From a top-down perspective, the outermost material of each of the first unit isolation layer 24A and the second unit isolation layer 24B can include silicon oxide.

[0162] Forming the first unit isolation layer 24A and the second unit isolation layer 24B may include forming unit isolation materials filling the unit isolation openings 22A and 22B, and planarizing the unit isolation materials and the topmost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first unit isolation layer 24A and the second unit isolation layer 24B may have different sizes or different volumes. Each of the first unit isolation layer 24A and the second unit isolation layer 24B may include a dual structure of silicon oxide and silicon oxycarbide. For example, for each unit isolation layer, silicon oxycarbide may be deposited after depositing silicon oxide. According to another embodiment of the present invention, the first unit isolation layer 24A and the second unit isolation layer 24B may include embedded air gaps, and the air gaps may be provided during the deposition of silicon oxycarbide. The second sacrificial pillar structure SV2 may be disposed between the first unit isolation layers 24A in the third direction D3, while the first sacrificial pillar structure SV1 may be disposed between the second unit isolation layers 24B in the third direction D3. The first unit isolation layer 24A and the second unit isolation layer 24B may vertically extend in the first direction D1.

[0163] The first unit isolation layer 24A and the second unit isolation layer 24B may correspond to the unit isolation layers ISOA and ISOB as Figures 2 to 3D shown. Each of the first unit isolation layer 24A and the second unit isolation layer 24B may include a stack of a unit isolation liner layer ISOL and a unit isolation gap fill layer ISOG, as Figure 3C and Figure 3D shown. The unit isolation liner layer ISOL may include silicon oxide, while the unit isolation gap fill layer ISOG may include silicon oxycarbide. According to another embodiment of the present invention, the first unit isolation layer 24A and the second unit isolation layer 24B may include embedded air gaps, and the embedded air gaps may be provided when the unit isolation gap fill layer ISOG is formed.

[0164] The first unit isolation layer 24A and the second unit isolation layer 24B and the first dielectric layer 19A may be in direct contact with each other. The horizontal level spacers 23 may be disposed between the horizontal layer 14B and the first unit isolation layer 24A and the second unit isolation layer 24B.

[0165] Fig.13 is a plan view showing a method of forming the first dielectric layer pattern 19B, FIG. 14A to FIG. 14D is a cross-sectional view taken along the line A-A' shown in Fig.13 showing a method of forming the first dielectric layer pattern 19B.

[0166] Referring to Fig.14A , FIG. 12A to FIG. 12B the hard mask layer pattern 17 and the topmost first dielectric layer 19A may be removed to form the hard mask layer depression 25.

[0167] Reference Fig. 14B , the top dielectric layer 26 can be formed to fill the hard mask layer depression 25. The top dielectric layer 26 can include silicon oxide.

[0168] Reference Fig. 14C , the second sacrificial pillar structure SV2 can be removed to form an initial vertical opening 27. Subsequently, the second dielectric layer 20 can be horizontally recessed. Thus, the first dielectric layer 19A and the dummy dielectric layer 19D can be exposed through the initial vertical opening 27.

[0169] Reference Fig.14D , the dummy dielectric layer 19D and the first dielectric layer 19A can be selectively horizontally recessed. As a result, a first dielectric layer pattern 19B and a dielectric layer depression 28 can be formed. A portion of the horizontal layer 14B can be exposed through the dielectric layer depression 28.

[0170] Fig.15A is a plan view showing a method of forming a vertical sacrificial structure 29, Fig. 15B is along Fig.15A the sectional view taken along the line A-A' shown in

[0171] Reference Fig.15A and Fig. 15B , the vertical sacrificial structure 29 can be formed to fill Figures 13 to 14D the dielectric layer depression 28 and the initial vertical opening 27 of

[0172] Fig.16A is a plan view showing a method of forming a vertical level path 30, Fig. 16B is along Fig.16A the sectional view taken along the line A-A' shown in

[0173] Reference Fig.16A and Fig. 16B , Fig. 15B the sacrificial pillar 21 of the first sacrificial pillar structure SV1 of

[0174] Subsequently, the dummy dielectric layer 19D below the vertical level path 30 can be removed to form a lower layer gap 19D'.

[0175] Fig.17A is a plan view showing a method of forming a first hole-like vertical opening 32, Fig. 17B is along Fig.17A the sectional view taken along the line A-A' shown in

[0176] Reference Fig.17Aand Fig. 17B , Fig.16A and Fig. 16B The second dielectric layer 20 of Fig. 16B can be cut 31 via a vertical-level path 30 to form a first hole-shaped vertical opening 32.

[0177] Subsequently, a first passivation layer BF1 filling the lower-layer gap 19D' can be formed. The first passivation layer BF1 can include silicon oxide. Forming the first passivation layer BF1 can include depositing silicon oxide to fill the lower-layer gap 19D' and etching the silicon oxide.

[0178] A second passivation layer BF2 can be formed in the lower region of the first hole-shaped vertical opening 32. For example, the surface of the support layer 11T can be oxidized to form the second passivation layer BF2.

[0179] Fig.18A is a plan view showing a method of forming a horizontal-level depression 33. Fig.18B is along Fig.18A The cross-sectional view taken along the line A-A' shown in Fig. 18C is along Fig.18A The cross-sectional view taken along the line B-B' shown in

[0180] Referring to 18A to 18C , Fig.17A and 17B The first dielectric layer pattern 19B of 17B can be removed through the first hole-shaped vertical opening 32 to form a horizontal-level depression 33. A portion of the horizontal layer 14B can be exposed through the horizontal-level depression 33. As Fig. 18C shown, the horizontal-level depression 33 can be provided between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal-level depressions 33 can be provided to face each other, with a horizontal layer 14B therebetween.

[0181] Fig.19A is a plan view showing a method of forming a horizontal wire 35. Fig.19B is along Fig.19A The cross-sectional view taken along the line A-A' shown in Fig.19C is along Fig.19A The cross-sectional view taken along the line B-B shown in

[0182] Referring to FIG. 19A to FIG. 19C ,an interlayer dielectric layer 34 can be formed over the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 can be referred to as a gate dielectric layer. The interlayer dielectric layer 34 can correspond to the interlayer dielectric layer GD as Figures 1A to 3B shown.

[0183] The interlayer dielectric layer 34 can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 34 can include SiO2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZrO 2 , AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0184] Subsequently, a horizontal wire 35 filling the horizontal-level recess 33 may be formed over the interlayer dielectric layer 34. Forming the horizontal wire 35 may include depositing a conductive material over the interlayer dielectric layer 34 to fill the horizontal-level recess 33 and performing an etch-back process on the conductive material. The horizontal wire 35 may include a pair of first horizontal wires 35A and second horizontal wires 35B facing each other, with a horizontal layer 14B therebetween. The first horizontal wire 35A and the second horizontal wire 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal wire 35A and the second horizontal wire 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal wire 35A and the second horizontal wire 35B may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal wire 35A and the second horizontal wire 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more.

[0185] The horizontal wire 35 may correspond to the second wire DWL as shown in Figures 1A to 1D , and the first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal line G1 and the lower horizontal line G2 as shown in Figures 1A to 1D . As shown in Figures 1A to 1D , each of the first horizontal wire 35A and the second horizontal wire 35B may have a cross shape and may include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0186] Fig. 20A is a plan view showing a method of forming a vertical wire 39, Fig. 20B is a cross-sectional view taken along the line A-A' shown in Fig. 20A .

[0187] Referring to Fig. 20A and Fig. 20B , a first capping layer 36 may be formed over FIG. 19A to FIG. 19COn a side surface of a horizontal wire 35. The first covering layer 36 may include silicon oxide, silicon nitride, silicon carbonitride, embedded air gaps, or a combination thereof. A deposition process of the covering material and an etch-back process of the covering material may be performed to form the first covering layer 36. When the first covering layer 36 is formed or after the first covering layer 36 is formed, a part of the interlayer dielectric layer 34 may be removed to expose a first edge portion of each horizontal layer 14B.

[0188] Vertical wires 39 may be formed that are coupled to the first edge portions of each horizontal layer 14B. The vertical wires 39 may fill the first hole-shaped vertical openings 32. The vertical wires 39 may be commonly coupled to the horizontal layers 14B disposed in the first direction D1. The vertical wires 39 may include titanium nitride, tungsten, or a combination thereof. The vertical wires 39 may be referred to as bit lines or vertical bit lines.

[0189] Before the vertical wires 39 are formed, a first doped region 37 and a second contact node 38 may be formed. The first doped region 37 may be formed in the first edge portion of each horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with an N-type impurity, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doped region 37 may be formed by a process of doping impurities.

[0190] The second contact node 38 may include doped polysilicon. The first doped region 37 may include impurities diffused from the second contact node 38.

[0191] The vertical wires 39 may correspond to the first wires BL as shown in Figures 1A to 1D .

[0192] The bottom surface of the vertical wires 39 may contact the barrier layer ESL. The barrier layer ESL may prevent bridging of adjacent vertical wires 39.

[0193] Fig.21A is a plan view showing a method of forming a preliminary second hole-shaped vertical opening 29V, Fig. 21B is a cross-sectional view taken along the line A-A' shown in Fig.21A .

[0194] Refer to Fig.21A and Fig. 21B , Fig. 20A and Fig. 20BA portion of the vertical sacrificial structure 29 may be removed to form a preliminary second hole-shaped vertical opening 29V. A side surface (i.e., the second edge portion) of each horizontal layer 14B may be exposed through each preliminary second hole-shaped vertical opening 29V. After the preliminary second hole-shaped vertical opening 29V is formed, a preliminary second covering layer 29A may be formed on the upper and lower surfaces of the horizontal layer 14B.

[0195] When the preliminary second covering layer 29A is formed, the lowermost dielectric layer 29L may be formed on the side surface of the first passivation layer BF1 by removing a portion of the vertical sacrificial structure 29.

[0196] Fig.22A is a plan view showing a method of forming a horizontal layer HL, Fig. 22B is a cross-sectional view taken along Fig.22A the line A-A' shown in

[0197] Referring to Fig.22A and Fig. 22B , a third passivation layer BF3 may be formed on the surface of the support layer 11T. The third passivation layer BF3 may include silicon oxide.

[0198] The second edge portion of the horizontal layer 14B may be horizontally recessed in the second direction D2 (see reference numeral '14C'). Thus, the horizontal layer may be retained as shown by the reference numeral "HL".

[0199] After the horizontal layer HL is formed, the preliminary second hole-shaped vertical opening may be enlarged as shown by the reference numeral "40". Hereinafter, the enlarged preliminary second hole-shaped vertical opening may be simply referred to as the second hole-shaped vertical opening 40.

[0200] Fig.23A is a plan view showing a method of forming a storage opening 41, Fig. 23B is a cross-sectional view taken along Fig.23A the line A-A' shown in

[0201] Referring to Fig.23A and Fig. 23B , the preliminary second covering layer 29A of Fig.22A and Fig. 22B may be selectively recessed to form a second covering layer 29C. The second covering layer 29C may include silicon oxide, silicon nitride, or a combination thereof.

[0202] After the second covering layer 29C is formed, a storage opening 41 that horizontally extends from the second hole-shaped vertical opening 40 may be formed. The storage opening 41 may be referred to as a capacitor opening.

[0203] The horizontal layer HL may include a first edge and a second edge. The first edge may refer to the portion coupled to the first contact node 38 and the vertical wire 39. The second edge may refer to the portion exposed through the storage opening 41.

[0204] The storage opening 41 may be disposed between the second dielectric layers 20. The second capping layer 29C may be disposed above and below the horizontal layer HL.

[0205] As described above, forming the horizontal layer HL and the storage opening 41 may include forming the second hole-shaped vertical opening 40, recessing the horizontal layer 14B, and forming the second capping layer 29C.

[0206] Fig.24A is a plan view showing a method of forming the second contact node 42, Fig. 24B is along Fig.24A the cross-sectional view taken along the line A-A' shown in

[0207] Referring to Fig.24A and Fig. 24B , the second doped region 43 may be respectively formed in the second edge of the horizontal layer HL. Forming the second doped region 43 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped region 43 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the doped polysilicon may be retained after the heat treatment is performed.

[0208] Subsequently, the second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doped region 43 may include impurities diffused from the second contact node 42.

[0209] Each horizontal layer HL may include a first doped region 37, a second doped region 43, and a channel 44 horizontally disposed in the second direction D2. Each channel 44 may be defined between each first doped region 37 and each second doped region 43. The channel 44 may vertically overlap with the horizontal wire 35. As Figures 1A to 1D shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0210] Fig.25A is a plan view showing a method of forming the first electrode 45, Fig.25B is along Fig.25A the cross-sectional view taken along the line A-A' shown in

[0211] Referring to Fig.25A and Fig.25B, the first electrode 45 of the data storage element can be formed over the second contact node 42. The first electrode 45 can have a horizontally oriented cylindrical shape. The first electrode 45 can be disposed in the storage opening 41, respectively. The first electrodes 45 adjacent to each other in the second direction D2 can be spaced apart from each other through the second hole-shaped vertical opening 40. The first electrodes 45 adjacent to each other in the third direction D3 can be spaced apart from each other through the first cell isolation layer 24A.

[0212] Fig.26A is a plan view showing a method of exposing the outer wall of the first electrode 45, Fig.26B is along Fig.26A the cross-sectional view taken along the line A-A' shown in

[0213] Referring to Fig.26A and Fig.26B , the second dielectric layer 20 can be horizontally recessed (see reference numeral '46'). As a result, the outer wall of the first electrode 45 can be exposed. The recessed second dielectric layer 20 can correspond to the inter-cell dielectric layer IL as shown in Figure 3B .

[0214] Fig.27A is a plan view showing a method of forming the dielectric layer 47 and the second electrode 48, Fig.27B is along Fig.27A the cross-sectional view taken along the line A-A' shown in

[0215] Referring to Fig.27A and Fig.27B , the dielectric layer 47 and the second electrode 48 can be sequentially formed over the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 can form the data storage element CAP.

[0216] Each first electrode 45 can include an internal space and a plurality of outer surfaces. The internal space of the first electrode 45 can include a plurality of inner surfaces. The outer surfaces of the first electrode 45 can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode 45 can extend vertically along the first direction D1. The horizontal outer surfaces of the first electrode 45 can extend horizontally along the second direction D2 or the third direction D3. The internal space of the first electrode 45 can be a three-dimensional space. The dielectric layer 47 can conformally cover the inner surfaces and the outer surfaces of the first electrode 45. The second electrode 48 can be disposed in the internal space of the first electrode 45 over the dielectric layer 47. Some of the outer surfaces of the first electrode 45 can be electrically connected to the second doped region 43 of the horizontal layer HL.

[0217] The first electrode 45 may have a cylindrical shape. The cylindrical shape of the first electrode 45 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surface of the first electrode 45 may be electrically connected to the second doped region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 may be disposed on the cylindrical inner surface of the first electrode 45. The second electrode 48 may extend vertically along the first direction D1.

[0218] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 48 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the internal space of the first electrode 45, titanium nitride (TiN) may serve as the second electrode 48 of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0219] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 may include silicon oxide, silicon nitride, a perovskite material, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 47 may include a high-k material, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO 3 ). The dielectric layer 47 may include a ZA (ZrO 2 / Al 2 O 3 ) stack, a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2) Stack, ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) Stack, ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) Stack, HA (HfO 2 / Al 2 O 3 ) Stack, HAH (HfO 2 / Al 2 O 3 / HfO 2 ) Stack, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) Stack, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) Stack, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) Stack, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) Stack, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) Stack, or AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / Al 2 O 3 ) stack.

[0220] According to another embodiment of the present invention, an interface control layer may also be formed between the first electrode 45 and the dielectric layer 47 to reduce leakage current. The interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 48 and the dielectric layer 47.

[0221] According to the above embodiment of the present invention, since the cross-shaped horizontal layer HL is formed, the channel width and the bridging between the memory cells can be improved.

[0222] In addition, since the trimmed target layer 19A is formed by trimming the trimmed target layer 19 and replacing the trimmed target layer 19A with the horizontal wire 35, the bridging between the vertically stacked horizontal wires 35 can be improved.

[0223] FIG. 28A to FIG. 28C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0224] Referring to Fig.28A , the stack SB10 may be formed on the substrate 11. The stack SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack may include a plurality of silicon-germanium layers 12 and a plurality of single-crystalline silicon layers 14' alternately stacked by an epitaxial growth process. The silicon-germanium layer 12 may be a sacrificial layer, and the single-crystalline silicon layer 14' may be a recessed target layer. The silicon-germanium layer 12 may correspond to Figure 4B the first layer 12A or the third layer 12B of Figure 4B , and the single-crystalline silicon layer 14' may correspond to Figure 4B the fourth layer 14 of

[0225] Subsequently, a series of processes as shown in 4A to 6B may be performed. For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B may be formed in the stack SB10.

[0226] Subsequently, referring to Fig.28B , the hard mask layer pattern 17 may be formed on the stack SB10.

[0227] Subsequently, the stack SB10 can be etched by using the hard mask layer pattern 17 as an etch stop. As a result, a plurality of first sacrificial vertical openings V1' and second sacrificial vertical openings V2' can be formed in the stack SB10.

[0228] Reference Fig.28C , a preliminary horizontal layer 14A' and a horizontal recess 18 can be formed. The preliminary horizontal layer 14A' and the horizontal recess 18 can be formed by the recess process of the silicon-germanium layer 12 and the single-crystalline silicon layer 14' shown in Fig.28B . After removing the silicon-germanium layer 12, a process of recessing the single-crystalline silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 8B 's preliminary horizontal layer 14A.

[0229] The silicon-germanium layer 12 can be recessed by a wet etching process or a dry etching process. The silicon-germanium layer 12 can be etched by using an etchant or an etching gas that is selective with respect to the single-crystalline silicon layer 14'.

[0230] The process of recessing the single-crystalline silicon layer 14' for forming the preliminary horizontal layer 14A' can be performed by using, for example, HotSC-1 (HSC1). HSC1 can include a solution in which ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) are mixed in a ratio of approximately 1:4:20. The single-crystalline silicon layer 14' can be selectively etched by using HSC1.

[0231] After the preliminary horizontal layer 14A' is formed, the first sacrificial vertical opening and the second sacrificial vertical opening can be enlarged as indicated by the reference numerals 'V1' and 'V2'. The preliminary horizontal layer 14A' can be arranged to be spaced apart from each other in the second direction D2 through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A' can have a shape in which a plurality of crosses are merged in the third direction D3. When the preliminary horizontal layer 14A' is formed, the surface of the support layer 11T can be recessed to a predetermined depth (see the reference numeral '11A'). As a result, the depths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can be increased.

[0232] Subsequently, a series of processes shown in FIG. 8A to FIG. 27B can be performed.

[0233] Figure 29 to Figure 31 is a perspective view showing a memory cell array according to other embodiments of the present invention. The memory cell arrays MCA100, MCA200, and MCA300 can be similar to Figure 3AThe memory cell array MCA1. Hereinafter, for a detailed description of the constituent elements that also appear in Figure 3A reference may be made to the above-described embodiments of the present invention.

[0234] Referring to Fig.29 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0235] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1. The row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0236] Each memory cell MC10 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above-described embodiments of the present invention.

[0237] The switching element TR may include a horizontal layer HL and a second wire DWL. The horizontal layer HL may extend along the second direction D2. The second wire DWL may extend along the third direction D3.

[0238] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL therebetween. As Figure 3B shown, an interlayer dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL.

[0239] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending along the third direction D3. The flat sidewalls FS may refer to vertical sidewalls. The flat sidewalls FS may have a linear shape extending along the third direction D3.

[0240] Referring to Fig.30 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0241] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked along the first direction D1. The row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged along the second direction D2 and the third direction D3.

[0242] Each memory cell MC20 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present invention.

[0243] The switching element TR may include a horizontal layer HL and a second wire SWL. The horizontal layer HL may extend along the second direction D2. The second wire SWL may extend along the third direction D3.

[0244] The second wire SWL may be a single structure. For example, the second wire SWL may be disposed above the horizontal layer HL. As Figure 3B shown, an interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second wire SWL. According to another embodiment of the present invention, the second wire SWL may be disposed below the horizontal layer HL.

[0245] The second wire SWL may include a pair of flat sidewalls FS extending along the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0246] According to another embodiment of the present invention, the second wire SWL may include a channel overlap portion WLP and a channel non-overlap portion NOL, as Figure 1C shown.

[0247] Reference Fig.31 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0248] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may have a plurality of memory cells MC30 stacked in the first direction D1. The row array of memory cells MC30 may have a plurality of memory cells MC30 horizontally disposed in the second direction D2 and the third direction D3.

[0249] Each memory cell MC30 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present invention.

[0250] The switching element TR may include a horizontal layer HL and a second wire GAA-WL. The horizontal layer HL may extend along the second direction D2. The second wire GAA-WL may extend along the third direction D3.

[0251] The second conductor GAA-WL can be a gate-all-around (GAA) structure. For example, the second conductor GAA-WL can extend along a third direction D3 while surrounding a horizontal layer HL. An interlayer dielectric layer GD can be formed between the horizontal layer HL and the second conductor GAA-WL. The interlayer dielectric layer GD can surround each horizontal layer HL.

[0252] The second conductor GAA-WL can include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS can refer to vertical sidewalls.

[0253] Similar to the above embodiments of the present invention, a barrier layer ESL and a substrate WF can be provided below the memory cell arrays MCA100, MCA200, and MCA300.

[0254] Fig.32 A memory cell array MCA400 according to another embodiment of the present invention is shown.

[0255] Fig.32 The memory cell array MCA400 can be similar to Figure 3B and Fig.27B the memory cell arrays.

[0256] Referring to Fig.32 , a barrier layer ESL thicker than the substrate 11 can be formed on the substrate 11. The barrier layer ESL can include silicon oxide. The barrier layer ESL can be formed by depositing silicon oxide on the substrate 11. In addition, the barrier layer ESL can be formed by bonding the substrate 11 to a substrate on which a memory cell array is formed.

[0257] Fig.33 A memory cell array MCA500 according to yet another embodiment of the present invention is shown.

[0258] Fig.33 The memory cell array MCA500 can be similar to Figure 3B and Figure 27B the memory cell arrays. The memory cell array MCA500 can be similar to Figure 31 the memory cell array MCA300. In the following, for a detailed description of the constituent elements that also appear in Figure 31 , reference can be made to the above embodiments of the present invention.

[0259] Referring to Figure 33, the memory cell array MCA500 may include a barrier layer ESL located above the substrate 11, and a three-dimensional array of memory cells MC disposed above the barrier layer ESL. Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP. A barrier layer ESL thicker than the substrate 11 may be formed above the substrate 11. The barrier layer ESL may include silicon oxide. The barrier layer ESL may be formed by depositing silicon oxide above the substrate 11. In addition, the barrier layer ESL may be formed by bonding the substrate 11 to a substrate on which a memory cell array is formed.

[0260] The first wire BL may be vertically oriented in a first direction D1. The first wire BL may include a bit line.

[0261] The switching element TR may have a function of controlling the supply of voltage (or current) to the data storage element CAP during a data write operation and a data read operation for the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire GAA-WL. The second wire GAA-WL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second wire GAA-WL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire GAA-WL may be referred to as a horizontal gate electrode or a horizontal word line. As described, the second wire GAA-WL of the memory cell array MCA500 may have a gate-all-around structure GAA.

[0262] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire GAA-WL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend along the first horizontal direction (i.e., the second direction D2). The second wire GAA-WL may extend along the second horizontal direction (i.e., the third direction D3).

[0263] The horizontal layer HL may be horizontally oriented from the first wire BL in the second direction D2. The second wire GAA-WL may be a gate-all-around structure. For example, the second wire GAA-WL may extend along the third direction D3 while surrounding the horizontal layer HL.

[0264] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0265] The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is an oxide semiconductor material, the channel CH may be formed of the oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0266] Each of the first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. Each of the first doped region SR and the second doped region DR may be doped with N-type conductive impurities or P-type conductive impurities. Each of the first doped region SR and the second doped region DR may include at least one impurity selected from the group consisting of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first wire BL, while the second doped region DR may be coupled to the data storage element CAP. The first doped region SR and the second doped region DR may be referred to as a first source / drain region and a second source / drain region.

[0267] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire GAA-WL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO 2 、Si 3 N 4 、HfO 2 、Al 2 O 3 、ZrO 2 、AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by a thermal oxidation process of a semiconductor material.

[0268] The second conductor GAA-WL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductor GAA-WL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductor GAA-WL may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The second conductor GAA-WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second conductor GAA-WL may include a stack of a low work function material and a high work function material.

[0269] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed with respect to the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN horizontally extending from a horizontal layer HL in the second direction D2. The data storage element CAP may further include a second electrode PN over the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed in the second direction D2. The second electrode PN may be disposed in an inner space of the first electrode SN over the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically connected to a second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to a common plate PL.

[0270] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, which may be a horizontal three-dimensional structure oriented in the second direction D2. In an example of the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0271] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductor BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0272] A second inter-cell dielectric layer CIL may be formed between data storage elements CAP. A first inter-cell dielectric layer IL may be formed between second wires GAA-WL. The thickness of the lowest layer of the first inter-cell dielectric layer IL in the first inter-cell dielectric layer IL may be the largest.

[0273] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second wire GAA-WL and the second doped region DR. The second spacer SP2 may be disposed between the first wire BL and the second wire GAA-WL. Both the first spacer SP1 and the second spacer SP2 may include a dielectric material. Both the first spacer SP1 and the second spacer SP2 may include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may include silicon nitride. The first spacer SP1 and the second spacer SP2 may be respectively disposed on both sides of the second wire GAA-WL and extend along a third direction D3 while surrounding a horizontal layer HL. The first spacer SP1 may be formed on one side surface of the second wire GAA-WL. The first spacer SP1 may cover one side surface of the first inter-cell dielectric layer IL.

[0274] According to an embodiment of the present invention, when a 3D memory cell is formed, a barrier layer may prevent bridging between adjacent vertical wires.

[0275] In addition, according to an embodiment of the present invention, a barrier layer may prevent bridging between a vertical wire and a data storage element.

[0276] According to an embodiment of the present invention, the yield of 3D memory cells may be increased.

[0277] Although the present invention has been described with respect to specific embodiments of the present invention, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stacked body on a lower structure in which a substrate, a barrier layer, and a support layer are sequentially stacked; forming a plurality of sacrificial vertical openings by etching the stack and the support layer using the barrier layer as an etch stop layer; as well as A three-dimensional memory cell is formed in the stack, the three-dimensional memory cell comprising a vertical conductive line, a horizontal conductive line and a data storage element.

2. The method according to claim 1, wherein: Forming the stacked body on the lower structure includes: forming a sacrificial barrier layer over the substrate; forming the support layer on the sacrificial barrier layer; forming an etching target layer on the support layer; forming a plurality of sacrificial isolation openings and the stack by etching the etch target layer and the support layer; forming a sacrificial spacer on a sidewall of the sacrificial isolation opening; forming an underlying gap by removing the sacrificial barrier layer; and The underlying gap is filled with the barrier layer.

3. The method according to claim 2, wherein: The sacrificial barrier layer includes a semiconductor material, and the barrier layer includes silicon oxide.

4. The method according to claim 2, wherein: Each of the substrate and the support layer includes single crystal silicon, and the sacrificial barrier layer includes silicon germanium.

5. The method according to claim 2, wherein: The etching target layer is formed on the supporting layer by an epitaxial growth process.

6. The method according to claim 2, wherein: The etch target layer includes a plurality of first semiconductor layers and a plurality of second semiconductor layers.

7. The method according to claim 2, wherein: The etching target layer includes a plurality of single crystal silicon layers and a plurality of silicon germanium layers which are alternately stacked.

8. The method according to claim 1, wherein: The vertical conductive line extends vertically and contacts the barrier layer.

9. A method for manufacturing a semiconductor device, the method comprising: forming a lower structure, the lower structure comprising a substrate, a sacrificial barrier layer, and a support layer stacked in sequence; forming an etch target layer above the lower structure, in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a plurality of sacrificial isolation openings and a stack by etching the etch target layer and the support layer using the sacrificial barrier layer as an etch stop layer; forming a sacrificial spacer on a sidewall of the sacrificial isolation opening; forming an underlying gap by removing the sacrificial barrier layer; as well as The underlying gap is filled with a barrier layer.

10. The method according to claim 9, wherein: The sacrificial barrier layer includes a semiconductor material, and the barrier layer includes silicon oxide.

11. The method according to claim 9, wherein: Each of the substrate and the support layer includes single crystal silicon, and the sacrificial barrier layer includes silicon germanium.

12. The method according to claim 9, wherein: The first semiconductor layer and the second semiconductor layer are formed on the supporting layer by an epitaxial growth process.

13. The method according to claim 9, wherein: The first semiconductor layer includes silicon germanium, and the second semiconductor layer includes single crystal silicon.

14. The method according to claim 9, further comprising: After filling the underlying gap with the barrier layer: forming a sacrificial vertical opening by etching the stack; removing the first semiconductor layer from the sacrificial vertical opening; forming a semiconductor layer pattern by recessing the second semiconductor layer; forming a horizontal conductive line extending in a direction intersecting an upper surface and a lower surface of the semiconductor layer pattern; as well as A vertical conductive line extending vertically from the barrier layer is formed in the sacrificial vertical opening.

15. The method according to claim 14, further comprising: After forming the vertical conductive line: Forming a hole-shaped opening by etching the stack and the support layer; forming a storage opening outside the hole-shaped opening; as well as A data storage element is formed in the storage opening.

16. A semiconductor device comprising: a lower structure comprising a substrate, a barrier layer and a support layer stacked in sequence; a memory cell array comprising a plurality of vertical conductive lines extending vertically from the barrier layer; as well as A cell isolation layer is disposed between the vertical conductive lines.

17. The semiconductor device according to claim 16, wherein: The barrier layer includes silicon oxide.

18. The semiconductor device according to claim 16, wherein: Each of the substrate and the support layer includes single crystal silicon.

19. The semiconductor device according to claim 16, wherein: The memory cell array further comprises: A plurality of horizontal layers, each of which horizontally extends from the vertical conductive line; a horizontal conductive line crossing the horizontal layer; and A plurality of data storage elements are respectively coupled to the horizontal layers.

20. The semiconductor device according to claim 16, wherein The support layer has a height lower than that of the vertical conductive line.

21. The semiconductor device according to claim 16, wherein: The thickness of the barrier layer is greater than the thickness of the substrate.

22. The semiconductor device according to claim 16, wherein The memory cell array further comprises: a plurality of horizontal layers, each of which extends horizontally from the vertical conductive line; a horizontal conductive line extending horizontally and surrounding the horizontal layer; and A plurality of data storage elements are respectively coupled to the horizontal layers.

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