Semiconductor device including memory cell having selector and buffer layer

Abstract

The invention relates to a semiconductor device including a memory cell having a selector and a buffer layer. A semiconductor device and a method of forming the same are disclosed. The semiconductor memory device has a memory cell including: a lower electrode; a selection element over the lower electrode; a buffer layer over the selection element; an intermediate electrode on the buffer layer; a memory layer over the intermediate electrode; and an upper electrode on the storage layer. The buffer layer includes titanium, nitrogen, and oxygen. The titanium content ratio in the buffer layer is 1.21 times higher than the nitrogen content ratio.

Description

[0001] Priority Claims and Cross - References to Related Applications

[0002] This patent document claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0180346, filed on December 13, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure provide semiconductor memory devices, each semiconductor memory device including a memory cell having a selection element and a buffer layer. Background Art

[0004] Recently, in accordance with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a need for semiconductor devices configured to store data in various electronic devices such as computers and portable communication devices. Accordingly, a semiconductor memory device that stores data using the switching characteristics according to voltage or current has been proposed. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a semiconductor memory device includes one or more memory cells, wherein each memory cell includes: a lower electrode; a selection element disposed on the lower electrode; a buffer layer disposed on the selection element; an intermediate electrode disposed on the buffer layer, the selection element, and the lower electrode; a storage layer disposed on the intermediate electrode and configured to store data; and an upper electrode disposed on the storage layer. The buffer layer includes titanium, nitrogen, and oxygen. In the buffer layer, the titanium content ratio is higher than 1.21 times the nitrogen content ratio.

[0006] According to an embodiment of the present disclosure, a semiconductor memory device having a memory cell includes: a lower interconnect extending in a first horizontal direction; a selection element disposed on the lower interconnect and configured to exhibit different conductive characteristics in response to an applied voltage relative to a threshold voltage; a buffer layer disposed in contact with the selection element; an intermediate electrode disposed to place the buffer layer and the selection element between the intermediate electrode and the lower interconnect; a storage layer disposed on the intermediate electrode; and an upper interconnect disposed on the storage layer. The upper interconnect extends in a second horizontal direction perpendicular to the first horizontal direction. The selection element includes a silicon oxide layer having: 1) at least one of boron or carbon, and 2) at least one of arsenic or germanium.

[0007] According to an embodiment of the present disclosure, a semiconductor memory device having a memory cell, the memory cell includes: a lower interconnect line extending in a first horizontal direction; a lower electrode disposed on the lower interconnect line; a select element disposed on the lower electrode and configured to exhibit different conductive characteristics in response to an applied voltage relative to a threshold voltage; a buffer layer disposed on the select element; an intermediate electrode disposed on the buffer layer; a storage layer disposed on the intermediate electrode; an upper electrode disposed on the storage layer; and an upper interconnect line disposed on the upper electrode and extending in a second horizontal direction perpendicular to the first horizontal direction. The select element includes a silicon oxide layer, the silicon oxide layer includes: 1) at least one of boron or carbon, and 2) at least one of arsenic or germanium. The buffer layer includes a silicon oxide layer, the silicon oxide layer includes titanium, nitrogen, and oxygen.

[0008] According to an embodiment of the present disclosure, a method of forming a semiconductor memory device includes: forming a lower electrode material layer; forming a preliminary select element material layer on the lower electrode material; forming a preliminary buffer material layer on the preliminary select element material layer; using the preliminary buffer material layer as an ion implantation buffer layer, implanting at least one of boron or carbon into the preliminary select element material layer to form a select element material layer and a buffer material layer from the preliminary select element material layer and the preliminary buffer material layer, respectively; forming an intermediate electrode material layer on the buffer material layer; forming a storage material layer on the intermediate electrode material layer; and forming an upper electrode on the storage material layer. The buffer material layer includes titanium, nitrogen, and oxygen, and in the buffer material layer, the oxygen content ratio is higher than the nitrogen content ratio.

[0009] According to an embodiment of the present disclosure, a method of forming a semiconductor memory device includes: forming a lower electrode material layer; forming a preliminary select element material layer on the lower electrode material; forming a preliminary buffer material layer on the preliminary select element material layer; using the preliminary buffer material layer as an ion implantation buffer layer, implanting at least one of boron and carbon into the preliminary select element material layer to form a select element material layer and a buffer material layer from the preliminary select element material layer; forming an intermediate electrode material layer on the buffer material layer; forming a storage material layer on the intermediate electrode material layer; and forming an upper electrode on the storage material layer. The preliminary select element material layer includes arsenic silicon oxide. The select element material layer includes arsenic silicon oxide doped with at least one of boron or carbon.

[0010] According to an embodiment of the present disclosure, a method of forming a semiconductor memory device includes: forming a lower electrode; forming a select element on the lower electrode; forming a buffer layer on the select element; forming an intermediate electrode on the buffer layer; forming a storage layer on the intermediate electrode; and forming an upper electrode on the storage layer. The select element includes a layer of arsenic silicon oxide doped with at least one of boron or carbon. The buffer layer includes titanium, nitrogen, and oxygen.

[0011] The above and other aspects of the disclosed technology are disclosed in the accompanying drawings, the detailed description, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a perspective view schematically showing a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 2A is along Figure 1 The longitudinal sectional view taken along line I-I' is used to illustrate the memory cell. Figure 2B is showing Figure 2A An enlarged view of a part of

[0014] Figures 3A to 3D is a diagram showing a method of forming a memory cell of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram showing a change in a titanium-nitrogen bonding structure in a buffer layer in a memory cell of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram showing the ratio of titanium content, the ratio of nitrogen content, and the ratio of oxygen content in a buffer layer in a memory cell of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 6 is an energy band diagram showing that a buffer layer improves an energy band gap in a memory cell of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some of the structures in the accompanying drawings may be enlarged to clearly show certain features of the described embodiments. When presenting specific examples of two or more layers in a multi-layer structure in the accompanying drawings or the description, the relative positional relationship of these layers shown in the figure or the order of arranging the layers reflects the specific implementation of the described or shown example, and there may be different relative positional relationships or orders of arranging the layers. In addition, the described or shown example of the multi-layer structure may not reflect all the layers present in that specific multi-layer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the described or shown multi-layer structure is referred to as "on the second layer" or "above the second layer" or "on the substrate" or "above the substrate", the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0020] Embodiments of the present disclosure provide a semiconductor memory device and a method of forming the same, the semiconductor memory device having a memory cell including a select element doped with at least one of boron (B) or carbon (C).

[0021] An embodiment of the present disclosure provides a semiconductor memory device and a method of forming the same, the semiconductor memory device having a memory cell including a titanium-rich and oxygen-rich buffer layer.

[0022] Figure 1 is a perspective view schematically showing a cross-point cell array 100 of a semiconductor memory device according to an embodiment of the present disclosure. Referring to Figure 1 , the cross-point cell array 100 of the memory device according to an embodiment of the present disclosure may include lower interconnects 10, upper interconnects 80, and memory cells MC located between the lower interconnects 10 and the upper interconnects 80. The lower interconnects 10 may extend parallel to each other in a first horizontal direction X. The upper interconnects 80 may extend parallel to each other in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. For example, in a top view, the lower interconnects 10 and the upper interconnects 80 may intersect each other. The memory cells MC may be disposed at the intersections between the lower interconnects 10 and the upper interconnects 80. Each memory cell MC may have a cylindrical shape extending in a vertical direction Z. The vertical direction Z may be perpendicular to the first horizontal direction X and the second horizontal direction Y respectively. The shape of the memory cell MC is not limited thereto, and other implementations are also possible.

[0023] Figure 2A is a longitudinal cross-sectional view taken along the line I-I' of Figure 1 to show the memory cell MC, Figure 2B is an enlarged view showing a part of Figure 2A Referring toFigure 1 and Figure 2A , according to an embodiment of the present disclosure, the memory cell MC may include a lower electrode 20, a selection element 30 located on the lower electrode 20, a buffer layer 40 located on the selection element 30, an intermediate electrode 50 located on the buffer layer 40, a storage layer 60 located on the intermediate electrode 50, and an upper electrode 70 located on the storage layer 60.

[0024] The lower interconnect 10 may extend in a first horizontal direction X. The lower interconnect 10 may be a word line or a source line. The lower interconnect 10 may include at least one of a metal layer, a metal nitride layer, a metal silicide layer, or a metal alloy layer. For example, the lower interconnect 10 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0025] The lower electrode 20 may be disposed on the lower interconnect 10 to have a columnar or pad shape. The lower electrode 20 may receive a voltage or current from the lower interconnect 10 and supply the voltage or current to the selection element 30. For example, the lower electrode 20 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0026] The select element 30 may be disposed on the lower electrode 20 to have a columnar or pad shape. The select element 30 may exhibit two different conductive states: a first non-conductive state, in which current is blocked or hardly flows in the select element 30 when the amplitude of the voltage applied to the select element 30 is less than a predetermined threshold voltage; and a second conductive state, in which current rapidly flows through the select element 30 at a voltage equal to or higher than the threshold voltage. The select element 30 may have a second conductive state, the conductivity of which is generated by an electric field generated between the lower electrode 20 and the intermediate electrode 50. For example, a channel may be formed in the select element 30 by the electric field. Thus, when the electric field is less than the threshold voltage or threshold current, the select element 30 may have non-conductive characteristics corresponding to the first non-conductive state. When the electric field is greater than or equal to the threshold voltage or threshold current, the select element 30 may have conductor characteristics corresponding to the second conductive state. Therefore, the voltage applied to the select element 30 can be used to selectively switch the select element 30 between the first non-conductive state and the second conductive state to selectively control the electrical connection to the storage layer 70 within each memory cell MC. A buffer layer 40 in contact with the select element 30 is provided to improve the operation of the select element 30 in the above two states by adjusting the electrical characteristics of the select element 30 via the material composition of the buffer layer 40. In one embodiment, the select element 30 may include an ion-doped insulating layer. For example, the select element 30 may include ion-doped silicon oxide, ion-doped titanium oxide, ion-doped aluminum oxide, ion-doped tungsten oxide, ion-doped hafnium oxide, ion-doped tantalum oxide, ion-doped niobium oxide, ion-doped silicon nitride, ion-doped titanium nitride, ion-doped aluminum nitride, ion-doped tungsten nitride, ion-doped hafnium nitride, ion-doped tantalum nitride, ion-doped niobium nitride, ion-doped silicon oxynitride, ion-doped titanium oxynitride, ion-doped aluminum oxynitride, ion-doped tungsten oxynitride, ion-doped hafnium oxynitride, ion-doped tantalum oxynitride, ion-doped niobium oxynitride, or at least one of combinations thereof. In one embodiment, the ions may include at least two of boron (B), carbon (C), arsenic (As), or germanium (Ge). For example, the select element 30 may include a silicon oxide material doped with 1) at least one of boron (B) or carbon (C) and 2) at least one of arsenic (As) or germanium (Ge). For example, the select element 30 doped with 1) at least one of boron (B) or carbon (C) and 2) at least one of arsenic (As) or germanium (Ge) may include, for example, BAs-SiO 2 , CAs-SiO 2 , BCAs-SiO 2 , BGe-SiO 2 , CGe-SiO 2 , BCGe-SiO 2 , BAsGe-SiO 2, CAsGe - SiO 2 or BCAsGe - SiO 2 .

[0027] The electrical characteristics of the selection element 30 can be adjusted based on the content (concentration) of boron (B) and / or carbon (C). For example, the bulk resistance and channel resistance of the selection element 30 can be adjusted. When boron (B) is implanted into the selection element 30, the bulk resistance and channel resistance can increase. When carbon (C) is implanted into the selection element 30, the bulk resistance and channel resistance can decrease. Therefore, in order to obtain appropriate characteristics, the boron (B) content (concentration) and / or carbon (C) content (density) in the selection element 30 can be adjusted. In this example, the boron (B) content and carbon (C) content can be adjusted separately.

[0028] The buffer layer 40 can be disposed on the selection element 30 to have a thin pad shape or a thin film shape. For example, the buffer layer 40 can be formed to have a thickness of several tens . The buffer layer 40 can change the energy bandgap of the selection element 30 to improve the operation. For example, the buffer layer 40 can increase the hole concentration by providing oxygen vacancies to the selection element 30, thereby increasing the work function. The buffer layer 40 can include titanium oxynitride (TiON). For example, the buffer layer 40 can include titanium-rich and oxygen-rich titanium oxynitride. The ratio of the titanium content in the buffer layer 40 can be 1.21 times or more of the nitrogen content ratio. For example, the number of titanium atoms in the buffer layer 40 can be greater than the number of nitrogen atoms. The ratio of the oxygen content in the buffer layer 40 can be higher than the nitrogen content ratio. For example, the number of oxygen atoms in the buffer layer 40 can be greater than the number of nitrogen atoms. The ratio of the titanium content in the buffer layer 40 can be higher than the oxygen content ratio. For example, the number of titanium atoms in the buffer layer 40 can be greater than the number of oxygen atoms. In one embodiment, the buffer layer 40 can include a titanium content ratio of about 50 at% (atom%, atomic percentage), an oxygen content ratio of about 30 at%, and a nitrogen content ratio of about 20 at%. Although it has been described above that the buffer layer 40 is disposed above the selection element 30, in some other implementations, the buffer layer 40 can be disposed below the selection element 30. In this example, the buffer layer 40 can be disposed below the selection element 30 and in contact with the selection element 30.

[0029] The intermediate electrode 50 can be disposed on the buffer layer 40 to have a columnar or pad shape. The intermediate electrode 50 can include a carbon layer. In one embodiment, the intermediate electrode 50 can include at least one conductor, such as a carbon-containing metal, a carbon-containing metal compound, a carbon-containing metal alloy, or a carbon-containing metal silicide. In another embodiment, the intermediate electrode 50 can include a carbon structure layer (such as a graphene layer).

[0030] The storage layer 60 may be disposed on the intermediate electrode 50 to have a columnar or pad shape. The storage layer 60 may include a variable resistance layer that stores different data by switching between different resistance states. For example, the storage layer 60 may include a variable magnetoresistance layer or a phase changeable resistance layer. In one embodiment, the storage layer 60 may include a magnetic tunnel junction (MTJ). The detailed structure of the MTJ will be described later with reference to Figure 2B discuss the detailed structure.

[0031] The upper electrode 70 may be disposed on the storage layer 60 and have a columnar or pad shape. The upper electrode 70 may supply the current passing through the storage layer 60 to the upper interconnection line 80. For example, the upper electrode 70 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0032] The upper interconnection line 80 may extend in the second horizontal direction Y. The upper interconnection line 80 may be a bit line or a word line. The upper interconnection line 80 may include a metal layer, a metal nitride layer, a metal silicide layer, or a metal alloy layer. In one embodiment, the upper interconnection line 80 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0033] Refer to Figure 2B, the storage layer 60 may include a magnetic tunnel junction (MTJ). For example, the storage layer 60 may include a lower magnetic layer 61, a tunneling barrier layer 62, and an upper magnetic layer 63. In one embodiment, the lower magnetic layer 61 may be a fixed (pinned) magnetization layer, and the upper magnetic layer 63 may be a free (variable) magnetization layer. In another embodiment, the lower magnetic layer 61 may be a free magnetization layer, and the upper magnetic layer 63 may be a fixed magnetization layer. The lower magnetic layer 61 and the upper magnetic layer 63 may include an alloy or a compound that includes at least two of iron (Fe), nickel (Ni), cobalt (Co), boron (B), platinum (Pt), or palladium (Pd). For example, the lower magnetic layer 61 and the upper magnetic layer 63 may each include at least one of an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, a Co-Fe-B alloy, a Co / Pt stack, or a Co / Pd stack. The tunneling barrier layer 62 may be disposed between the lower magnetic layer 61 and the upper magnetic layer 63. Electrons may tunnel through the tunneling barrier layer 62 through an electric field between the lower electrode 20 and the upper electrode 70. The tunneling barrier layer 62 may include an insulating metal oxide layer. For example, the tunneling barrier layer 62 may include at least one of magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), titanium oxide (TiO), vanadium oxide (VO), niobium oxide (NbO), aluminum oxide (AlO), tantalum oxide (TaO), ruthenium oxide (RuO), beryllium oxide (BeO), barium oxide (BaO), or bismuth oxide (BiO).

[0034] Figures 3A to 3D is a diagram showing a method of forming a storage cell MC of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure. For example, Figures 3A to 3D is along Figure 1 The longitudinal sectional view taken along the line I-I' of.

[0035] Figure 4 is a diagram showing a change in a titanium-nitrogen bonding structure in a buffer layer 40 in a storage cell MC of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure. Figure 5 is a diagram showing the ratio of titanium content, the ratio of nitrogen content, and the ratio of oxygen content in a buffer layer 40 in a storage cell MC of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure. Figure 6 is an energy band diagram showing that the buffer layer 40 according to an embodiment of the present disclosure improves the energy band gap in a storage cell MC of a cross-point cell array of a semiconductor memory device.

[0036] Refer to Figure 3A, A method of forming a memory cell MC of a cross-point cell array of a semiconductor memory device according to an embodiment of the present disclosure may include: forming a lower interconnect 10; forming a lower electrode material layer 25 on the lower interconnect 10; forming a preliminary select element material layer 35p on the lower electrode material layer 25; and forming a preliminary buffer material layer 45p on the preliminary select element material layer 35p. The lower interconnect 10 may extend in a first horizontal direction X. Each of the lower electrode material layer 25, the preliminary select element material layer 35p, and the preliminary buffer material layer 45p may be formed along the first horizontal direction X. Forming the lower interconnect 10, the lower electrode material layer 25, the preliminary select element material layer 35p, and the preliminary buffer material layer 45 may include performing a deposition process, a lithography process, and an etching process. In one embodiment, the lower interconnect 10 and the lower electrode material layer 25 may each include at least one of a metal layer, a metal nitride layer, a metal silicide layer, or a metal alloy layer. The preliminary select element material layer 35p may include a doped oxide. For example, the preliminary select element material layer 35p may include silicon oxide doped with arsenic (As) (As-SiO 2 ). The preliminary buffer material layer 45p may include titanium nitride. In one embodiment, the preliminary buffer material layer 45p may further include oxygen. Thus, the preliminary buffer material layer 45p may include an initial titanium oxynitride. In the preliminary buffer material layer 45p, the titanium content ratio and the nitrogen content ratio may be similar to each other. In the preliminary buffer material layer 45p, the titanium content ratio may be slightly higher than the nitrogen content ratio (e.g., about 1.06:1). In the preliminary buffer material layer 45p, the nitrogen content ratio may be higher than the oxygen content ratio. For example, referring to Figure 5 (a), the initial titanium oxynitride of the preliminary buffer material layer 45p may include a titanium content ratio of greater than about 40 at%, a nitrogen content ratio of greater than about 40 at%, and an oxygen content ratio of less than about 20 at%.

[0037] Referring to Figure 3B , the method may further include forming a buffer material layer 45 and a select element material layer 35 by performing an ion implantation process. During the ion implantation process, at least one of boron ions or carbon ions may pass through the preliminary buffer material layer 45p and be implanted into the preliminary select element material layer 35p. The preliminary buffer material layer 45p may be used as an ion implantation buffer layer. For example, the ion implantation process may include implanting boron ions or carbon ions at a dose between 1E10 and 1E15 at an acceleration voltage of about 1 keV to about 3 keV. In the ion implantation process, the boron ions and carbon ions may partially break the titanium-nitrogen bonds in the preliminary buffer material layer 45p. The broken bonds may bond and combine with oxygen ions. Thus, titanium nitride may be oxidized.

[0038] Referring to Figure 4, the titanium-nitrogen triple bond in the preliminary buffer material layer 45p can be partially replaced by titanium-nitrogen double bonds or titanium-nitrogen single bonds in the buffer material layer 45. The bonds broken by boron ions and / or carbon ions can be re-bonded and re-combined with oxygen ions or other ions (M). The other ions M can be at least one of titanium, nitrogen, oxygen or other impurity ions. Therefore, the titanium content ratio and nitrogen content ratio in the preliminary buffer material layer 45p can be changed to the titanium content ratio and nitrogen content ratio in the buffer material layer 45. Refer to Figure 5 (b), the titanium content ratio in the buffer material layer 40 can be higher than the titanium content ratio in the preliminary buffer material layer 45p. The nitrogen content ratio in the buffer material layer 45 can be lower than the nitrogen content ratio in the preliminary buffer material layer 45p. The oxygen content ratio in the buffer material layer 45 can be higher than the oxygen content ratio in the preliminary buffer material layer 45p. In one embodiment, the titanium content ratio in the buffer material layer 45 can be higher than or equal to about 45 at%. For example, the titanium content ratio in the buffer material layer 45 can be about 50 at%. In one embodiment, the nitrogen content ratio in the buffer material layer 45 can be less than or equal to about 25 at%. For example, the nitrogen content ratio in the buffer material layer 45 can be about 20 at%. In one embodiment, the oxygen content ratio in the buffer material layer 45 can be higher than or equal to about 25 at%. For example, the oxygen content ratio in the buffer material layer 45 can be about 30 at%. The titanium content ratio in the buffer material layer 45 can be higher than the nitrogen content ratio and oxygen content ratio. The oxygen content ratio in the buffer material layer 45 can be higher than the nitrogen content ratio. Therefore, the buffer material layer 45 can include titanium-rich and oxygen-rich titanium oxynitride instead of the preliminary buffer material layer 45p. Boron ions and carbon ions can diffuse uniformly in the select element material 35.

[0039] Refer to Figure 3C , the method may further include: forming an intermediate electrode material layer 55, a storage material layer 65 and an upper electrode material layer 75 on the buffer material layer 45. The intermediate electrode material layer 55 can be completely formed on the buffer material layer 44. The intermediate electrode material layer 55 can include at least one of conductive layers, such as a carbon layer, a carbon-containing metal layer, a carbon-containing metal compound layer, a carbon-containing metal alloy, a carbon-containing metal silicide or a graphene layer. The storage material layer 65 can be completely formed on the intermediate electrode material layer 55. Further refer to Figure 2B , forming the storage material layer 65 may include forming a lower magnetic layer 61, a tunneling barrier layer 62 and an upper magnetic layer 63. The tunneling barrier layer 62 can be disposed between the lower magnetic layer 61 and the upper magnetic layer 63. The upper electrode material layer 75 can be completely formed on the storage material layer 65. The upper electrode material layer 75 can include at least one of a metal layer, a metal nitride layer, a metal silicide layer or a metal alloy layer. Forming the intermediate electrode material layer 55, the storage material layer 65 and the upper electrode material layer 75 may include performing a deposition process, a lithography process and an etching process.

[0040] Referring to Figure 3D , the method may further include forming the lower electrode 20, the select element 30, the buffer layer 45, the intermediate electrode 55, the storage layer 60, and the upper electrode 70 to form the memory cell MC by performing an etching process to pattern the upper electrode material layer 75, the storage material layer 65, the intermediate electrode material layer 55, the buffer material layer 45, the select element material layer 35, and the lower electrode material layer 25.

[0041] Thereafter, referring to Figure 2A , the method may further include forming the upper interconnection 80. The upper interconnection 80 may include at least one of a metal, a metal nitride, a metal silicide, and a metal alloy. Forming the upper interconnection 80 may include performing a deposition process, a lithography process, and an etching process.

[0042] Figure 6 is a band diagram showing that the buffer layer 40 according to an embodiment of the present disclosure improves the bandgap in the memory cell MC of the cross-point cell array of the semiconductor memory device. The buffer layer 40 may provide an intermediate energy level such that holes H can more easily cross the energy barrier of the select element 30. Accordingly, holes H may be gradually provided to the select element 30, and the channel formation characteristics of the select element 30 may be improved. Since holes H can be more easily provided to the select element 30, the concentration of holes H in the select element 30 may increase. Carbon ions may improve the conductivity of the select element 30, and boron ions may improve the insulating properties of the select element 30. Accordingly, by implanting carbon ions and boron ions, the electrical characteristics of the select element 30 may have an appropriate balance.

[0043] According to an embodiment of the present disclosure, the electrical performance of the select element 30 doped with boron (B) or carbon (C) may be improved.

[0044] According to an embodiment of the present disclosure, the bandgap characteristics of the select element of the titanium-rich and oxygen-rich buffer layer may be improved.

[0045] Although this patent document contains many details, these details should not be construed as limitations on any invention or the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of separate embodiments in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although the above features may be described as acting in certain combinations and even initially claimed as such, in some cases, one or more features of the claimed combination may be deleted from the claimed combination, and the claimed combination may relate to a sub-combination or a variation of a sub-combination.

[0046] Similarly, although the operations are depicted in the drawings in a particular order, this should not be construed as requiring that the operations be performed in the particular order or sequence shown, or that all of the illustrated operations be performed, to achieve the desired result. Additionally, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0047] Only some embodiments and examples are described. Enhancements and variations can be made to the disclosed embodiments and other embodiments based on what is described and shown in this patent document.

Claims

1. A semiconductor memory device comprising one or more memory cells, in, Each storage unit includes: Lower electrode; A selection element disposed on the lower electrode; a buffer layer disposed on the selection element; an intermediate electrode disposed on the buffer layer, the selection element and the lower electrode; a storage layer disposed on the intermediate electrode and storing data; and an upper electrode disposed on the storage layer, in: The buffer layer includes titanium, nitrogen and oxygen, and The titanium content ratio in the buffer layer is 1.21 times higher than the nitrogen content ratio.

2. The semiconductor memory device according to claim 1, in, The oxygen content ratio in the buffer layer is higher than the nitrogen content ratio.

3. The semiconductor memory device according to claim 2, in, The titanium content ratio in the buffer layer is higher than the oxygen content ratio.

4. The semiconductor memory device according to claim 1, in, The selection element includes a silicon oxide layer including one of boron or carbon and one of arsenic or germanium.

5. The semiconductor memory device according to claim 1, in, The intermediate electrode includes at least one of a carbon layer, a metal layer including carbon, or a metal compound layer including carbon.

6. The semiconductor memory device according to claim 1, in, The storage layer includes a lower magnetic layer, an upper magnetic layer, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

7. The semiconductor memory device according to claim 1, further comprising: a lower interconnection line disposed below the lower electrode and extending in a first horizontal direction; as well as An upper interconnection line is disposed on the upper electrode and extends in a second horizontal direction perpendicular to the first horizontal direction.

8. A semiconductor memory device having a memory cell, the memory cell comprising: a lower interconnect line extending in a first horizontal direction; a selection element disposed above the lower interconnect line and exhibiting different conductive characteristics in response to an applied voltage relative to a threshold voltage; a buffer layer disposed in contact with the selection element; an intermediate electrode configured to place the buffer layer and the selection element between the intermediate electrode and the lower interconnection line; A storage layer disposed on the intermediate electrode; as well as an upper interconnection line disposed above the storage layer, wherein the upper interconnection line extends in a second horizontal direction perpendicular to the first horizontal direction, The selection element includes a silicon oxide layer, and the silicon oxide layer has: 1) at least one of boron or carbon; and 2) at least one of arsenic or germanium.

9. The semiconductor memory device according to claim 8, in, The buffer layer includes titanium, nitrogen and oxygen.

10. The semiconductor memory device according to claim 9, in, The oxygen content ratio in the buffer layer is higher than the nitrogen content ratio.

11. The semiconductor memory device according to claim 9, in, The content ratio of titanium in the buffer layer is 1.21 times that of nitrogen.

12. The semiconductor memory device according to claim 9, in, The titanium content ratio in the buffer layer is higher than the oxygen content ratio.

13. The semiconductor memory device according to claim 8, in, The intermediate electrode includes at least one of a carbon layer, a metal layer including carbon, or a metal compound layer including carbon.

14. A semiconductor memory device having a memory cell, the memory cell comprising: a lower interconnect line extending in a first horizontal direction; a lower electrode disposed on the lower interconnection line; a selection element disposed on the lower electrode and exhibiting different conductive characteristics in response to an applied voltage relative to a threshold voltage; a buffer layer disposed on the selection element; an intermediate electrode disposed on the buffer layer; A storage layer disposed on the intermediate electrode; an upper electrode disposed on the storage layer; as well as an upper interconnection line disposed above the upper electrode and extending in a second horizontal direction perpendicular to the first horizontal direction, The selection element comprises a silicon oxide layer, wherein the silicon oxide layer comprises: 1) at least one of boron or carbon; and 2) at least one of arsenic or germanium, and Wherein, the buffer layer comprises a silicon oxide layer, and the silicon oxide layer comprises titanium, nitrogen and oxygen.

15. The semiconductor memory device according to claim 14, in, The oxygen content ratio in the buffer layer is higher than the nitrogen content ratio.

16. The semiconductor memory device according to claim 14, in, The content ratio of titanium in the buffer layer is 1.21 times that of nitrogen.

17. The semiconductor memory device according to claim 16, in, The titanium content ratio in the buffer layer is higher than the oxygen content ratio.

18. The semiconductor memory device according to claim 14, in, The silicon oxide layer includes an arsenic silicon oxide layer, and the arsenic silicon oxide layer includes at least one of boron or carbon.

19. The semiconductor memory device according to claim 14, in, The intermediate electrode includes at least one of a carbon layer, a metal layer including carbon, or a metal oxide layer including carbon.

20. A method of forming a semiconductor memory device, comprising: forming a lower electrode material layer, forming a preliminary selection element material layer on the lower electrode material layer, forming a preliminary buffer material layer on the preliminary selected element material layer, implanting at least one of boron or carbon into the preliminary selection element material layer using the preliminary buffer material layer as an ion implantation buffer layer to form a selection element material layer and a buffer material layer from the preliminary selection element material layer and the preliminary buffer material layer, respectively, forming an intermediate electrode material layer on the buffer material layer, forming a storage material layer on the intermediate electrode material layer, and forming an upper electrode on the storage material layer, in: The buffer material layer includes titanium, nitrogen and oxygen, and The oxygen content ratio in the buffer material layer is higher than the nitrogen content ratio.

21. The method according to claim 20, in, The selection element material layer includes a silicon oxide layer, and the silicon oxide layer includes: 1) at least one of boron or carbon; and 2) at least one of arsenic or germanium.

22. The method according to claim 20, in, The titanium content ratio in the buffer material layer is 1.21 times the nitrogen content ratio.

23. The method according to claim 20, in, The titanium content ratio in the buffer material layer is higher than the oxygen content ratio.

24. The method according to claim 20, in, The nitrogen content ratio in the preliminary buffer material layer is higher than the oxygen content ratio.

25. The method according to claim 20, in, The titanium content ratio in the preliminary buffer material layer is less than 1.21 times the nitrogen content ratio.

26. A method of forming a semiconductor memory device, comprising: forming a lower electrode material layer, forming a preliminary selection element material layer on the lower electrode material layer, forming a preliminary buffer material layer on the preliminary selected element material layer, implanting at least one of boron or carbon into the preliminary selection element material layer using the preliminary buffer material layer as an ion implantation buffer layer to form a selection element material layer and a buffer material layer from the preliminary selection element material layer and the preliminary buffer material layer, forming an intermediate electrode material layer on the buffer material layer, forming a storage material layer on the intermediate electrode material layer, and forming an upper electrode on the storage material layer, Wherein, the preliminary selected element material layer includes arsenic silicon oxide, and Wherein, the selection element material layer includes arsenic silicon oxide doped with at least one of boron or carbon.

27. The method according to claim 26, in, The buffer material layer includes titanium, nitrogen and oxygen, and Wherein, the oxygen content ratio in the buffer material layer is higher than the nitrogen content ratio.

28. The method according to claim 27, in, The titanium content ratio in the buffer material layer is 1.21 times the nitrogen content ratio.

29. The method according to claim 27, in, The nitrogen content ratio in the preliminary buffer material layer is higher than the oxygen content ratio.

30. The method according to claim 26, in, The titanium content ratio in the preliminary buffer material layer is less than 1.21 times the nitrogen content ratio.

31. A method of forming a semiconductor memory device, comprising: forming a lower electrode, forming a selection element on the lower electrode, forming a buffer layer on the selection element, forming an intermediate electrode on the buffer layer, forming a storage layer on the intermediate electrode, and forming an upper electrode on the storage layer, wherein the selection element comprises an arsenic silicon oxide layer doped with at least one of boron or carbon, and wherein the buffer layer comprises titanium, nitrogen and oxygen.

32. The method according to claim 31, in, The oxygen content ratio in the buffer layer is higher than the nitrogen content ratio.

33. The method according to claim 31, in, The content ratio of titanium in the buffer layer is 1.21 times that of nitrogen.

34. The method according to claim 31, in, The titanium content ratio in the buffer layer is higher than the oxygen content ratio.

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