Data erasing method and device, computer equipment and storage medium

Abstract

The invention discloses a data erasing method and device, computer equipment and a storage medium, and relates to the technical field of flash memories, the data erasing method comprises the following steps: because a cache vacancy rate can reflect a load condition, a command vacancy time length can reflect a storage task density, data stored in a preset type of flash memory block is relatively important and needs to be erased in time, and the data damage risk is reduced; under the condition that the command idle duration is greater than the idle duration threshold, the current storage task density is relatively low. Therefore, through comprehensive consideration, when the command idle duration is larger than the idle duration threshold value (determined in real time according to the cache idle rate) and the target flash memory block is not the flash memory block of the preset type, the performance index value of the target flash memory block is obtained in real time, the corresponding setting strategy is selected according to the performance index value, and different erasing modes are set for different flash memory blocks. In this way, the erasing mode of the flash memory block is dynamically adjusted by combining various factors to perform the erasing operation, and the flexibility is high.

Description

Technical Field

[0001] This application relates to the field of flash memory technology, and in particular, to a data erasure method, apparatus, computer device, and storage medium. Background Art

[0002] In the field of flash memory technology, when erasing the data stored in a flash memory block, generally, a voltage is applied to all the memory cells in the flash memory block to migrate the electrons in the floating gate of the memory cell to the substrate, so that the electrons originally stored in the floating gate are released, and the erasure operation is completed.

[0003] However, currently, the erasure operation is performed using a fixed erasure mode (i.e., using a fixed erasure voltage and erasure duration), and the flexibility is low. Summary of the Invention

[0004] This application provides a data erasure method, apparatus, computer device, storage medium, and program product to at least solve the problem of low flexibility of the erasure operation.

[0005] This application provides a data erasure method, including:

[0006] Obtaining the command idle duration, cache idle rate, and the tag of at least one flash memory block included in the flash memory;

[0007] Obtaining an idle duration threshold matching the cache idle rate according to the cache idle rate;

[0008] When it is determined that the command idle duration is greater than the idle duration threshold and, according to the tag of the target flash memory block, it is determined that the target flash memory block is not marked as a preset type, obtaining the performance metric value of the target flash memory block, where the target flash memory block is any one of the at least one flash memory block;

[0009] Selecting a setting strategy corresponding to the erasure mode of the target flash memory block according to the number of performance metric values of the target flash memory block;

[0010] Setting the erasure mode of the target flash memory block according to the setting strategy;

[0011] Performing a data erasure operation corresponding to the erasure mode on the target flash memory block according to the erasure mode of the target flash memory block.

[0012] This application also provides a data erasure apparatus, including:

[0013] An acquisition module, configured to acquire the command idle duration, the cache idle rate, and the tags respectively corresponding to at least one flash memory block included in the flash memory; acquire an idle duration threshold matching the cache idle rate according to the cache idle rate; when it is determined that the command idle duration is greater than the idle duration threshold and, according to the tag of the target flash memory block, it is determined that the target flash memory block is not marked as a preset type, acquire the performance metric value of the target flash memory block, where the target flash memory block is any one of the at least one flash memory block;

[0014] A selection module, configured to select a setting strategy corresponding to the erasure mode of the target flash memory block according to the number of performance metric values of the target flash memory block;

[0015] A setting module, configured to set the erasure mode of the target flash memory block according to the setting strategy;

[0016] An erasure module, configured to perform a data erasure operation corresponding to the erasure mode on the target flash memory block according to the erasure mode of the target flash memory block.

[0017] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above data erasure methods when executing the computer program.

[0018] This application also provides a computer-readable storage medium, in which a computer program is stored, where the computer program implements the steps of any one of the above data erasure methods when executed by a processor.

[0019] This application also provides a computer program product, including a computer program, where the computer program implements the steps of any one of the above data erasure methods when executed by a processor.

[0020] With this application, since the cache idle rate can reflect the load condition of the device executing this solution and the command idle duration can reflect the current storage task density, this solution obtains the command idle duration and the cache idle rate for subsequent analysis operations. Moreover, to enhance flexibility, this solution does not use a fixed idle duration threshold for comparison, but determines the corresponding idle duration threshold according to the cache idle rate. Since the data stored in the flash memory blocks of the preset type is relatively important and needs to be erased in a timely manner to reduce the risk of data corruption, and when the command idle duration is greater than the idle duration threshold, it means that the current storage task density is low and there is no need to complete the erasure task as soon as possible. Therefore, by comprehensively considering these factors, this solution selects to obtain the performance metric value of the target flash memory block in real time when the command idle duration is greater than the idle duration threshold and the target flash memory block is not of the preset type, selects the corresponding setting strategy according to the data of the performance metric value, and then, according to the setting strategy, sets different erasure modes for different flash memory blocks for subsequent erasure operations. In this way, by dynamically adjusting the erasure mode of the flash memory block in combination with various factors for erasure operations, the flexibility of the erasure operations can be improved, so that different erasure modes can be used for erasure operations under different load conditions, and the flash memory lifespan, overall performance, and user experience can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 The structural schematic diagram of a data erasure system provided by an embodiment of this application;

[0023] Figure 2 The flowchart of a data erasure method provided by an embodiment of this application;

[0024] Figure 3 The structural schematic diagram of another data erasure system provided by an embodiment of this application;

[0025] Figure 4 The flowchart of another data erasure method provided by an embodiment of this application;

[0026] Figure 5 The structural schematic diagram of a data erasure device provided by an embodiment of this application;

[0027] Figure 6 The structural schematic diagram of an electronic device provided by an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0029] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0030] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] The embodiments of the present application can be implemented by a data erasure system. As Figure 1 shown, the data erasure system may include a flash memory (Flash) and a flash memory controller. The flash memory may include at least one flash memory block, and each flash memory block may include at least one storage unit. The flash memory block is the basic unit for performing an erasure operation. During the erasure process, the flash memory controller may apply a 0V voltage to the control gates of all word lines (WL) of the flash memory block, and a high voltage (for example, 20V) is constantly applied to the substrate. In this way, under the action of the tunneling effect, the electrons in the floating gate of each storage unit migrate to the substrate, so that the electrons originally stored in the floating gate are released, resulting in the threshold voltage of the storage unit being reduced to the erased state, achieving the purpose of emptying all the electrons in the storage unit.

[0032] The embodiments of the present application provide a data erasure method, which can be executed by the above-mentioned flash memory controller. As Figure 2 shown, the process of the data erasure method may include the following steps:

[0033] Step S201, obtain the command idle duration, the cache idle rate, and the marks respectively corresponding to at least one flash memory block included in the flash memory.

[0034] The flash memory controller may periodically obtain the command idle duration, the cache idle rate, and the marks respectively corresponding to at least one flash memory block included in the flash memory.

[0035] Among them, obtaining the command idle duration of the current period may include the following steps:

[0036] Step 1: Obtain the timestamps corresponding to multiple write commands recorded in the current cycle.

[0037] Step 2: Calculate the idle duration between two adjacent write commands according to the timestamps corresponding to the two adjacent write commands.

[0038] Step 3: Determine the average idle duration according to each idle duration.

[0039] Step 4: Determine the average idle duration as the command idle duration.

[0040] Specifically, each time the flash memory controller receives a write command, it can record the timestamp when the write command is received. When performing the operations in the current cycle, the flash memory controller can calculate the interval duration (i.e., the idle duration) between all adjacent two write commands according to the timestamps of all write commands recorded in the current cycle. Then, the flash memory controller can calculate the average idle duration according to each idle duration and determine the average idle duration as the command idle duration. The flash memory controller can monitor its own cache idle rate in real time and read the latest cache idle rate at the trigger moment of the current cycle. In addition, the flash memory controller can read the tags of each flash block recorded in the firmware. In this way, the flash memory controller obtains the command idle duration, the cache idle rate, and the tags corresponding to at least one flash block included in the flash memory.

[0041] Step S202: Obtain the idle duration threshold that matches the cache idle rate according to the cache idle rate.

[0042] Specifically, the flash memory controller can determine the target preset cache idle rate range in which the cache idle rate falls according to multiple preset cache idle rate ranges and the cache idle rate, and determine the idle duration threshold corresponding to the target preset cache idle rate range as the target idle duration threshold.

[0043] For example, the multiple preset cache idle rate ranges can include "greater than 80%", "50%-80%", and "less than 50%", and the idle duration thresholds corresponding to the three preset cache idle rate ranges decrease from high to low. Since a higher cache idle rate means a higher current load, the idle duration threshold can be increased to reduce the probability that the command idle duration is greater than the idle duration threshold. Furthermore, the flash block can be erased with a higher erasure voltage and a shorter erasure duration to complete the write operation as soon as possible and reduce the performance impact. While a lower cache idle rate means a lower current load, the idle duration threshold can be decreased to increase the probability that the command idle duration is greater than the idle duration threshold. Furthermore, different erasure modes can be used for the flash block according to the performance index value of the flash block for erasure operation, which can balance the load and improve the lifespan of the flash memory.

[0044] Step S203: When it is determined that the command idle duration is greater than the idle duration threshold and, based on the label of the target flash memory block, it is determined that the target flash memory block is not labeled as the preset type, obtain the performance metric value of the target flash memory block.

[0045] Among them, the target flash memory block is any one of at least one flash memory block. The performance metric value of the target flash memory block may include one or more of the performance metric values such as the number of erasures, access frequency, and invalid data ratio. The preset type is used to indicate that the data stored in the flash memory block is critical data, that is, data that the user deems to be of a relatively high level of importance, or data that the storage software determines belongs to a specified type according to preset rules. The invalid data ratio refers to the proportion of invalid data in all data in the flash memory block. Invalid data refers to data that has been deleted, overwritten, or damaged. Usually, the firmware will mark these unnecessary data.

[0046] Specifically, the flash memory controller can first determine whether the command idle duration is greater than the idle duration threshold. If so, it means that the density of the current processing task is relatively low, and it can continue to analyze each flash memory block to determine the priority. For each flash memory block, the flash memory controller can, based on the label of the flash memory block, determine whether the data stored in the flash memory block is critical data. When it is determined that the data stored in the flash memory block is critical data, read the number of erasures and access frequency of the target flash memory block from the memory of the flash memory controller, and determine the proportion of the data marked as invalid data in all data in the flash memory block.

[0047] Each time the flash memory controller performs an erasure operation on a flash memory block, increment the number of erasures of the flash memory block by one, and record the identification information of the flash memory block and its number of erasures in its own memory. Also, for each flash memory block, the flash memory controller can periodically count the access (access includes read, write, and erasure, etc.) frequency of each flash memory block, and record the identification information of the flash memory block and its access frequency in its own memory. In this way, when setting the erasure mode for the flash memory block in each cycle, these data can be directly read from the memory for use in the subsequent process of determining the priority.

[0048] In some alternative embodiments, when it is determined that the command idle duration is greater than the idle duration threshold and, based on the label of the target flash memory block, it is determined that the target flash memory block has been labeled as the preset type, set the erasure mode of the target flash memory block to the first erasure mode.

[0049] Among them, the erasure duration included in the first erasure mode is the shortest among the erasure durations included in all erasure modes, and the erasure voltage included in the first erasure mode is the highest among the erasure voltages included in all erasure modes.

[0050] Specifically, when the flash memory controller determines that the command idle duration is greater than the idle duration threshold, it indicates that the current processing task frequency of the flash memory controller is relatively low. However, for the target flash memory block, since the stored data is critical data, the target flash memory block can be preferentially erased to reduce the risk of data corruption and improve the erasure stability.

[0051] In some alternative embodiments, when it is determined that the command idle duration is greater than the idle duration threshold and, according to the label of the target flash memory block, it is determined that the target flash memory block has been labeled as a preset type, the priority of the target flash memory block is set to the highest priority. The flash memory controller can determine whether the priority of the target flash memory block in the current cycle is consistent with that in the previous cycle. If they are consistent, the erasure operation continues in the current cycle according to the original erasure mode. If they are inconsistent, the corresponding first erasure mode is determined according to the highest priority, and then the target flash memory block is erased in the current cycle according to the first erasure mode.

[0052] In some alternative embodiments, when the flash memory controller determines that the command idle duration is less than or equal to the idle duration threshold, it indicates that the current processing task frequency of the flash memory controller is relatively high, that is, the data of the flash memory block needs to be erased in a relatively short time. Therefore, the flash memory controller can set the erasure mode of all flash memory blocks to the above-mentioned first erasure mode.

[0053] Step S204: Select a setting strategy corresponding to the erasure mode of the target flash memory block according to the number of performance metric values of the target flash memory block.

[0054] Among them, when the performance metric value of the target flash memory block includes one, the selected setting strategy is to set the erasure mode of the target flash memory block according to the performance metric value of the target flash memory block. Or, when the performance metric values of the target flash memory block include multiple, the selected setting strategy is to set the erasure mode of the target flash memory block according to the performance metric value of the target flash memory block and the cache idle rate.

[0055] Step S205: Set the erasure mode of the target flash memory block according to the setting strategy.

[0056] Each erasure mode includes an erasure duration and an erasure voltage.

[0057] Case 1: When the performance metric value of the target flash memory block includes one, setting the erasure mode of the target flash memory block according to the performance metric value of the target flash memory block may specifically include the following steps:

[0058] Step 1: According to the performance metric value, determine the performance metric value range into which the performance metric value falls among multiple preset performance metric value ranges.

[0059] Step 2: Determine the priority corresponding to the performance metric value range in which the performance metric value falls as the priority of the target flash block.

[0060] Among them, when the performance metric value is the invalid data ratio, the performance metric value is directly proportional to the priority, that is, the larger the invalid data ratio, the higher the priority, and the smaller the invalid data ratio, the lower the priority. Since flash blocks with a higher invalid data ratio complete the erase operation faster, therefore, setting a higher priority for flash blocks with a higher invalid data ratio can improve the erase efficiency as a whole, that is, it can improve the overall read / write performance.

[0061] When the performance metric value is the access frequency, the performance metric value is directly proportional to the priority, that is, the larger the access frequency, the higher the priority, and the lower the access frequency, the lower the priority. Generally, flash blocks with a high access frequency are called hot blocks, and flash blocks with a low access frequency are called cold blocks. Since blocks with a high access frequency usually store "hot data", therefore, this type of flash block can be preferentially erased to optimize the space utilization rate.

[0062] When the performance metric value is the number of erase times, the performance metric value is directly proportional to the priority, that is, the more the number of erase times, the higher the priority, and the fewer the number of erase times, the lower the priority. Since the physical state of a block with more erase times may be worse, or it is about to reach the end of its life, therefore, the erase operation should be preferentially considered, and it should be used first when the flash block can still be used.

[0063] Step 3: Set the erase mode corresponding to the priority of the target flash block as the erase mode of the target flash block.

[0064] Specifically, the memory of the flash controller can store a first mapping relationship between the performance metric value range and the priority, and a second mapping relationship between the priority and the erase mode. The flash controller can determine which performance metric range the performance metric value falls into according to multiple preset performance metric value ranges, and then, according to the performance metric value range in which the performance metric value falls and the first mapping relationship, determine the priority corresponding to the performance metric value range in which the performance metric value falls, and determine the priority corresponding to the performance metric value range in which the performance metric value falls as the priority of the target flash block. Then, the flash controller can determine the erase mode corresponding to the target flash block according to the priority of the target flash block and the second mapping relationship. Finally, the erase mode corresponding to the priority of the target flash block can be set as the erase mode of the target flash block.

[0065] For example, the second mapping relationship can be as shown in Table 1.

[0066] Table 1

[0067] Priority Erase Mode First Mode1 Second Mode2 Third Mode3

[0068] For example, the specific settings of the erasure mode can be as shown in Table 2.

[0069] Table 2

[0070] Erase Mode Erase Voltage Erase Duration Mode1 20V 6ms Mode2 18V 8ms Mode3 16V 10ms

[0071] In Case 2, when there are multiple performance metric values for the target flash block, the erasure mode of the target flash block is set according to the performance metric values of the target flash block and the cache free rate. Specifically, it may include the following steps:

[0072] Step 1: Obtain the weight value of each performance metric value corresponding to the cache free rate according to the cache free rate.

[0073] Step 2: Determine the priority of the target flash block according to each performance metric value and the weight value of each performance metric value.

[0074] Step 3: Set the erasure mode corresponding to the priority of the target flash block as the erasure mode of the target flash block.

[0075] For example, when the performance metric values of the target flash block include the above-mentioned erasure count, access frequency, and invalid data ratio, Step 1 may specifically include:

[0076] When it is determined that the cache free rate is greater than the preset threshold, the first preset weight value is determined as the weight value of the erasure count, and the second preset weight value is respectively determined as the weight values of the access frequency and the invalid data ratio, where the first preset weight value is less than the second preset weight value. Alternatively, when it is determined that the cache free rate is less than or equal to the preset threshold, the third preset weight value is determined as the weight value of the erasure count, and the fourth preset weight value is respectively determined as the weight values of the access frequency and the invalid data ratio, where the third preset weight value is greater than the fourth preset weight value. Since a small cache free rate indicates a high current load, setting larger weights for the access frequency and the invalid data ratio can quickly release space and respond to a large number of write requests. When the cache free rate is large, it indicates a low current load. Setting a large weight for the erasure count can preferentially process flash blocks with a large number of erasures to reduce further wear and extend the flash life.

[0077] The above Step 2 may specifically include the following two methods:

[0078] Method 1: Determine the normalized value corresponding to the target performance metric value based on the target performance metric value, the pre-acquired maximum performance metric value and minimum performance metric value corresponding to the target performance metric value, where the target performance metric value is any one of the multiple performance metric values of the target flash memory block. Determine the performance score of the target flash memory block according to the normalized value and the weight value corresponding to each performance metric value. Determine the priority of the target flash memory block according to the performance score of the target flash memory block and the mapping relationship between the performance score range and the priority.

[0079] Specifically, the flash memory controller can determine the maximum number of erasures and the minimum number of erasures based on the number of erasures of all flash memory blocks, determine the maximum access frequency and the minimum access frequency based on the access frequency of all flash memory blocks, and determine the maximum invalid data ratio and the minimum invalid data ratio based on the invalid data ratio of all flash memory blocks. For the number of erasures of the target flash memory block, the flash memory controller can calculate the difference between the maximum number of erasures and the minimum number of erasures, and determine the ratio of the number of erasures of the target flash memory block to this difference as the normalized value corresponding to the number of erasures of the target flash memory block. For the access frequency of the target flash memory block, the flash memory controller can calculate the difference between the maximum access frequency and the minimum access frequency, and determine the ratio of the access frequency of the target flash memory block to this difference as the normalized value corresponding to the access frequency of the target flash memory block. For the invalid data ratio of the target flash memory block, the flash memory controller can calculate the difference between the maximum invalid data ratio and the minimum invalid data ratio, and determine the ratio of the invalid data ratio of the target flash memory block to this difference as the normalized value corresponding to the invalid data ratio of the target flash memory block.

[0080] After calculating the normalized value corresponding to each performance metric value, the flash memory controller can calculate the product of each performance metric value and its corresponding weight value, and then add up all the products to obtain the performance score of the target flash memory block. The mapping relationship between the performance score range and the priority can be stored in the memory of the flash memory controller. In this way, the flash memory controller can determine the priority corresponding to the performance score range in which the performance score falls as the priority of the target flash memory block.

[0081] Method 2: According to the target performance index value and multiple preset performance index value ranges, determine the performance index value range into which the target performance index value falls, where the target performance index value is any one of the multiple performance index values of the target flash memory block. Determine the priority corresponding to the target performance index value as the priority corresponding to the performance index value range into which the target performance index value falls. According to the priority and weight value corresponding to each performance index value, determine the priority of the target flash memory block (for example, first determine the priority score according to the priority and weight value corresponding to each performance index value, and then determine the priority score range into which the priority score falls, and determine the priority corresponding to this priority score range as the priority of the target flash memory block). In this way, the efficiency of determining the priority can be improved and resource occupancy can be reduced.

[0082] After determining the priority of the target flash memory block, the flash memory controller can determine the erasure mode corresponding to the target flash memory block according to the priority of the target flash memory block and the second mapping relationship. Finally, the erasure mode corresponding to the priority of the target flash memory block can be set as the erasure mode of the target flash memory block.

[0083] In some alternative embodiments, after determining the priority of the target flash memory block in the current cycle, the flash memory controller can determine whether the priority of the target flash memory block in the current cycle is the same as the priority in the previous cycle. If they are the same, there is no need to perform subsequent operations of matching the erasure mode and switching the erasure mode. If they are different, then perform subsequent operations of matching the erasure mode and switching the erasure mode. In this way, resources can be saved.

[0084] Step S206: Perform a data erasure operation corresponding to the erasure mode on the target flash memory block according to the erasure mode of the target flash memory block.

[0085] Specifically, in the current cycle, the flash memory controller can apply a voltage to the target flash memory block according to the erasure duration and erasure voltage included in the erasure mode of the target flash memory block to complete the erasure operation of the target flash memory block.

[0086] In some alternative embodiments, when it is monitored that the cache idle rate is less than the preset idle rate threshold, the erasure mode of each flash memory block is set to the first erasure mode.

[0087] Specifically, when the flash memory controller monitors that the cache idle rate is less than the preset idle rate threshold, it can set the erasure modes of all flash memory blocks to the first erasure mode to complete the erasure operation as soon as possible and perform subsequent read and write operations.

[0088] In the data erasure method provided by the embodiments of the present application, since the cache idle rate can reflect the load condition of the device executing this solution, and the command idle duration can reflect the current storage task density, therefore, this solution obtains the command idle duration and the cache idle rate for subsequent analysis operations. Moreover, in order to enhance flexibility, this solution does not use a fixed idle duration threshold for comparison, but determines the corresponding idle duration threshold according to the cache idle rate. Since the data stored in the flash memory blocks of the preset type is relatively important and needs to be erased in a timely manner to reduce the risk of data corruption, and when the command idle duration is greater than the idle duration threshold, it means that the current storage task density is relatively low. Therefore, by considering these two points comprehensively, when the command idle duration is greater than the idle duration threshold and the target flash memory block is not of the preset type, the performance metric value of the target flash memory block is obtained in real time, and the corresponding setting strategy is selected according to the data of the performance metric value. Furthermore, according to the setting strategy, different erasure modes are set for different flash memory blocks for subsequent erasure operations. In this way, by dynamically adjusting the erasure mode of the flash memory block in combination with various factors for the erasure operation, the flexibility can be improved, so that different erasure modes can be used for the erasure operation in different situations, and the overall performance and user experience can be improved. In addition, in the fixed erasure mode adopted in the related art, the erasure voltage is relatively high and the erasure duration is relatively short, which will cause a relatively large loss of the insulating layer of the storage unit in the flash memory block, and thus lead to a relatively low lifespan of the flash memory. However, in this solution, for different flash memory blocks, different erasure modes can be adopted according to the performance of the flash memory block, which can improve the lifespan of the flash memory.

[0089] The following uses a specific example to illustrate the data erasure method. As Figure 3 shown, the flash memory controller may specifically include multiple hardware modules such as an idle detection module, a priority setting module, an access count module, an erasure count module, a data monitoring module, a cache management module, a mode selection module, and an erasure execution module.

[0090] The idle detection module is used to calculate the command idle duration between two consecutive write commands, and determine the corresponding idle duration threshold according to the obtained cache idle rate, and then compare the command idle duration with the idle duration threshold. The erase count module is used to count the number of erasures of each flash memory block. The access count module is used to count the access frequency of each flash memory block. The data monitoring module is used to record the invalid data ratio of each flash memory block. The cache management module is used to monitor the cache idle rate. The priority setting module is used to determine the priority of each flash memory block according to whether each flash memory block is marked as a preset type, and according to the number of erasures, access frequency, and invalid data ratio of each flash memory block, and establish a priority queue. The elements of the priority queue may include the identification information, number of erasures, access frequency, data invalid ratio, and priority of the flash memory block. The mode selection module is used to set the erase mode of each flash memory block according to the priority of each flash memory block. The erase execution module is used to perform an erase operation corresponding to the erase mode on each flash memory block according to the erase mode of each flash memory block.

[0091] As Figure 4 shown, the idle detection module can obtain the cache idle rate from the cache management module, obtain the corresponding idle duration threshold according to the cache idle rate, and calculate the command idle duration. When it is determined that the command idle duration is less than or equal to the idle duration threshold, a notification can be sent to the mode selection module. After receiving the notification, the mode selection module can choose to set all flash memory modules to the first erase mode (for example, Mode1 in Table 1) to complete the erase operation as soon as possible for subsequent write operations. When it is determined that the command idle duration is greater than the idle duration threshold, a notification can be sent to the priority setting module. After receiving the notification, the priority setting module can create a priority queue. The priority setting module can obtain the judgment result of whether each flash memory block is critical data from the data monitoring module. If the judgment result is yes, the priority of the flash memory block can be set to the highest priority (for example, the first priority in Table 1). If the judgment result is no, the priority of each flash memory block can be further determined by combining the number of erasures, access frequency, data invalid ratio, and cache idle rate. The priority setting module can send the priority of each flash memory block to the mode selection module. In this way, the mode selection module can set the erase mode of each flash memory block according to the priority of each flash memory block and the mapping relationship between the priority and the erase mode. The erase execution module can perform the erase operation according to the set erase mode. At the same time, when the priority of the flash memory block changes, the erase mode can be switched in time to achieve dynamic erasure.

[0092] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0093] An embodiment of the present application further provides a data erasure device, as Figure 5 shown, including:

[0094] An acquisition module 510, configured to acquire the command idle duration, the cache idle rate, and the tags respectively corresponding to at least one flash memory block included in the flash memory; according to the cache idle rate, acquire an idle duration threshold matching the cache idle rate; when it is determined that the command idle duration is greater than the idle duration threshold, and according to the tag of the target flash memory block, it is determined that the target flash memory block is not marked as a preset type, acquire the performance metric value of the target flash memory block, where the target flash memory block is any one of the at least one flash memory block;

[0095] A selection module 520, configured to select a setting policy corresponding to the erasure mode of the target flash memory block according to the number of performance metric values of the target flash memory block;

[0096] A setting module 530, configured to set the erasure mode of the target flash memory block according to the setting policy;

[0097] An erasure module 540, configured to perform a data erasure operation corresponding to the erasure mode on the target flash memory block according to the erasure mode of the target flash memory block.

[0098] In some alternative embodiments, when the performance metric value of the target flash memory block includes one, the selected setting policy is to set the erasure mode of the target flash memory block according to the performance metric value of the target flash memory block; or, when the performance metric value of the target flash memory block includes multiple, the selected setting policy is to set the erasure mode of the target flash memory block according to the performance metric value of the target flash memory block and the cache idle rate.

[0099] In some alternative embodiments, when the performance metric value of the target flash memory block includes one, the setting module 530 is specifically configured to:

[0100] According to the performance metric value, determine the performance metric value range in which the performance metric value falls among multiple preset performance metric value ranges;

[0101] Determine the priority corresponding to the performance metric value range in which the performance metric value falls as the priority of the target flash memory block;

[0102] Set the erasure mode corresponding to the priority of the target flash memory block as the erasure mode of the target flash memory block.

[0103] In some alternative embodiments, when there are multiple performance metric values for the target flash block; the setting module 530 is specifically configured to:

[0104] Obtain the weight value corresponding to each performance metric value according to the cache free rate;

[0105] Determine the priority of the target flash block according to each performance metric value and the weight value of each performance metric value;

[0106] Set the erasure mode corresponding to the priority of the target flash block as the erasure mode of the target flash block.

[0107] In some alternative embodiments, the performance metric values of the target flash block include the number of erasures, access frequency, and invalid data ratio; the setting module 530 is specifically configured to:

[0108] When it is determined that the cache free rate is greater than a preset threshold, determine the first preset weight value as the weight value of the number of erasures, and determine the second preset weight value as the weight values of the access frequency and the invalid data ratio respectively, where the first preset weight value is less than the second preset weight value;

[0109] Or,

[0110] When it is determined that the cache free rate is less than or equal to the preset threshold, determine the third preset weight value as the weight value of the number of erasures, and determine the fourth preset weight value as the weight values of the access frequency and the invalid data ratio respectively, where the third preset weight value is greater than the fourth preset weight value.

[0111] In some alternative embodiments, the setting module 530 is specifically configured to:

[0112] Determine the normalized value corresponding to the target performance metric value according to the target performance metric value and the pre-obtained maximum performance metric value and minimum performance metric value corresponding to the target performance metric value, where the target performance metric value is any one of the multiple performance metric values of the target flash block;

[0113] Determine the performance score of the target flash block according to the normalized value and weight value corresponding to each performance metric value;

[0114] Determine the priority of the target flash block according to the performance score of the target flash block and the mapping relationship between the performance score range and the priority.

[0115] In some alternative embodiments, each erasure mode includes an erasure duration and an erasure voltage; the setting module 530 is further configured to:

[0116] When it is determined that the command idle duration is less than or equal to the idle duration threshold and, based on the label of the target flash memory block, it is determined that the target flash memory block has been labeled as a preset type, set the erasure mode of the target flash memory block to the first erasure mode, where the erasure duration included in the first erasure mode is the shortest among the erasure durations included in all erasure modes, and the erasure voltage included in the first erasure mode is the highest among the erasure voltages included in all erasure modes.

[0117] For the description of the features in the corresponding embodiments of the data erasure device, reference can be made to the relevant description in the corresponding embodiments of the data erasure method, which will not be elaborated here one by one.

[0118] An embodiment of the present application further provides an electronic device, such as Figure 6 shown, including a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above embodiments of the data erasure method.

[0119] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute the steps in any of the above embodiments of the data erasure method when running.

[0120] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0121] An embodiment of the present application further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the data erasure method are implemented.

[0122] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the data erasure method are implemented.

[0123] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0124] The above has introduced in detail a data erasure method, apparatus, computer device, storage medium, and program product provided by this application. Specific examples have been used herein to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data erasure method, characterized in that: include: Acquire a command idle time, a cache idle rate, and a mark of at least one flash memory block included in the flash memory; According to the cache idle rate, obtaining an idle duration threshold that matches the cache idle rate; When it is determined that the idle time length of the command is greater than the idle time length threshold, and according to the mark of the target flash memory block, it is determined that the target flash memory block is not marked as a preset type, obtaining a performance indicator value of the target flash memory block, wherein the target flash memory block is any one of the at least one flash memory block; Selecting a setting strategy corresponding to an erase mode of the target flash memory block according to the number of performance indicator values ​​of the target flash memory block; According to the setting strategy, setting the erase mode of the target flash memory block; According to the erasure mode of the target flash memory block, a data erasure operation corresponding to the erasure mode is performed on the target flash memory block.

2. The data erasing method according to claim 1, characterized in that: When the performance indicator value of the target flash memory block includes one, the setting strategy selected is to set the erase mode of the target flash memory block according to the performance indicator value of the target flash memory block; or, when the performance indicator value of the target flash memory block includes multiple, the setting strategy selected is to set the erase mode of the target flash memory block according to the performance indicator value of the target flash memory block and the cache free rate.

3. The data erasing method according to claim 2, characterized in that: When the performance indicator value of the target flash memory block includes one, setting the erasure mode of the target flash memory block according to the setting strategy includes: According to the performance indicator value, determining a performance indicator value range within which the performance indicator value falls within a plurality of preset performance indicator value ranges; Determine the priority corresponding to the performance indicator value range within which the performance indicator value falls as the priority of the target flash memory block; An erase mode corresponding to the priority level of the target flash memory block is set as the erase mode of the target flash memory block.

4. The data erasing method according to claim 2, characterized in that: When the performance indicator value of the target flash memory block includes multiple values; setting the erase mode of the target flash memory block according to the setting strategy includes: According to the cache idle rate, obtaining a weight value of each performance indicator value corresponding to the cache idle rate; Determining the priority of the target flash memory block according to each of the performance indicator values ​​and a weight value of each of the performance indicator values; An erase mode corresponding to the priority level of the target flash memory block is set as the erase mode of the target flash memory block.

5. The data erasing method according to claim 4, characterized in that: The performance indicator values ​​of the target flash memory block include the number of erase times, the access frequency, and the invalid data ratio; and obtaining the weight value of each performance indicator value corresponding to the cache idle rate according to the cache idle rate includes: When it is determined that the cache idle rate is greater than a preset threshold, a first preset weight value is determined as the weight value of the number of erasures, and a second preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively, wherein the first preset weight value is less than the second preset weight value; or, When it is determined that the cache free rate is less than or equal to the preset threshold, the third preset weight value is determined as the weight value of the number of erasures, and the fourth preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively, wherein the third preset weight value is greater than the fourth preset weight value.

6. The data erasing method according to claim 4, characterized in that: Determining the priority of the target flash memory block according to each of the performance indicator values ​​and the weight value of each of the performance indicator values ​​includes: Determine a normalized value corresponding to the target performance indicator value according to the target performance indicator value, and a pre-acquired maximum performance indicator value and a minimum performance indicator value corresponding to the target performance indicator value, wherein the target performance indicator value is any one of a plurality of performance indicator values ​​of the target flash memory block; Determining a performance score of the target flash memory block according to a normalized value and a weight value corresponding to each of the performance indicator values; The priority of the target flash memory block is determined according to the performance score of the target flash memory block and the mapping relationship between the performance score range and the priority.

7. The data erasing method according to any one of claims 1 to 6, characterized in that: Each erasing mode includes an erasing time and an erasing voltage; the method further includes: When it is determined that the command idle time is less than or equal to the idle time threshold, and based on the mark of the target flash memory block, it is determined that the target flash memory block has been marked as a preset type, the erase mode of the target flash memory block is set to a first erase mode, wherein the erase time included in the first erase mode is the shortest of the erase times respectively included in all erase modes, and the erase voltage included in the first erase mode is the highest of the erase voltages respectively included in all erase modes.

8. A data erasing device, characterized in that: include: An acquisition module, used to acquire a command idle time, a cache idle rate, and a mark corresponding to at least one flash memory block included in the flash memory; According to the cache idle rate, an idle duration threshold value matching the cache idle rate is obtained; when it is determined that the command idle duration is greater than the idle duration threshold value, and according to the mark of the target flash memory block, it is determined that the target flash memory block is not marked as a preset type, a performance indicator value of the target flash memory block is obtained, wherein the target flash memory block is any one of the at least one flash memory block; A selection module, configured to select a setting strategy corresponding to an erasure mode of the target flash memory block according to the number of performance indicator values ​​of the target flash memory block; A setting module, used for setting the erasure mode of the target flash memory block according to the setting strategy; The erasing module is used to perform a data erasing operation corresponding to the erasing mode on the target flash memory block according to the erasing mode of the target flash memory block.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data erasure method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data erasing method according to any one of claims 1 to 7.

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