Memory, memory system, and operating method of memory

Abstract

The invention discloses a memory, a memory system and an operation method of the memory, and belongs to the technical field of storage. The method comprises the following steps: receiving an erasure command which indicates to erase data stored in a storage block in a memory, reading a numerical value stored in a register, and if it is determined that configuration data of the memory is stored in the storage block based on the numerical value stored in the register, stopping executing the erasure command. According to the method and the device, whether the erasure command aims at the configuration data or not is judged according to the value stored in the determination, and the erasure command is stopped under the condition that the erasure command aims at the configuration data, so that the potential data loss risk caused by the erasure command is avoided, and the user experience is improved. And the system failure rate caused by data damage or loss can be reduced, so that the reliability and the stability of the memory can be remarkably improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a storage system, and a method of operating the memory. Background Technology

[0002] As a carrier of information, memory plays a vital role in electronic devices. Whether it is a smartphone, a personal computer, or a large server in a data center, different types of memory are needed to store the operating system, applications, and user data.

[0003] However, if the memory's configuration data is incorrectly modified or lost, the memory may experience serious consequences such as malfunction, performance degradation, or even failure to boot. Therefore, there is an urgent need for a memory operation method to improve the reliability and security of memory. Summary of the Invention

[0004] This application provides a memory, a memory system, and a method for operating the memory, which can improve the reliability and security of the memory. The technical solution is as follows:

[0005] On one hand, a memory is provided, the memory including a memory block and peripheral circuitry, the memory block being coupled to the peripheral circuitry via word lines, the peripheral circuitry including a control logic unit and registers, the control logic unit being configured to:

[0006] Receive an erase command, the erase command instructing the data stored in the storage block to be erased;

[0007] Read the value stored in the register;

[0008] If the value stored in the register determines that the memory block stores the configuration data of the memory, then the erase command is stopped.

[0009] The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

[0010] In one possible implementation, the control logic unit is further configured as follows:

[0011] If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

[0012] In one possible implementation, the control logic unit is further configured as follows:

[0013] Receive a control command that instructs the first value to be written into the register;

[0014] Write the first value into the register.

[0015] In one possible implementation, the control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

[0016] In one possible implementation, the control command includes a target character that indicates access to data in the storage block.

[0017] In one possible implementation, the characteristic is that,

[0018] The target character includes a first character that indicates access to the user configuration data in the storage block; or...

[0019] The target character includes a second character that indicates access to the system configuration data in the storage block.

[0020] In one possible implementation, the control logic unit is further configured as follows:

[0021] A second value is written to the register, indicating that the memory block is not selected.

[0022] On the other hand, a storage system is provided, the storage system including a memory and a controller coupled to the memory and configured to control the memory; the memory includes memory blocks and peripheral circuitry, the memory blocks being coupled to the peripheral circuitry via word lines, the peripheral circuitry including control logic units and registers;

[0023] The controller is configured to send an erase command to the memory, the erase command instructing the data stored in the memory block to be erased;

[0024] The control logic unit is configured to: receive an erase command from the controller; read the value stored in the register; and if it is determined based on the value stored in the register that the memory block stores the configuration data of the memory, then stop executing the erase command.

[0025] The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

[0026] In one possible implementation, the control logic unit is further configured as follows:

[0027] If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

[0028] In one possible implementation, the controller is further configured to send a control command to the memory, the control command instructing the first value to be written to the register;

[0029] The control logic unit is further configured to: receive a control command from the controller; and write the first value into the register.

[0030] In one possible implementation, the control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

[0031] In one possible implementation, the control command includes a target character that indicates access to data in the storage block.

[0032] In one possible implementation, the target character includes a first character indicating access to the user configuration data in the storage block; or...

[0033] The target character includes a second character that indicates access to the system configuration data in the storage block.

[0034] In one possible implementation, the control logic unit is further configured as follows:

[0035] A second value is written to the register, indicating that the memory block is not selected.

[0036] On the other hand, a method for operating a memory is provided, the method comprising:

[0037] Receive an erase command, the erase command instructing the erasure of data stored in a memory block;

[0038] Read the value stored in the register;

[0039] If the value stored in the register determines that the memory block stores the configuration data of the memory, then the erase command is stopped.

[0040] The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

[0041] In one possible implementation, determining that the memory block stores configuration data of the memory based on the value stored in the register includes:

[0042] If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

[0043] In one possible implementation, before receiving the erase command, the method further includes:

[0044] Receive a control command that instructs the first value to be written into the register;

[0045] Write the first value into the register.

[0046] In one possible implementation, the control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

[0047] In one possible implementation, the control command includes a target character that indicates access to data in the storage block.

[0048] In one possible implementation, the target character includes a first character indicating access to the user configuration data in the storage block; or...

[0049] The target character includes a second character that indicates access to the system configuration data in the storage block.

[0050] In one possible implementation, after stopping the execution of the erase command, the method further includes:

[0051] A second value is written to the register, indicating that the memory block is not selected.

[0052] This application, upon receiving an erase command, determines whether the erase command targets configuration data by checking the stored values. If the erase command targets configuration data, execution is stopped. This avoids the potential data loss risk caused by the erase command and reduces the system failure rate due to data corruption or loss, significantly improving the reliability and stability of the memory. Furthermore, this application determines whether the memory card storing configuration data is selected at the register level, thereby determining whether to stop the erase command. Since reading values ​​from registers is typically a fast and low-overhead operation, upon receiving an erase command, this application can quickly check the registers to determine whether to stop the command execution. This ensures rapid response and protects configuration data, reducing potential risks caused by processing delays. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application;

[0055] Figure 2 This is a schematic diagram of a storage device provided in an embodiment of this application;

[0056] Figure 3 This is a schematic diagram of another storage device provided in an embodiment of this application;

[0057] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application;

[0058] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111 provided in an embodiment of this application;

[0059] Figure 6 This is a schematic diagram of a peripheral circuit provided in an embodiment of this application;

[0060] Figure 7 This is a flowchart of a memory operation method provided in an embodiment of this application;

[0061] Figure 8 This is an operational schematic diagram of a memory provided in an embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0063] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application. For example... Figure 1 As shown, the storage system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0064] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. In one possible implementation, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0065] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0066] In some embodiments, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In such a scenario, such as... Figure 1 As shown, the storage system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0067] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0068] As an example, such as Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 400. The memory card 400 may include PCMCIA (PC) cards, CompactFlash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may also include a connector 410 for coupling the memory card 400 to the host.

[0069] As another example, such as Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 500. The solid-state drive 500 may also include a connector 510 for coupling the solid-state drive 500 to the host. The storage capacity and / or operating speed of the solid-state drive 500 is greater than that of the memory card 400.

[0070] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0071] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application. Figure 4 As shown, the memory 100 includes:

[0072] Storage array 110, which includes multiple rows of storage cells;

[0073] Multiple word lines 120 are coupled to multiple rows of memory cells;

[0074] Peripheral circuitry 130 is coupled to a plurality of word lines 120 and configured to perform operations such as programming (i.e., writing data) or reading data on a selected memory cell line among a plurality of memory cell lines, wherein the selected memory cell line is the memory cell line coupled to the selected word line, wherein, in order to perform operations such as programming or reading data, peripheral circuitry 130 is configured to perform the memory operation method provided in the embodiments of this application.

[0075] Storage array 110 can be a NAND flash memory storage array. For example... Figure 1 As shown, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 that are coupled in series and stacked vertically.

[0076] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 113 and the drain select gate 114 can be configured to activate the selected memory string 111 during read and program operations.

[0077] In some embodiments, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read from or written to the bit line 115 via an output bus (not shown).

[0078] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0079] like Figure 4 As shown, the storage string 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (SL) 118. The sources of all storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called the common source line or array common source (ACS).

[0080] The source line 118 can be used for grounding, so that the sources of each memory cell in the memory string of block 140 can be grounded in some subsequent operations. In one possible implementation, in some other operations, the sources of each memory cell in the memory string of block 140 can also be connected to a high voltage via the source line 118.

[0081] Each block 140 is the basic data unit used for the erase operation, meaning that all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0082] like Figure 4 As shown, the same layer of storage cells 112 of adjacent storage strings 111 in the same block 140 can be coupled through word lines 120. Word lines 120 are used to select which layer of storage cells 112 in the block 140 is affected by read and program operations.

[0083] In some embodiments, each word line 120 is coupled to a page 150 to which the memory cell 112 belongs, and the page 150 is a basic data unit for programming operations. The size of the page 150 may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page 150. It is understood that a memory cell row consists of multiple memory cells 112 located on the same page 150.

[0084] It should be noted that within a block of 140, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple to one or more pages. For example, for SLC, a word line couples to one page, and for MLC, a word line couples to two pages.

[0085] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111, provided in an embodiment of this application. Figure 5 As shown, the storage string 111 may extend vertically over the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0086] The stacked layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stacked layer 102 can determine the number of memory cells 112 in the memory array 110.

[0087] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Furthermore, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the stacked layer 102 as a DSG line 116, at the bottom of the stacked layer 102 as an SSG line 117, or between the DSG line 116 and the SSG line 117 as a word line 120.

[0088] like Figure 5 As shown, the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer.

[0089] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a pillar shape). The layers in the semiconductor channel and the memory film are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order.

[0090] It should be understood that, despite Figure 5 As not shown, the memory array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0091] Return to reference Figure 4 The peripheral circuitry 130 can be coupled to the memory array 110 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 112 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116.

[0092] Peripheral circuitry 130 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry 130 is shown, including a page buffer / sensor amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0093] Page buffer / sensor amplifier 131 can be configured to read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic unit 135. For example, page buffer / sensor amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of memory array 110. Page buffer / sensor amplifier 131 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 112 coupled to selected word line 120. Page buffer / sensor amplifier 131 can also sense a low-power signal from bit line 115, which represents a data bit stored in memory cell 112, and amplify a small voltage swing to a recognizable logic level during read operations.

[0094] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and to select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0095] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and to select / deselect block 140 of the memory array 110 and to select / deselect word lines 120 of block 140. The row decoder / word line driver 133 can also be configured to drive word lines 120 using word line voltages (VWL) generated from a voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive SSG lines 117 and DSG lines 116. As described in detail below, the row decoder / word line driver 133 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines 120.

[0096] Voltage generator 134 can be configured to be controlled by control logic unit 135 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.

[0097] The control logic unit 135 can be coupled to various circuits in the peripheral circuitry described above and is configured to control the operation of each circuit. In some embodiments, the control logic unit is also configured to execute the memory operation method provided in the embodiments of this application.

[0098] Register 136 may be coupled to control logic unit 135. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in the peripheral circuitry. In some embodiments, the register is also used to store status information of a target memory block, which is a memory block storing configuration data, indicating whether the target memory block is selected.

[0099] Interface (I / F) 137 can be coupled to control logic unit 135 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 135, as well as to buffer status information received from control logic unit 135 and relay it to the host. Interface 137 can also be coupled to column decoder / bit line driver 132 via data bus 138 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0100] The above description of the memory-related hardware embodiments has similar beneficial effects to the method embodiments described below. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0101] In the above Figures 1 to 6In this embodiment, the memory cell 112 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. This application does not limit the specific type of memory cell.

[0102] The operation method of the memory provided in the embodiments of this application will be explained in detail below.

[0103] Figure 7 This is a flowchart of a memory operation method provided in an embodiment of this application, which is applied to... Figure 6 The control logic unit in the peripheral circuitry of the memory shown. Please refer to... Figure 7 The method includes the following steps.

[0104] Step 701: Receive an erase command, which instructs the data stored in the memory block to be erased.

[0105] In some embodiments, if a technician wants to erase the data stored in a memory block, he can trigger an erase command. In this case, the control logic unit can receive the erase command.

[0106] The erase command can be a command that conforms to the Open NAND Flash Interface (ONFI) or Joint Electron Device Engineering Council (JEDEC) protocol standard, and this application embodiment does not limit it.

[0107] In some embodiments, before receiving an erase command, the control logic unit may also receive a control command that instructs the first value to be written to a register.

[0108] The register can be one of the above. Figure 6 The registers in the peripheral circuitry of the memory shown.

[0109] The specific content of control commands includes various types, and two of them will be introduced below.

[0110] The first type of control command includes a register identifier and a value indication information. The register identifier indicates the register, and the value indication information indicates the first value.

[0111] For example, the register identifier could be reg_specialblk, and its first value could be 1. In this case, the control command could be reg_specialblk = 1.

[0112] It should be noted that the value in the register describes whether the storage block containing configuration data is selected. If the storage block is selected, it indicates that write, read, or erase operations may be performed on that storage block subsequently. Configuration data includes user configuration data and / or system configuration data. User configuration data represents the attribute information of the memory, while system configuration data represents the configuration information of the memory. For example, system configuration data typically includes startup parameters, security settings, etc., but this embodiment does not limit the scope of the application.

[0113] In some embodiments, if the value in the register is a first value, it indicates that the storage block containing configuration data is selected. In other embodiments, the numerical indication information may also indicate a second value, which is different from the first value. If the value in the register is the second value, it indicates that the storage block containing configuration data is not selected.

[0114] Before receiving a control command, the control logic unit can also receive a first test command, which instructs the control logic unit to enter test mode 1.

[0115] In the embodiments of this application, there are restrictions on the input order of instructions (e.g., the input order of instructions can be test command, control command, and erase command). In this way, accidental touches of sensitive operations (such as erase operation) can be limited, which helps to prevent accidental or unauthorized changes.

[0116] The second type involves control commands that include target characters, which indicate access to data in the storage block.

[0117] In one possible implementation, the target character includes a first character that indicates access to user configuration data in the storage block.

[0118] For example, the first character can be a hexadecimal number, such as BA.

[0119] Before receiving a control command, the control logic unit can also receive a second test command, which instructs the control logic unit to enter test mode 2.

[0120] In another possible implementation, the target character includes a second character that indicates access to system configuration data in the storage block.

[0121] For example, the first character can be a hexadecimal number, such as B5.

[0122] Before receiving control commands, the control logic unit can also receive a third test command. The second test command instructs the control logic unit to enter test mode 3.

[0123] Step 702: Read the value stored in the register.

[0124] Step 703: If the value stored in the register indicates that the memory block contains memory configuration data, then stop executing the erase command.

[0125] If the value stored in the register is the first value, it is determined that the storage block contains configuration data, and the first value indicates that the storage block is selected.

[0126] In some embodiments, the erase command may be a command conforming to the ONFI or JEDEC protocol standard. In such cases, in practical applications, erase commands conforming to the ONFI or JEDEC protocol standard typically require specifying the address of the storage block or region to be erased. In certain special cases, such as global erase commands or when the device supports a specific erase mode, it may not be necessary to specify a specific address. Whether the address is received or ignored is related to the specific product definition, and this application embodiment does not limit this. However, regardless of whether the address is received or ignored, this application embodiment does not execute the erase command.

[0127] In one possible implementation, after stopping the execution of the erase command, the control logic unit can also issue an error message to indicate that the erase command is at risk.

[0128] In some embodiments, if the value stored in the register is a first value, it is determined that the memory block does not store configuration data. In this case, an erase command can be executed.

[0129] In one possible implementation, after stopping the erase command, the control logic unit can also write a second value to the register, which indicates that the memory block has not been selected.

[0130] The operation method of the memory provided in the embodiments of this application will be described again next.

[0131] Please refer to Figure 8 , Figure 8 This is a schematic diagram of memory operation provided in an embodiment of this application. Since accessing configuration data or selecting the memory block corresponding to the configuration data causes a change in the value in the register, and the changed value indicates that the memory block corresponding to the configuration data has been selected, this embodiment of the application, upon receiving an erase command, can determine whether the erase command is for configuration data by checking the value stored in the memory. If it is determined that the erase command is for configuration data, the execution of the erase command is stopped. In other words, this embodiment of the application can accurately identify the erase command and promptly terminate its execution, whether accessing the memory block corresponding to user configuration data, accessing the memory block corresponding to system configuration data, or accessing the memory block corresponding to configuration data by selecting its address.

[0132] Since the loss of configuration data can lead to complex recovery processes and even cause memory malfunction, this embodiment of the application, upon receiving an erase command, determines whether the erase command is for configuration data by checking the stored values. If the erase command is indeed for configuration data, execution is stopped. This avoids the potential risk of data loss due to the erase command and reduces the system failure rate caused by data corruption or loss, thus significantly improving the reliability and stability of the memory. Furthermore, this embodiment determines whether the memory card storing configuration data is selected at the register level, thereby determining whether to stop the erase command. Since reading values ​​from registers is typically a fast and low-overhead operation, this embodiment can quickly check registers upon receiving an erase command to determine whether execution should be stopped. This ensures that the control logic unit responds quickly and protects the configuration data, reducing potential risks caused by processing delays. Furthermore, as part of a hardware component, registers typically possess high reliability and stability (for example, the data in registers is usually not easily altered by software errors or external interference). Therefore, the data in registers has high credibility, providing an accurate basis for subsequent judgments on whether to stop executing the erase command.

[0133] based on Figure 7 As illustrated in the embodiments shown, this application also provides a memory. The memory includes a memory block and peripheral circuitry. The memory block is coupled to the peripheral circuitry via word lines. The peripheral circuitry includes a control logic unit and registers. The control logic unit is configured to implement the operation method of the memory provided in this application.

[0134] Specifically, the control logic unit is configured to: receive an erase command, the erase command instructing the data stored in the memory block to be erased; read the value stored in the register; if it is determined based on the value stored in the register that the memory block stores configuration data of the memory, then stop executing the erase command; wherein, the configuration data includes user configuration data or system configuration data, the user configuration data representing the attribute information of the memory, and the system configuration data representing the configuration information of the memory.

[0135] For details on the implementation of the functions of the aforementioned control logic unit, please refer to [link / reference]. Figure 7 The embodiments shown will not be described in detail here.

[0136] Additionally, embodiments of this application also provide a storage system including a memory and a controller coupled to the memory and configured to control the memory. The memory includes memory blocks and peripheral circuitry, the memory blocks being coupled to the peripheral circuitry via word lines, the peripheral circuitry including control logic units and registers.

[0137] The controller is configured to send an erase command to the memory, the erase command instructing the data stored in the memory block to be erased.

[0138] The control logic unit is configured to: receive an erase command from the controller; read the value stored in the register; and if, based on the value stored in the register, it is determined that the memory block stores configuration data of the memory, then stop executing the erase command. The configuration data includes user configuration data or system configuration data, where the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory. Detailed implementation processes are described in the corresponding contents of the above embodiments and will not be repeated here.

[0139] In addition, embodiments of this application also provide a peripheral circuit, wherein the control logic unit of the peripheral circuit includes at least one software module, which is used to implement... Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0140] In addition, embodiments of this application also provide a computer storage medium on which instructions are stored, which are executed by a control logic unit in a memory. Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0141] On the other hand, a computer program product containing instructions is provided, which is implemented when the instructions are executed in the control logic unit. Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0142] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0143] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes memory blocks and peripheral circuitry. The memory blocks are coupled to the peripheral circuitry via word lines. The peripheral circuitry includes a control logic unit and registers. The control logic unit is configured to: Receive an erase command, the erase command instructing the data stored in the storage block to be erased; Read the value stored in the register; If the value stored in the register determines that the memory block stores the configuration data of the memory, then the erase command is stopped. The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

2. The memory as claimed in claim 1, characterized in that, The control logic unit is further configured to: If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

3. The memory as described in claim 2, characterized in that, The control logic unit is further configured to: Receive a control command that instructs the first value to be written into the register; Write the first value into the register.

4. The memory as described in claim 3, characterized in that, The control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

5. The memory as described in claim 3, characterized in that, The control command includes a target character that indicates access to data in the storage block.

6. The memory as claimed in claim 5, characterized in that, The target character includes a first character that indicates access to the user configuration data in the storage block; or... The target character includes a second character that indicates access to the system configuration data in the storage block.

7. The memory as claimed in claim 3, characterized in that, The control logic unit is further configured to: A second value is written to the register, indicating that the memory block is not selected.

8. A storage system, characterized in that, The storage system includes a memory and a controller coupled to the memory and configured to control the memory; the memory includes memory blocks and peripheral circuitry, the memory blocks being coupled to the peripheral circuitry via word lines, the peripheral circuitry including control logic units and registers; The controller is configured to send an erase command to the memory, the erase command instructing the data stored in the memory block to be erased; The control logic unit is configured to receive an erase command from the controller; Read the value stored in the register; if it is determined from the value stored in the register that the memory block stores the configuration data of the memory, then stop executing the erase command; The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

9. The storage system as described in claim 8, characterized in that, The control logic unit is further configured to: If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

10. The storage system as claimed in claim 9, characterized in that, The controller is also configured to send a control command to the memory, the control command instructing the first value to be written to the register; The control logic unit is further configured to: receive a control command from the controller; and write the first value into the register.

11. The storage system as claimed in claim 10, characterized in that, The control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

12. The storage system as claimed in claim 10, characterized in that, The control command includes a target character that indicates access to data in the storage block.

13. The storage system as claimed in claim 12, characterized in that, The target character includes a first character that indicates access to the user configuration data in the storage block; or... The target character includes a second character that indicates access to the system configuration data in the storage block.

14. The storage system as claimed in claim 10, characterized in that, The control logic unit is further configured to: A second value is written to the register, indicating that the memory block is not selected.

15. A method for operating a memory, characterized in that, The method includes: Receive an erase command, the erase command instructing the erasure of data stored in a memory block; Read the value stored in the register; If the value stored in the register determines that the memory block stores the configuration data of the memory, then the erase command is stopped. The configuration data includes user configuration data or system configuration data, wherein the user configuration data represents the attribute information of the memory, and the system configuration data represents the configuration information of the memory.

16. The method as described in claim 15, characterized in that, The step of determining that the memory block stores configuration data of the memory based on the value stored in the register includes: If the value stored in the register is a first value, it is determined that the storage block stores the configuration data, and the first value indicates that the storage block is selected.

17. The method as described in claim 16, characterized in that, Before receiving the erase command, the method further includes: Receive a control command that instructs the first value to be written into the register; Write the first value into the register.

18. The method as described in claim 17, characterized in that, The control command includes a register identifier and a value indication information, wherein the register identifier indicates the register and the value indication information indicates the first value.

19. The method as described in claim 17, characterized in that, The control command includes a target character that indicates access to data in the storage block.

20. The method as described in claim 19, characterized in that, The target character includes a first character that indicates access to the user configuration data in the storage block; or... The target character includes a second character that indicates access to the system configuration data in the storage block.

21. The method of claim 17, characterized in that, After stopping the execution of the erase command, the method further includes: A second value is written to the register, indicating that the memory block is not selected.

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