On-chip network interface automatic matching method and system based on hierarchical tag driving

Abstract

The present invention is applicable to the field of chip technology and provides a method and system for automatically matching network-on-chip interfaces based on hierarchical tagging. The method comprises: extracting module definitions, port lists, and interface signal information from module Verilog files; hierarchically tagging interface signals based on naming rules; defining connection rules; executing an automatic matching algorithm based on the tag information to determine the connection relationship between signals; generating complete top-level Verilog code based on the matching results; and providing a visual interactive interface, a hierarchical tree view to display interface status, and support for filtering, grouping, and highlighting. Specifically targeting large, complex chip designs centered around NoCs, the present invention achieves efficient and accurate automatic signal connection by systematically parsing the structural information contained in signal naming rules. Furthermore, a hierarchical visual interface is provided to help users quickly locate and resolve connection issues.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and in particular relates to a method and system for automatically matching an on-chip network interface based on hierarchical tag driving. Background Art

[0002] As the scale and complexity of integrated circuit designs continue to grow exponentially, the number of functional modules and interface signals included in modern chip designs has reached unprecedented levels. In large-scale system-on-chip (SoC) designs, Network-on-Chip (NoC) is widely used to construct the chip's top-level topology. All agent modules communicate through the NoC, resulting in a top-level architecture that often contains a large number of module instantiations. These interfaces are large and complex, exhibiting distinct hierarchical characteristics, and typically utilize standard bus interfaces that account for over 95%. Existing tools lack specialized optimization mechanisms for this type of architecture.

[0003] Currently, during the design process, design engineers often need to manually write thousands of interconnected signal lines, and the top-level topology may need to undergo hundreds of iterative modifications. Manual connection work not only consumes a lot of engineering time, but is also very prone to errors, affecting design reliability.

[0004] While existing automatic wiring technologies attempt to automate the generation of top-level files by manually writing configuration files or templates to define module hierarchies and interface information, reducing manual intervention, when the number of modules exceeds 100 or the complexity of interfaces increases, the cost of maintaining configuration files increases exponentially. Manual synchronization of module names, port names, and parameters requires time-consuming and prone to typos and parameter omissions, resulting in inefficient design iterations.

[0005] Furthermore, matching mechanisms based on generic interface names or keywords cannot handle the signal-level matching requirements of complex bus protocols such as AXI (Advanced Xtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus). Signals with the same name in multiple modules may be incorrectly connected due to differences in bit width or protocol type. Existing technologies lack protocol awareness, leading to signal timing errors that require manual secondary debugging. While some tools allow users to customize connection relationships, they lack intelligent conflict detection mechanisms. Manual modifications can disrupt implicit dependencies between modules, and they cannot automatically verify bit width matching or direction consistency, leading to functional anomalies after synthesis.

[0006] The visual interface design also has defects. When the module interface exceeds 100 levels, the signal group is not effectively folded or the status is not marked. Users need to manually expand a large number of signals. The key connection status is difficult to quickly identify, and the debugging efficiency drops sharply.

[0007] The protocol version adaptation limitations of naming rules further exacerbate maintenance difficulties. When modules need to support multiple protocols or protocol upgrades, naming conflicts require modifications to all related modules, leading to frequent compatibility issues. The systematic lack of verification mechanisms further hinders the discovery of potential issues such as bit width mismatches and clock domain asynchrony until the synthesis or simulation stages, making manual line-by-line troubleshooting time-consuming and labor-intensive. The fundamental contradiction lies in the over-reliance of existing technologies on manual input and universal matching rules, which fail to address the imbalance between automation and design complexity in large-scale chip design. Furthermore, they lack protocol-aware intelligent matching, dynamic priority management, and deep verification capabilities.

[0008] Therefore, in general, the existing on-chip network interface matching method has problems such as low interface matching efficiency, high complexity of on-chip network architecture connection, inability to uniformly handle diverse standard interfaces, insufficient visualization of interface connection status, and difficulty in coordinating user-defined rules with automatic matching. Summary of the Invention

[0009] In view of the above problems, the purpose of the present invention is to provide a method and system for automatic matching of on-chip network interfaces based on hierarchical tag driving, aiming to solve the above technical problems.

[0010] The present invention adopts the following technical solutions:

[0011] On the one hand, the method for automatically matching network-on-chip interfaces based on hierarchical tag driving comprises the following steps:

[0012] Step S1: Read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and Agent module files and all interface signals through syntax parsing;

[0013] Step S2: hierarchically label the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all label information into a hierarchical structure;

[0014] Step S3: If the user provides a custom configuration file, obtain the custom connection relationship between the interfaces according to the configuration file;

[0015] Step S4: Automatically match interfaces using a multi-dimensional interface matching algorithm based on the tag information to obtain automatically matched connection relationships between interfaces, wherein the priority of the customized connection relationship is higher than the priority of the automatically matched connection relationship; finally, the customized connection relationship and the automatically matched connection relationship are merged to form a complete connection relationship table;

[0016] Step S5: Generate a complete top-level Verilog code according to the connection relationship table.

[0017] Furthermore, the method further comprises the following steps:

[0018] Step S6: Display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to the operation instructions.

[0019] On the other hand, the hierarchical tag-driven on-chip network interface automatic matching system includes:

[0020] The parsing unit is used to read the NoC module file and the Agent module file respectively, and extract the definition of the NoC module and Agent module files and all interface signals through syntax parsing;

[0021] A hierarchical labeling unit is used to label NoC module interface signals and Agent module interface signals in a hierarchical manner according to naming rules, and organize all labeling information into a hierarchical structure;

[0022] A user-defined processing unit is used to obtain the customized connection relationship between interfaces according to a customized configuration file if the user provides the configuration file;

[0023] An automatic matching unit is used to automatically match interfaces using a multi-dimensional interface matching algorithm according to the tag information to obtain automatic matching connection relationships between interfaces, where the priority of custom connection relationships is higher than that of automatic matching connection relationships; finally, the custom connection relationships and automatic matching connection relationships are merged to form a complete connection relationship table;

[0024] The integrated generation unit is used to generate complete top-level Verilog code based on the connection relationship table.

[0025] Furthermore, the system further comprises:

[0026] GUI unit, used to display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to the operation instructions

[0027] The beneficial effects of the present invention are as follows: the present invention provides an automatic matching method and system for on-chip network interfaces based on hierarchical tag driving. The technical solution of the present invention is specifically aimed at large-scale complex chip designs centered on NoC. By systematically parsing the structural information contained in the signal naming rules, efficient and accurate automatic signal connection is achieved, and a hierarchical visual interface is provided to help users quickly locate and solve connection problems.

[0028] Specifically: First, the present invention proposes a multi-dimensional interface matching algorithm based on the characteristics of the NoC architecture, which significantly improves the connection accuracy through standardized naming rules and a hierarchical tag structure; secondly, it designs flexible user-defined connection rules and establishes a clear priority mechanism to ensure the coordinated work of automatic matching and custom-specified connections; at the same time, it constructs a hierarchical visual expression, which intuitively displays the connection status from module to signal in a multi-level folding form, and distinguishes success / partial success / failure status through color marking; in addition, it also develops a multi-mode operation engine that supports command line and graphical interface, and adapts to the needs of different development environments through unified back-end processing logic.

[0029] The technology of the present invention breaks through the universal limitations of traditional automatic wiring tools and provides a professional solution based on the characteristics of NoC architecture, effectively solving core problems such as low interface matching efficiency, high error rate, and difficult debugging in complex chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Flowchart of a method for automatically matching network-on-chip interfaces based on hierarchical tag driving provided by a first embodiment of the present invention;

[0031] Figure 2 It is a specific flow chart of step S2;

[0032] Figure 3 It is a specific flow chart of step S3;

[0033] Figure 4 is a specific flow chart of step S4;

[0034] Figure 5 It is a specific flow chart of step S5;

[0035] Figure 6 This is a sample diagram showing the interface.

[0036] Figure 7 This is a principle block diagram of an on-chip network interface automatic matching system based on hierarchical tag driving provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] The present invention provides a hierarchical tag-driven automatic matching method and system for on-chip network interfaces. This method fully leverages the interconnectivity of modern chips centered around the NoC (Network Control Module) (NC) and automatically analyzes NoC module interfaces, extracts hierarchical tags, identifies the standard interface connection relationships between the NoC and all Agent modules, and automatically establishes matching connections. Traditional interface matching methods typically rely on user-defined connection relationship files, failing to consider the specific requirements of modern chip designs. In contrast, the present invention utilizes the characteristics of the NoC, eliminating the need for user pre-definition and requiring only code file input to automatically connect all standard interfaces. Furthermore, users can access the connected top-level files without any intervention. Using a graphical interface optimized for the NoC's characteristics, users can quickly identify unconnected non-standard interface signals among thousands of connections. The present invention also incorporates a user-defined connection function. When unconnected non-standard interface signals exist, the system supports importing user-defined connection configurations to automatically connect the remaining non-standard signals. To illustrate the technical solution of the present invention, a specific embodiment will be provided below.

[0039] Example 1:

[0040] like Figure 1 As shown, this embodiment provides an on-chip network interface automatic matching method based on hierarchical tag driving, including the following steps:

[0041] Step S1: Read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and the Agent module files and all interface signals through syntax parsing.

[0042] First, you need to input the Verilog files for all modules you want to connect, including the NoC module file and the Agent module file, or specify a directory containing these files. You can specify the input files or directory using command-line parameters or a graphical interface. A Verilog parser is then used to read and parse all input files, extracting key information.

[0043] First, the NoC module's Verilog file is read. Through syntax parsing, the NoC module definition and all port signals are extracted, including signal name, direction (input / output), and bit width. Similarly to the NoC module, the Verilog files of each Agent module are read and all interface signals are extracted.

[0044] Step S2: hierarchically label the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all label information into a hierarchical structure.

[0045] In this step, hierarchical marking is applied to the extracted interface signals, standard interfaces are identified and marked, and all interface signals are marked and classified. Figure 2 As shown, the specific process of hierarchical labeling is as follows:

[0046] S21 . For each interface signal of the NoC module, identify the standard interface type to which the interface signal belongs by analyzing keywords and structural features in the signal name.

[0047] For NoC modules, this step identifies each interface signal by naming it, identifying its standard interface type. Interface signal naming follows specific rules. This embodiment specifically analyzes keywords and structural features in the signal name to determine the standard interface type to which the signal belongs, such as ACE (AXI Coherency Extensions), AXI (Advanced Xtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus). ACE, AXI, AHB, and APB are all on-chip bus protocols introduced by ARM, used to enable high-speed data transmission and communication between different modules within the chip.

[0048] S22. Extract the target module name and interface serial number of the target Agent module contained in the signal name, and extract the channel and specific signal type to which the interface signal belongs.

[0049] For example, extracting "ddrc" from "ddrc_0_aw_ready" as the target module name indicates that the signal needs to be connected to the DDR controller module. Extracting "0" from "ddrc_0_aw_ready" as the interface number indicates that this is the first group of interfaces.

[0050] For example, for the AXI interface, extract channel information (such as the AXI interface has five independent channels, namely read address channel, read data channel, write address channel, write data channel and write response channel) and signal type (such as valid signal VALID, ready signal READY, data signal DATA, etc., VALID and READY signals together constitute the handshake signal, which is used for synchronization and coordination between master and slave devices to ensure the accuracy and stability of data transmission).

[0051] For interfaces such as AHB and APB, the corresponding signal types are also extracted.

[0052] S23. Create a multi-level tag for each interface signal, including interface type, target module name, interface serial number, channel and signal type.

[0053] Here, based on the information extracted in the previous steps, a tag containing multiple dimensions such as target module name, interface type, interface serial number, channel, and signal type is created for each signal.

[0054] S24. For each interface signal of the Agent module, identify the standard interface type to which the interface signal belongs, extract the interface serial number contained in the signal name, and create a corresponding multi-level tag including the interface type and the interface serial number.

[0055] Similarly, the interface signals of the Agent module are identified using similar naming rules. Unlike NoC modules, the signal naming of the Agent module typically does not include the target module name, but instead focuses on the interface number and interface type. A corresponding multi-level tag is then created for each interface signal of the Agent module.

[0056] S25. Integrate and organize all tag information of the NoC module and the Agent module into a tree-like hierarchical structure.

[0057] This step integrates all the tag information of the NoC module and the Agent module and organizes them into a tree-like hierarchical structure to facilitate subsequent matching operations.

[0058] Step S3: If the user provides a custom configuration file, the custom connection relationship between interfaces is obtained according to the configuration file.

[0059] This step involves custom matching, primarily for intervening in non-standard signal connections that aren't automatically matched. If you provide a custom connection profile, the rules in that profile are applied, giving priority to the user-specified connection rules. Custom matching takes precedence over automatic matching.

[0060] like Figure 3 As shown, the specific process of step S3 is as follows:

[0061] S31. Parse the user-provided custom configuration file and extract each connection rule therefrom, including source module, source signal, target module, and target signal.

[0062] For example, it can read the Excel spreadsheet or other configuration files provided by the user, obtain the user-defined connection relationship, and then extract each connection rule from the configuration file, including source module, source signal, target module, target signal and other information.

[0063] S32. Convert the extracted connection rules into custom connection relationships that are compatible with the automatic matching connection relationship.

[0064] This step converts the connection rules extracted into an internal representation that is compatible with automatic matching. It should be noted that before carrying out the automatic matching algorithm, these custom connections are first applied, and the user-defined connection rules are prioritized to ensure that these connections are set up by the user's intention. Moreover, the interface signals that have been connected by the custom rules are marked to avoid subsequent automatic matching process from having an impact on them. When carrying out automatic matching, the interface signal will be checked to see if it has been connected by the custom rules. If so, the signal is skipped.

[0065] Step S4: Automatically match interfaces using a multi-dimensional interface matching algorithm according to the tag information to obtain automatic matching connection relationships between interfaces, wherein the priority of the custom connection relationship is higher than the priority of the automatic matching connection relationship; finally, merge the custom connection relationship and the automatic matching connection relationship to form a complete connection relationship table.

[0066] Based on the above hierarchical tags, this step uses a multi-dimensional interface matching algorithm for automatic matching, comprehensively considering information from multiple dimensions such as module name, interface type, and interface serial number, to achieve high-precision interface matching, such as Figure 4 The specific process is as follows:

[0067] S41 , grouping all tag information of the NoC modules according to the target module names to obtain target module groups.

[0068] S42. For each target module group, further group them according to interface type and interface serial number.

[0069] S43. For each target module group, search for a module with the same name as the target module in the parsed Agent modules, and select the corresponding interface type and interface serial number.

[0070] The automatic matching process described above first groups all NoC module tags by target module name, facilitating subsequent matching for specific modules. Within each target module group, signals are further subdivided by interface type and interface number to form more refined groupings. The agent then searches for modules with the same name and selects the matching interface type and interface number.

[0071] S44, perform a preliminary bidirectional signal match between the NoC module interface signal and the Agent module signal, then perform an accurate match based on the signal's function in the interface, and finally verify whether the bit widths of the signals on both sides of the match are consistent. If they are inconsistent, mark them as potential problems.

[0072] Finally, the interface signals in the selected NoC interface group and the Agent interface group are matched. A preliminary match is performed based on the signal direction (NoC module input corresponds to Agent module output, and vice versa). Then, a precise match is performed based on the interface signal's function within the interface. Finally, the bit widths of the matched signals are verified to be consistent. Any inconsistency is flagged as a potential issue.

[0073] S45 , establishing a connection relationship for the successfully matched interface signal pair and updating the connection status, that is, automatically matching the connection relationship, and recording the unsuccessfully matched signals for subsequent processing or reminder.

[0074] Each pair of successfully matched signals is recorded and their connection status is updated to prepare for subsequent code generation. For signals that fail to find a match, they are recorded and displayed in the graphical interface for further processing by the user.

[0075] It should be noted that the priority of the custom connection relationship is higher than that of the automatic matching connection relationship. The custom connection relationship of the custom connection rule is processed first, and the signal of the custom connection relationship is marked. During automatic matching, the signal of the marked custom connection relationship is skipped.

[0076] Therefore, this automatic matching method combines multiple dimensions (module name, interface type, interface serial number, signal function, etc.) for comprehensive judgment rather than simple string matching, which greatly improves the matching accuracy.

[0077] S46. Merge the custom connection relationship and the automatically matched connection relationship to generate a final complete connection relationship table.

[0078] Finally, the custom connection relationships and automatically matched connection relationships are merged to form a complete connection relationship table, preparing for subsequent code generation. Therefore, through this mechanism, designers can flexibly handle special cases, such as non-standard named signals, interfaces that require special processing, or connection methods that differ from automatic matching.

[0079] Step S5: Generate a complete top-level Verilog code according to the connection relationship table.

[0080] Based on the connection relationship determined above, this step can automatically generate a complete top-level Verilog code, including module instantiation, signal declaration and connection statements. Figure 5 As shown, the specific process of step S5 is as follows:

[0081] S51. Generate top-level module declaration: Create a Verilog code skeleton for the top-level module, including the module name and all required input and output interfaces.

[0082] S52. Generate internal wire declarations: Generate wire declarations of the appropriate width for each matching signal pair, and handle unconnected signals according to preset settings, such as leaving them floating or connecting them to their default values. In Verilog, wire types are generally used to connect signals in combinational logic circuits, such as between modules and for inputs and outputs at the gate level.

[0083] S53. Generate instantiation code for the NoC module: Create instantiation statements for the NoC module, including the module name, instance name, and mapping relationships from all interfaces to wires.

[0084] S54. Generate instantiation code for each Agent module: Create an instantiation statement for each Agent module, which also includes the module name, instance name, and mapping relationships between all interfaces and wires.

[0085] S55. Write the generated complete top-level Verilog code into a specified output file.

[0086] The code generated using this method is well-readable and well-structured, making it easy to adjust or modify later. Clear annotations and default handling methods are provided for unsuccessful signal connections, preventing potential design issues. A graphical interface displays connection results for easy verification and debugging. Users can adjust configurations or manually modify connections based on verification results. The finalized top-level code is output to a specified file, completing the automatic wiring process.

[0087] Step S6: Display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to the operation instructions.

[0088] In order to help designers intuitively view and verify the connection results, the steps of this embodiment provide a hierarchical folding visualization interface.

[0089] like Figure 6 An example interface is shown. The left side of the interface displays the NoC module interface tree, organized hierarchically by target module name, interface type, and interface number, making it easy for users to quickly locate specific interfaces. The right side of the interface displays the agent module interface tree, allowing users to select a single or multiple agent modules for easy comparison and analysis. Connection status statistics are displayed for each node, such as "10 / 12 signals connected," allowing users to easily understand the connection completion rate.

[0090] Connection status is color-coded, with green indicating full connection success, yellow indicating partial connection success, and red indicating complete connection failure. Node expansion / collapse support allows users to expand or collapse any node, facilitating quick navigation between different hierarchies, making it particularly suitable for handling the numerous signals in large designs. A global filtering function is also provided, allowing users to display only unconnected signals, allowing for quick identification of problem areas. Filtering by module name, interface type, and other criteria is also available, helping users focus on specific modules or interfaces.

[0091] This visual design greatly simplifies the connection verification process, enabling designers to quickly identify connection issues and improve debugging efficiency. The entire process supports both command-line and graphical user interface modes to accommodate different usage scenarios and user preferences. The command-line mode is suitable for integration into automated scripts, while the graphical user interface mode provides more intuitive operation and feedback, making it particularly suitable for interactive design and debugging.

[0092] The method of the embodiment of the present invention realizes a complete process from inputting a Verilog file to generating a top-level wiring code, and solves the top-level wiring problem in the design of a large-scale system chip.

[0093] Example 2:

[0094] This embodiment provides an on-chip network interface automatic matching system based on hierarchical tag driving, such as Figure 7 As shown, the system includes:

[0095] The parsing unit 100 is used to read the NoC module file and the Agent module file respectively, and extract the definition of the NoC module and the Agent module file and all interface signals through syntax parsing;

[0096] The hierarchical marking unit 200 is used to hierarchically mark the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all the marking information into a hierarchical structure;

[0097] The user-defined processing unit 300 is configured to obtain a customized connection relationship between interfaces according to a customized configuration file provided by the user;

[0098] Automatic matching unit 400 is configured to automatically match interfaces using a multi-dimensional interface matching algorithm according to the tag information to obtain automatically matched connection relationships between interfaces, wherein a custom connection relationship has a higher priority than an automatically matched connection relationship; and finally, the custom connection relationship and the automatically matched connection relationship are merged to form a complete connection relationship table.

[0099] The integrated generation unit 500 is used to generate a complete top-level Verilog code according to the connection relationship table.

[0100] Furthermore, the system further comprises:

[0101] The GUI unit 600 is used to display the interface status in a hierarchical, foldable, and visual tree view, and to filter, group, or highlight according to operation instructions.

[0102] Each functional unit in this embodiment implements steps S1-S6 in the first embodiment. The responsibilities of each functional unit are clear and the interaction relationship is clear. The parsing unit is responsible for extracting module definitions, port lists and interface signal information from the Verilog file; the hierarchical labeling unit block implements hierarchical labeling of interface signals based on naming rules; the user-defined processing unit manages custom connection rules; the automatic matching unit executes the automatic matching algorithm according to the label information to determine the connection relationship between signals; the integrated generation unit generates a complete top-level Verilog code based on the matching results; the GUI unit provides a visual interactive interface, a hierarchical tree view to display the interface status, and supports filtering, grouping and highlighting. These functional units work together to realize the complete process from inputting the Verilog file to generating the top-level connection code.

[0103] The functional units in this embodiment adopt a modular design, which provides excellent scalability and maintainability while maintaining core functionality. Each unit interacts through clearly defined interfaces, making it easy to add new features or support new interface types. For example, the system can be expanded to support a wider range of standard bus protocols or add more complex matching algorithms to handle special cases.

[0104] On the one hand, the present invention does not require additional user input. It utilizes the NoC structured naming rule system to extract and match the multi-dimensional hierarchical tags of "module name + interface type + interface serial number" to identify the target Agent module, interface type and interface serial number to which each interface signal is to be connected, thereby achieving targeted and efficient matching of full-system interfaces based on the NoC architecture. Compared with traditional interface identification and matching methods, the present invention is more in line with the actual needs of large-scale chip design and is more targeted. It theoretically breaks through the limitations of traditional general matching methods and significantly improves matching accuracy and processing efficiency.

[0105] Furthermore, the present invention not only designs an efficient automatic matching algorithm based on practical applications to automatically connect standard interface types, but also introduces a user-defined rule priority mechanism. By building a complete user-defined rule system, users can define specific connection relationships through external configuration files and implement a priority-based rule application strategy during the automatic matching process, effectively addressing special connection requirements and handling exceptions.

[0106] In summary, the technical solution of this invention is applicable to all chip designs based on NoC interconnection. Without user intervention, it can automatically match and connect standard interface signals, completing more than 95% of the top-level signal connections. Users only need to intervene in the remaining 5% of non-standard signal connections to complete the top-level file, which will greatly reduce the user's workload and improve the efficiency of chip design iterations.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for automatically matching network-on-chip interfaces based on hierarchical tag driving, characterized in that: The method comprises the following steps: Step S1: Read the NoC module file and the Agent module file respectively, and extract the definitions of the NoC module and Agent module files and all interface signals through syntax parsing; Step S2: hierarchically label the NoC module interface signals and the Agent module interface signals according to the naming rules, and organize all label information into a hierarchical structure; Step S3: If the user provides a custom configuration file, obtain the custom connection relationship between the interfaces according to the configuration file; Step S4: Automatically match interfaces using a multi-dimensional interface matching algorithm based on the tag information to obtain automatically matched connection relationships between interfaces, wherein the priority of the customized connection relationship is higher than the priority of the automatically matched connection relationship; finally, the customized connection relationship and the automatically matched connection relationship are merged to form a complete connection relationship table; Step S5: Generate a complete top-level Verilog code according to the connection relationship table; The specific process in step S2 is as follows: S21. For each interface signal of the NoC module, identify the standard interface type to which the interface signal belongs by analyzing the keywords and structural features in the signal name; S22, extracting the target module name and interface serial number of the target Agent module contained in the signal name, and extracting the channel and specific signal type to which the interface signal belongs; S23. Create a multi-level tag for each interface signal, including interface type, target module name, interface serial number, channel, and signal type; S24. For each interface signal of the Agent module, identify the standard interface type to which the interface signal belongs, extract the interface serial number contained in the signal name, and create a corresponding multi-level tag including the interface type and the interface serial number; S25. Integrate and organize all tag information of the NoC module and the Agent module into a tree-like hierarchical structure.

2. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving according to claim 1, wherein: The method further comprises the steps of: Step S6: Display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to the operation instructions.

3. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving according to claim 2, wherein: The specific process of step S3 is as follows: S31, parsing the custom configuration file provided by the user, and extracting each connection rule therefrom, including source module, source signal, target module, and target signal; S32. Convert the extracted connection rules into custom connection relationships that are compatible with the automatic matching connection relationship.

4. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving according to claim 3, wherein: The specific process in step S4 is as follows: S41, grouping all tag information of the NoC modules according to the target module names to obtain target module groups; S42. For each target module group, further group them according to interface type and interface serial number; S43, for each target module group, search for the target module name in the parsed Agent module Modules with the same name, and select the corresponding interface type and interface number; S44, performing a preliminary bidirectional signal match between the NoC module interface signal and the Agent module signal, then performing an accurate match based on the signal's function in the interface, and finally verifying whether the bit widths of the signals on both sides are consistent. If they are inconsistent, it is marked as a potential problem; S45. Establishing a connection relationship for the successfully matched interface signal pair and updating the connection status, i.e., automatically matching the connection relationship, and recording unsuccessfully matched signals for subsequent processing or reminders; wherein, the priority of the custom connection relationship is higher than the priority of the automatically matched connection relationship, and the custom connection relationship of the custom connection rule is processed first, and the signals of the custom connection relationship are marked. During automatic matching, the signals marked with the custom connection relationship are skipped; S46. Merge the custom connection relationship and the automatically matched connection relationship to generate a final complete connection relationship table.

5. The method for automatically matching network-on-chip interfaces based on hierarchical tag driving according to claim 4, wherein: The specific process of step S5 is as follows: S51. Generate top-level module declaration: Create the Verilog code framework of the top-level module; S52, generate internal wire declaration: generate a wire declaration of corresponding width for each matched signal pair, and process unconnected signals according to the preset; S53, generating instantiation code of the NoC module; S54, generating instantiation codes of each Agent module; S55. Write the generated complete top-level Verilog code into a specified output file.

6. A hierarchical tag-driven on-chip network interface automatic matching system, characterized in that: The system comprises: The parsing unit is used to read the NoC module file and the Agent module file respectively, and extract the definition of the NoC module and Agent module files and all interface signals through syntax parsing; A hierarchical labeling unit is used to label NoC module interface signals and Agent module interface signals in a hierarchical manner according to naming rules, and organize all labeling information into a hierarchical structure; A user-defined processing unit is used to obtain the customized connection relationship between interfaces according to a customized configuration file if the user provides the configuration file; An automatic matching unit is used to automatically match interfaces using a multi-dimensional interface matching algorithm according to the tag information to obtain automatic matching connection relationships between interfaces, where the priority of custom connection relationships is higher than that of automatic matching connection relationships; finally, the custom connection relationships and automatic matching connection relationships are merged to form a complete connection relationship table; An integrated generation unit for generating complete top-level Verilog code based on the connection relationship table; The execution process of the hierarchical marking unit is as follows: S21. For each interface signal of the NoC module, identify the standard interface type to which the interface signal belongs by analyzing the keywords and structural features in the signal name; S22, extracting the target module name and interface serial number of the target Agent module contained in the signal name, and extracting the channel and specific signal type to which the interface signal belongs; S23. Create a multi-level tag for each interface signal, including interface type, target module name, interface serial number, channel, and signal type; S24. For each interface signal of the Agent module, identify the standard interface type to which the interface signal belongs, extract the interface serial number contained in the signal name, and create a corresponding multi-level tag including the interface type and the interface serial number; S25. Integrate and organize all tag information of the NoC module and the Agent module into a tree-like hierarchical structure.

7. The hierarchical tag-driven on-chip network interface automatic matching system according to claim 6, characterized in that: The system further comprises: GUI unit, used to display the interface status in a hierarchical, foldable, and visual tree view, and filter, group, or highlight according to operation instructions.

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