Split gate type flash memory device and preparation method thereof

Abstract

The invention provides a split gate type flash memory device and a preparation method thereof, in the preparation method, discrete floating gate structures are set to be groove-shaped, the side walls of the floating gate structures are U-shaped, and the U-shaped openings of the two discrete floating gate structures are opposite, so that the height of the floating gate structures and the floating gate structure side walls attached to the outer side wall structures is increased, and the reliability of the floating gate structures is improved. Therefore, the control gate structure can be embedded into the groove of the floating gate structure, the coupling area ratio of the control gate structure to the floating gate structure through the ONO film layer is improved, the coupling effect of the control gate structure to the floating gate structure is improved, the control gate operation voltage can be reduced, and the reliability of the device is improved. The situation that the device is broken down in advance during programming operation, erasing operation and reading operation is avoided, and meanwhile the situation that interference occurs to the reading operation is also avoided.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a split-gate flash memory device and a method for manufacturing the same. Background Art

[0002] In existing NORD FLASH (flash memory) devices, the coupling effect of the control gate (CG) on the floating gate (FG) is weak. During programming / erasing / reading operations, a relatively high voltage is applied at the control gate end, which is prone to interference during frequent reading operations. At the same time, the ONO film layer and the gate oxide layer bear a relatively high pressure, and there is a risk of premature breakdown of the flash memory device. Summary of the Invention

[0003] The present application provides a split-gate flash memory device and a method for manufacturing the same, which can solve at least one of the problems in traditional NORD flash memory devices, such as the weak coupling effect of the control gate on the floating gate, resulting in interference during reading operations and premature breakdown of the device during programming / erasing / reading operations.

[0004] On the one hand, an embodiment of the present application provides a method for manufacturing a split-gate flash memory device, including:

[0005] Providing a substrate, on the surface of which a gate oxide layer and a substrate cushion layer are formed. Among them, a plurality of isolation structures are formed in the substrate cushion layer, the gate oxide layer, and a part of the substrate thickness at intervals in the X direction, and each of the isolation structures is arranged in the Y direction. A flash memory cell is formed between two adjacent isolation structures;

[0006] Etching the substrate cushion layer in the middle region of each flash memory cell to the surface of the gate oxide layer, where the substrate cushion layer in the edge regions of two adjacent isolation structures and each flash memory cell forms an uncovered groove;

[0007] Forming a floating gate material layer, which covers the side walls and the bottom wall of the groove, and also covers the substrate cushion layer and the isolation structures;

[0008] Forming a sacrificial oxide layer, which fills the groove and covers the floating gate material layer;

[0009] Grinding and removing the sacrificial oxide layer and the floating gate material layer that exceed the upper surface of the substrate cushion layer;

[0010] Etching back to remove the sacrificial oxide layer in the groove to obtain the floating gate material layer in the shape of a groove, and etching back to remove a part of the thickness of the isolation structures to form a certain height difference between the isolation structures and the substrate cushion layer;

[0011] Form an ONO film layer, where the ONO film layer covers the floating gate material layer in the groove, and covers the liner layer and the remaining thickness of the isolation structure;

[0012] Form a control gate material layer, where the control gate material layer covers the ONO film layer and fills the remaining space of the groove;

[0013] Form an interlayer insulating layer, where the interlayer insulating layer covers the control gate material layer;

[0014] Form a hard mask layer, where the hard mask layer covers the interlayer insulating layer;

[0015] Etch the hard mask layer to the surface of the interlayer insulating layer to form an opening, where the opening is arranged along the X direction and the width of the opening along the Y direction is less than the width of the floating gate material layer in the groove shape along the Y direction;

[0016] According to the opening, etch down the interlayer insulating layer, the control gate material layer, and the ONO film layer to the surface of the floating gate material layer to form a first trench, where the first trench cuts the control gate material layer from the middle position to obtain a discrete control gate structure;

[0017] Form a first sidewall material layer, where the first sidewall material layer covers the sidewalls and the bottom wall of the first trench and fills the first trench;

[0018] In the first trench, etch down the first sidewall material layer and the floating gate material layer to the surface of the gate oxide layer to form a second trench, where the opening size of the second trench along the Y direction is less than the opening size of the first trench along the Y direction, and the second trench cuts the floating gate material layer in the groove shape from the middle position to obtain a discrete floating gate structure, where the sidewalls of the discrete floating gate structure are U-shaped and the U-shaped openings of the discrete floating gate structures face each other;

[0019] Form a second sidewall material layer, where the second sidewall material layer covers the sidewalls of the second trench;

[0020] Form word line polysilicon, where the word line polysilicon covers the second sidewall material layer on the sidewalls of the second trench and the gate oxide layer on the bottom wall of the second trench, and fills the second trench;

[0021] Remove the hard mask layer;

[0022] Remove the interlayer insulating layer, the control gate material layer, the ONO film layer, and the liner layer outside the floating gate structure to the surface of the gate oxide layer;

[0023] Form an outer wall structure, and the outer wall structure covers the outer side surfaces of the floating gate structure, the ONO film layer, the control gate structure, and the interlayer insulating layer.

[0024] Optionally, in the method for manufacturing the split-gate flash memory device, the ratio of the sidewall height of the discrete floating gate structure in the Z direction to the width of the floating gate structure in the Y direction is (1:1.5) to (1:1).

[0025] Optionally, in the method for manufacturing the split-gate flash memory device, the ratio of the sidewall height of the discrete floating gate structure in the Z direction to the width of the floating gate structure in the X direction is (1:3) to (2:5).

[0026] Optionally, in the method for manufacturing the split-gate flash memory device, the height of the sidewall of the floating gate structure is at least 750 angstroms.

[0027] Optionally, in the method for manufacturing the split-gate flash memory device, the materials of the liner layer and the hard mask layer are both silicon nitride.

[0028] Optionally, in the method for manufacturing the split-gate flash memory device, the material of the first sidewall material layer is silicon nitride.

[0029] Optionally, in the method for manufacturing the split-gate flash memory device, the material of the second sidewall material layer is silicon dioxide.

[0030] Optionally, in the method for manufacturing the split-gate flash memory device, the material of the interlayer insulating layer is silicon dioxide.

[0031] On the other hand, an embodiment of the present application further provides a split-gate flash memory device, including:

[0032] A substrate, on the surface of which a gate oxide layer is formed. Among them, a plurality of isolation structures spaced apart from each other in the X direction are formed in the gate oxide layer and a part of the thickness of the substrate. Each of the isolation structures is arranged in the Y direction, and the isolation structure extends beyond the surface of the gate oxide layer by a certain height. A flash memory cell is formed between two adjacent isolation structures;

[0033] A floating gate material layer in a groove shape, which is located on the gate oxide layer between two adjacent isolation structures. Among them, the floating gate material layer is in an uncovered groove shape and the sidewalls around the floating gate material layer extend beyond the isolation structure by a certain height;

[0034] An ONO film layer, which covers the sidewalls and the bottom wall of the floating gate material layer in a groove shape and the tops of the sidewalls around the floating gate material layer;

[0035] A control gate material layer that covers the ONO film layer and fills the remaining space of the floating gate material layer in a groove shape;

[0036] An interlayer insulating layer that covers the control gate material layer;

[0037] A first trench that is arranged along the X direction and the width of the first trench along the Y direction is smaller than the width of the floating gate material layer in a groove shape along the Y direction. The first trench is located at the middle position of the floating gate material layer. Among them, the first trench cuts the control gate material layer from the middle position to obtain a discrete control gate structure;

[0038] A first sidewall material layer that covers the sidewalls of the first trench;

[0039] A second trench that the opening size of the second trench along the Y direction is smaller than the opening size of the first trench along the Y direction and the second trench is located in the first trench. The second trench cuts the floating gate material layer in a groove shape from the middle position to obtain a discrete floating gate structure. Among them, the sidewalls of the discrete floating gate structure are U-shaped and the U-shaped openings of the discrete floating gate structures face each other;

[0040] A second sidewall material layer that covers the sidewalls of the second trench;

[0041] A word line polysilicon that covers the second sidewall material layer on the sidewalls of the second trench and the gate oxide layer on the bottom wall of the second trench, and fills the second trench;

[0042] An outer sidewall structure that covers the outer sides of the floating gate structure, the ONO film layer, the control gate structure, and the interlayer insulating layer.

[0043] The technical solution of this application has at least the following advantages:

[0044] In this application, the discrete floating gate structure is set as a groove type with three-side enclosing walls. The sidewalls of the floating gate structure are U-shaped and the U-shaped openings of the two discrete floating gate structures face each other. This application raises the height of the sidewall of the floating gate structure that fits with the outer sidewall structure, so that the control gate structure can be embedded into the groove of the floating gate structure, improving the coupling area ratio of the control gate structure to the floating gate structure through the ONO film layer, enhancing the coupling effect of the control gate structure on the floating gate structure, reducing the control gate operating voltage, avoiding the situation that the device is prematurely broken down during programming, erasing, or reading operations, and also avoiding the situation of interference during reading operations. Description of the Drawings

[0045] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figures 1 - 23 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a split-gate flash memory device according to an embodiment of the present invention;

[0047] Among them, the reference numerals are explained as follows:

[0048] 10 - Substrate, 11 - Gate oxide layer, 12 - Substrate cushion layer, 13 - Isolation structure, 14 - Groove, 15 - Floating gate material layer, 16 - Sacrificial oxide layer, 17 - ONO film layer, 18 - Control gate material layer, 19 - Interlayer insulating layer, 20 - Hard mask layer, 21 - First trench, 22 - First sidewall material layer, 23 - Second trench, 24 - Second sidewall material layer, 25 - Word line polysilicon, 26 - Outer sidewall structure, 27 - Opening. Specific embodiments

[0049] The following will clearly and completely describe the technical solutions in the present application in conjunction with the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0050] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0051] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0052] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0053] The embodiment of the present application provides a method for manufacturing a split-gate flash memory device, including:

[0054] First, perform Step 1: Refer to Figure 1 , Figure 1 is a schematic structural diagram of any flash memory cell after forming a plurality of isolation structures in the embodiment of the present application. Provide a substrate 10, on the surface of which a gate oxide layer 11 and a liner layer 12 are formed. Among them, a plurality of isolation structures 13 spaced apart from each other along the X direction are formed in the liner layer 12, the gate oxide layer 11, and a part of the thickness of the substrate 10.

[0055] Among them, each of the isolation structures 13 is arranged along the Y direction, and a flash memory cell is formed between two adjacent isolation structures 13.

[0056] In this embodiment, the isolation structure 13 is a shallow trench isolation structure (STI), and its material is silicon dioxide.

[0057] In this embodiment, the material of the liner layer 12 is silicon nitride.

[0058] Then, perform Step 2: Refer to Figure 2 , Figure 2 is a schematic structural diagram of a semiconductor structure after forming an open-top groove in the embodiment of the present application. Etch the liner layer 12 in the middle region of each flash memory cell to the surface of the gate oxide layer 11. Among them, two adjacent isolation structures 13 and the liner layer 12 in the edge region of each flash memory cell form an open-top groove 14.

[0059] Next, perform Step 3: Refer to Figure 3 , Figure 3 is a schematic structural diagram of a semiconductor structure after forming a floating gate material layer in the embodiment of the present application. Form a floating gate material layer 15, and the floating gate material layer 15 covers the side walls and the bottom wall of the groove 14, and also covers the liner layer 12 and the isolation structures 13.

[0060] Further, perform Step Four: Refer to Figure 4 , Figure 4 is a schematic diagram of a semiconductor structure after forming a sacrificial oxide layer in an embodiment of the present application. A sacrificial oxide layer 16 is formed, and the sacrificial oxide layer 16 fills the groove 14 and covers the floating gate material layer 15.

[0061] Next, perform Step Five: Refer to Figure 5 , Figure 5 is a schematic diagram of a semiconductor structure after grinding and removing the sacrificial oxide layer and the floating gate material layer that exceed the upper surface of the liner layer. The sacrificial oxide layer 16 and the floating gate material layer 15 that exceed the upper surface of the liner layer 12 are ground and removed.

[0062] Further, perform Step Six: Refer to Figure 6 , Figure 6 is a schematic diagram of a semiconductor structure after forming the floating gate material layer in a groove shape in an embodiment of the present application. The sacrificial oxide layer 16 in the groove 14 is etched back to obtain the floating gate material layer 15 in a groove shape, and a part of the thickness of the isolation structure 13 is etched back so that the isolation structure 13 forms a certain height difference with the liner layer 12; further, after etching back a part of the thickness of the isolation structure 13, the isolation structure 13 also forms a certain height difference with the floating gate material layer 15 in a groove shape.

[0063] Next, perform Step Seven: Refer to Figure 7 , Figure 7 is a schematic diagram of a semiconductor structure after forming an ONO film layer in an embodiment of the present application. An ONO film layer 17 is formed, and the ONO film layer 17 covers the floating gate material layer 15 in the groove 14, and covers the liner layer 12 and the remaining thickness of the isolation structure 13.

[0064] Further, perform Step Eight: Refer to Figure 8 , Figure 8 is a schematic diagram of a semiconductor structure after forming a control gate material layer in an embodiment of the present application. A control gate material layer 18 is formed, and the control gate material layer 18 covers the ONO film layer 17 and fills the remaining space of the groove 14.

[0065] Next, perform Step Nine: Refer to Figure 9 , Figure 9 is a schematic diagram of a semiconductor structure after etching a hard mask layer to form an opening in an embodiment of the present application. An interlayer insulating layer 19 is formed, and the interlayer insulating layer 19 covers the control gate material layer 18.

[0066] In this embodiment, the material of the interlayer insulating layer 19 is silicon dioxide.

[0067] Further, perform Step Ten: Continue to refer to Figure 9 , to form a hard mask layer 20, and the hard mask layer 20 covers the interlayer insulating layer 19.

[0068] In this embodiment, the material of the hard mask layer 20 is silicon nitride.

[0069] Next, perform Step Eleven: Continue to refer to Figure 9 , etch the hard mask layer 20 to the surface of the interlayer insulating layer 19 to form an opening 27, wherein the opening 27 is arranged along the X direction and the width of the opening 27 along the Y direction is smaller than the width of the grooved floating gate material layer 15 along the Y direction.

[0070] Further, perform Step Twelve: Refer to Figures 10 - 13 , Figure 10 is a cross-sectional view of the interior of the floating gate along the Y direction after the formation of the first trench in the embodiment of the present application, Figure 11 is a cross-sectional view of the side wall of the floating gate along the Y direction after the formation of the first trench in the embodiment of the present application, Figure 12 is a cross-sectional view of the interior of the floating gate along the X direction after the formation of the interlayer insulating layer in the embodiment of the present application, Figure 13 is a cross-sectional view of the side wall of the floating gate along the X direction after the formation of the interlayer insulating layer in the embodiment of the present application. According to the opening 27, etch the interlayer insulating layer 19, the control gate material layer 18, and the ONO film layer 17 downward to the surface of the floating gate material layer 15 to form a first trench 21, wherein the first trench 21 cuts the control gate material layer 18 from the middle position to obtain a discrete control gate structure.

[0071] Next, perform Step Thirteen: Refer to Figure 14 and Figure 15 , Figure 14 is a cross-sectional view of the interior of the floating gate along the Y direction after the formation of the second trench in the embodiment of the present application, Figure 15 is a cross-sectional view of the side wall of the floating gate along the Y direction after the formation of the second trench in the embodiment of the present application. Form a first sidewall material layer 22, and the first sidewall material layer 22 covers the side wall and the bottom wall of the first trench 21 and fills the first trench 21.

[0072] In this embodiment, the material of the first sidewall material layer 22 is silicon nitride.

[0073] Further, perform Step Fourteen: Continue to refer to Figure 14 and Figure 15, etch the first sidewall material layer 22 and the floating gate material layer 14 downward in the first trench 21 to the surface of the gate oxide layer 11 to form a second trench 23, wherein the opening size of the second trench 23 in the Y direction is smaller than the opening size of the first trench 21 in the Y direction, and the second trench 23 cuts the grooved floating gate material layer 15 from the middle position to obtain discrete floating gate structures, wherein the sidewalls of the discrete floating gate structures are U-shaped, and the U-shaped openings of the discrete floating gate structures face each other.

[0074] Preferably, referring to Figure 14 and Figure 15 , the ratio of the sidewall height d1 of the discrete floating gate structure in the Z direction to the width d3 of the floating gate structure in the Y direction is (1:1.5) to (1:1).

[0075] More preferably, referring to Figure 12 and Figure 13 , the ratio of the sidewall height d1 of the discrete floating gate structure in the Z direction to the width d2 of the floating gate structure in the X direction is (1:3) to (2:5).

[0076] Furthermore, the height of the sidewall of the floating gate structure is at least 750 angstroms.

[0077] In this application, the discrete floating gate structure is set as a groove type with a three-sided enclosure form. The sidewalls of the floating gate structure are U-shaped and the U-shaped openings of the two discrete floating gate structures face each other. In this application, the height of the sidewall of the floating gate structure that fits with the outer wall structure is increased, so that the control gate structure can be embedded into the groove of the floating gate structure, improving the coupling area ratio of the control gate structure to the floating gate structure through the ONO film layer, enhancing the coupling effect of the control gate structure on the floating gate structure, reducing the control gate operating voltage, avoiding the situation that the device is prematurely broken down during programming, erasing or reading operations, and also avoiding the situation of interference during reading operations.

[0078] Next, perform step fifteen: referring to Figure 16 and Figure 17 , Figure 16 is a cross-sectional view of the floating gate interior along the Y direction after forming the second sidewall material layer in the embodiment of the present application, Figure 17 is a cross-sectional view of the sidewall of the floating gate along the Y direction after forming the second sidewall material layer in the embodiment of the present application. Form the second sidewall material layer 24, and the second sidewall material layer 24 covers the sidewalls of the second trench 23, that is, the second sidewall material layer 24 covers the first sidewall material layer 22 on the sidewalls of the second trench 23.

[0079] In this embodiment, the material of the second sidewall material layer 24 is silicon dioxide.

[0080] Further, perform Step Sixteen: Refer to Figure 18 and Figure 19 , Figure 18 is a cross-sectional view of the interior of the floating gate along the Y direction after forming the word line polysilicon in the embodiment of the present application, Figure 19 is a cross-sectional view of the sidewall of the floating gate along the Y direction after forming the word line polysilicon in the embodiment of the present application. The word line polysilicon 25 is formed to cover the second sidewall material layer 24 on the sidewall of the second trench 23 and the gate oxide layer 11 on the bottom wall of the second trench 23, and to fill the second trench 23.

[0081] Next, perform Step Seventeen: Refer to Figure 20 and Figure 21 , Figure 20 is a cross-sectional view of the interior of the floating gate along the Y direction after removing the hard mask layer, the interlayer insulating layer, the control gate material layer, the ONO film layer, and the liner layer outside the floating gate structure in the embodiment of the present application, Figure 21 is a cross-sectional view of the sidewall of the floating gate along the Y direction after removing the hard mask layer, the interlayer insulating layer, the control gate material layer, the ONO film layer, and the liner layer outside the floating gate structure in the embodiment of the present application. Remove the hard mask layer 20.

[0082] Further, perform Step Eighteen: Continue to refer to Figure 20 and Figure 21 , and remove the interlayer insulating layer 19, the control gate material layer 18, the ONO film layer 17, and the liner layer 12 outside the floating gate structure to the surface of the gate oxide layer 11.

[0083] Finally, perform Step Nineteen: Refer to Figure 22 and Figure 23 , Figure 22 is a cross-sectional view of the interior of the floating gate along the Y direction after forming the outer wall structure in the embodiment of the present application, Figure 23 is a cross-sectional view of the sidewall of the floating gate along the Y direction after forming the outer wall structure in the embodiment of the present application. The outer wall structure 26 is formed to cover the outer sides of the floating gate structure, the ONO film layer 17, the control gate structure, and the interlayer insulating layer 19.

[0084] It should be noted that since processes such as forming the discrete control gate structure (forming the first trench) and forming the discrete floating gate structure (forming the second trench) are all performed in the YZ cross-section (YZ plane) along the Y direction, after removing the hard mask layer 20, the cross-sectional view of the interior of the floating gate along the X direction and the cross-sectional view of the sidewall of the floating gate along the X direction do not change. Therefore, in Steps Thirteen to Nineteen, the cross-sectional view of the interior of the floating gate along the X direction and the cross-sectional view of the sidewall of the floating gate along the X direction can still be referred toFigure 12 and Figure 13 。

[0085] Based on the same inventive concept, an embodiment of the present application further provides a split-gate flash memory device. Referring to Figure 22 and Figure 23 , and referring to Figure 12 and Figure 13 , the split-gate flash memory device includes:

[0086] A substrate 10, on the surface of which a gate oxide layer 11 is formed. Among them, a plurality of isolation structures 13 spaced apart from each other in the X direction are formed in the gate oxide layer 11 and a part of the thickness of the substrate 10. Each of the isolation structures 13 is arranged in the Y direction, and the isolation structure 13 extends beyond the surface of the gate oxide layer 11 by a certain height. A flash memory cell is formed between two adjacent isolation structures 13;

[0087] A floating gate material layer 15 in a groove shape, which is located on the gate oxide layer 11 between two adjacent isolation structures 13. Among them, the floating gate material layer 15 is in an uncovered groove shape and the side walls around the floating gate material layer 15 extend beyond the isolation structure 13 by a certain height;

[0088] An ONO film layer 17, which covers the side walls and the bottom wall of the floating gate material layer 15 in a groove shape and the top ends of the side walls around the floating gate material layer 15;

[0089] A control gate material layer 18, which covers the ONO film layer 17 and fills the remaining space of the floating gate material layer 15 in a groove shape;

[0090] An interlayer insulating layer 19, which covers the control gate material layer 18;

[0091] A first trench 21, which is arranged in the X direction and the width of the first trench 21 in the Y direction is smaller than the width of the floating gate material layer 15 in a groove shape in the Y direction. The first trench 21 is located at the middle position of the floating gate material layer 15. Among them, the first trench 21 cuts the control gate material layer 18 from the middle position to obtain a discrete control gate structure;

[0092] A first sidewall material layer 22, which covers the side walls of the first trench 21;

[0093] A second groove 23, the opening dimension of the second groove 23 in the Y direction being smaller than the opening dimension of the first groove 21 in the Y direction and the second groove 23 being located in the first groove 21, the second groove 23 cutting the groove-shaped floating gate material layer 15 from a middle position to obtain discrete floating gate structures, wherein the side walls of the discrete floating gate structures are U-shaped and the U-shaped openings of the discrete floating gate structures face each other;

[0094] A second sidewall material layer 24, the second sidewall material layer 24 covering the side walls of the second groove 23;

[0095] Word line polysilicon 25, the word line polysilicon 25 covering the second sidewall material layer 24 on the side walls of the second groove 23 and the gate oxide layer 11 on the bottom wall of the second groove 23 and filling the second groove 23;

[0096] An outer sidewall structure 26, the outer sidewall structure 26 covering the outer sides of the floating gate structure, the ONO film layer 17, the control gate structure and the interlayer insulating layer 19.

[0097] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of this application.

Claims

1. A method for preparing a split-gate flash memory device, characterized in that: include: A substrate is provided, wherein a gate oxide layer and a liner layer are formed on the surface of the substrate, wherein a plurality of isolation structures spaced from each other along the X direction are formed in the liner layer, the gate oxide layer and a portion of the thickness of the substrate, each of the isolation structures is arranged along the Y direction, and a flash memory unit is formed between two adjacent isolation structures; Etching the liner layer in the middle area of ​​each of the flash memory cells to the surface of the gate oxide layer, wherein two adjacent isolation structures and the liner layer in the edge area of ​​each of the flash memory cells form an uncovered groove; forming a floating gate material layer, wherein the floating gate material layer covers the sidewalls and the bottom wall of the groove, and covers the liner layer and the isolation structure; forming a sacrificial oxide layer, wherein the sacrificial oxide layer fills the groove and covers the floating gate material layer; Grinding and removing the sacrificial oxide layer and the floating gate material layer beyond the upper surface of the liner layer; Etching back to remove the sacrificial oxide layer in the groove to obtain the floating gate material layer in the shape of a groove, and etching back to remove a portion of the thickness of the isolation structure to form a certain height difference between the isolation structure and the liner layer; forming an ONO film layer, wherein the ONO film layer covers the floating gate material layer in the groove, and covers the liner layer and the remaining thickness of the isolation structure; forming a control gate material layer, wherein the control gate material layer covers the ONO film layer and fills the remaining space of the groove; forming an interlayer insulating layer, wherein the interlayer insulating layer covers the control gate material layer; forming a hard mask layer, wherein the hard mask layer covers the interlayer insulating layer; Etching the hard mask layer to the surface of the interlayer insulating layer to form an opening, wherein the opening is arranged along the X direction and the width of the opening along the Y direction is smaller than the width of the groove-shaped floating gate material layer along the Y direction; According to the opening, the interlayer insulating layer, the control gate material layer, and the ONO film layer are etched downward to the surface of the floating gate material layer to form a first trench, wherein the first trench cuts the control gate material layer from a middle position to obtain two separate control gate structures; forming a first spacer material layer, wherein the first spacer material layer covers the sidewall and bottom wall of the first trench and fills the first trench; Etching the first spacer material layer and the floating gate material layer downward in the first trench to the surface of the gate oxide layer to form a second trench, wherein the opening size of the second trench along the Y direction is smaller than the opening size of the first trench along the Y direction, and the second trench cuts the groove-shaped floating gate material layer from the middle position to obtain two discrete floating gate structures, wherein the sidewalls of the discrete floating gate structures are U-shaped, and the U-shaped openings of the discrete floating gate structures are opposite to each other; forming a second spacer material layer, wherein the second spacer material layer covers the sidewall of the second trench; Forming word line polysilicon, wherein the word line polysilicon covers the second spacer material layer on the sidewall of the second trench and the gate oxide layer on the bottom wall of the second trench, and fills the second trench; removing the hard mask layer; Removing the interlayer insulating layer, the control gate material layer, the ONO film layer and the liner layer outside the floating gate structure to the surface of the gate oxide layer; An outer sidewall structure is formed, and the outer sidewall structure covers the outer side surfaces of the floating gate structure, the ONO film layer, the control gate structure and the interlayer insulating layer.

2. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The ratio of the sidewall height of the discrete floating gate structure along the Z direction to the width of the floating gate structure along the Y direction is (1:1.5) to (1:1).

3. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The ratio of the sidewall height of the discrete floating gate structure along the Z direction to the width of the floating gate structure along the X direction is (1:3) to (2:5).

4. The method for preparing a split-gate flash memory device according to claim 2 or 3, characterized in that: The height of the sidewall of the floating gate structure along the Z direction is at least 750 angstroms.

5. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The material of the liner layer and the material of the hard mask layer are both silicon nitride.

6. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The first spacer material layer is made of silicon nitride.

7. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The second sidewall material layer is made of silicon dioxide.

8. The method for preparing a split-gate flash memory device according to claim 1, characterized in that: The material of the interlayer insulating layer is silicon dioxide.

9. A split-gate flash memory device, characterized in that: include: A substrate, a gate oxide layer is formed on the surface of the substrate, wherein a plurality of isolation structures spaced from each other along the X direction are formed in the gate oxide layer and a portion of the thickness of the substrate, each of the isolation structures is arranged along the Y direction, the isolation structure exceeds the surface of the gate oxide layer by a certain height, and a flash memory unit is formed between two adjacent isolation structures; A floating gate material layer in a groove shape, the floating gate material layer being located on the gate oxide layer between two adjacent isolation structures, wherein the floating gate material layer is in an uncovered groove shape and the sidewalls around the floating gate material layer exceed the isolation structure by a certain height; An ONO film layer, wherein the ONO film layer covers the sidewalls and bottom wall of the groove-shaped floating gate material layer and the top of the sidewalls around the floating gate material layer; A control gate material layer, wherein the control gate material layer covers the ONO film layer and fills the remaining space of the groove-shaped floating gate material layer; an interlayer insulating layer, wherein the interlayer insulating layer covers the control gate material layer; a first trench, the first trench being arranged along the X direction and having a width along the Y direction smaller than a width of the groove-shaped floating gate material layer along the Y direction, the first trench being located in the middle of the floating gate material layer, wherein the first trench cuts the control gate material layer from the middle to obtain a discrete control gate structure; A first spacer material layer, wherein the first spacer material layer covers the sidewall of the first trench; a second trench, wherein the opening size of the second trench along the Y direction is smaller than the opening size of the first trench along the Y direction and the second trench is located in the first trench, and the second trench cuts the groove-shaped floating gate material layer from a middle position to obtain a discrete floating gate structure, wherein the sidewall of the discrete floating gate structure is U-shaped, and the U-shaped openings of the discrete floating gate structure are opposite; A second spacer material layer, wherein the second spacer material layer covers a sidewall of the second trench; Word line polysilicon, the word line polysilicon covers the second spacer material layer on the sidewall of the second trench and the gate oxide layer on the bottom wall of the second trench, and fills the second trench; An outer sidewall structure covers the outer side surfaces of the floating gate structure, the ONO film layer, the control gate structure and the interlayer insulating layer.

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