Semiconductor device and operating method thereof

Abstract

The invention relates to a semiconductor device and an operating method thereof. The semiconductor device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed to be spaced apart from the first conductive lines in a third direction and extending in a second direction crossing the first direction; a plurality of memory cells overlapping an intersection region between the first conductive line and the second conductive line; and a first variable resistance pattern formed between the memory cell and the first conductive line and / or between the memory cell and the second conductive line.

Description

[0001] Priority Claims and Cross - References to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0183513, filed with the Korean Intellectual Property Office on December 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to semiconductor technology, and more particularly, to a semiconductor device including a variable resistance pattern and a method for operating the semiconductor device. Background Art

[0004] Recently, the trends of miniaturization, low power consumption, high performance, and diversification of electronic devices have demanded semiconductor devices that can store data in various electronic devices such as computers and portable communication devices. Researchers and industries are studying and developing such semiconductor devices. Such semiconductor devices can store data by using the characteristic of switching between different resistance states according to the applied voltage or current. Examples of such semiconductor devices include resistive random access memory (RRAM), phase - change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuses, etc. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a semiconductor device that can improve operating performance by preventing defects such as leakage current, and a method for operating the semiconductor device.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed to be spaced apart from the first conductive lines in a third direction and extending in a second direction intersecting the first direction; a plurality of memory cells stacked in a crossing region between the first conductive lines and the second conductive lines; and a first variable resistance pattern formed between the memory cell and the first conductive line and / or formed between the memory cell and the second conductive line.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The semiconductor device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed to be spaced apart from the first conductive lines in a third direction and extending in a second direction intersecting the first direction; a plurality of memory cells stacked with a crossing region between the first conductive lines and the second conductive lines; and a first variable resistance pattern formed between the memory cells and the first conductive lines and / or between the memory cells and the second conductive lines. The method includes: determining whether there is a defective memory cell among the memory cells; and when there is a defective memory cell, performing a reset operation to change a resistance state of the first variable resistance pattern coupled to the defective memory cell to a high resistance state.

[0008] The above and other aspects of the disclosed technology are disclosed in the accompanying drawings, the detailed description, and the claims. Description of the Drawings

[0009] Figure 1A is a perspective view showing an example of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1B is a view showing Figure 1A a cross-sectional view of an example of the memory cell 120 shown.

[0011] Figure 1C is a view showing Figure 1A a cross-sectional view of another example of the memory cell 120 shown.

[0012] Figure 1D is a view showing Figure 1B a cross-sectional view of an example of the second variable resistance pattern 127 shown.

[0013] Figures 2A to 2C is a view showing Figure 1A a cross-sectional view of an example of various states of the semiconductor device shown.

[0014] Figure 3 is an example of a flowchart showing a method for operating a semiconductor device according to an embodiment of the present disclosure. Detailed Description

[0015] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, the same reference numerals refer to the same components in the various drawings and embodiments of the present disclosure.

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or the substrate.

[0018] Figure 1A is a perspective view showing an example of a semiconductor device according to an embodiment of the present disclosure.

[0019] Referring to Figure 1A , the semiconductor device according to this embodiment of the present disclosure may include: a plurality of first conductive lines 110 formed on a substrate 100 and extending in a first direction D1; a plurality of second conductive lines 140 formed to be spaced apart from the first conductive lines 110 in a third direction D3 and extending in a second direction D2 intersecting the first direction D1; a plurality of memory cells 120 respectively located between the first conductive lines 110 and the second conductive lines 140 and stacked in a cross-sectional area of the first conductive lines 110 and the second conductive lines 140; and a first variable resistance pattern 130 interposed between each of the memory cells 120 and each of the second conductive lines 140. Here, the first direction D1 and the second direction D2 may correspond to horizontal directions substantially parallel to the top surface of the substrate 100. For example, the first direction D1 and the second direction D2 may be perpendicular to each other in the same plane. The third direction D3 may correspond to a vertical direction substantially perpendicular to the top surface of the substrate 100. However, the present disclosure is not limited thereto, and the first direction D1 to the third direction D3 may be changed in various ways on the premise that the first direction D1 to the third direction D3 intersect each other. For example, different from that shown, the first direction D1 and the second direction D2 may correspond to vertical directions, while the third direction D3 may correspond to a horizontal direction.

[0020] The substrate 100 may include a semiconductor material such as silicon. A required predetermined underlying structure (not shown) may be formed in the substrate 100. For example, the substrate 100 may be electrically connected to the first conductive lines 110 and / or the second conductive lines 140, and may include a driving circuit (not shown) for controlling the first conductive lines 110 and / or the second conductive lines 140.

[0021] The first conductive line 110 and the second conductive line 140 may be electrically coupled to the lower end and the upper end of each memory cell 120, respectively, and transmit an operating voltage and / or an operating current to the memory cell 120 to operate the memory cell 120. In an example as Figure 1A shown, the memory cell 120 is located below the second conductive line 140 and above the first conductive line 110, and is coupled to the first conductive line 110 and the second conductive line 140. When the first conductive line 110 is used as a word line, the second conductive line 140 may be used as a bit line. Conversely, when the first conductive line 110 is used as a bit line, the second conductive line 140 may be used as a word line. Each of the first conductive line 110 and the second conductive line 140 may include various conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc., metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof, and may have a single-layer structure or a multi-layer structure.

[0022] The memory cell 120 may store data. The memory cell 120 may be configured to store data based on various schemes for storing data. For example, the memory cell 120 may store two different data by switching between different resistance states according to a voltage or current applied via the first conductive line 110 and the second conductive line 140. In some embodiments, by controlling the voltage or current applied to the memory cell 120, the memory cell 120 may store more than two different data. This will be described below with reference to Figures 1B to 1D how to store data in the memory cell 120.

[0023] Figure 1B is a cross-sectional view showing an example of the memory cell 120 as Figure 1A shown.

[0024] Referring to Figure 1B , the memory cell 120 may include a stacked structure of a first electrode 121, a selector pattern 123, a second electrode 125, a second variable resistance pattern 127, and a third electrode 129.

[0025] The first electrode 121 may be interposed between the first conductive line 110 and the selector pattern 123 and may be used to electrically connect the first conductive line 110 and the selector pattern 123 to each other while physically separating the first conductive line 110 and the selector pattern 123 from each other. The second electrode 125 may be interposed between the selector pattern 123 and the variable resistance pattern 127 and may be used to electrically connect the selector pattern 123 and the variable resistance pattern 127 to each other while physically separating the selector pattern 123 and the variable resistance pattern 127 from each other. The third electrode 129 may be interposed between the variable resistance pattern 127 and the second conductive line 140 and may be used to electrically connect the variable resistance pattern 127 and the second conductive line 140 to each other while physically separating the variable resistance pattern 127 and the second conductive line 140 from each other. Each of the first electrode 121, the second electrode 125, and the third electrode 129 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc., metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof. In some embodiments, at least one of the first electrode 121, the second electrode 125, and the third electrode 129 may include a carbon electrode.

[0026] The selector pattern 123 may be used to control access to the memory cell 120 and prevent leakage current that may occur between memory cells 120 sharing the first conductive line 110 or the second conductive line 140. In some embodiments, the selector pattern 123 may have threshold switching characteristics to selectively switch between two conductive states: (1) a non-conductive state that blocks or allows little current to flow when the applied voltage is less than a predetermined threshold; and (2) a conductive state that allows current to rapidly increase and flow when the applied voltage is equal to or greater than the predetermined threshold. This threshold may be referred to as a threshold voltage or a threshold current, and the selector pattern 123 may be in an on state or an off state based on the threshold voltage or the threshold current.

[0027] For example, the selector pattern 123 may include OTS (bidirectional threshold switching) materials such as diodes or chalcogenide-based materials, MIEC (mixed ionic electronic conducting) materials such as metal-containing chalcogenide-based materials, MIT (metal insulator transition) materials such as NbO2 or VO2, tunneling dielectric layers having a relatively wide bandgap such as SiO2 or Al2O3, etc.

[0028] In some embodiments, selector pattern 123 may include a dielectric material doped with a dopant. The dielectric material may include a dielectric material having a relatively wide bandgap, e.g., a dielectric material having a bandgap of about 5.0 eV or greater. For example, the dielectric material may include a silicon-containing dielectric material (such as silicon oxide, silicon nitride, or silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. In selector pattern 123, there may be deep traps whose energy levels are closer to the energy level of the valence band compared to the conduction band energy level of the dielectric material in the dielectric material. The dopant can be used to create shallow traps that provide a path for the migration of conductive carriers (such as electrons or holes) in the dielectric material. The energy level of the shallow trap may be closer to the conduction band energy level compared to the equilibrium band energy level of the dielectric material. For example, when the dielectric material contains silicon, the dopant may include a metal whose valence is different from that of silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. When the dielectric material contains a metal, the dopant may include a metal whose valence is different from that of the metal, silicon, etc. For example, selector pattern 123 may include silicon dioxide (SiO2) doped with arsenic (As). In the off state where no voltage or a voltage less than a predetermined threshold is applied to selector pattern 123, conductive carriers such as electrons can be trapped in the deep traps of selector pattern 123. By applying a voltage equal to or greater than the threshold voltage to selector pattern 123 in the off state, selector pattern 123 can be operated to be in the on state, in which current flows through selector pattern 123. When a voltage equal to or greater than the threshold voltage is applied to selector pattern 123, the conductive carriers trapped in the deep traps can jump to the shallow traps by thermionic emission or tunneling. As the conductive carriers migrate through the shallow traps, a current flow coupling the first electrode 121 and the second electrode 125 can be formed. When the voltage applied to selector pattern 123 in the on state decreases, the number of conductive carriers migrating from the deep traps to the shallow traps decreases, and selector pattern 123 can be turned off again.

[0029] Thus, in Figure 1B the example of, each memory cell 120 has: an internal memory cell access control circuit, which is selector pattern 123; and an external memory cell access control circuit, which is a first variable resistance pattern 130 that is serially connected to memory cell 120 and is located outside memory cell 120. The internal memory cell access control circuit (selector pattern 123) and the external memory cell access control circuit (first variable resistance pattern 130) are operated to control the electrical connection of memory cell 120 to the corresponding first and second conductive lines for memory cell 120.

[0030] The second variable resistance pattern 127 may be part of the memory cell 120 for storing data. In this embodiment, the second variable resistance pattern 127 may have a variable resistance characteristic of switching between different resistance states for storing data and for data writing operations according to the applied voltage. The second variable resistance pattern 127 may have a single-layer structure or a multi-layer structure, including various materials used in RRAM, PRAM, FRAM, MRAM, etc., for example, metal oxides such as transition metal oxides or perovskite-based materials, phase change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc.

[0031] However, the layer structure of the memory cell 120 is not limited to the layer structure described above, but may be changed differently. For example, at least one of the first electrode 121, the selector pattern 123, the second electrode 125, and the third electrode 129 may be omitted. In some embodiments, in addition to the above layers 121 to 129, the memory cell 120 may further include one or more layers (not shown) that can improve the characteristics of the memory cell 120. In some embodiments, the positions of the selector pattern 123 and the second variable resistance pattern 127 may be switched.

[0032] Figure 1C is a cross-sectional view showing Figure 1A another example of the memory cell 120 shown.

[0033] Referring to Figure 1C , the memory cell 120 may include a stacked structure of a first electrode 122, a self-selective memory pattern 124, and a second electrode 126.

[0034] The self - selectable memory pattern 124 can operate as a memory element and a selection element. In some embodiments, the self - selectable memory pattern 124 can have: a variable - resistance characteristic that exhibits different resistance states or resistance values, thereby operating as a memory element to store different data according to different resistance states of the self - selectable memory pattern 124 based on the voltage or current applied through the first electrode 122 and the second electrode 126; and a threshold - switching characteristic. When the voltage applied through the first electrode 122 and the second electrode 126 is less than the threshold voltage, the self - selectable memory pattern 124 is turned off to be non - conductive, and thus prevents current or keeps the current from flowing through the self - selectable memory pattern 124 almost not at all. Or when the applied voltage is equal to or greater than the threshold voltage, the self - selectable memory pattern 124 is turned on to be conductive, and thus allows current to flow through the self - selectable memory pattern 124 violently. In some embodiments, the threshold voltage of the memory cell 120 can depend on the resistance state of the memory cell 120. In other words, according to different resistance states, the memory cell 120 can have different threshold voltages. For example, when the memory cell 120 is in the first resistance state, it can have a first threshold voltage, while when the memory cell 120 is in a second resistance state different from the first resistance state, it can have a second threshold voltage different from the first threshold voltage. As a result, the memory cell 120 can be implemented as a self - selectable memory element, operating as a memory element and a selection element.

[0035] Figure 1D is a cross - sectional view showing Figure 1B an example of the second variable - resistance pattern 127 shown.

[0036] Referring to Figure 1D , the second variable - resistance pattern 127 can be a magnetic tunnel junction structure, and it can include a fixed layer 127A, a tunnel barrier layer 127B, and a free layer 127C.

[0037] The fixed layer 127A can be a layer having a fixed magnetization direction that can be compared with the magnetization direction of the free layer 127C, and the fixed layer 127A can also be referred to as a reference layer. The free layer 127C can be a layer that can store different data by having a variable magnetization direction, and the free layer 127C can also be referred to as a storage layer. The tunnel barrier layer 127B can physically separate the fixed layer 127A and the free layer 127C from each other and enable carriers (e.g., electrons) to tunnel between the fixed layer 127A and the free layer 127C. Each of the fixed layer 127A and the free layer 127C can have a single-layer structure or a multi-layer structure including a ferromagnetic material. For example, each of the fixed layer 127A and the free layer 127C can include an alloy containing Fe, Ni, or Co as a main component. For example, each of the fixed layer 127A and the free layer 127C can include at least one of Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, Fe-Pd alloy, or Co-Fe-B alloy, or at least one of Co / Pt stacked structure or Co / Pd stacked structure. The tunnel barrier layer 127B can have a single-layer structure or a multi-layer structure including a dielectric material. For example, the tunnel barrier layer 127B can include a dielectric oxide such as MgO, CaO, SrO, TiO, VO, or NbO.

[0038] In this magnetic tunnel junction structure, the magnetization direction of the free layer 127C can vary according to the applied voltage or current. When the magnetization direction of the free layer 127C is parallel to the magnetization direction of the fixed layer 127A, the magnetic tunnel junction structure can have a low-resistance state and can store, for example, data "1". On the other hand, when the magnetization direction of the free layer 127C is antiparallel to the magnetization direction of the fixed layer 127A, the magnetic tunnel junction structure can have a high-resistance state and can store, for example, data "0". In some other embodiments, when the magnetic tunnel junction structure has a high-resistance state, the magnetic tunnel junction structure can store data "1", while when the magnetic tunnel junction structure has a low-resistance state, the magnetic tunnel junction structure can store data "0".

[0039] As long as the magnetic tunnel junction structure includes the fixed layer 127A, the free layer 127C, and the tunnel barrier layer 127B located between the fixed layer 127A and the free layer 127C, the layer structure of the magnetic tunnel junction structure can be modified differently. For example, the positions of the fixed layer 127A and the free layer 127C can be switched. In some embodiments, the magnetic tunnel junction structure can also include one or more layers (although not shown) to improve the characteristics of the magnetic tunnel junction structure.

[0040] Return reference Figure 1A, the storage cell 120 may have a columnar shape that overlaps with the crossing regions of the first conductive line 110 and the second conductive line 140. In this figure, the storage cell 120 is shown as having a cylindrical shape, but the present disclosure is not limited thereto, and the storage cell 120 may have various shapes such as a square column, an elliptical column, etc. In this figure, the multiple layers forming the storage cell 120 (e.g., Figure 1B the illustrated layers 121 to 129) have sidewalls that are aligned with each other by using mask patterning. However, the present disclosure is not limited thereto. In particular, when the second variable resistance pattern 127 has a multilayer structure such as a magnetic tunnel junction structure, it may be difficult to etch all the layers forming the storage cell 120 at one time. In this case, the layers forming the storage cell 120 may be divided into two or more parts and patterned separately. For example, Figure 1B the selector pattern 123 and the second variable resistance pattern 127 may be patterned separately using different masks, and as a result, they may have sidewalls that are not aligned with each other.

[0041] In a semiconductor device, various operations can be performed, including a programming operation of storing data in one or more storage cells 120 selected from a plurality of storage cells 120, a reading operation of reading data stored in one or more storage cells 120 selected from a plurality of storage cells 120, etc. The voltage or current applied through the first conductive line 110 and the second conductive line 140 for various operations such as programming operations and reading operations may hereinafter be referred to as an operation voltage or an operation current.

[0042] In some embodiments, some of the storage cells 120 may correspond to defective storage cells that operate abnormally. The defective storage cells may interfere with the operation of the semiconductor device in several ways. For example, during the operation of the semiconductor device, when an excessive current called an overshoot current or a spike current inadvertently flows through the storage cell 120, a short circuit failure of the storage cell 120 may occur. Since the storage cell 120 having a short circuit failure allows the supplied current to flow through it, the leakage current of the entire semiconductor device may increase, which causes the operation of the normal storage cells to be interrupted. This is because when the leakage current increases, more current is required to operate the normal storage cells.

[0043] According to this embodiment of the present disclosure, even in the presence of defective storage cells, the undesired effects caused by the defective storage cells, such as an increase in the leakage current of the semiconductor device, can be prevented by blocking and / or reducing the current flowing through the defective storage cells. It is proposed that the embodiments of the present disclosure include a first variable resistance pattern 130 between each storage cell 120 and each second conductive line 140.

[0044] The first variable resistance pattern 130 may have variable resistance characteristics that switch between different resistance states according to the voltage or current applied to the first variable resistance pattern 130. The first variable resistance pattern 130 may switch between a low resistance state for providing an electrical connection to the memory cell 120 via the first variable resistance pattern 130 and a high resistance state for blocking the electrical connection to the memory cell 120 via the first variable resistance pattern 130. In the following description, the operation of changing the resistance state of the first variable resistance pattern 130 from the high resistance state to the low resistance state may be referred to as a set operation, and the voltage or current required for the first variable resistance pattern 130 for the set operation may be referred to as a set voltage or a set current. In the following description, the operation of changing the resistance state of the first variable resistance pattern 130 from the low resistance state to the high resistance state may be referred to as a reset operation, and the voltage or current required for the first variable resistance pattern 130 for the reset operation may be referred to as a reset voltage or a reset current. The first variable resistance pattern 130 may have a single-layer structure or a multi-layer structure including various materials used in RRAM, PRAM, FRAM, MRAM, etc. Example materials used in the first variable resistance pattern 130 may include, for example, metal oxides such as transition metal oxides, perovskite-based materials, phase change materials such as chalcogenide-based materials, or ferromagnetic materials, ferroelectric materials, etc.

[0045] In these embodiments, the magnitude of the set voltage or set current of the first variable resistance pattern 130 and the magnitude of the reset voltage or reset current may be greater than the magnitude of the operating voltage or operating current of the memory cell 120. This may prevent the resistance state of the first variable resistance pattern 130 from changing during the operation of the memory cell. Accordingly, it is possible to prevent a set / reset operation from being performed during the operation of the memory cell 120, which will be described later. Thus, when the memory cell 120 includes a second variable resistance pattern 127 as shown in Figure 1B or as shown in Figure 1CWhen the self-selective storage pattern 124 shown is selected, the magnitude of the set / reset voltage or set / reset current of the first variable resistance pattern 130 may be greater than the magnitude of the set / reset voltage or set / reset current required during the set / reset operation in which the resistance state of the second variable resistance pattern 127 or the self-selective storage pattern 124 is changed. This is because: the set / reset voltage or set / reset current of the second variable resistance pattern 127 or the self-selective storage pattern 124 corresponds to a part of the operating voltage or operating current. Since the set / reset voltage or set / reset current of the first variable resistance pattern 130 is different from the set / reset voltage or set / reset current of the second variable resistance pattern 127, the first variable resistance pattern 130 and the second variable resistance pattern 127 may have different materials or layer structures from each other. For example, the first variable resistance pattern 130 may include a phase change material, and the second variable resistance pattern 127 may include Figure 1D the magnetic tunnel junction structure described in. When the first variable resistance pattern 130 includes a phase change material, the low-resistance first variable resistance pattern 130 may have a crystalline state, while the high-resistance first variable resistance pattern 130 may have an amorphous state. The case where the amorphous phase change material changes to the crystalline phase change material may correspond to the set operation, and the case where the crystalline phase change material changes to the amorphous phase change material may correspond to the reset operation.

[0046] The first variable resistance pattern 130 may have a columnar shape stacked with each storage cell 120. For example, the first variable resistance pattern 130 may be patterned together with the storage cell 120 to have a cylindrical shape, wherein the sidewall of the first variable resistance pattern 130 is aligned with the storage cell 120. However, the present disclosure is not limited thereto, and as long as the first variable resistance pattern 130 has a columnar shape stacked with each storage cell 120, the sidewall of the first variable resistance pattern 130 does not have to be aligned with the sidewall of the storage cell 120, and the shape of the first variable resistance pattern 130 may also be changed differently. In this embodiment of the present disclosure, the first variable resistance pattern 130 is shown to be between the second conductive line 140 and the storage cell 120, but the present disclosure is not limited thereto. For another example, the first variable resistance pattern 130 may be between the first conductive line 110 and the storage cell 120. Additionally, for another example, the first variable resistance pattern 130 may be between the first conductive line 110 and the storage cell 120 and between the second conductive line 140 and the storage element 120.

[0047] When the first variable resistance pattern 130 is in a low resistance state, for example, when the first variable resistance pattern 130 includes a crystalline phase change material, it can be said that the storage cell 120 and the second conductive line 140 are electrically connected through the first variable resistance pattern 130. This is because the first variable resistance pattern 130 is in a low resistance state, and thus, current flows smoothly between the storage cell 120 and the second conductive line 140. On the other hand, when the first variable resistance pattern 130 is in a high resistance state, for example, when the first variable resistance pattern 130 includes an amorphous phase change material, it can be said that the storage cell 120 and the second conductive line 140 are resistively disconnected through the first variable resistance pattern 130. This is because the first variable resistance pattern 130 is in a high resistance state, and thus, the current flow between the storage cell 120 and the second conductive line 140 is significantly reduced or substantially blocked.

[0048] By coupling normal storage cells among the storage cells 120 to the first variable resistance pattern 130 in a low resistance state and coupling defective storage cells among the storage cells 120 to the first variable resistance pattern 130 in a high resistance state, the semiconductor device can normally perform operations of the normal storage cells without interruption while blocking and / or reducing the current flowing through the defective storage cells. A detailed description will be given below with reference to Figures 2A to 2C for details.

[0049] Figures 2A to 2C is a cross-sectional view showing Figure 1A various states of the semiconductor device shown.

[0050] Referring to Figure 2A , all of the storage cells 120 can correspond to normal storage cells 120'. All of the first variable resistance patterns 130 respectively coupled to the storage cells 120 can have a low resistance state LRS.

[0051] In this case, the storage cells 120 can operate normally according to the operation voltage or operation current applied through the first conductive line 110 and the second conductive line 140. When the storage cells 120 operate, the first variable resistance pattern 130 in the low resistance state LRS can act like a conductor, and thus the operation of the storage cells 120 can be uninterrupted. As described above, since the magnitude of the set / reset voltage or set / reset current of the first variable resistance pattern 130 is greater than the magnitude of the operation voltage or operation current of the storage cells 120, the low resistance state LRS of the first variable resistance pattern 130 can be maintained even when the storage cells 120 operate.

[0052] Referring to Figure 2B, at least one of the memory cells 120 may correspond to the defective memory cell 120″. For example, as shown in the figure, among the memory cells 120, the middle memory cell 120 may correspond to the defective memory cell 120″. A permanent conduction path CP may be generated in the defective memory cell 120″, resulting in a short circuit fault. Except for the defective memory cell 120″, the other memory cells among the memory cells 120 may correspond to the normal memory cells 120′. Here, all the first variable resistance patterns 130 respectively coupled to the memory cells 120 may have a low resistance state LRS.

[0053] The normal memory cell 120′ may operate normally according to the operation voltage or operation current applied through the first conductive wire 110 and the second conductive wire 140. Since the first variable resistance pattern 130 in the low resistance state LRS can act like a conductor, the operation of the normal memory cell 120′ may not be interrupted.

[0054] On the other hand, due to the presence of the permanent conduction path CP in the defective memory cell 120″, even if the operation voltage or operation current is applied to the defective memory cell 120″ through the first conductive wire 110 and the second conductive wire 140, normal operation cannot be performed in the defective memory cell 120″. In addition, due to the conduction path CP of the defective memory cell 120″, leakage current may occur between the first conductive wire 110 and the second conductive wire 140 through the defective memory cell 120″ and the first variable resistance pattern 130 in the low resistance state LRS. Therefore, as shown below Figure 2C shown, the first variable resistance pattern 130 coupled to the defective memory cell 120″ may need to have a high resistance state.

[0055] Reference Figure 2C , at least one of the memory cells 120, such as the middle memory cell 120, may correspond to the defective memory cell 120″ having a permanent conduction path CP. Except for the defective memory cell 120″, the other memory cells among the memory cells 120 may correspond to the normal memory cells 120′. The first variable resistance pattern 130 coupled to the defective memory cell 120″ may be in a high resistance state HRS, while the first variable resistance pattern 130 coupled to the normal memory cell 120′ may be in a low resistance state LRS.

[0056] The normal memory cell 120′ may operate normally according to the operation voltage or operation current applied through the first conductive wire 110 and the second conductive wire 140. Since the first variable resistance pattern 130 in the low resistance state LRS can act like a conductor, the operation of the normal memory cell 120′ may not be interrupted.

[0057] On the other hand, application of an operating voltage or an operating current to the defective memory cell 120″ can be prevented. Since the first variable resistance pattern 130 in the high resistance state HRS acts like an insulator, it can substantially block the electrical connection between the defective memory cell 120″ and the second conductive line 140. Since the defective memory cell 120″ is a memory cell that cannot operate normally, it is not actually used as a memory cell, and by using the first variable resistance pattern 130 in the high resistance state HRS, leakage current through the defective memory cell 120 can be blocked and / or reduced.

[0058] Figure 3 is a flowchart illustrating a method for operating a semiconductor device according to an embodiment of the present disclosure.

[0059] First, in step S301, before operating the memory cell 120, a set operation for changing the resistance states of all the first variable resistance patterns 130 to the low resistance state can be performed. When at least one of the first variable resistance patterns 130 is in the high resistance state before operating the memory cell 120, the set operation can be performed. When all the first variable resistance patterns 130 are in the low resistance state, step S301 can be omitted. In other words, step S301 can be selectively performed.

[0060] Subsequently, in step S303, various operations such as a programming operation and a reading operation can be performed on the memory cell 120. Here, since all the first variable resistance patterns 130 are in the low resistance state, the operation of the memory cell 120 can be uninterrupted. Since the operating voltage or operating current of the memory cell 120 is less than the set / reset voltage or set / reset current of the first variable resistance pattern 130, the low resistance state of the first variable resistance pattern 130 can be maintained in step S303.

[0061] Subsequently, in step S305, a verification operation can be performed to determine whether there is a defective memory cell 120 in which a defect such as a short circuit fault has occurred in step S303. Whether a short circuit fault has occurred in the memory cell 120 can be determined by comparing the current flowing through the memory cell 120 with a predetermined reference current. The voltage or current applied to the memory cell 120 during the verification operation can be the same as or similar to the voltage or current applied during the reading operation. Therefore, even during the verification operation, the resistance state of the first variable resistance pattern 130 can be maintained. The verification operation can be performed in a section that does not overlap with the programming operation and / or the reading operation of the memory cell 120. For example, as shown in the figure, the verification operation can be performed after the programming / reading operation of the memory cell 120.

[0062] When it is determined that a short - circuit fault has occurred in the memory cell 120, for example, when the current flowing through the memory cell 120 is greater than a predetermined reference current, a reset operation of changing the low - resistance state of the first variable - resistance pattern 130 to a high - resistance state can be performed in step S307. This operation can be performed only on the first variable - resistance pattern 130 coupled to the memory cell 120 in which the short - circuit fault has occurred. In other words, a reset voltage or a reset current can be applied to the first variable - resistance pattern 130 coupled to the memory cell 120 in which the short - circuit fault has occurred through the first conductive line 110 and the second conductive line 140 coupled to the memory cell 120 in which the short - circuit fault has occurred. The low - resistance state can be maintained by preventing the reset operation on the first variable - resistance pattern 130 coupled to the normal memory cell 120'. To this end, the first conductive line 110 and the second conductive line 140 coupled to the normal memory cell 120' can be in a floating state, or a ground voltage can be applied to them.

[0063] Conversely, when it is determined that no short - circuit fault has occurred in the memory cell 120, for example, when the current flowing through the memory cell 120 is less than a predetermined reference current, there is no need to perform a reset operation or the like, and the process can be ended.

[0064] The above steps S305 and S307 can be repeatedly performed at a predetermined interval. For example, whenever the programming operation and / or the reading operation of the memory cell 120 is performed a predetermined number of times, steps S305 and S307 can be performed. In addition, for example, whenever a predetermined time has elapsed, steps S305 and S307 can be performed.

[0065] According to an embodiment of the present disclosure, by preventing defects such as leakage current, a semiconductor device and its operation method can have improved operation characteristics.

[0066] Although the present disclosure has been described with respect to specific embodiments, various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of first conductive lines extending along a first direction; a plurality of second conductive lines disposed to be spaced apart from the plurality of first conductive lines in a third direction and extending in a second direction intersecting the first direction; a plurality of memory cells, the plurality of memory cells overlapping intersection regions between the plurality of first conductive lines and the plurality of second conductive lines; as well as A plurality of first variable resistance patterns are respectively coupled in series to the plurality of storage cells, each storage cell corresponds to a first variable resistance pattern, so that each first variable resistance pattern and the corresponding storage cell are connected between a corresponding first conductive line among the plurality of first conductive lines and a corresponding second conductive line among the plurality of second conductive lines.

2. The semiconductor device according to claim 1, wherein: Among the plurality of first variable resistance patterns, a first variable resistance pattern coupled in series to a defective memory cell having a short failure among the plurality of memory cells has a high resistance state among different resistance states of the first variable resistance pattern.

3. The semiconductor device according to claim 1, wherein: Among the plurality of first variable resistance patterns, a first variable resistance pattern coupled in series to a normal memory cell having no short failure among the plurality of memory cells has a low resistance state among different resistance states of the first variable resistance pattern.

4. The semiconductor device according to claim 1, wherein: A magnitude of a voltage or a current required to change a resistance state of each first variable resistance pattern is greater than a magnitude of an operating voltage or an operating current required by a memory cell of the plurality of memory cells during a program operation or a read operation.

5. The semiconductor device according to claim 1, wherein: During a program operation or a read operation of a memory cell among the plurality of memory cells, a resistance state of the first variable resistance pattern remains unchanged.

6. The semiconductor device according to claim 1, wherein: The first variable resistance pattern includes a phase change material.

7. The semiconductor device according to claim 6, wherein: A memory cell of the plurality of memory cells includes a magnetic tunnel junction structure.

8. The semiconductor device according to claim 1, wherein: A memory cell of the plurality of memory cells further includes a second variable resistance pattern exhibiting different resistance states for storing data for the memory cell.

9. The semiconductor device according to claim 8, wherein: A voltage or current required to change the resistance state of the first variable resistance pattern is greater than a voltage or current required to change the resistance state of the second variable resistance pattern.

10. The semiconductor device according to claim 2, wherein: The defective memory cell includes a permanent conductive path that allows current to pass through the defective memory cell.

11. The semiconductor device according to claim 3, wherein: The normal memory cell is electrically connected to one of the plurality of first conductive lines or one of the plurality of second conductive lines through the first variable resistance pattern having the low resistance state.

12. The semiconductor device according to claim 2, wherein: The defective memory cell is electrically disconnected from the first conductive line or the second conductive line by the first variable resistance pattern having a high resistance state.

13. A method for operating a semiconductor device, in, The semiconductor device comprises: A plurality of first conductive lines extending along a first direction; a plurality of second conductive lines disposed to be spaced apart from the plurality of first conductive lines in a third direction and extending in a second direction intersecting the first direction; a plurality of memory cells overlapping intersection regions between the plurality of first conductive lines and the plurality of second conductive lines; and a plurality of first variable resistance patterns, the plurality of first variable resistance patterns being formed to be connected in series with the plurality of memory cells, respectively, each memory cell corresponding to one first variable resistance pattern, so that each first variable resistance pattern and the corresponding memory cell are connected between a corresponding first conductive line among the plurality of first conductive lines and a corresponding second conductive line among the plurality of second conductive lines, Wherein, the method comprises: determining whether there is a defective memory cell having a short circuit failure among the plurality of memory cells; and In response to determining that a defective memory cell exists, a reset operation is performed so that the first variable resistance pattern coupled to the defective memory cell exhibits a high resistance state to block an electrical connection with the defective memory cell.

14. The method of claim 13, wherein: The determining step and the executing step are performed at a different time than when a program operation or a read operation is performed on a memory cell among the plurality of memory cells.

15. The method of claim 14, wherein: During the programming operation or the reading operation of the memory cell, a resistance state of the first variable resistance pattern remains unchanged.

16. The method of claim 14, wherein: A magnitude of a reset voltage or a reset current required during the reset operation is greater than a magnitude of an operating voltage or an operating current required during the program operation or the read operation.

17. The method according to claim 14, further comprising: Before performing the programming operation or the reading operation, A set operation is performed so that a first variable resistance pattern coupled to each of the plurality of memory cells exhibits a low resistance state.

18. The method of claim 17, wherein: A magnitude of a set voltage or a set current required during the set operation is greater than a magnitude of an operating voltage or an operating current required during the program operation or the read operation.

19. The method of claim 13, wherein: The step of determining whether there is a defective memory cell among the plurality of memory cells comprises: comparing a current flowing through each of the plurality of memory cells with a reference current; and A memory cell through which a current greater than the reference current flows is determined as the defective memory cell.

20. The method of claim 19, wherein: A memory cell through which a current smaller than the reference current flows is determined as a normal memory cell.

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