Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel makes the overlapping area of ​​one clock signal line and all corresponding vias in a repeating unit equal to the overlapping area of ​​the other clock signal line and all corresponding vias in a repeating unit. Furthermore, the overlapping area of ​​any clock signal line and a via in a repeating unit is equal to the product of the width of the clock signal line, the width of the via, and the number of vias in a column within the repeating unit. This ensures that when the position of the vias shifts, the overlapping area of ​​any clock signal line and the via remains unchanged, and the overlapping areas of each clock signal line and via are equal. This makes the parasitic capacitance of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance changes in the clock signal lines, thus enabling the display panel to display normally.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used due to their advantages such as self-emission, wide color gamut, low power consumption, and the ability to achieve flexible displays. OLED displays employ GOA (Gate Driver On Array) technology to reduce bezels. To release moisture within the organic layer of the GOA region and reduce its impact on the electrical performance of the device, existing OLED displays feature a trench design on the large metal area above the organic layer. Specifically, existing OLED displays trench the metal of the anode layer on the clock signal lines, with one trench located on the first and second clock lines, and another trench located on the third and fourth clock lines, ensuring that the trench areas on each clock line are equal. However, during the actual fabrication process, mask misalignment can occur during the trenching of the anode layer, causing the trench to shift relative to the clock line. This results in different overlap areas between different clock lines and the trench, altering the parasitic capacitance between the clock lines and the metal of the anode layer. Consequently, the total impedance of the clock lines changes, affecting their signal delay. Furthermore, the changing trends between adjacent clock lines are opposite, leading to increased differences in signal delay between different clock lines and impacting signal output.

[0003] Therefore, existing OLED display devices have a technical problem where the clock line is offset due to a slot offset, resulting in excessive changes in the parasitic capacitance of the clock line, which affects the display. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the technical problem in existing OLED display devices where the clock line is offset due to the clock line's slot, resulting in excessive changes in the parasitic capacitance of the clock line and affecting the display.

[0005] This application provides a display panel, which includes a display area and a driving circuit area disposed on at least one side of the display area. The display panel includes:

[0006] Multiple clock signal lines are disposed within the driving circuit area, and the multiple clock signal lines extend along a first direction;

[0007] A low-potential signal line is disposed within the driving circuit area, and the orthogonal projection of multiple clock signal lines onto the low-potential signal line is located within the low-potential signal line.

[0008] The low-potential signal line has multiple vias, and the via array is configured to form multiple repeating units. Within each repeating unit, the number of vias in each column is the same. In any two clock signal lines, the overlap area of ​​one clock signal line and all corresponding vias in a repeating unit is equal to the overlap area of ​​another clock signal line and all corresponding vias in a repeating unit. Furthermore, the overlap area of ​​any clock signal line and corresponding vias in a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the via in the first direction, and the number of vias in a column within a repeating unit. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0009] In some embodiments, each column of through holes is arranged along the first direction, and there is a spacing between adjacent rows of through holes in the first direction.

[0010] In some embodiments, the number of columns of vias is equal to the number of clock signal lines, each column of vias corresponds to each clock signal line, the vias are symmetrically arranged about the center line of the clock signal line, and the distance between the end of the via corresponding to one clock signal line and the other clock signal line is greater than or equal to the maximum offset of the via, and the width of the via extending beyond the clock signal line is greater than or equal to the maximum offset of the via.

[0011] In some embodiments, the width of the via is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

[0012] In some embodiments, the spacing between adjacent clock signal lines is greater than the sum of the maximum offset of the via and half the width of the portion of the via extending beyond the clock signal line.

[0013] In some embodiments, each column of vias is provided in a one-to-one correspondence with each clock signal line. Within the repeating unit, the minimum distance between the two ends of the vias and the corresponding clock signal lines is not equal. In any two clock signal lines, one end of each via is equal to the minimum distance between the corresponding clock signal line, and the other end of each via is equal to the minimum distance between the corresponding clock signal line.

[0014] In some embodiments, each column of vias is provided in a one-to-one correspondence with each clock signal line, with one end of the via corresponding to one clock signal line aligned with one end of the clock signal line, and the other end of the via aligned with one end of another clock signal line.

[0015] In some embodiments, the minimum distance between the left end of the through hole and the corresponding clock signal line is greater than the minimum distance between the right end of the through hole and the corresponding clock signal line; or the minimum distance between the left end of the through hole and the corresponding clock signal line is less than the minimum distance between the right end of the through hole and the corresponding clock signal line.

[0016] In some embodiments, the via includes a first via corresponding to two adjacent clock signal lines and a second via corresponding to one clock signal line. Along a first direction, in two adjacent columns of vias, one end of one column of vias closer to the other column of vias is on the same straight line as one end of the other column of vias.

[0017] In some embodiments, the first via is symmetrically arranged about the center line of the portion of the low-potential signal line located between two adjacent clock signal lines, and the width of the portion of the second via extending beyond the clock signal line is greater than the maximum offset of the via.

[0018] In some embodiments, the via is located at one end of one clock signal line and one end of the via corresponding to another clock signal line, respectively, on the center line of the two clock signal lines.

[0019] In some embodiments, among the first vias and second vias corresponding to the same clock signal line, the overlap area between one second via and the corresponding clock signal line is less than the overlap area between one first via and the corresponding clock signal line, the overlap area between another second via and the corresponding clock signal line is greater than the overlap area between another first via and the corresponding clock signal line, and the overlap area between any first via and the corresponding two adjacent clock signal lines is not equal.

[0020] In some embodiments, the display panel includes two sets of first scanning drive units arranged symmetrically, each set of first scanning drive units includes four clock signal lines, and the through holes include two columns of second through holes and three columns of first through holes, with the three columns of first through holes located between the two columns of second through holes.

[0021] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0022] Beneficial Effects: This application provides a display panel and a display device. The display panel includes a display area and a driving circuit area disposed on at least one side of the display area. The display panel includes multiple clock signal lines and low-potential signal lines. The clock signal lines are disposed in the driving circuit area and extend along a first direction. The low-potential signal lines are disposed within the driving circuit area, and the orthographic projection of the multiple clock signal lines onto the low-potential signal lines is located within the low-potential signal lines. Multiple through-holes are formed on the low-potential signal lines. The through-hole array is configured to form multiple repeating units. In each repeating unit, the number of through-holes in each column is the same. In any two clock signal lines, the overlap area of ​​one clock signal line and all corresponding through-holes in a repeating unit is equal to the overlap area of ​​another clock signal line and all corresponding through-holes in a repeating unit. The overlap area of ​​any clock signal line and a corresponding through-hole in a repeating unit is equal to the product of the width of the clock signal line in a second direction, the length of the through-hole in the first direction, and the number of through-holes in a column in a repeating unit. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. This application ensures that, for any two clock signal lines, the overlapping area of ​​one clock signal line and all corresponding vias within a repeating unit is equal to the overlapping area of ​​the other clock signal line and all corresponding vias within a repeating unit. Furthermore, the overlapping area of ​​any clock signal line and a via within a repeating unit is equal to the product of the width of the clock signal line, the width of the via, and the number of vias in a column within a repeating unit. This ensures that when the position of the vias shifts, the overlapping area of ​​any clock signal line and the via remains unchanged, and the overlapping area of ​​each clock signal line and via is equal. This makes the parasitic capacitance of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance variations in the clock signal lines, thus ensuring normal display on the display panel. Attached Figure Description

[0023] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the existing display device when the slots for the clock line and low-potential power signal line are not offset.

[0025] Figure 2 for Figure 1 A schematic diagram showing the offset of the slots for the clock line and low-potential power signal line in the circuit.

[0026] Figure 3 for Figure 1 A bar chart showing the offset of the slots for the clock line and low-potential power signal line in relation to the change in parasitic capacitance of the clock signal line.

[0027] Figure 4This is a first schematic diagram of a display panel provided in an embodiment of this application.

[0028] Figure 5 This is a second schematic diagram of a display panel provided in an embodiment of this application.

[0029] Figure 6 This is a third schematic diagram of a display panel provided in an embodiment of this application.

[0030] Figure 7 This is a fourth schematic diagram of a display panel provided in an embodiment of this application.

[0031] Figure 8 This is a first schematic diagram showing that the vias of the clock signal line and the low-potential signal line provided in this application embodiment are not offset.

[0032] Figure 9 for Figure 8 A schematic diagram showing the offset between the positions of the clock signal line and the via in the low-potential signal line.

[0033] Figure 10 for Figure 8 A bar chart showing the offset of the vias in the clock signal line and the low-potential signal line, and the change in the parasitic capacitance of the clock signal line.

[0034] Figure 11 This is a second schematic diagram showing the clock signal line and the low-potential signal line vias provided in an embodiment of this application when they are not offset.

[0035] Figure 12 for Figure 11 A schematic diagram showing the position of the via in the provided clock signal line and the low-potential signal line being offset.

[0036] Figure 13 for Figure 11 A bar chart showing the offset of the vias in the provided clock signal line and low-potential signal line, and the change in the parasitic capacitance of the clock signal line. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0040] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0041] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0042] like Figure 1 As shown, Figure 1 (a) in the diagram is a stack-up diagram of the low-potential power supply signal line and the clock line. Figure 1 (b) in the middle is Figure 1 An exploded view of the low-potential power supply signal line in (a) of the diagram. Figure 1 (c) in the middle is Figure 1 A breakdown diagram of the clock lines in (a) of the image. Figure 1 As can be seen, existing OLED display devices, in order to release moisture from the organic layer in the gate driving circuit region, will create a trench in the corresponding region of the clock line for the low-potential power signal line 12 of the anode layer. Specifically, as shown... Figure 1 As shown, in theory, one row of slots 121 is located on the first clock line 111 and the second clock line 112, and another row of slots 121 is located on the third clock line 113 and the fourth clock line 114. However, in the actual fabrication process, due to the misalignment between the mask and the anode layer, the slots may shift.

[0043] like Figure 2 As shown, Figure 2 (a) in the diagram is a schematic of the OLED display device when the notch is shifted 3 micrometers to the left. Figure 2 (b) in the diagram is a schematic of the OLED display device when the notch is offset 2 micrometers to the left. Figure 2 (c) in the diagram is a schematic of the OLED display device when the notch is offset to the left by 1 micrometer. Figure 2 (d) in the diagram is a schematic of the OLED display device when the notch is offset to the right by 1 micrometer. Figure 2 (e) in the diagram is a schematic of the OLED display device when the notch is offset 2 micrometers to the right. Figure 2 (f) in the diagram is a schematic of the OLED display device when the notch is offset 3 micrometers to the right. Figure 2 As can be seen, when the slot shifts, the overlap area between two adjacent clock lines and the slot changes. The different overlap areas between two adjacent clock lines and the slot cause the parasitic capacitance between the clock lines and the low-potential power signal lines to change.

[0044] like Figure 3 As shown, Figure 3 In (a), -3 on the x-axis indicates that the trench has shifted 3 micrometers to the left, and 3 indicates that the trench has shifted 3 micrometers to the right. Similarly, other values ​​and... Figure 3 The values ​​in (b) can be found in the above explanation. Figure 3 In the figure, (a) represents the change in parasitic capacitance of each clock line and low-potential power supply signal line at different offsets. Figure 3 In (a) of the diagram, the horizontal axis represents the offset between the clock line and the low-potential power signal line, and the vertical axis represents the change in the parasitic capacitance of the clock line and the low-potential power signal line compared to when the clock line and the low-potential power signal line are not offset. Figure 3 The bar chart shows the changes in parasitic capacitance between different clock lines and low-potential power signal lines. CK1-ANO represents the change in parasitic capacitance between the first clock line and the low-potential power signal line, CK2-ANO represents the change in parasitic capacitance between the second clock line and the low-potential power signal line, CK3-ANO represents the change in parasitic capacitance between the third clock line and the low-potential power signal line, and CK4-ANO represents the change in parasitic capacitance between the fourth clock line and the low-potential power signal line. Figure 3 (b) in the figure represents the change in parasitic capacitance of each clock line and all signal lines at different offsets. Figure 3 In (b) of the diagram, the horizontal axis represents the offset between the clock line and the low-potential power signal line, and the vertical axis represents the change in parasitic capacitance of the clock line and all signal lines compared to when the clock line and the low-potential power signal line have no offset. Figure 3 The bar chart in the figure represents the change in parasitic capacitance between different clock lines and all signal lines. CK1-Total represents the change in parasitic capacitance between the first clock line and all signal lines, CK2-Total represents the change in parasitic capacitance between the second clock line and all signal lines, CK3-Total represents the change in parasitic capacitance between the third clock line and all signal lines, and CK4-Total represents the change in parasitic capacitance between the fourth clock line and all signal lines.

[0045] from Figure 2 and Figure 3As can be seen, compared to when the notches on the clock lines and low-potential power signal lines are not offset, when the low-potential power signal lines are misaligned with the mask, causing the notches on the low-potential power signal lines to shift relative to the clock lines, the parasitic capacitance between each clock line and the low-potential power signal line changes. Furthermore, the trends of these changes in parasitic capacitance between adjacent clock lines and the low-potential power signal lines are opposite. For example, the trends of these changes in parasitic capacitance between the first clock line 111 and the second clock line 112 and the low-potential power signal line 12 are opposite. This leads to an increase in the signal delay difference between different clock lines. Understandably, because of the change in parasitic capacitance between the clock lines and the low-potential power signal lines, the electrical signal output by the clock lines does not match the preset electrical signal, and the increased signal delay difference between different clock lines results in different turn-on times or turn-on voltages for different transistors, affecting the display effect. Therefore, existing OLED display devices suffer from the technical problem of excessive changes in parasitic capacitance on the clock lines due to notch offset, which affects the display.

[0046] This application provides a display panel and a display device to address the aforementioned technical problems.

[0047] Figure 4 This is a first schematic diagram of a display panel provided in an embodiment of this application. Figure 5 This is a second schematic diagram of a display panel provided in an embodiment of this application. Figure 6 This is a third schematic diagram of a display panel provided in an embodiment of this application. Figure 7 This is a fourth schematic diagram of a display panel provided in an embodiment of this application. Figure 8 This is a first schematic diagram showing that the vias of the clock signal line and the low-potential signal line provided in this application embodiment are not offset. Figure 9 for Figure 8 A schematic diagram showing the offset between the positions of the clock signal line and the via in the low-potential signal line. Figure 10 for Figure 8 A bar chart showing the offset of the vias in the clock signal line and the low-potential signal line, and the change in the parasitic capacitance of the clock signal line. Figure 11 This is a second schematic diagram showing the clock signal line and the low-potential signal line vias provided in an embodiment of this application when they are not offset. Figure 12 for Figure 11 A schematic diagram showing the position of the via in the provided clock signal line and the low-potential signal line being offset. Figure 13 for Figure 11 A bar chart showing the offset of the vias in the provided clock signal line and low-potential signal line, and the change in the parasitic capacitance of the clock signal line.

[0048] like Figures 4 to 13As shown, this application embodiment provides a display panel 2, which includes a display area 21 and a driving circuit area 221 disposed on at least one side of the display area 21. The display panel 2 includes:

[0049] Multiple clock signal lines 41 are disposed in the driving circuit area 221, and the multiple clock signal lines 41 extend along the first direction X;

[0050] A low-potential signal line 42 is disposed within the driving circuit area 221, and the orthogonal projections of multiple clock signal lines 41 onto the low-potential signal line 42 are located within the low-potential signal line 42.

[0051] The low-potential signal line 42 has multiple through holes 421, and the array of through holes 421 forms multiple repeating units 40. Within each repeating unit 40, the number of through holes 421 in each column is the same (e.g., Figure 8 In each repeating unit 40, the number of vias in each column is 1. In any two clock signal lines 41, the overlapping area of ​​all the vias 421 corresponding to one clock signal line 41 and one repeating unit 40 is equal to the overlapping area of ​​all the vias 421 corresponding to the other clock signal line 41 and one repeating unit 40 (e.g., in...). Figure 8 In the above, the overlap area between the first clock signal line 311 and all the corresponding vias 421 within a repeating unit 40 is L4*L1*1, and the overlap area between the second clock signal line 312 and all the corresponding vias 421 within a repeating unit 40 is L4*L1*1 (both are equal). Furthermore, the overlap area between any clock signal line 41 and the corresponding via 421 within a repeating unit 40 is equal to the product of the width L1 of the clock signal line 41 in the second direction Y, the length L4 of the via 421 in the first direction X, and the number of vias 421 in a column within a repeating unit 40 (e.g., in...). Figure 8 In the above, the overlapping area of ​​the first clock signal line 311 and all the corresponding through holes 421 in a repeating unit 40 is L4*L1*1); the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0052] This application provides a display panel that ensures that the overlapping area of ​​one clock signal line and all corresponding vias within a repeating unit is equal to the overlapping area of ​​the other clock signal line and all corresponding vias within a repeating unit. Furthermore, the overlapping area of ​​any clock signal line and a via within a repeating unit is equal to the product of the width of the clock signal line, the width of the via, and the number of vias in a column within the repeating unit. This ensures that when the position of the vias shifts, the overlapping area of ​​any clock signal line and the via remains unchanged, and the overlapping areas of each clock signal line and via are equal. This makes the parasitic capacitance of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance variations in the clock signal lines, thus enabling the display panel to display normally.

[0053] Specifically, in the accompanying drawings of this application, the number of through holes in each column of the repeating unit 40 is 1, but the embodiments of this application are not limited to this. For example, the number of through holes in each column of the repeating unit 40 is 2.

[0054] Specifically, such as Figure 4 As shown, the display panel 2 includes a display area 21 and a non-display area 22. The non-display area 22 includes a driving circuit area 221 and a bonding area 222. The driving circuit area 221 is provided with a gate driving circuit, such as... Figure 5 As shown, the gate driving circuit includes a first scan driving unit 31, a second scan driving unit 32, a third scan driving unit 34, and a signal control unit 33. The first scan driving unit 31 and the signal control unit 33 can be disposed in the driving circuit area 221 on both sides of the display area 21. The first scan driving unit 31 includes a clock signal line 41.

[0055] Specifically, the low-potential signal line 42 refers to the low-potential power supply signal line connected to the light-emitting device of the display panel. After connecting to the common electrode of the display panel, this low-potential signal line 42 is transferred through the pixel electrode layer 521 and then connected to the signal line of the second source-drain layer 517 for signal input (other parts of the low-potential signal line 42 are not shown in the figure). Therefore, in Figure 7 In the pixel electrode layer 521, a portion is a low-potential signal line 42, which does not contact the pixel electrode in the pixel electrode layer 521.

[0056] Specifically, such as Figure 5 , Figure 8 As shown, the multiple clock signal lines 41 include a first clock signal line 311, a second clock signal line 312, a third clock signal line 313, and a fourth clock signal line 314. The width of each clock signal line 41 is equal, and the spacing between adjacent clock signal lines 41 is equal.

[0057] Specifically, such as Figure 7As shown, the clock signal line 41 will be routed in parallel using the second source-drain layer 517 and the third source-drain layer 519.

[0058] In some embodiments, such as Figure 8 As shown, each column of the through holes 421 is arranged along the first direction X, and there is a gap between adjacent rows of through holes 421 in the first direction X. By making adjacent columns of through holes alternate vertically in the direction of the clock signal line, the through holes on each clock signal line are more evenly distributed, which can release moisture in each area and improve the performance of the display panel.

[0059] Specifically, Figure 8 (a) in the diagram is the first overlay diagram of clock signal line 41 and low-level signal line 42. Figure 8 (b) in the middle is Figure 8 The exploded view of the low-potential signal line 42 in (a) is shown below. Figure 8 (c) in the middle is Figure 8 The exploded view of clock signal line 41 in (a) is shown.

[0060] Specifically, it is understandable that Figure 8 and Figure 9 The accompanying drawings may represent the designs within different display panels during the actual manufacturing process.

[0061] Specifically, it can be seen that within adjacent columns of vias, in the direction of the clock signal lines, one column of vias is shifted downwards relative to the other column, making the vias on each clock signal line more evenly distributed. This releases moisture from each area and prevents moisture intrusion that could alter the performance of the thin-film transistor. However, the embodiments of this application are not limited to this; adjacent columns of vias can be made to contact each other in the direction of the clock signal lines.

[0062] In some embodiments, the left end of the leftmost via extends beyond the leftmost clock signal line, and the right end of the rightmost via extends beyond the rightmost clock signal line. Half the width of the portion of the via extending beyond the clock signal line is greater than the maximum offset of the via. By ensuring that the vias overlap with each clock signal line, and that half the width of the portion extending beyond the clock signal line is greater than the maximum offset of the via, the overlapping area between the via and any clock signal line is equal when the via's position shifts. This results in a smaller variation in the parasitic capacitance between each clock signal line and the low-potential signal line, and the variation in parasitic capacitance between adjacent clock signal lines and low-potential signal lines is similar or even the same. This avoids excessive variation in parasitic capacitance between clock signal lines and low-potential signal lines, which could lead to display defects, and also avoids excessive differences in parasitic capacitance between different clock signal lines and low-potential signal lines, further preventing display defects.

[0063] Specifically, such as Figure 8 As shown, the left end of the leftmost through-hole 421 extends beyond the leftmost clock signal line. Figure 8 The first clock signal line 311 is located in the middle, and the right end of the through hole 421 located on the far right extends beyond the rightmost clock signal line. Figure 8 The second clock signal line 314 is provided in the middle, and the width of the portion of the through hole 421 extending beyond the clock signal line 41 is greater than half of the maximum offset of the through hole 421, so as to... Figure 8 For example, half the width of the portion of the via 421 that extends beyond the clock signal line 41 is (L3-L1) / 2. If this value is greater than the maximum offset of the via, then the overlap area between the via and any clock signal line can be equal.

[0064] Specifically, in the embodiments of this application, a via in an unoffset state means that the via is located at the theoretically designed position and there is no alignment offset between the mask and the pixel electrode layer. A via in an offset state means that the via is located at a non-theoretically designed position and there is an alignment offset between the mask and the pixel electrode layer, resulting in an offset of the via's position.

[0065] Specifically, the maximum offset of a via refers to the maximum lateral offset of the via relative to its designed position during the actual fabrication process. For example, in the design, the center line of the via coincides with the center line of the clock signal line. However, in the actual fabrication process, the maximum rightward offset of the center line of the via relative to the center line of the clock signal line is 3 micrometers. Considering that the maximum offset to both sides is equal when the via is offset, the maximum offset of the via is 3 micrometers. However, when the offset to both sides is unequal when the via is offset, the maximum offset of the via is taken as the offset to one side that is greater.

[0066] In some embodiments, such as Figure 8 As shown, the number of columns of vias 421 is equal to the number of clock signal lines 41. Each column of vias 421 corresponds one-to-one with each clock signal line 41. The vias 421 are symmetrically arranged about the center line of the clock signal lines 41. The distance between the end of the via 421 corresponding to one clock signal line 41 and the other clock signal line 41 is greater than or equal to the maximum offset of the via 421. The width of the portion of any via 421 that extends beyond the clock signal line 41 (e.g., in...) Figure 8 The offset of (L3-L1) / 2) is greater than or equal to the maximum offset of the through hole 421.

[0067] Specifically, when designing the relative positions of vias and clock signal lines, the vias can be kept in an unoffset state, or in the actual product, the vias can be symmetrical about the center line of the clock signal line. This ensures that even if the vias are offset relative to the clock signal line during the actual manufacturing process, the width of the portion of the via extending beyond the clock signal line on either side is greater than or equal to the maximum offset of the via, and the distance between the end of the via closest to another clock signal line and that other clock signal line is greater than or equal to the maximum offset of the via. Therefore, the overlap area between the clock signal line and the corresponding via does not change. This results in a small or even no change in the parasitic capacitance between the clock signal line and the low power signal line, a small or even no change in the impedance of the clock signal line, and a small or even equal difference in the impedance of any two clock signal lines, avoiding display defects caused by impedance differences between different clock signal lines.

[0068] Specifically, such as Figure 8 As shown, the number of columns of vias 421 is 4, and the number of clock signal lines 41 is 4, both equal. This ensures that each column of vias 421 corresponds one-to-one with each clock signal line 41, and the vias 421 are symmetrically arranged about the center line of the clock signal line 41. The widths of the two portions of the vias 421 extending beyond the clock signal line 41 are equal, and the distance between the via 421 corresponding to each clock signal line 41 and another clock signal line 41 is greater than or equal to the maximum offset of the via 421. For example, the distance between the via 421 corresponding to the first clock signal line 311 and the second clock signal line 312 is greater than the maximum offset of the via 421. This prevents the via corresponding to the first clock signal line from shifting to the second clock signal line, thus maintaining the overlap area between each clock signal line and the via. Furthermore, the width of the portion of the via extending beyond the clock signal line 41 on either side is greater than or equal to the maximum offset of the via 421. For example... Figure 8 The width of the through hole extending beyond the first clock signal line 311 on the right side is greater than the maximum offset of the through hole 421.

[0069] Specifically, by setting each column of vias to correspond one-to-one with the clock signal lines, and when the vias are in an unoffset state, the vias are symmetrically arranged about the clock signal lines, and the distance between the end of the via corresponding to one clock signal line and the other clock signal line is greater than or equal to the maximum offset of the via, and the width of the via extending beyond the clock signal line is greater than the maximum offset of the via, the vias will not shift to another clock signal line when offset occurs. Furthermore, the overlap area between a single via and its corresponding clock signal line remains the product of the length of the via and the width of the clock signal line, ensuring that the overlap area between the via and the clock signal line does not change. This results in a small or even no change in the parasitic capacitance between the clock signal line and the low power signal line, a small or even no change in the impedance of the clock signal line, and a small or even equal difference in the impedance of any two clock signal lines, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0070] Specifically, the above embodiments are illustrated using the example of a via being symmetrical about the center line of a clock signal line. However, the embodiments of this application are not limited to this. For example, when the via is in an unoffset state, i.e. in theoretical design or in actual products, the via may not be symmetrical about the center line of the clock signal line. However, the distance between the two ends of the via and other clock signal lines is greater than or equal to the maximum offset of the via, and the width of the portion of the via that extends beyond the corresponding clock signal line is greater than or equal to the maximum offset of the via. This ensures that the via will not be offset to another clock signal line, and the overlapping area between the via and the corresponding clock signal line does not change.

[0071] For example, the leftmost via is not symmetrical about the center line of the first clock signal line 311, but the width of the portion of the leftmost via extending beyond the first clock signal line 311 on either side is greater than or equal to the maximum offset of the via, and the distance between the two sides of the via and other clock signal lines is greater than or equal to the maximum offset of the via. For example, the width of the portion of the via extending beyond the first clock signal line 311 on the left is 4, and the width of the portion of the via extending beyond the first clock signal line 311 on the right is 3, but both are greater than the maximum offset of the via. This makes the overlapping area of ​​the first clock signal line and the via equal to the overlapping area of ​​other clock signal lines and the via.

[0072] In some embodiments, such as Figure 8As shown, the width L3 of the via 421 is equal to the sum of the width L1 of the clock signal line 41 and the spacing L2 between adjacent clock signal lines 41. By making the width of the via equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines, and by symmetrically arranging the vias about the clock signal lines, the width of the via extending beyond the clock signal line is greater than or equal to the maximum offset of the via. Therefore, the two parts of the via extending beyond the clock signal line are symmetrical about the clock signal line, and in two adjacent columns of vias, the right end of one column is aligned with the left end of the other column. This ensures that when the vias are offset, whether to the left or right, the overlap area between the clock signal line and the via remains unchanged. Furthermore, the overlap area between each clock signal line and the via is close to or even equal, resulting in minimal or no impedance change in each clock signal line. Additionally, the impedance difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0073] Specifically, taking a clock signal line width of 8 micrometers and an adjacent clock signal line spacing of 6 micrometers as an example, and a via width of 14 micrometers and a length of 14 micrometers, the width of the via extending beyond the clock signal line is 3 micrometers. Taking a maximum via offset of 3 micrometers as an example, regardless of whether the via is offset to the left or right, the overlap area between a single via and a clock signal line remains 14 micrometers * 8 micrometers, and the overlap area between each clock signal line and the via is the same. Therefore, the impedance change difference between each clock signal line is small (the change may be caused by the offset of the via position, resulting in a slight change in the electrical properties of each signal line, causing the impedance change of the clock signal line) or even does not change, avoiding display defects caused by impedance changes of the clock signal lines. Furthermore, the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0074] In some embodiments, such as Figure 8 As shown, the spacing L2 between adjacent clock signal lines 41 is greater than the sum of the maximum offset of the via 421 and half the width of the portion of the via extending beyond the clock signal line 41. By making the spacing between adjacent clock signal lines greater than the sum of the maximum offset of the via and half the width of the portion of the via extending beyond the clock signal line, even if the via is offset during actual fabrication, it will not offset onto adjacent clock signal lines. Furthermore, the width of the via extending beyond the clock signal line is greater than or equal to the maximum offset of the via. This ensures that the overlap area between the clock signal lines and the vias remains unchanged, and the overlap areas of each clock signal line and the vias are close to or even equal. This results in minimal or no impedance change in each clock signal line, and the impedance difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0075] Specifically, taking an 8-micrometer spacing between adjacent clock signal lines, a 3-micrometer maximum offset of the via, and an 8-micrometer width of the via extending beyond the clock signal line as an example, the spacing between adjacent clock signal lines is greater than the sum of the maximum offset of the via and half the width of the via extending beyond the clock signal line. Therefore, when the via is offset, it will not shift to other clock signal lines, and the overlap area between the via and the clock signal line remains unchanged.

[0076] Specifically, the above embodiments are illustrated using the example of a via being symmetrical about the centerline of a clock signal line. However, the embodiments of this application are not limited to this. For example, when the via is in an unoffset state, the width of the portion of the via extending beyond the clock signal line on either side is greater than or equal to the maximum offset of the via. The spacing between adjacent clock signal lines is greater than or equal to the sum of the maximum offset of the via and the maximum width of the portion of the via extending beyond the clock signal line. For instance, if the widths of the two portions of the via extending beyond the clock signal line are unequal, with one portion having a width of 4 micrometers and the other portion having a width of 3 micrometers, then the maximum width of the portion of the via extending beyond the clock signal line is 4 micrometers. At the same time, the spacing between adjacent clock signal lines is greater than or equal to the sum of the maximum offset of the via and the maximum width of the portion of the via extending beyond the clock signal line. For example, if the spacing between adjacent clock signal lines is 8 micrometers and the maximum offset of the via is 3 micrometers, the via will not offset to other clock signal lines when offset occurs, and the overlap area between each clock signal line and the via will not change.

[0077] In some embodiments, such as Figure 9 As shown, each column of through holes 421 is arranged in a one-to-one correspondence with each clock signal line 41. Within the repeating unit 40, the minimum distance between the two ends of the through holes 421 and the corresponding clock signal line 41 is not equal. In any two clock signal lines 41, one end of each through hole 421 is equal to the minimum distance between the corresponding clock signal line 41, and the other end of each through hole 421 is equal to the minimum distance between the corresponding clock signal line 41.

[0078] Specifically, in the actual manufacturing process, due to process deviations, the position of the vias may shift relative to the theoretically designed position. In this case, the minimum distance between the two ends of the via and the corresponding clock signal line is not equal. However, within any two clock signal lines, the minimum distance between one end of each via and the corresponding clock signal line is equal, and the minimum distance between the other end of each via and the corresponding clock signal line is equal. This ensures that the relative offset between each via and the clock signal line is the same, and the overlap area between each via and the corresponding clock signal line remains unchanged. This allows the parasitic capacitance change between the clock signal line and the low power signal line to be small or even non-existent, the impedance change of the clock signal line to be small or even non-existent, and the impedance change difference between any two clock signal lines to be small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0079] Specifically, the minimum distance between the two ends of the through hole 421 and the corresponding clock signal line 41 means that the through hole has left and right ends. The distance L6 between the left end of the through hole and the left end of the corresponding clock signal line is the minimum distance between the left end of the through hole and the corresponding clock signal line. The distance L7 between the right end of the through hole and the right end of the corresponding clock signal line is the minimum distance between the two ends of the through hole and the corresponding clock signal line.

[0080] Specifically, such as Figure 9 As shown, the distance L6 between the left end of the via and the left end of the corresponding clock signal line and the distance L7 between the right end of the via and the right end of the corresponding clock signal line are not equal. However, in any two clock signal lines 41, such as the first clock signal line 311 and the second clock signal line 312, the distance between the left end of the via 421 corresponding to the first clock signal line 311 and the left end of the first clock signal line 311 is equal to the distance between the left end of the via 421 corresponding to the second clock signal line 312 and the left end of the second clock signal line 312. The distance between the right end of the via 421 corresponding to the first clock signal line 311 and the right end of the first clock signal line 311 is equal to the distance between the right end of the via 421 corresponding to the second clock signal line 312 and the right end of the second clock signal line 312. This makes the offset between the via and the clock signal line equal for each clock signal line, and the overlap area between each via and the corresponding clock signal line remains unchanged.

[0081] In some embodiments, such as Figure 9 (a) and Figure 9As shown in (f), each column of vias 421 is configured in a one-to-one correspondence with each clock signal line 41. One end of the via 421 corresponding to one clock signal line 41 is aligned with one end of the clock signal line 41, and the other end of the via 421 is aligned with one end of another clock signal line 41. By aligning one end of a via with one end of another clock signal line, the via is prevented from shifting to another clock signal line. This keeps the overlap area between each clock signal line and the via constant, resulting in minimal or no impedance change in each clock signal line. Furthermore, the impedance difference between any two clock signal lines is minimal or even equal, preventing display defects caused by impedance differences between different clock signal lines.

[0082] In some embodiments, such as Figure 9 As shown, when the via 421 is in the offset state, one end of the via 421 corresponding to one clock signal line 41 is aligned with one end of another clock signal line 41. By aligning one end of one via with one end of another clock signal line when the via is in the offset state, the via is prevented from shifting to another clock signal line. This keeps the overlap area between each clock signal line and the via constant, resulting in minimal or no impedance change in each clock signal line. Furthermore, the impedance difference between any two clock signal lines is minimal or even equal, preventing display defects caused by impedance differences between different clock signal lines.

[0083] Specifically, taking a maximum offset of 3 micrometers for the through-hole as an example, Figure 9 (a) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 3 micrometers to the left relative to the clock signal line. Figure 9 (b) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 2 micrometers to the left relative to the clock signal line. Figure 9 (c) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 1 micrometer to the left relative to the clock signal line. Figure 9 (d) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 1 micrometer to the right relative to the clock signal line. Figure 9 (e) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 2 micrometers to the right relative to the clock signal line. Figure 9 (f) in the middle is Figure 8 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 3 micrometers to the right relative to the clock signal line.

[0084] like Figure 9As shown in (a), when via 421 is in the offset state, the left end of via 421 corresponding to the second clock signal line 312 is aligned with the right end of the first clock signal line 311, the left end of via 421 corresponding to the third clock signal line 313 is aligned with the right end of the second clock signal line 312, and the left end of via 421 corresponding to the fourth clock signal line 314 is aligned with the right end of the third clock signal line 313. Figure 9 As shown in (f), the right end of the through hole 421 corresponding to the first clock signal line 311 is aligned with the left end of the second clock signal line 312, the right end of the through hole 421 corresponding to the second clock signal line 312 is aligned with the left end of the third clock signal line 313, and the right end of the through hole 421 corresponding to the third clock signal line 313 is aligned with the left end of the fourth clock signal line 314.

[0085] Specifically, when the via is at its maximum offset, one end of the via is aligned with one end of another clock signal line, preventing the via from shifting to other clock signal lines. This avoids changes in the impedance of the clock signal line due to changes in the overlap area between the clock signal line and the via, thus improving the display effect of the display panel.

[0086] In some embodiments, such as Figure 9 (a) to Figure 9 As shown in (c), the minimum distance L6 between the left end of the through-hole 421 and the corresponding clock signal line 41 is greater than the minimum distance L7 between the right end of the through-hole 421 and the corresponding clock signal line 41; or as shown in (c). Figure 9 (d) to Figure 9 In (f), the minimum distance L6 between the left end of the through hole 421 and the corresponding clock signal line 41 is less than the minimum distance L7 between the right end of the through hole 421 and the corresponding clock signal line 41. Figure 9 In (a), L7 is 0. Figure 9 In (f), L6 is 0).

[0087] In some embodiments, such as Figure 9As shown, when the via 421 is in an offset state, there is a gap between the two ends of the via 421 corresponding to a clock signal line 41 and the two clock signal lines 41 on both sides of the clock signal line 41, and the gaps between the two ends of the via 421 and the two clock signal lines 41 on both sides of the clock signal line 41 are not equal. By making the two ends of the via have gaps with the two clock signal lines on both sides, and the gaps between the two ends of the via and the two clock signal lines on both sides of the clock signal line are not equal, the via will not shift to other clock signal lines when it is offset, and the overlap area between the via and the corresponding clock signal line remains unchanged, so that the impedance change of each clock signal line is small or even does not change, and the impedance change difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0088] Specifically, such as Figure 9 (b) Figure 9 (c) Figure 9 (d) and Figure 9 As shown in (e), the distance between the left end of the through hole 421 corresponding to the second clock signal line 312 and the first clock signal line 311 is not equal to the distance between the right end of the through hole 421 corresponding to the second clock signal line 312 and the third clock signal line 313.

[0089] Specifically, for vias with clock signal lines on both sides, there can be a gap between the via and the clock signal lines on both sides. For vias with clock signal lines on only one side, there can be a gap between the via and the clock signal line on one side, and the widths of the two parts of the via extending beyond the corresponding clock signal line are not equal.

[0090] Specifically, the vias on each clock signal line have the same length and the same width.

[0091] Specifically, such as Figure 10 As shown, Figure 10 In (a), -3 on the x-axis indicates that the via has shifted 3 micrometers to the left, and 3 indicates that the via has shifted 3 micrometers to the right. Similarly, other values ​​and... Figure 10 The values ​​in (b) can be found in the above explanation. Figure 10 (a) in the middle is Figure 8 The change in parasitic capacitance of each clock signal line and low-level signal line at different offsets. Figure 10 In (a) of the diagram, the horizontal axis represents the offset between the vias of the clock signal line and the low-potential signal line, and the vertical axis represents the change in the parasitic capacitance between the clock signal line and the low-potential signal line compared to when the vias of the clock signal line and the low-potential signal line are not offset. Figure 10The bar chart shows the changes in parasitic capacitance between different clock signal lines and low-potential signal lines. CK1-ANO represents the change in parasitic capacitance between the first clock signal line 311 and the low-potential signal line, CK2-ANO represents the change in parasitic capacitance between the second clock signal line 312 and the low-potential signal line, CK3-ANO represents the change in parasitic capacitance between the third clock signal line 313 and the low-potential signal line, and CK4-ANO represents the change in parasitic capacitance between the fourth clock signal line 314 and the low-potential signal line. Figure 10 (b) in the middle is Figure 8 The change in parasitic capacitance of each clock signal line and all signal lines at different offsets. Figure 10 In (b), the horizontal axis represents the offset between the clock signal line and the via of the low-potential signal line, and the vertical axis represents the change in parasitic capacitance of the clock signal line and all signal lines compared to when the vias of the clock signal line and the low-potential signal line are not offset. Figure 10 The bar chart in the figure represents the change in parasitic capacitance between different clock signal lines and all signal lines. CK1-Total represents the change in parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the change in parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the change in parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the change in parasitic capacitance between the fourth clock signal line and all signal lines.

[0092] from Figure 3 and Figure 10 As can be seen from the comparison, compared with display devices in the prior art, in the display panel provided in this application, the changes in parasitic capacitance of each clock signal line and low-potential signal line, as well as the changes in parasitic capacitance of each clock signal line and all signal lines, are significantly reduced with the change in the offset of the via. For example, Figure 3 In the process, the parasitic capacitance change between each clock line and the low-potential power signal line reached 3.3%, and the parasitic capacitance change between each clock line and all signal lines reached 2.7%. Figure 10 In this application, the parasitic capacitance change between each clock signal line and the low-potential signal line is less than 0.9%, and the parasitic capacitance change between each clock signal line and all signal lines is less than 0.3%. That is, the parasitic capacitance change on each clock signal line is small, the parasitic capacitance on the clock signal lines is relatively stable, and the change trend of some clock signal lines is the same, so that the parasitic capacitance of each clock signal line is similar or even equal. This avoids different signal delays between adjacent clock signal lines and avoids signal delay changes caused by impedance changes of clock signal lines, so that the display panel can display normally.

[0093] In some embodiments, such as Figure 11As shown, the via 421 includes a first via 421a corresponding to two adjacent clock signal lines 41 and a second via 421b corresponding to one clock signal line 41. In the first direction X, in two adjacent columns of vias 421, one end of one column of vias 421 closer to the other column of vias 421 is on the same straight line as one end of the other column of vias 421. By aligning one end of the second via with one end of the first via, and ensuring that the width of the second via extending beyond the clock signal line is greater than the maximum offset of the via, the overlap area between the clock signal line and the via does not change. This results in minimal or no impedance change in each clock signal line, and the impedance difference between any two clock signal lines is minimal or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0094] In some embodiments, such as Figure 11 As shown, the first via 421a is symmetrically arranged about the center line of the portion of the low-potential signal line 42 located between two adjacent clock signal lines 41, and the second via 421b extends beyond the width of the portion of the clock signal line 41 (e.g., in...). Figure 11 The offset of L5 is greater than the maximum offset of the via 421. By symmetrically setting the first via about the center line of the portion of the low-potential signal line located between two adjacent clock signal lines, aligning one end of the second via with one end of the first via, and ensuring that the width of the portion of the second via extending beyond the clock signal line is greater than the maximum offset of the via, the overlap area between the clock signal line and the via does not change. This results in minimal or no impedance change in each clock signal line, and minimal or even equal impedance change between any two clock signal lines, avoiding display defects caused by impedance differences between different clock signal lines.

[0095] Specifically, with Figure 11 The relative positions of the vias and clock signal lines in the display panel shown are the relative positions of the vias and clock signal lines when the vias are in their unoffset state, or in other words, when the vias are in their theoretically designed positions. From Figure 11 As can be seen, even if the position of the via is shifted during the actual fabrication process, the overlap area between the via and the clock signal line will not change, and the overlap area between each clock signal line and the via remains unchanged. This results in a small or even no change in the impedance of each clock signal line, and the impedance difference between any two clock signal lines is small or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0096] Specifically, Figure 11 (a) in the diagram is a second overlay diagram of clock signal line 41 and low-level signal line 42. Figure 11 (b) in the middle is Figure 11 The exploded view of the low-potential signal line 42 in (a) is shown below. Figure 11 (c) in the middle is Figure 11 The exploded view of clock signal line 41 in (a) is shown.

[0097] Specifically, it is understandable that Figure 11 and Figure 12 The accompanying drawings may represent the designs within different display panels during the actual manufacturing process.

[0098] Specifically, such as Figure 11 As shown, some vias 421 are located on two clock signal lines 41, and some vias 421 are located on one clock signal line 41.

[0099] In some embodiments, such as Figure 11 As shown, one end of the via 421 corresponding to one clock signal line 41 and the other end corresponding to another clock signal line 41 are respectively located on the center lines of the two clock signal lines 41. This ensures that when adjacent columns of vias are offset, the increased overlap area between one column of vias and the clock signal line is equal to the decreased overlap area between the other column of vias and the clock signal line. This prevents the overlap area between the clock signal lines and the vias from changing, resulting in minimal or no impedance change in each clock signal line. Furthermore, the impedance difference between any two clock signal lines is small or even equal, avoiding display defects caused by impedance differences between different clock signal lines.

[0100] Specifically, when the via 421 is in an unoffset state, when two adjacent columns of vias are offset, the increased overlap area between one column of vias and the clock signal line is equal to the decreased overlap area between the other column of vias and the clock signal line. This ensures that the overlap area between the clock signal line and the via does not change, resulting in a small or even no change in the impedance of each clock signal line. Furthermore, the impedance difference between any two clock signal lines is small or even equal, thus avoiding display defects caused by impedance differences between different clock signal lines.

[0101] Specifically, the two ends of the first via are located on the center lines of two clock signal lines, and one end of the second via is located on the center line of a clock signal line.

[0102] Specifically, such as Figure 11 As shown, the left end of the first through hole 421a located on the first clock signal line 311 is located on the center line of the first clock signal line 311, and the right end of the first through hole 421a is located on the center line of the second clock signal line 312.

[0103] In some embodiments, such as Figure 12As shown, among the first via 421a and the second via 421b corresponding to the same clock signal line 41, the overlapping area of ​​one second via 421b with the corresponding clock signal line 41 is smaller than the overlapping area of ​​one first via 421a with the corresponding clock signal line 41, and the overlapping area of ​​another second via 421b with the corresponding clock signal line 41 is larger than the overlapping area of ​​another first via 421a with the corresponding clock signal line 41. Furthermore, the overlapping area of ​​any first via 421a with the corresponding two adjacent clock signal lines 41 is not equal. When a via is offset, the overlap area between a second via and a clock signal line decreases, while the overlap area between the corresponding first via and the clock signal line increases. Conversely, when a second via is offset, the overlap area between the corresponding first via and the clock signal line decreases. This ensures that the overlap area between each clock signal line and the via remains unchanged, resulting in minimal or no impedance change for each clock signal line. Furthermore, the impedance difference between any two clock signal lines is minimal or even equal, preventing display defects caused by impedance differences between different clock signal lines.

[0104] Specifically, when the via 421 is in an offset state, the offset of the vias corresponding to any two clock signal lines is made equal, so that the overlap area between each clock signal line and the corresponding via remains unchanged.

[0105] Specifically, such as Figure 11 As shown, the display panel also includes a low-voltage signal line 44 and a start signal line 43. Since a DC signal is transmitted on the low-voltage signal line 44, the overlap between the low-voltage signal line 44 and the via will not affect the signal on the low-voltage signal line 44. As for the start signal line 43, the overlap between the via and the start signal line 43 will reduce the impedance of the start signal line and reduce signal loss.

[0106] Specifically, taking a maximum offset of 3 micrometers for the through-hole as an example, Figure 12 (a) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 3 micrometers to the left relative to the clock signal line. Figure 12 (b) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 2 micrometers to the left relative to the clock signal line. Figure 12 (c) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 1 micrometer to the left relative to the clock signal line. Figure 12 (d) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 1 micrometer to the right relative to the clock signal line. Figure 12 (e) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 2 micrometers to the right relative to the clock signal line. Figure 12 (f) in the middle is Figure 11 The overlay diagram of the clock signal line and the low-potential signal line when the via is offset 3 micrometers to the right relative to the clock signal line.

[0107] like Figure 11 , Figure 12 (a) Figure 12 (b) and Figure 12 As shown in (c), when the via 421 is in a leftward offset state, the overlap area between the first clock signal line 311 and the corresponding second via 421b is smaller than the overlap area between the first clock signal line 311 and the corresponding first via 421a, and the overlap area between the fourth clock signal line 314 and the corresponding second via 421b is larger than the overlap area between the fourth clock signal line 314 and the corresponding first via 421a; Figure 11 , Figure 12 (d) Figure 12 (e) and Figure 12 As shown in (f), when via 421 is offset to the right, the overlap area between the first clock signal line and the corresponding second via 421b is greater than the overlap area between the first clock signal line 311 and the corresponding first via 421a, and the overlap area between the fourth clock signal line 314 and the corresponding second via 421b is less than the overlap area between the fourth clock signal line 314 and the corresponding first via 421a. Furthermore, in Figure 12 (a) to Figure 12 In (f), the overlap area between any clock signal line 41 and the corresponding two first vias is different.

[0108] Specifically, when a via is offset, the first and second vias are offset in the same direction. The increased overlap area between a second via and a clock signal line is equal to the decreased overlap area between the corresponding first via and the clock signal line. The decreased overlap area between a second via and a clock signal line is equal to the increased overlap area between the corresponding first via and the clock signal line. The increased overlap area between a first via and a clock signal line is equal to the decreased overlap area between another first via and the clock signal line. This ensures that the overlap area between each clock signal line and the via remains unchanged.

[0109] Specifically, such as Figure 13 As shown, Figure 13 In (a), -3 on the x-axis indicates that the via has shifted 3 micrometers to the left, and 3 indicates that the via has shifted 3 micrometers to the right. Similarly, other values ​​and... Figure 13 The values ​​in (b) can be found in the above explanation. Figure 13 (a) in the middle is Figure 11The change in parasitic capacitance of each clock signal line and low-level signal line at different offsets. Figure 13 In (a) of the diagram, the horizontal axis represents the offset between the vias of the clock signal line and the low-potential signal line, and the vertical axis represents the change in the parasitic capacitance between the clock signal line and the low-potential signal line compared to when the vias of the clock signal line and the low-potential signal line are not offset. Figure 13 The bar chart shows the changes in parasitic capacitance between different clock signal lines and low-potential signal lines. CK1-ANO represents the change in parasitic capacitance between the first clock signal line 311 and the low-potential signal line, CK2-ANO represents the change in parasitic capacitance between the second clock signal line 312 and the low-potential signal line, CK3-ANO represents the change in parasitic capacitance between the third clock signal line 313 and the low-potential signal line, and CK4-ANO represents the change in parasitic capacitance between the fourth clock signal line 314 and the low-potential signal line. Figure 13 (b) in the middle is Figure 11 The change in parasitic capacitance of each clock signal line and all signal lines at different offsets. Figure 13 In (b), the horizontal axis represents the offset between the clock signal line and the via of the low-potential signal line, and the vertical axis represents the change in parasitic capacitance of the clock signal line and all signal lines compared to when the vias of the clock signal line and the low-potential signal line are not offset. Figure 13 The bar chart in the figure represents the change in parasitic capacitance between different clock signal lines and all signal lines. CK1-Total represents the change in parasitic capacitance between the first clock signal line and all signal lines, CK2-Total represents the change in parasitic capacitance between the second clock signal line and all signal lines, CK3-Total represents the change in parasitic capacitance between the third clock signal line and all signal lines, and CK4-Total represents the change in parasitic capacitance between the fourth clock signal line and all signal lines.

[0110] from Figure 3 and Figure 13 As can be seen from the comparison, compared with display devices in the prior art, in the display panel provided in this application, the changes in parasitic capacitance of each clock signal line and low-potential signal line, as well as the changes in parasitic capacitance of each clock signal line and all signal lines, are significantly reduced with the change in the offset of the via. For example, Figure 3 In the process, the parasitic capacitance change between each clock line and the low-potential power signal line reached 3.3%, and the parasitic capacitance change between each clock line and all signal lines reached 2.7%. Figure 13In this application, the parasitic capacitance change between each clock signal line and the low-potential signal line is less than 0.3%, and the parasitic capacitance change between each clock signal line and all signal lines is less than 0.1%. That is, the parasitic capacitance change on each clock signal line is small, the parasitic capacitance on the clock signal lines is relatively stable, and the change trend of some clock signal lines is the same, so that the parasitic capacitance of each clock signal line is similar or even equal. This avoids different signal delays between adjacent clock signal lines and avoids signal delay changes caused by impedance changes of clock signal lines, so that the display panel can display normally.

[0111] In some embodiments, such as Figures 5 to 11 As shown, the display panel 2 includes two sets of first scan driving units 31 arranged symmetrically, and each set of first scan driving units 31 includes four clock signal lines 41.

[0112] In some embodiments, the through hole 421 includes two rows of second through holes 421b and three rows of first through holes 421a, with the three rows of first through holes 421a located between the two rows of second through holes 421b.

[0113] Specifically, the width of the first through hole and the width of the second through hole may not be equal, but the lengths of the first through hole and the second through hole are equal.

[0114] Specifically, when the via is in the unoffset state, the second via 421b may not overlap with the low voltage signal line 44, and / or the second via 421b may not overlap with the starting signal line 43. Alternatively, the second via 421b may not overlap with the low voltage signal line, but may overlap with the starting signal line 43. Or, the second via 421b may overlap with the low voltage signal line, but may not overlap with the starting signal line 43.

[0115] Specifically, the above embodiments are illustrated by taking the equal area, length and width of each through hole as an example. However, the embodiments of this application are not limited to this. It is only necessary to ensure that the overlap area between any clock signal line and the corresponding through hole remains unchanged in any state, and that the overlap area between any two clock signal lines and the through holes is equal.

[0116] In some embodiments, such as Figure 6As shown, the display panel 2 includes: a substrate 501, a light-shielding layer 502, a buffer layer 503, a barrier layer 504, a first active layer 50, a first gate insulating layer 506, a first metal layer 507, a second gate insulating layer 508, a second metal layer 509, a first interlayer insulating layer 510, a second active layer 511, a third gate insulating layer 512, a third metal layer 513, a second interlayer insulating layer 514, a first source / drain layer 515, a first planarization layer 516, a second source / drain layer 517, a second planarization layer 518, a third source / drain layer 519, a third planarization layer 520, a pixel electrode layer 521, and a pixel definition layer 522. A source layer 505 is disposed on one side of the substrate 501, a first gate insulating layer 506 is disposed on one side of the first active layer 505, a first metal layer 507 is disposed on the side of the first gate insulating layer 506 away from the first active layer 505, a second gate insulating layer 508 is disposed on the side of the first metal layer 507 away from the first gate insulating layer 506, a second metal layer 509 is disposed on the side of the second gate insulating layer 508 away from the first metal layer 507, a first interlayer insulating layer 510 is disposed on the side of the second metal layer 509 away from the second gate insulating layer 508, and a second active layer 511 is disposed on the first interlayer insulating layer 510. An insulating layer 510 is disposed on the side of the second metal layer 509 away from the second metal layer 509. A third gate insulating layer 512 is disposed on the side of the second active layer 511 away from the first interlayer insulating layer 510. A third metal layer 513 is disposed on the side of the third gate insulating layer 512 away from the second active layer 511. A second interlayer insulating layer 514 is disposed on the side of the third metal layer 513 away from the third gate insulating layer 512. A first source-drain layer 515 is disposed on the side of the second interlayer insulating layer 514 away from the third metal layer 513. A first planarization layer 516 is disposed on the first source-drain layer 515 away from the second interlayer insulating layer 514. On one side, the second source-drain layer 517 is disposed on the side of the first planarization layer 516 away from the first source-drain layer 515, the second planarization layer 518 is disposed on the side of the second source-drain layer 517 away from the first planarization layer 516, the third source-drain layer 519 is disposed on the side of the second planarization layer 518 away from the second source-drain layer 517, the third planarization layer 520 is disposed on the side of the third source-drain layer 519 away from the second planarization layer 518, the pixel electrode layer 521 is disposed on the side of the third planarization layer 520 away from the third source-drain layer 519, and the pixel definition layer 522 is disposed on the side of the pixel electrode layer 521 away from the third planarization layer 520.

[0117] Specifically, the substrate 501 supports various layers disposed on the substrate 501. When the display panel 2 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 2 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0118] Specifically, the substrate 501 is used to support the various film layers disposed on the substrate 501. The substrate 501 can be made of an insulating material such as glass, quartz, or polymer resin. The substrate 501 can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0119] Specifically, the substrate 501 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material, such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0120] Specifically, the thin-film transistors in the display panel can be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance.

[0121] Specifically, the above embodiments have described the display panel in the embodiments of this application from different perspectives. When there is no conflict between the embodiments, the embodiments can be combined to achieve better technical effects.

[0122] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0123] As can be seen from the above embodiments:

[0124] This application provides a display panel and a display device. The display panel includes a display area and a driving circuit area disposed on at least one side of the display area. The display panel includes multiple clock signal lines and low-potential signal lines. The clock signal lines are disposed in the driving circuit area and extend along a first direction. The low-potential signal lines are disposed within the driving circuit area, and the orthographic projection of the multiple clock signal lines onto the low-potential signal lines is located within the low-potential signal lines. Multiple through-holes are formed on the low-potential signal lines. The through-hole array is configured to form multiple repeating units. In each repeating unit, the number of through-holes in each column is the same. In any two clock signal lines, the overlap area of ​​one clock signal line and all corresponding through-holes in a repeating unit is equal to the overlap area of ​​another clock signal line and all corresponding through-holes in a repeating unit. The overlap area of ​​any clock signal line and a corresponding through-hole in a repeating unit is equal to the product of the width of the clock signal line in a second direction, the length of the through-hole in the first direction, and the number of through-holes in a column in a repeating unit. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. This application ensures that, for any two clock signal lines, the overlapping area of ​​one clock signal line and all corresponding vias within a repeating unit is equal to the overlapping area of ​​the other clock signal line and all corresponding vias within a repeating unit. Furthermore, the overlapping area of ​​any clock signal line and a via within a repeating unit is equal to the product of the width of the clock signal line, the width of the via, and the number of vias in a column within a repeating unit. This ensures that when the position of the vias shifts, the overlapping area of ​​any clock signal line and the via remains unchanged, and the overlapping area of ​​each clock signal line and via is equal. This makes the parasitic capacitance of each clock signal line similar or even equal, thereby avoiding different signal delays between adjacent clock signal lines and avoiding signal delay changes caused by impedance variations in the clock signal lines, thus ensuring normal display on the display panel.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0126] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a driving circuit area disposed on at least one side of the display area. Multiple clock signal lines are disposed within the driving circuit area, and the multiple clock signal lines extend along a first direction; A low-potential signal line is disposed within the driving circuit area, and the orthogonal projection of multiple clock signal lines onto the low-potential signal line is located within the low-potential signal line. The low-potential signal line has multiple vias, and the via array is configured to form multiple repeating units. Within each repeating unit, the number of vias in each column is the same. In any two clock signal lines, the overlap area of ​​one clock signal line and all corresponding vias in a repeating unit is equal to the overlap area of ​​another clock signal line and all corresponding vias in a repeating unit. Furthermore, the overlap area of ​​any clock signal line and corresponding vias in a repeating unit is equal to the product of the width of the clock signal line in the second direction, the length of the via in the first direction, and the number of vias in a column within a repeating unit. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel as described in claim 1, characterized in that, Each column of through holes is arranged along the first direction, and there is a gap between adjacent rows of through holes in the first direction.

3. The display panel as described in claim 1, characterized in that, The number of columns of the vias is equal to the number of clock signal lines. Each column of vias corresponds to each clock signal line. The vias are symmetrical about the center line of the clock signal lines. The distance between the end of the via corresponding to one clock signal line and the other clock signal line is greater than or equal to the maximum offset of the via. The width of the via extending beyond the clock signal line is greater than or equal to the maximum offset of the via.

4. The display panel as described in claim 3, characterized in that, The width of the through hole is equal to the sum of the width of the clock signal line and the spacing between adjacent clock signal lines.

5. The display panel as described in claim 3, characterized in that, The spacing between adjacent clock signal lines is greater than the sum of the maximum offset of the via and half the width of the portion of the via extending beyond the clock signal line.

6. The display panel as described in claim 1, characterized in that, Each column of vias is configured in a one-to-one correspondence with each clock signal line. Within the repeating unit, the minimum distance between the two ends of the via and the corresponding clock signal line is not equal. In any two clock signal lines, one end of each via is equal to the minimum distance between the corresponding clock signal line, and the other end of each via is equal to the minimum distance between the corresponding clock signal line.

7. The display panel as described in claim 6, characterized in that, Each column of vias is configured in a one-to-one correspondence with each clock signal line. One end of the via corresponding to one clock signal line is aligned with one end of the clock signal line, and the other end of the via is aligned with one end of another clock signal line.

8. The display panel as described in claim 6, characterized in that, The minimum distance between the left end of the through hole and the corresponding clock signal line is greater than the minimum distance between the right end of the through hole and the corresponding clock signal line; or the minimum distance between the left end of the through hole and the corresponding clock signal line is less than the minimum distance between the right end of the through hole and the corresponding clock signal line.

9. The display panel as claimed in claim 1, characterized in that, The via includes a first via corresponding to two adjacent clock signal lines and a second via corresponding to one clock signal line. Along the first direction, in two adjacent columns of vias, one end of one column of vias closer to the other column of vias is on the same straight line as one end of the other column of vias.

10. The display panel as claimed in claim 9, characterized in that, The first via is symmetrically arranged about the center line of the portion of the low-potential signal line located between two adjacent clock signal lines, and the width of the portion of the second via extending beyond the clock signal line is greater than the maximum offset of the via.

11. The display panel as claimed in claim 10, characterized in that, The via is located at one end of one clock signal line and one end of the other clock signal line, respectively, on the center line of the two clock signal lines.

12. The display panel as claimed in claim 9, characterized in that, In the first via and the second via corresponding to the same clock signal line, the overlap area between the second via and the corresponding clock signal line is less than the overlap area between the first via and the corresponding clock signal line, the overlap area between the second via and the corresponding clock signal line is greater than the overlap area between the first via and the corresponding clock signal line, and the overlap area between any first via and the corresponding two adjacent clock signal lines is not equal.

13. The display panel as claimed in claim 9, characterized in that, The display panel includes two sets of first scanning drive units arranged symmetrically. Each set of first scanning drive units includes four clock signal lines. The through holes include two columns of second through holes and three columns of first through holes, with the three columns of first through holes located between the two columns of second through holes.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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