Clock control device and clock control method of serial peripheral interface

Abstract

The invention provides a clock control device and a clock control method for a serial peripheral interface, which are characterized in that a local delay module is used for delaying a local clock signal so as to output a local delay clock signal to a clock selection module; one of a local delay clock signal and an external clock signal is selected through a clock selection module to serve as a basic clock signal to be output to a first delay module, phase delay is carried out on the basic clock signal through the first delay module, a first delay clock signal is obtained, and the control device sends the first delay clock signal to a second delay module. And the receiving work clock is used for sampling external data signals transmitted by the storage device.

Description

Technical Field

[0001] The present invention relates to the technical field of serial peripheral interface, and particularly to a clock control device and a clock control method for a serial peripheral interface. Background Art

[0002] When implementing communication between a master device and a slave device by applying a serial peripheral interface (SPI), the master device transmits a chip select signal through a chip select signal port to select a corresponding slave device for communication, transmits a clock signal through a clock signal port to synchronize the communication between the master device and the slave device, and realizes data transmission between the master device and the slave device through a signal input / output terminal. The master device of SPI is usually connected to storage media such as SPI Flash and SPI pseudo-random static memory (SPI PSRAM) with single, double, four or eight data lines as the slave device.

[0003] Since the slave device drives data output according to the clock signal output by the master device, and the master device also shares a clock signal with the slave device when receiving the data output by the slave device. Therefore, there is a large delay between the clock signal output by the master device and the data signal received.

[0004] Specifically, the clock signal output by the master device is transmitted to the slave device after passing through the output path of the master device and then through the circuit transmission path between the master device and the slave device; when the slave device applies the received clock signal, there will also be a corresponding transmission path inside the slave device, so that the slave device can drive data output according to the clock signal output by the master device. When the master device receives the data output by the slave device, the data output by the slave device also needs to pass through the circuit transmission path between the master device and the slave device before being transmitted to the master device, and then is utilized by the master device through the input path of the master device. However, when the clock signal passes through the output path of the master device, the circuit transmission path between the master device and the slave device, and the internal transmission path of the slave device, there will be delays, resulting in a delay in the data output by the slave device according to the clock signal. At the same time, when the data signal output by the slave device passes through the circuit transmission path between the master device and the slave device and the input path of the master device, there will also be delays. Therefore, the delay difference between the data signal received by the master device and the clock signal output by the master device is further increased. If the master device still uses the same clock signal as the slave device to collect the data signal output by the slave device, then the data transmission frequency needs to be reduced to a very low level so that the master device can collect correct data. Therefore, for the case where the serial peripheral interface realizes communication between the master device and the slave device in the double data rate (DDR) mode, the transmission rate of the SPI interface of the master device is difficult to exceed 100 MHz, which cannot meet the high-speed transmission requirements. Summary of the Invention

[0005] An embodiment of the present invention provides a clock control device and a clock control method for a serial peripheral interface, which is beneficial to improving the data transmission rate between the control device and the storage device.

[0006] An embodiment of the present invention provides a clock control device for a serial peripheral interface, which is arranged in a control device, wherein the control device communicates with a storage device through the serial peripheral interface. The clock control device of the serial peripheral interface includes a local delay module, a clock selection module, and a first delay module. The local delay module is used to receive the local clock signal of the control device, perform delay, and output a local delayed clock signal. The clock selection module is used to receive the local delayed clock signal and an external clock signal, and select one of the clock signals to output as a basic clock signal. The first delay module is used to perform phase delay on the basic clock signal and output a first delayed clock signal for the control device to use as the receiving working clock for sampling the external data signal transmitted by the storage device.

[0007] The present invention also provides a clock control method for a serial peripheral interface. The clock control method includes: receiving a local clock signal and an external clock signal, and delaying the local clock signal to output a local delayed clock signal. According to a clock selection control signal, select one of the external clock signal and the local delayed clock signal as a basic clock signal. Perform phase delay on the basic clock signal to output a first delayed clock signal. Wherein, the first delayed clock signal is used by the control device as the receiving working clock for sampling the external data signal transmitted by the storage device.

[0008] An embodiment of the present invention provides a clock control device and a clock control method for a serial peripheral interface. The local delay module delays the local clock signal to output a local delayed clock signal to the clock selection module. The clock selection module selects one of the local delayed clock signal and the external clock signal as a basic clock signal and outputs it to the first delay module, so as to use the first delay module to perform phase delay on the basic clock signal to obtain a first delayed clock signal. By enabling the control device to use the first delayed clock signal as the receiving working clock for sampling the external data signal transmitted by the storage device, the delay caused by the local clock signal passing through the output path of the control device, the circuit transmission path between the control device and the storage device, and the internal transmission path of the storage is compensated, thereby compensating for the delay of the external data signal, reducing the delay difference between the receiving working clock and the external data signal, and enabling the control device to collect correct data without reducing the data transmission frequency, which is beneficial to improving the data transmission rate between the control device and the storage device and meeting the high-speed transmission requirements. Description of the Drawings

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figures 1A - 1B It is a schematic connection diagram of a control device and a storage device provided by an embodiment of the present invention.

[0011] Figure 2 It is a schematic structural diagram of a clock control device for a serial peripheral interface provided by an embodiment of the present invention.

[0012] Figure 3 It is a command sequence in single data rate mode.

[0013] Figure 4 It is a command sequence in double data rate mode.

[0014] Figures 5A - 5D It is a timing diagram of a local clock signal, a gating signal, and a local delayed clock signal provided by an embodiment of the present invention.

[0015] Figure 6 It is a schematic structural diagram of a delay chain provided by an embodiment of the present invention.

[0016] Figure 7 It is a schematic structural diagram of a clock phase delay module provided by an embodiment of the present invention.

[0017] Figure 8 It is a schematic structural diagram of a second delay module provided by an embodiment of the present invention.

[0018] Figure 9 It is a flowchart of a clock control method for a serial peripheral interface provided by an embodiment of the present invention;

[0019] Figure 10 It is a flowchart of generating a local delayed clock signal provided by an embodiment of the present invention.

[0020] Figure 11 It is a flowchart of obtaining a preset input delay value when using a local clock signal as a reference clock signal provided by an embodiment of the present invention.

[0021] Figure 12 It is a flowchart of obtaining a preset output delay value provided by an embodiment of the present invention.

[0022] Figure 13 It is a flowchart of obtaining a preset input delay value when using an external clock signal as a reference clock signal provided by an embodiment of the present invention. Detailed implementation manners

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0024] Specifically, Figures 1A - 1B is a schematic connection diagram of a control device and a storage device provided by an embodiment of the present invention. Among them, the control device 10 includes a register 101, a clock control device 102, a data buffer (i.e., FIFO) 103, and a shift register 104. The bus BL is an internal bus for the control device 10 to communicate with other modules (for example, an AXI advanced high-performance bus or an AHB bus). In one embodiment, the control device 10 is a memory controller in a microcontroller; in other embodiments, the control device 10 may further include other modules coupled through the bus BL. In other words, the control device 10 is the microcontroller itself. The control device 10 transmits a chip select signal through the chip select signal port nCS to select the corresponding storage device 20, transmits a clock signal to the storage device 20 through the clock signal port CK, and communicates with the storage device 20 through the signal input / output ports IO0 to IO3. Among them, the control device 10 can be used as the master device, and the storage device 20 can be used as the slave device.

[0025] Please continue to refer to Figure 1B , in some embodiments, the control device 10 outputs a local clock signal SCK and data DO to the storage device 20. The storage device 20 drives the data output with the local clock signal SCK output by the control device 10, and the control device 10 receives the data (i.e., DI) output by the storage device 20 with the local clock signal SCK.

[0026] Optionally, as described above, the control device 10 can be a micro control unit or a memory controller, etc., and the storage device 20 can be a flash memory or a PSRAM, etc.

[0027] Figure 2It is a schematic structural diagram of a clock control device for a serial peripheral interface provided by an embodiment of the present invention. An embodiment of the present invention provides a clock control device 30 for a serial peripheral interface, which is arranged in a control device 10. Among them, the control device 10 communicates with a storage device 20 through the serial peripheral interface.

[0028] The clock control device 30 for the serial peripheral interface includes a local delay module 301, a clock selection module 302, and a first delay module 303.

[0029] The local delay module 301 is used to receive the local clock signal SCK of the control device 10, perform delay, and output a local delayed clock signal rclk.

[0030] The clock selection module 302 is used to receive the local delayed clock signal rclk and an external clock signal DQS, and select one of the clock signals to output as a basic clock signal bclk.

[0031] The first delay module 303 is used to perform phase delay on the basic clock signal bclk and output a first delayed clock signal dclk for the control device 10 to use as a receiving working clock for sampling an external data signal transmitted by the storage device 20.

[0032] In the clock control device 30 provided by the present invention, by setting the local delay module 301 to delay the local clock signal SCK, that is, the sampling start time corresponding to the local clock signal SCK is delayed, and the delay caused by the local clock signal SCK passing through the output path of the control device 10, the circuit transmission path between the control device 10 and the storage device 20, and the internal transmission path of the storage device 20 can be compensated, so that the delay of the external data signal driven and output by the storage device 20 according to the local clock signal SCK is compensated. Among them, the sampling start time is the time when the control device 10 starts to sample the input external data signal.

[0033] By setting the first delay module 303 to perform phase delay on the basic clock signal bclk, that is, the sampling start time corresponding to the basic clock signal bclk is delayed, so that the sampling start time corresponding to the first delayed clock signal dclk lags behind the sampling start time corresponding to the basic clock signal bclk. When the control device 10 uses the first delayed clock signal dclk as the receiving working clock to sample the external data signal, the delay difference between the receiving working clock and the external data signal can be reduced, so that the control device 10 can collect correct data according to the first delayed clock signal dclk without having to collect data by reducing the data transmission frequency, which is beneficial to improving the data transmission rate between the control device 10 and the storage device 20 and meeting the high-speed transmission requirements.

[0034] By setting the clock selection module 302, one of the local delay clock signal rclk and the external clock signal DQS is selected as the basic clock signal bclk, so that the clock control device 30 is compatible with the design of the storage device 20 supporting the external clock signal DQS and the design of the storage device 20 not supporting the external clock signal DQS.

[0035] Optionally, the external clock signal DQS comes from the storage device 20 and is synchronized with the external data signal.

[0036] That is, in the design where the storage device 20 supports the external clock signal DQS, the storage device 20 controls the simultaneous output of the external data signal and the external clock signal DQS. The control device 10 serves as the receiving end to receive the external data signal and the external clock signal DQS. The clock selection module 302 in the clock control device 30 can select one of the external clock signal DQS and the local delay clock signal rclk as the basic clock signal bclk and output it to the first delay module 303. Then, the basic clock signal bclk is phase-delayed by the first delay module 303 to obtain the first delayed clock signal dclk. Therefore, when the clock selection module 302 selects the external clock signal DQS as the basic clock signal bclk, the control device 10 can sample the external data signal according to the first delayed clock signal dclk generated based on the external clock signal DQS. Correspondingly, when the clock selection module 302 selects the local delay clock signal rclk as the basic clock signal bclk, the control device 10 can sample the external data signal according to the first delayed clock signal dclk generated based on the local clock signal SCK.

[0037] In the design where the storage device 20 does not support the external clock signal DQS, the storage device 20 outputs the external data signal but does not output the external clock signal DQS. Therefore, the control device 10 serves as the receiving end to only receive the external data signal. The clock selection module 302 outputs the local delay clock signal rclk as the basic clock signal bclk to the first delay module 303, and then the basic clock signal bclk is phase-delayed by the first delay module 303 to obtain the first delayed clock signal dclk. Therefore, the control device 10 can sample the external data signal according to the first delayed clock signal dclk generated based on the local clock signal SCK.

[0038] In the design where the storage device 20 supports an external clock signal DQS, although the storage device 20 controls the simultaneous output of the external data signal and the external clock signal DQS, which can make the external clock signal DQS and the external data signal have the same delay on the circuit transmission path between the storage device 20 and the control device 10, since the output of the external data signal is driven by the local clock signal SCK, therefore, the delay generated by the local clock signal SCK will cause a delay in the external data signal. Subsequently, when the control device 10 directly samples the external data signal using the external clock signal DQS, it may still affect the accuracy of data sampling. Therefore, the clock control device 30 in the present invention is provided with a clock selection module 302 and a first delay module 303. While realizing the selection of the local clock signal SCK and the external clock signal DQS, the first delay module 303 can perform phase delay on the local delayed clock signal rclk or the external clock signal DQS to improve the accuracy of data sampling.

[0039] Optionally, in some embodiments, the local delay module 301 is used to delay the local clock signal SCK by an integer multiple of the first unit time length to achieve coarse adjustment of the local clock signal SCK, thereby accelerating the adjustment speed of the local clock signal SCK.

[0040] Optionally, in some embodiments, the first unit time length is equal to 0.5 cycles of the local clock signal SCK, so that the transition edge of the local delayed clock signal rclk corresponds to the transition edge of the local clock signal SCK. Among them, the transition edge includes the rising edge and the falling edge.

[0041] Please continue to refer to Figure 2 , the local delay module 301 includes a first register 3011, a delay control unit 3012, and a gating unit 3013.

[0042] The first register 3011 is used to configure the delay of the local clock signal SCK so that the delay of the local clock signal SCK is equal to an integer multiple of the first unit time length.

[0043] The delay control unit 3012 is used to control the enabling of the gating signal ck_en after the delay of the local clock signal SCK according to the configuration of the first register 3011.

[0044] The gating unit 3013 is used to gate the local clock signal SCK according to the gating signal ck_en to generate the local delayed clock signal rclk.

[0045] By controlling the gating unit 3013 with the gating signal ck_en, when the storage device 20 outputs corresponding data, the local clock signal SCK is controlled to be output to the clock selection module 302, so as to achieve coarse adjustment of the local clock signal SCK in steps of a first unit duration (for example, 0.5 cycles of the local clock signal SCK), and then generate a local delayed clock signal rclk.

[0046] Figure 3 is the timing diagram in the single data rate mode, Figure 4 is the timing diagram in the double data rate mode. In the double data rate mode, since the control device 10 and the storage device 20 send one bit of data corresponding to both the rising edge and the falling edge of the local clock signal SCK, and due to the delay caused by the transmission path from the storage device 20 to the control device 10 for the external data signal received by the control device 10, the local clock signal SCK of the control device 10 and the external data signal are asynchronous, and the control device 10 cannot sample the correct data. Therefore, when the local delay module 301 delays the local clock signal SCK, a register can be correspondingly set to achieve the design of delaying the local clock signal SCK by half a cycle duration, and a register can be correspondingly set to achieve the design of delaying the local clock signal SCK by one cycle duration, so as to achieve the delay of an integer multiple of the first unit duration for the local clock signal SCK.

[0047] Correspondingly, the first register 3011 further includes a first sub-register and a second sub-register. The first sub-register is configured to delay the local clock signal SCK by 0.5 cycles, and the second sub-register is configured to delay the local clock signal SCK in units of 1 cycle. By configuring the values of the first sub-register and the second sub-register, the local clock signal SCK can be delayed by an integer multiple of 0.5 cycles.

[0048] Figures 5A - 5D is the timing diagram of the local clock signal, the gating signal and the local delayed clock signal provided by the embodiment of the present invention. Among them, qspi_state represents the instruction / address / data transmitted on the SPI bus (for example, qspi_state corresponds to Figure 3 and Figure 4 IO0~IO3, or corresponding to IO0~IO7 of the eight-line OSPI, for transmitting instructions / addresses / data); CMD corresponds to the instruction stage, ADDR corresponds to the address stage, DUMMY corresponds to the empty cycle, and DATA corresponds to the data stage. IDLE corresponds to the state where the chip select signal has an invalid level.

[0049] By setting the values of the first sub-register and the second sub-register, the delay of the local clock signal SCK is adjusted. For example, the value of the first sub-register is set to 0 or 1 (i.e., SSHIFT = 0 or 1). The value of the second sub-register being set to 3'b000 represents a binary value with a bit width of 3 and a value of 0 (i.e., RXSFT = 3'b000); the value of the second sub-register being set to 3'b001 represents a binary value with a bit width of 3 and a value of 1 (i.e., RXSFT = 3'b001).

[0050] Please continue to refer to Figure 5A , when the value of the first sub-register of the first register 3011 is set to 0 (i.e., SSHIFT = 0) and the value of the second sub-register of the first register 3011 is set to 3'b000 (i.e., RXSFT = 3'b000), the local delay module 301 is configured not to delay the local clock signal SCK. Since the local clock signal SCK also needs to be controlled by the gating signal ck_en, therefore, the first rising edge of the local delayed clock signal rclk lags behind the rising edge of the gating signal ck_en by one cycle, and the first rising edge of the local delayed clock signal rclk corresponds to the falling edge of the 8th pulse of the local clock signal SCK.

[0051] Please continue to refer to Figure 5B , when the value of the first sub-register of the first register 3011 is set to 1 (i.e., SSHIFT = 1) and the value of the second sub-register of the first register 3011 is set to 3'b000 (i.e., RXSFT = 3'b000), the local delay module 301 is configured to delay the local clock signal SCK by 0.5 cycle. Therefore, relative to Figure 5A the setting where the value of the first sub-register of the first register 3011 is set to 0 and the value of the second sub-register of the first register 3011 is set to 3'b000, Figure 5B when the value of the first sub-register of the first register 3011 is set to 1 and the value of the second sub-register of the first register 3011 is set to 3'b000 in

[0052] Please continue to refer to Figure 5C , when the value of the first sub-register of the first register 3011 is set to 0 (i.e., SSHIFT = 0) and the value of the second sub-register of the first register 3011 is set to 3'b001, the local delay module 301 is configured to delay the local clock signal SCK by 1 cycle. Therefore, relative to Figure 5BThe value of the first sub - register of the first register 3011 is set to 1, and the value of the second sub - register of the first register 3011 is set to 3'b000. When the value of the first sub - register of the first register 3011 is set to 0 and the value of the second sub - register of the first register 3011 is set to 3'b001, the first rising edge of the local delayed clock signal rclk corresponds to the falling edge of the 9th pulse of the local clock signal SCK, realizing a delay of 1 cycle for the local clock signal SCK.

[0053] Please continue to refer to Figure 5D , when the value of the first sub - register of the first register 3011 is set to 1 (i.e., SSHIFT = 1) and the value of the second sub - register of the first register 3011 is set to 3'b001 (i.e., RXSFT = 3'b001), the local delay module 301 is configured to delay the local clock signal SCK by 1.5 cycles. Thus, relative to Figure 5C the setting where the value of the first sub - register of the first register 3011 is set to 0 and the value of the second sub - register of the first register 3011 is set to 3'b001, when the value of the first sub - register is set to 1 and the value of the second sub - register is set to 3'b001, the first rising edge of the local delayed clock signal rclk corresponds to the rising edge of the 10th pulse of the local clock signal SCK, realizing a delay of 1.5 cycles for the local clock signal SCK.

[0054] It can be understood that 3 - bit binary codes are stored in the second sub - register, and the value range of the second sub - register is binary values from 000 to 111 (i.e., decimal values from 0 to 7). Further, when the value of the second sub - register is from 010 to 111, the configuration of the second sub - register can realize a delay of 2 to 7 cycles for the local clock signal SCK. Combined with the value of the first sub - register (i.e., SSHIFT = 0 or 1), it can be further set whether to delay the local clock signal SCK by 0.5 cycle.

[0055] It can be understood that the number of bits of the binary code stored in the second sub - register is not limited to 3. For example, the number of bits of the binary code stored in the second sub - register can be 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0056] Optionally, the number of bits of the binary code stored in the second sub - register can be determined according to the phase difference between the external data signal and the local clock signal SCK. For example, in actual tests, when the system clock frequency of the control device 10 is set to 200 MHz, the external data signal and the local clock signal SCK are asynchronously different by about 8.1 nanoseconds. The number of bits of the binary code stored in the second sub - register can be set to 3, so that the local delay module 301 can realize a setting of delaying the local clock signal SCK by 0 to 7.5 cycles through the first sub - register and the second sub - register.

[0057] It should be noted that Figures 5A - 5D The last pulse of the local delayed clock signal rclk shown is for writing data into the data buffer to reduce the delay caused when the signal passes through each logic device inside the control device 10.

[0058] Although the local delayed clock signal rclk can be roughly adjusted from the local clock signal SCK through the local delay module 301, when the control device 10 samples the external clock signal DQS using the local delayed clock signal rclk, it may not be able to sample the correct data. For example, when the system clock frequency of the control device 10 is set to 200 MHz, the external data signal and the local clock signal SCK are asynchronously different by about 8.1 nanoseconds. By using the local delay module 301 to delay the local clock signal SCK by 1.5 cycles, a local delayed clock signal rclk with an asynchronous time difference within 0.5 cycles from the external clock signal DQS is obtained. However, there is still an asynchronous time difference of 0.6 nanoseconds between the local delayed clock signal rclk and the external data signal that cannot be compensated.

[0059] Moreover, although the external clock signal DQS and the external data signal Din are synchronous signals, in fact, they may not meet Figure 1B the timing requirements for the setup of the flip-flop state shown. When the control device 10 directly samples the external data signal using the external clock signal DQS, there may also be problems with sampling accuracy. Therefore, the first delay module 303 can be used to finely adjust the local delayed clock signal rclk and the external clock signal DQS. That is, the first delay module 303 is used to delay the basic clock signal bclk by a second duration.

[0060] Optionally, in some embodiments, to achieve fine adjustment of the local delayed clock signal rclk and the external clock signal DQS, the second duration is made less than or equal to the first unit duration (for example, 0.5 cycles) to control the delay accuracy of the first delay module 303 for the basic clock signal bclk.

[0061] Optionally, the first delay module 303 delays the basic clock signal bclk in picosecond (ps) unit steps.

[0062] Optionally, please continue to refer to Figure 3 , the first delay module 303 includes one of the second register 3031, the Clock Phase Delay Module (CPDM), and the delay chain DLC.

[0063] The first delay module 303 adjusts one cycle of the base clock signal bclk through P levels of time lengths, and the second time length is set by setting M bits (where M is less than or equal to N) out of N bits in P second registers 3031 (for example, P of the subsequent Figure 7 12 second registers DLSTCNT[6:0]), and P is configured by a third register.

[0064] Figure 6 FIG. 6 is a schematic structural diagram of a delay chain provided by an embodiment of the present invention. The delay chain DLC includes a plurality of delay units DU, a plurality of first multiplexers MUX1, a second multiplexer MUX2, and a signal distributor SD.

[0065] Optionally, the plurality of delay units DU include, but are not limited to, D flip-flops. Each delay unit DU can provide the same or substantially the same delay amount.

[0066] The plurality of delay units DU are serially connected in sequence, the plurality of first multiplexers MUX1 are serially connected in sequence, the first delay unit DU0 of the plurality of delay units DU receives the base clock signal bclk, the first first multiplexer MUX10 of the plurality of first multiplexers MUX1 receives the base clock signal bclk, and the second multiplexer MUX2 receives the base clock signal bclk. The output end of each delay unit DU is electrically connected to the input end of a first multiplexer MUX1 correspondingly. The selection ends of the plurality of first multiplexers MUX1 are electrically connected to the second register 3031 to delay the base clock signal bclk for a second time length according to the configuration of the second register 3031. The last first multiplexer MUX1n among the plurality of first multiplexers MUX1 is electrically connected to the second multiplexer MUX2, and the second multiplexer MUX2 is configured to output a first delayed clock signal dclk.

[0067] Optionally, the second register 3031 provides a delay signal to the selection ends of the plurality of first multiplexers MUX1 through a decoder. The delay signal is represented as a level signal transmitted by a bus, and the value range of the delay signal is 0 to 2 to the power of N. Among them, the second register 3031 can store N-bit binary codes.

[0068] The signal distributor SD receives the delay signal and correspondingly controls the selection ends of the plurality of first multiplexers MUX1 according to the delay signal to set the corresponding first multiplexer MUX1, so as to correspondingly control the plurality of delay units DU to implement the delay of the base clock signal bclk. For example, the signal distributor SD receives the delay signal DLYEN[31:0] to divide the delay signal DLYEN[31:0] into DLYEN[0], DLYEN[1],..., DLYEN

[31] to correspondingly control the selection ends of the plurality of first multiplexers MUX1.

[0069] Optionally, only one level signal in the delay signals DLYEN[31:0] corresponds to a high level state, and the remaining multiple level signals correspond to low level states. For example, the second register 3031 can store a 5-bit binary code. If the 1st bit and the 3rd bit in the second register 3031 are set (i.e., corresponding to the binary value of 01010), then the 10th level signal in the delay signals DLYEN[31:0] corresponds to a high level state. The signal distributor SD sets DLYEN[0] to DLYEN

[10] according to the delay signals, thereby selecting the first first multiplexer MUX10 to the tenth first multiplexer MUX19, and then correspondingly controlling the first delay unit DU0 to the tenth delay unit DU9 to implement the delay of the basic clock signal bclk.

[0070] Optionally, the signal distributor SD is further configured to generate a bypass level signal OCKEN, and the bypass level signal OCKEN has two logic states (i.e., logic 0 and logic 1). The second multiplexer MUX2 is configured to select and output the basic clock signal bclk or the first delayed clock signal dclk according to the logic state of the bypass level signal OCKEN.

[0071] Figure 7 FIG. is a schematic structural diagram of a clock phase delay module provided by an embodiment of the present invention. The clock phase delay module CPDM includes a plurality of serially connected delay chains DLC, a sampler SA, a register interface REI, and an output multiplexer OMUX. The clock phase delay module CPDM communicates with the bus AHB or AXI through the register interface REI. The sampler SA is electrically connected to the register interface REI and the output multiplexer OMUX. A plurality of delay chains DLC are connected in series, and a plurality of delay chains DLC are electrically connected to the output multiplexer OMUX.

[0072] Optionally, the clock phase delay module CPDM includes x delay chains DLC, and the structure of each delay chain DLC can refer to Figure 6 the setting.

[0073] Figure 7 An exemplary clock phase delay module CPDM includes 12 delay chains DLC (i.e., x = 12), and each delay chain DLC includes 128 delay units DU.

[0074] Optionally, please continue to refer to Figure 3 and Figure 7, when delaying the basic clock signal bclk, the clock phase delay module CPDM selects the corresponding delay chain DLC according to the delay chain selection signal cpsel. The value configured by the second register 3031 is converted into a delay signal through a decoder and output to the selection terminal of the multiplexer in the delay chain DLC, so as to control the corresponding delay unit DU to delay the basic clock signal bclk, and output the first delayed clock signal dclk through the output multiplexer OMUX.

[0075] Optionally, the delay chain selection signal cpsel is the value configured by the third register.

[0076] In Figure 7 In the embodiment where the first delay module 303 is implemented by the clock phase delay module CPDM as shown, the first delay module 303 further configures the enable of the delay chain DLC through the third register (such as the third register DLLEN[11:0]), that is, configures several levels of using the clock phase delay module CPDM. As Figure 7 As shown, there are a total of 12 delay chains DLC (x = 12). Setting 1 bit in the third register DLLEN[11:0] represents enabling the corresponding 1 delay chain DLC among the 12 delay chains of the first delay module 303, and setting P bits represents enabling P delay chains DLC in the clock phase delay module CPDM.

[0077] In Figure 7In one embodiment, first, according to the 1-cycle duration of the basic clock signal bclk and the minimum adjustment precision or step size of the clock phase delay module CPDM (i.e., the delay duration of each delay unit DU in each delay chain DLC of the clock phase delay module CPDM), it is determined how many levels among the x levels are at most required for the corresponding second duration (for example, it is determined that P levels are required), and then the values of the second registers 3031 of the P levels are further configured according to the second duration. For example, if the 1-cycle duration of the basic clock signal bclk is 2.6 ns and the minimum adjustment precision of the clock phase delay module CPDM is 20 ps, then at most 130 delay units DU are required to achieve the adjustment of the second duration (the maximum value is the 1-cycle duration of bclk). Therefore, only enabling 2 levels among the x levels of the first delay module 303 can meet the requirements (i.e., P = 2. For example, only enabling the first-level delay chain DLC1 and the second-level delay chain DLC2 among the 12 delay chains of the clock phase delay module CPDM can meet the requirements). When delaying the basic clock signal bclk, the second register 3031 of the first-level delay chain DLC1 is configured (all 7 bit positions of DLSTCNT[6:0] are set (i.e., all 128 delay units DU of the first-level delay chain DLC1 are fully enabled), the second bit of the second register 3031 (DLSTCNT[6:0]) of the second-level delay chain DLC2 is set (i.e., corresponding to the binary value of 0000010, then the first 2 delay units DU at the front of the second-level delay chain DLC2 are opened), and at the same time, the lowest 2 bit positions of the third register DLLEN[11:0] are both set to 1 (i.e., configuring P = 2) to control the basic clock signal bclk to be delayed by the second duration.

[0078] In Figure 7 In another embodiment, when the basic clock signal bclk is also delayed by 1 cycle duration, it is adjusted through P levels. Different from the previous embodiment, in this embodiment, the third register is configured with P = x, that is, all x delay chains DLC of the clock phase delay module CPDM will be enabled (in Figure 7In the illustrated embodiment, when x = 12, all 12 delay chains DLC1 to DLC12 are enabled. At this time, the 12 bits of the third register DLLEN[11:0] are all set to 1, that is, P = 12 is configured. The maximum value of the second duration (i.e., the basic clock signal bclk is delayed by 1 cycle duration) is divided into 12 equal parts, and then the second register 3031 corresponding to each stage delay duration is used to set how many delay units DU need to be enabled at each level. For example, if the 1 cycle duration of the basic clock signal bclk is 2.4 ns, then divided into 12 equal parts is 200 ps. If the minimum adjustment accuracy of the clock phase delay module CPDM is 20 ps, then each of the 12 delay chains DLC1 to DLC12 needs to enable 10 delay units DU. This embodiment is simpler in programming than the previous embodiment. The values of 3031 (DLSTCNT[6:0]) of all 12 second registers are the same, which is the decimal number 10. However, the disadvantage is that it must be adjusted with a step size or accuracy of 12 times the delay duration of a single delay unit DU of the CPDM as the adjustment step size or accuracy of the second duration, and the adjustment accuracy is relatively low. It is suitable for occasions where the frequency of the basic clock signal bclk to be adjusted is relatively low.

[0079] It should be noted that the sum of the P-level time lengths may be equal to 1 cycle time length or may not be equal to 1 cycle time length.

[0080] It should be noted that the difference between the clock phase delay module CPDM and the delay chain DLC is that the clock phase delay module CPDM also needs to sample the level of the delayed basic clock signal bclk with the input basic clock signal bclk. When the lower-level level can be sampled, it indicates that the basic clock signal bclk has been delayed by one cycle duration. After that, the scan completion flag is set, and the second register 3031 is configured to take several equal parts of the phase in the N equal parts of a cycle.

[0081] It can be understood that in addition to adjusting the received working clock of the control device 10, the transmitted working clock of the control device 10 can also be adjusted to compensate for the delay of the signal on the transmission path between the control device 10 and the control device 10.

[0082] Figure 8It is a schematic structural diagram of a second delay module for adjusting the transmission working clock of the control device 10 provided by an embodiment of the present invention. Optionally, in some embodiments, the clock control device 30 further includes a second delay module 304. The second delay module 304 is used to delay the local clock signal SCK by a time length within 0.5 cycles to obtain a delayed clock signal CK1 for the control device 10 to use as the transmission working clock for transmitting the internal data signal DAi to the storage device 20. By delaying the local clock signal SCK, the moment when the storage device 20 drives the external data signal to output is delayed, so that the reception working clock of the control device 10 is synchronized with the external data signal received by the control device 10.

[0083] Optionally, in some embodiments, the second delay module 304 is further used to output the internal data signal DAi after delaying it by a time length of 0.5 cycles to obtain a delayed data signal DA1.

[0084] Optionally, in some embodiments, the second delay module 304 includes one of a clock phase delay module CPDM and a delay chain DLC. Among them, the structure of the second delay module 304 can be referred to Figures 6 - 7 for setting, which will not be elaborated here.

[0085] Optionally, the second delay module 304 can be configured to delay at least one of the internal data signal DAi and the local clock signal SCK through the configuration of the fourth register.

[0086] Optionally, in some embodiments, the clock control device 30 operates in a double data rate mode, and the frequency of the local clock signal SCK is equal to the system clock of the control device 10 (for example, the frequency corresponding to the system clock of the control device 10 is 200 MHz, and the local clock signal SCK is not frequency-divided from the system clock and is also 200 MHz).

[0087] Since when the clock control device 30 operates in a double data rate mode and the frequency of the local clock signal SCK is equal to the system clock of the control device 10, if the control device 10 changes data at the falling edge of the local clock signal SCK, it may be incorrect for the storage device 20 to sample data at the rising edge of the local clock signal SCK. To ensure that the data sampled by the storage device 20 is correct, when the clock control device 30 operates in a double data rate mode and the frequency of the local clock signal SCK is equal to the system clock of the control device 10, the second delay module 304 is used to delay the local clock signal SCK by a time length within 0.5 cycles and output the internal data signal DAi after delaying it by a time length of 0.5 cycles, so that the rising edge of the local clock signal SCK is synchronously postponed backward to the center position of the original internal data signal DAi, so that the storage device 20 can sample the data of the delayed internal data signal DA1.

[0088] Optionally, in some embodiments, the first delay module 303 and the second delay module 304 are disposed in the microcontroller unit.

[0089] Figure 9 is a flowchart of a clock control method for a serial peripheral interface provided by an embodiment of the present invention. The present invention also provides a clock control method for a serial peripheral interface. The clock control method includes:

[0090] Step S1: Receive a local clock signal SCK and an external clock signal DQS, and delay the local clock signal SCK to output a local delayed clock signal rclk;

[0091] Step S2: Select one of the external clock signal DQS and the local delayed clock signal rclk as a basic clock signal bclk according to a clock selection control signal rcksel; and,

[0092] Step S3: Perform phase delay on the basic clock signal bclk to output a first delayed clock signal dclk. The first delayed clock signal dclk is used by the control device 10 as a reception working clock for sampling an external data signal transmitted by the sampling storage device 20.

[0093] Optionally, as Figure 2 shown, the local clock signal SCK is delayed by the local delay module 301, the basic clock signal bclk is selected by the clock selection module 302 according to the clock selection control signal rcksel, and the basic clock signal bclk is phase-delayed by the first delay module 303.

[0094] As Figure 10 is a flowchart of generating a local delayed clock signal provided by an embodiment of the present invention; optionally, in step S1, it includes:

[0095] Step S11: According to a preset input delay value, control the local clock signal SCK to be delayed by an integer multiple of a first unit time length, and then enable a gating signal ck_en; and,

[0096] Step S12: Gate the delayed local clock signal SCK according to the gating signal ck_en to generate a local delayed clock signal rclk.

[0097] Optionally, as Figure 2As shown, the preset input delay value can be configured through the first register 3011 to implement delaying the local clock signal SCK by an integer multiple of the first unit duration. Through the delay control unit 3012, after delaying the local clock signal SCK by an integer multiple of the first unit duration, the gating signal ck_en is enabled. The local delayed clock signal rclk is generated through the gating unit 3013.

[0098] Optionally, in some embodiments, in step S3, it includes step S31: According to the preset input delay value, delay the basic clock signal bclk by a second duration less than or equal to the first unit duration to output it as the first delayed clock signal dclk.

[0099] Among them, the basic clock signal bclk is delayed by the second duration through the first delay module 303 to output it as the first delayed clock signal dclk.

[0100] In addition to Figure 9 adjusting the receiving working clock of the control device 10 through the steps shown, the transmitting working clock of the control device 10 can also be adjusted. Optionally, in some embodiments, the clock control method further includes: In the double data rate mode and when the frequency of the local clock signal SCK is equal to the system clock of the control device 10, according to the preset output delay value, delay the local clock signal SCK by a duration within 0.5 cycles, and delay the internal data signal (i.e., DAi) by a time length of 0.5 cycles for output, so that the control device 10 can use it as the transmitting working clock for transmitting the internal data signal to the storage device 20.

[0101] Optionally, the preset output delay value can be configured through the fourth register to delay the local clock signal SCK by a duration within 0.5 cycles and delay the internal data signal by a time length of 0.5 cycles through the second delay module 304 in the double data rate mode and when the frequency of the local clock signal SCK is equal to the system clock of the control device 10.

[0102] Optionally, before configuring according to the preset input delay value (such as step S11) and the preset output delay value (such as step S31), it is also necessary to first obtain the preset input delay value and the preset output delay value through the scan test process. Therefore, before the step of configuring according to the preset input delay value and the preset output delay value, it also includes the scan test process steps for how to obtain the preset input delay value and the preset output delay value.

[0103] Figure 11 It is a flowchart for obtaining the preset input delay value when the local clock signal is used as the reference clock signal provided by the embodiments of the present invention. Before step S11, it includes:

[0104] Step S101: Gradually adjust the input delay value in the second unit time period, and delay the local clock signal SCK according to the delay time period corresponding to the input delay value.

[0105] Step S102: In the read mode, select the delayed local clock signal SCK to sample the external data signal.

[0106] When the external data signal cannot be successfully sampled in Step S102, execute Step S103a: Record the delay time period corresponding to the input delay value as the first delay value, and determine whether the first delay value is less than the first unit time period.

[0107] When the judgment result of Step S103a is yes (that is, when the first delay value is less than the first unit time period), repeat Steps S101 to S102, and when the external data signal cannot be successfully sampled in Step S102, repeat Step S103a.

[0108] When the judgment result of Step S103a is no (such as when the first delay value is equal to the first unit time period), execute Step S104a: That is, calculate the product of the number of times the first delay value is equal to the first unit time period and the first unit time period, so as to delay the local clock signal SCK by an integer multiple of the first unit time period. After executing Step S104a, repeat Steps S101 to S102 again, and when the external data signal cannot be successfully sampled in Step S102, repeat Step S103a; when the judgment result of Step S103a is no, repeat Step S104a.

[0109] When the external data signal is successfully sampled in Step S102, execute the following steps:

[0110] Step S103b: Record the input delay value as the first value.

[0111] Step S104b: Continue to gradually adjust the input delay value in the second unit time period, delay the local clock signal SCK according to the delay time period corresponding to the input delay value, and correspondingly sample the external data signal in the read mode until the external data signal cannot be successfully sampled in the read mode, and record the corresponding input delay value as the second value.

[0112] Step S105: Calculate the average value of the first value and the second value to obtain the preset input delay value corresponding to the control device 10 when using the local clock signal SCK as the basic clock signal bclk.

[0113] Among them, the second unit time period corresponds to the delay time period that each delay unit DU of the first delay module 303 can achieve. Optionally, the second unit time period is in picoseconds.

[0114] Please continue to refer to Figures 3 - 4 , in the single data rate mode, both the control device 10 and the storage device 20 send data corresponding to the falling edge of the local clock signal SCK and sample data corresponding to the rising edge of the local clock signal SCK, and the rising edge of the local clock signal SCK corresponds to the data center position. Therefore, in the single data rate mode, the commands and data sent from the control device 10 to the storage device 20 can be accurately received by the storage device 20, but the data fed back from the storage device 20 to the control device 10 may not be received by the control device 10 due to the delay on the transmission path. In the double data rate mode, the control device 10 and the storage device 20 each send one bit of data corresponding to both the rising edge and the falling edge of the local clock signal SCK. Therefore, when the control device 10 sends and receives data, affected by the delay on the transmission path, the data sent by the control device 10 may not be received by the storage device 20, and the data sent by the storage device 20 may not be received by the control device 10 either. Therefore, the steps shown in Figure 11 can be executed in the single data rate mode to first determine the preset input delay value corresponding to when the control device 10 receives the data sent by the storage device 20 as the receiving end. The preset input value determined in the single data rate mode is applicable to the double data rate mode.

[0115] Therefore, before step S101, it further includes:

[0116] Step S1001: Set the system clock of the control device 10 to the first frequency, initialize the storage device 20 in the single data rate mode, and write data into the storage device 20;

[0117] Step S1002: Set the system clock of the control device 10 to the second frequency, and sample the data of the storage device 20 in the single data rate mode and when the first delay module 303 is not enabled. If the data of the storage device 20 can be successfully sampled, set the sampling success flag bit.

[0118] Among them, the first frequency can be 30 MHz, and the second frequency can be 200 MHz.

[0119] Optionally, as shown in Figure 7 , the first delay module 303 can be enabled through the first delay enable signal, and the number of delay chains DLC in the first delay module 303 can be configured through the third register. If the delay chain selection signal is set to 1, one delay chain DLC in the first delay module 303 is selected for invocation.

[0120] Optionally, as shown in Figure 6As shown, the number of delay units DU in the first delay module 303 can be determined according to the input delay value, and the local clock signal SCK can be delayed by applying the delay duration achievable by the called delay unit DU.

[0121] Optionally, the value range of the input delay value is 0 to X. Here, X is the number of delay units DU included in the first delay module 303.

[0122] Optionally, when the input delay value is set to 1, 1 delay unit DU is called correspondingly. Correspondingly, the first delay module 303 delays the local clock signal according to the delay duration achievable by one delay unit DU (i.e., the second unit duration).

[0123] Optionally, the number of called delay units DU is configured through the second register 3031. The input delay value is the value configured by the second register 3031.

[0124] To verify whether the setting of the input delay value is appropriate, after delaying the local clock signal SCK according to the input delay value, the configuration control device 10 samples the external data signal in the read mode by applying the delayed local clock signal SCK, so as to verify whether the setting of the input delay value is appropriate according to whether data can be sampled by the configuration control device 10 in the read mode.

[0125] Since the delay duration achievable by each delay unit DU is less than the first unit duration, and the input delay value can be incremented from 0 or decremented from X, thus, when the input delay value is incremented from 0 or decremented from X to the delay duration achievable by the called multiple delay units DU equal to the first unit duration or an integer multiple of the first unit duration, the local delay module 301 can be directly called to delay the local clock signal SCK, so as to reduce the number of delay units DU called in the first delay module 303. Therefore, by judging whether the first delay value is less than the first unit duration, the configurations of the first sub-register and the second sub-register in the local delay module 301 can be correspondingly obtained. The delay duration of the local clock signal SCK by the local delay module 301 can be obtained according to the product of the number of times the first delay value is equal to the first unit duration and the first unit duration.

[0126] Therefore, in the step of obtaining the preset input delay value, there is a nested loop of two layers. The inner loop adjusts the input delay value in terms of the second unit duration so that multiple delay units DU of the first delay module 303 delay the local clock signal SCK. The outer loop is that the local delay module 301 delays the local clock signal SCK in integer multiples of the first unit duration.

[0127] Optionally, when executing Figure 11When performing the steps shown, the input delay value decreases from X to save the scanning time. Optionally, when the input delay value decreases from X, the input delay value decreases by 1 each time to control the compensation accuracy.

[0128] In order to make the control device 10 sample the external data signal corresponding to the center position of the external data signal when performing the steps shown, an average value is calculated based on the first value corresponding to the successful sampling of the external data signal for the first time and the input delay value (i.e., the second value) corresponding to the situation where the external data signal cannot be successfully sampled again after the first successful sampling of the external data signal, and this average value is used as the preset input delay value corresponding to when the local clock signal SCK is based on the basic clock signal bclk. Figure 11

[0129] Optionally, the reading mode includes an indirect reading mode.

[0130] Figure 11 According to Figure 11 the steps shown, the preset input delay value corresponding to when the control device 10 receives the data sent by the storage device 20 as the receiving end and the local clock signal SCK is based on the basic clock signal bclk has been determined. Therefore, based on the steps shown, the preset output delay value corresponding to when the control device 10 is the output end can be further obtained.

[0131] Figure 12 Correspondingly, is the flowchart for obtaining the preset output delay value provided by the embodiment of the present invention. After step S105, it includes:

[0132] Step S106: In the double data rate mode, control the frequency of the local clock signal SCK to be the system clock of the control device 10, and gradually adjust and set the output delay value in the third unit time length to delay the local clock signal SCK according to the delay time length corresponding to the output delay value.

[0133] Step S107: Sample the external data signal in the reading mode.

[0134] When the external data signal cannot be successfully sampled in step S107, continue to repeat steps S106 to S107.

[0135] When the external data signal is successfully sampled in step S107, perform the following steps:

[0136] Step S108: Record the output delay value as the third value.

[0137] ​Step S109: Continue to gradually adjust the output delay value in the third unit time duration, delay the local clock signal SCK according to the delay time duration corresponding to the output delay value, and sample the external data signal correspondingly in the read mode until the external data signal cannot be sampled in the read mode, and record the corresponding output delay value as the fourth value.

[0138] Step S1010: Calculate the average value of the third value and the fourth value to obtain the preset output delay value.

[0139] Among them, the third unit time duration corresponds to the delay time duration that each delay unit DU of the second delay module 304 can achieve.

[0140] Optionally, in the double data rate mode, control the frequency of the local clock signal SCK to be 200 MHz.

[0141] Optionally, the second delay module 304 can be enabled through the second delay enable signal, and the number of delay units DU in the second delay module 304 is determined according to the output delay value, so as to apply the delay time duration that the called delay unit DU can achieve to delay the local clock signal SCK.

[0142] Optionally, as Figure 6 shown, the value range of the output delay value is 0 to Y. Among them, Y is the number of delay units DU included in the second delay module 304. Optionally, when the output delay value is set to 1, 1 delay unit DU is correspondingly called, and the second delay module 304 delays the local clock signal according to the delay time duration that one delay unit DU can achieve (i.e., the third unit time duration). Optionally, when performing Figure 12 the steps shown, the output delay value increases from 0.

[0143] Optionally, configure the number of called delay units DU through the fourth register. The output delay value is the value configured by the fourth register.

[0144] To verify whether the setting of the output delay value is appropriate, after delaying the local clock signal SCK according to the output delay value, configure the control device 10 to sample the external data signal in the read mode by using the delayed local clock signal SCK, so as to verify whether the setting of the output delay value is appropriate according to whether the control device 10 can sample data in the read mode.

[0145] Based on the third value corresponding to the first successful sampling of the external data signal and the output delay value (i.e., the fourth value) corresponding to the inability to successfully sample the external data signal again after the first successful sampling of the external data signal, calculate the average value as the preset output delay value corresponding to the local clock signal SCK as the basic clock signal bclk.

[0146] Optionally, after step S1010, it further includes: switching the memory mapping mode and sampling the external data signal.

[0147] In some embodiments, since the storage module supports the design of the external clock signal DQS, the control device 10 can sample the external data signal according to the external clock signal DQS. Therefore, based on the determined preset output delay value, the corresponding preset input delay value when the external clock signal DQS is used as the base clock signal bclk can be obtained.

[0148] Correspondingly, Figure 13 FIG. is a flowchart of obtaining a preset input delay value when the external clock signal is used as the reference clock signal according to an embodiment of the present invention. After step S1010, it includes:

[0149] Step S1011: Select the external clock signal DQS as the base clock signal bclk.

[0150] Step S1012: Gradually adjust and set the input delay value in the second unit time length, and delay the external clock signal DQS according to the delay time length corresponding to the input delay value.

[0151] Step S1013: In the read mode, select the delayed external clock signal DQS to sample the external data signal.

[0152] When the external data signal cannot be successfully sampled in step S1013, repeat steps S1012 to S1013.

[0153] When the external data signal is successfully sampled in step S1013, execute the following steps:

[0154] Step S1014: Record the input delay value as the fifth value.

[0155] Step S1015: Continue to gradually adjust the input delay value in the second unit time length, delay the external clock signal DQS according to the delay time length corresponding to the input delay value, and sample the external data signal in the read mode until the external data signal cannot be sampled in the read mode, and record the corresponding input delay value as the sixth value.

[0156] Step S1016: Calculate the average value of the fifth value and the sixth value to obtain the preset input delay value corresponding to the control device 10 when the external clock signal DQS is used as the base clock signal bclk.

[0157] In Figure 13In the steps shown, the first delay module 303 can still be enabled through the first delayed enable signal, the number of delay chains in the first delay module 303 can be selected and called through the delay chain selection signal, and the number of delay units DU in the first delay module 303 can be determined through the input delay value, so as to apply the delay duration that can be achieved by the called delay unit DU to delay the external clock signal DQS. It can be understood that in the execution of Figure 11 and Figure 13 steps, the value of the delay chain selection signal can be different, and the value of the input delay value can be different.

[0158] Optionally, in the execution of Figure 11 and Figure 13 steps, the corresponding second unit duration can be different.

[0159] It can be understood that since the external data signal and the external clock signal DQS are transmitted to the control device 10 through similar transmission paths, therefore, when the control device 10 uses the external clock signal DQS as the basic clock signal bclk, the step of obtaining the preset input delay value can use only one layer of loop (that is, adjusting the input delay value with the second unit duration so that multiple delay units DU of the first delay module 303 delay the external clock signal DQS).

[0160] After delaying the external clock signal DQS according to the input delay value, configure the control device 10 to sample the external data signal using the delayed external clock signal DQS in the read mode, so as to verify whether the setting of the input delay value is appropriate when the corresponding external clock signal DQS is used as the basic clock signal bclk according to whether data can be sampled by the control device 10 in the read mode.

[0161] Calculate the average value based on the fifth value corresponding to the successful sampling of the external data signal for the first time and the input delay value (i.e., the sixth value) corresponding to the failure to sample the external data signal again after the first successful sampling of the external data signal, so as to be used as the preset input delay value corresponding to the external clock signal DQS as the basic clock signal bclk.

[0162] Optionally, after step 1016, it further includes: switching the memory mapping mode, sampling the external data signal, so as to verify whether the preset input delay value and the setting of the preset input delay value are applicable to the double data rate mode.

[0163] In this article, specific examples are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A clock control device for a serial peripheral interface, which is provided in a control device, wherein the control device communicates with a storage device through the serial peripheral interface, and is characterized in that, Comprising: A local delay module for receiving the local clock signal of the control device, delaying it, and outputting a local delayed clock signal; A clock selection module for receiving the local delayed clock signal and an external clock signal, and selecting one of the clock signals as the basic clock signal for output; And A first delay module for performing phase delay on the basic clock signal to output a first delayed clock signal for the control device to use as the receiving working clock for sampling the external data signal transmitted by the storage device.

2. The clock control device according to claim 1, characterized in that, The external clock signal comes from the storage device and is synchronized with the external data signal.

3. The clock control device according to claim 1, characterized in that, The local delay module is used to delay the local clock signal by an integer multiple of a first unit duration.

4. The clock control device according to claim 3, characterized in that, The first unit duration is equal to 0.5 cycles of the local clock signal.

5. The clock control device according to claim 3, characterized in that, The local delay module includes: A first register for configuring the delay of the local clock signal, and the delay is equal to an integer multiple of the first unit duration; A delay control unit for controlling the enabling of a gating signal after the delay of the local clock signal according to the configuration of the first register; A gating unit for gating the local clock signal according to the gating signal to generate the local delayed clock signal.

6. The clock control device according to claim 3, characterized in that, The first delay module is used to delay the basic clock signal by a second duration and includes one of a clock phase delay module and a delay chain.

7. The clock control device according to claim 6, characterized in that, The second duration is less than or equal to the first unit duration.

8. The clock control device according to claim 6, characterized in that, The first delay module adjusts 1 cycle of the basic clock signal through P levels of time lengths, and the second duration is set by setting M bits out of N bits in P second registers, where M is less than or equal to N, and P is configured by a third register.

9. The clock control device according to claim 1, characterized in that, The clock control device further includes a second delay module for delaying the local clock signal by a time length within 0.5 cycles for the control device to use as the sending working clock for transmitting internal data signals to the storage device.

10. The clock control device according to claim 9, characterized in that, The second delay module is further used to delay the internal data signal by a time length of 0.5 cycles for output.

11. The clock control device according to claim 9, characterized in that, The clock control device operates in a double data rate mode, and the frequency of the local clock signal is equal to the system clock of the control device.

12. The clock control device according to claim 9, characterized in that, The second delay module includes one of a clock phase delay module and a delay chain.

13. The clock control device according to claim 9, characterized in that, The first delay module and the second delay module are arranged in a micro control unit.

14. A clock control method for a serial peripheral interface, characterized in that, The clock control method includes: Receiving a local clock signal and an external clock signal, and delaying the local clock signal to output a local delayed clock signal; Selecting one of the external clock signal and the local delayed clock signal as the basic clock signal according to a clock selection control signal; Performing phase delay on the basic clock signal to output a first delayed clock signal; wherein, the first delayed clock signal is used by the control device as the receiving working clock for sampling the external data signal transmitted by the storage device.

15. The clock control method according to claim 14, wherein, The step of delaying the local clock signal to output a local delayed clock signal includes: According to a preset input delay value, after controlling the local clock signal to be delayed by an integer multiple of a first unit duration, enable the gating signal; Gate the delayed local clock signal according to the gating signal to generate the local delayed clock signal.

16. The clock control method according to claim 15, wherein, The step of performing phase delay on the basic clock signal to output a first delayed clock signal includes: According to the preset input delay value, delay the basic clock signal by a second duration less than or equal to the first unit duration, and output it as the first delayed clock signal.

17. The clock control method according to claim 14, wherein, The clock control method further includes: In the double data rate mode, when the frequency of the local clock signal is equal to the system clock of the control device, according to a preset output delay value, delay the local clock signal by a duration within 0.5 cycle, and delay the internal data signal by a duration of 0.5 cycle for output, so that the control device uses it as the transmission working clock for transmitting the internal data signal to the storage device.

18. The clock control method according to claim 16, wherein, Before the step of, according to a preset input delay value, controlling the local clock signal to be delayed by an integer multiple of a first unit duration and then enabling the gating signal, it includes: Gradually adjust the input delay value in a second unit duration, and delay the local clock signal according to the delay duration corresponding to the input delay value; In the read mode, select the delayed local clock signal to sample the external data signal; When the external data signal cannot be successfully sampled in the read mode, record the delay duration corresponding to the input delay value as a first delay value, and determine whether the first delay value is less than the first unit duration; When the first delay value is less than the first unit duration, continue to gradually adjust the input delay value in the second unit duration, delay the local clock signal according to the delay duration corresponding to the input delay value, and sample the external data signal in the read mode, so as to update the recorded first delay value when the external data signal cannot be successfully sampled in the read mode, and determine whether the first delay value is less than the first unit duration; When the first delay value is equal to the first unit duration, calculate the product of the number of times the first delay value is equal to the first unit duration and the first unit duration, delay the local clock signal by an integer multiple of the first unit duration, reset the input delay value, delay the local clock signal according to the delay duration corresponding to the input delay value, and sample the external data signal in the read mode; When the external data signal is successfully sampled in the read mode, record the input delay value as a first value; Continue to gradually adjust the input delay value in the second unit duration and delay the local clock signal according to the delay duration corresponding to the input delay value, and correspondingly sample the external data signal in the read mode until the input delay value corresponding thereto is recorded as a second value when the external data signal cannot be successfully sampled in the read mode; Calculate the average value of the first value and the second value to obtain the preset input delay value corresponding to the control device when using the local clock signal as the base clock signal.

19. The clock control method according to claim 18, wherein, After the step of calculating the average value of the first value and the second value to obtain the preset input delay value corresponding to the control device when using the local clock signal as the base clock signal, the following steps are included: In double data rate mode, control the frequency of the local clock signal to be the system clock of the control device, and gradually adjust and set the output delay value in third unit time intervals, and delay the local clock signal according to the delay duration corresponding to the output delay value; Sample the external data signal in the read mode; When the external data signal cannot be successfully sampled in the read mode, continue to adjust the output delay value and delay the local clock signal according to the delay duration corresponding to the output delay value, and sample the external data signal in the read mode correspondingly; When the external data signal is successfully sampled in the read mode, record the output delay value as the third value; Continue to gradually adjust the output delay value in third unit time intervals and delay the local clock signal according to the delay duration corresponding to the output delay value, and sample the external data signal in the read mode correspondingly, until the external data signal cannot be sampled in the read mode, and record the corresponding output delay value as the fourth value; Calculate the average value of the third value and the fourth value to obtain the preset output delay value.

20. The clock control method according to claim 19, wherein, After the step of calculating the average value of the third value and the fourth value to obtain the preset output delay value, the following steps are included: Select the external clock signal as the base clock signal; Gradually adjust and set the input delay value in second unit time intervals, and delay the external clock signal according to the delay duration corresponding to the input delay value; In the read mode, select the delayed external clock signal to sample the external data signal; When the external data signal cannot be successfully sampled in the read mode, continue to gradually adjust the input delay value in second unit time intervals and delay the external clock signal according to the delay duration corresponding to the input delay value, and sample the external data signal in the read mode; When the external data signal is successfully sampled in the read mode, record the input delay value as the fifth value; Continue to gradually adjust the input delay value in second unit time intervals and delay the external clock signal according to the delay duration corresponding to the input delay value, and sample the external data signal in the read mode, until the external data signal cannot be sampled in the read mode, and record the corresponding input delay value as the sixth value; Calculate the average value of the fifth value and the sixth value to obtain the preset input delay value corresponding to the control device when using the external clock signal as the basic clock signal.

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