Driving method for driving display panel, driving integrated circuit, and display device

Abstract

The present disclosure relates to a driving method for driving a display panel, the driving method comprising: determining whether to perform a refresh operation on a current frame to be displayed by the display panel; and when it is determined that the refresh operation is not performed on the current frame, not transmitting a frame scan start signal (such as an STV signal) to the display panel, and reducing a frequency of a gate clock signal or fixing the gate clock signal to a specific voltage level.

Description

Technical Field

[0001] The present disclosure relates to a driving technology of a display panel, and more particularly, to a driving method, a driving integrated circuit, and a display device for a display panel. Background Art

[0002] With the continuous development of display technology, consumers have higher and higher requirements for the performance of display screens (such as the screens of mobile phones or tablets). Therefore, in order to improve the user experience, it is not only required that the images presented by the display panel have high resolution, good color, and brightness, but also the smoothness of dynamic pictures should be ensured, and this performance index is mainly determined by the refresh rate of the display panel.

[0003] In this field, the refresh rate refers to the number of times of refreshing the displayed picture within a unit time. Each displayed picture corresponds to one frame. Therefore, the refresh rate can also be called the frame rate, which is usually measured in Hertz (Hz). Currently, common frame rates of display screens are, for example, 60Hz, 90Hz, 144Hz, 240Hz. For example, if the frame rate of a display panel is 60Hz, it means that the display panel displays 60 frames of pictures per second. Thus, the higher the frame rate of the display panel, the smoother the dynamic pictures presented, and the better the user's viewing experience of the dynamic pictures. Relatively, since the number of frames to be displayed within a unit time increases, it means that the frequency of scanning and resetting (i.e., refreshing operation) of pixels by the display panel will also increase, which will cause the overall power consumption of the display panel to increase sharply accordingly, and further lead to problems such as insufficient battery life and overheating of the display device. Summary of the Invention

[0004] In view of this, technologies such as adaptive frame rate and multi - area frame rate can be adopted, so that the display panel can display at different frame rates according to the characteristics of the picture to be displayed. For example, a lower frame rate is used to display static pictures or static areas in the picture, thereby reducing the power consumption of the display panel to a certain extent. Nevertheless, there is still a need in this field to propose a method and device for further reducing the power consumption of the display panel.

[0005] To at least solve the above - mentioned technical problems in this field, the present disclosure provides a driving method, a driving integrated circuit, and a corresponding display device for driving a display panel to reduce the power consumption of the display panel.

[0006] According to one aspect of the present disclosure, there is provided a driving method for driving a display panel, the driving method including: determining whether to perform a refresh operation on a current frame to be displayed by the display panel; and when it is determined not to perform a refresh operation on the current frame, not sending a frame scan start signal to the display panel.

[0007] Wherein, according to an embodiment of the present disclosure, the driving method further includes: when it is determined that no refresh operation is to be performed on the current frame, reducing the frequency of the gate clock signal sent to the display panel or fixing the gate clock signal sent to the display panel at a specific voltage level.

[0008] Wherein, according to an embodiment of the present disclosure, the driving method further includes: obtaining frame refresh information indicating whether a refresh operation is to be performed on at least a part of the current frame; and determining whether to perform a refresh operation on at least a part of the current frame to be displayed on the display panel according to the frame refresh information; wherein, when it is determined that no refresh operation is to be performed on all regions of the current frame, no frame scan start signal is sent to the display panel, and the frequency of the gate clock signal is reduced or the gate clock signal is fixed at a specific voltage level; and when it is determined that a refresh operation is to be performed on at least a part of the current frame, a frame scan start signal is sent to the display panel to start the refresh operation on at least a part of the regions, specifically, a frame scan start signal, a refresh control signal, and a gate clock signal are sent to the gate driving circuit integrated on the array of the display panel; wherein, the gate driving circuit integrated on the array is composed of a plurality of cascaded gate driving units, and in response to the first-stage gate driving unit in the gate driving circuit integrated on the array receiving the frame scan start signal, the gate driving circuit integrated on the array performs a refresh operation on at least a part of the regions based on the refresh control signal and the gate clock signal.

[0009] According to another aspect of the present disclosure, there is provided a driving integrated circuit for driving a display panel, including: a module for determining whether to perform a refresh operation on the current frame to be displayed on the display panel; and a module for sending a frame scan start signal for starting the refresh operation and a gate clock signal for performing the refresh operation to the display panel, wherein when it is determined that no refresh operation is to be performed on the current frame, the driving integrated circuit does not send a frame scan start signal to the display panel.

[0010] Wherein, according to an embodiment of the present disclosure, when it is determined that no refresh operation is to be performed on the current frame, the driving integrated circuit reduces the frequency of the gate clock signal or fixes the gate clock signal at a specific voltage level.

[0011] Wherein, according to an embodiment of the present disclosure, the driving integrated circuit further includes a module for obtaining frame refresh information, wherein the frame refresh information indicates whether a refresh operation is to be performed on at least a part of the current frame, and the driving integrated circuit determines whether to perform a refresh operation on at least a part of the current frame according to the frame refresh information; and when it is determined that no refresh operation is to be performed on all regions of the current frame, the driving integrated circuit does not send a frame scan start signal to the display panel, and reduces the frequency of the gate clock signal or fixes the gate clock signal at a specific voltage level.

[0012] According to another aspect of the present disclosure, a display device is provided, including: a display panel including an integrated-on-array gate driving circuit composed of a plurality of cascaded gate driving units; and a driving integrated circuit configured to receive frame refresh information indicating whether to perform a refresh operation on at least a part of regions in a current frame to be displayed on the display panel, and send a frame scan start signal for starting the refresh operation to the integrated-on-array gate driving circuit, wherein when the frame refresh information indicates that no refresh operation is to be performed on all regions in the current frame, the driving integrated circuit does not send the frame scan start signal to the integrated-on-array gate driving circuit, and / or the driving integrated circuit reduces the frequency of the gate clock signal or fixes the gate clock signal at a specific voltage level.

[0013] According to the above driving method for driving a display panel and the driving integrated circuit of the present disclosure, the behavior of sending relevant signals to the display panel can be adjusted according to whether a current frame or at least a part of regions therein needs to perform a refresh operation. Specifically, the present disclosure proposes a scheme for a dynamic frame scan start signal. For frames that do not need to be refreshed, no frame scan start signal is provided, thereby reducing the switching loss of the gate driving circuit. Further, a scheme for dynamic gate clock refresh is also proposed. For frames that do not need to be refreshed, by reducing the frequency of the gate clock signal or fixing the gate clock signal at a specific level, the power consumption can be further reduced and normal display can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Advantages of various aspects of the present disclosure will become clearer and easier to understand from the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings, wherein:

[0015] Figure 1A is a block diagram showing a display panel and a driving integrated circuit for driving the display panel according to an embodiment of the present disclosure;

[0016] Figure 1B is a block diagram showing another display panel and a driving integrated circuit for driving the display panel according to an embodiment of the present disclosure;

[0017] Figure 2 is a schematic structural diagram showing an integrated-on-array gate driving circuit according to an embodiment of the present disclosure;

[0018] Figure 3 is an exemplary circuit diagram showing a first-stage gate driving unit in the integrated-on-array gate driving circuit according to an embodiment of the present disclosure;

[0019] Figure 4 is a signal timing diagram showing a conventional signal for controlling a refresh operation;

[0020] Figure 5 is an overall flowchart showing a driving method for driving a display panel by an integrated circuit according to an embodiment of the present disclosure;

[0021] Figures 6 - 7 is a signal timing diagram showing a signal for controlling a refresh operation; and

[0022] Figure 8 is a schematic diagram of a display panel based on multi-region frame rate control according to an embodiment of the present disclosure.

[0023] It should be understood that these drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, and do not constitute a limitation to the present disclosure. In addition, in the drawings, the same reference numerals generally represent the same elements or steps.

[0024] List of Reference Numerals

[0025] 100: Display panel

[0026] 101: Dynamic region

[0027] 102: Static region

[0028] 110: Pixel array

[0029] 120, 120’: Gate driver circuit integrated on array

[0030] 121 to 12n: First-stage gate driving units

[0031] 1210: Logic operation module

[0032] 200: Driving integrated circuit

[0033] 210: Interface unit

[0034] 220: Control unit

[0035] 230: Source driver unit Detailed Embodiments

[0036] In order to better elaborate the technical solutions of the present disclosure, the present disclosure will be described in detail below with reference to the drawings and specific embodiments. It should be understood that based on the embodiments described in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure, and the embodiments described herein are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. These embodiments are merely illustrative and exemplary, and therefore should not be construed as limiting the scope of the present disclosure.

[0037] In the following, for purposes of illustration rather than limitation, the present disclosure will mainly describe the technical concept of the present disclosure by taking a display panel based on multi-region frame rate control as an example. It should be understood that the technical solution of the present disclosure can also be applied to display panels of other frame refresh technologies such as adaptive frame rate.

[0038] Figure 1A is a block diagram showing a display panel and a driving integrated circuit for driving the display panel according to an embodiment of the present disclosure. As Figure 1A shown, the display panel 100 may include a pixel array 110 and a gate drive on array (GOA) circuit 120. The pixel array 110 is an array composed of pixels in multiple rows and columns. The GOA circuit 120 is coupled to the gate lines in the pixel array 110 to perform a row-by-row scan of the corresponding pixel rows in the pixel array 110 to execute a refresh operation on the pixels. The internal circuit of the GOA circuit will be described in detail below in conjunction with Figures 2 - 3 In addition, the driving integrated circuit 200 is configured to receive display-related signals and provide several signals for driving and displaying to the display panel 100. Specifically, it may include: an interface unit 210, which is configured to receive a frame display signal related to the current frame to be displayed on the display panel 100 (e.g., from an external device or other components of the device), such as frame refresh information indicating whether to perform a refresh operation on the current frame, display data for displaying the current frame, or signals of this kind; a control unit 220, which is configured to provide a frame scan start (such as "source timing validation", STV) signal to the GOA circuit 120 in the display panel 100 according to the frame display signal, so that the GOA circuit 120 can start the execution of the GOA refresh operation in response to this signal, and send a refresh control (such as "multi-region frame rate control", MAFR_CTRL) signal and a gate clock (GCK) signal to the GOA circuit 120, so that the GOA circuit 120 can perform a refresh operation based on the MAFR_CTRL signal and the GCK signal; and a source drive unit 230, which is coupled to the source lines in the pixel array 110 to provide an image data (Data) signal for displaying to the pixel array 110. In addition, the interface unit 210, the control unit 220, and the source drive unit 230 can be communicatively coupled to each other to achieve signal transmission. The various units included in the driving integrated circuit 200 described in the above example are only examples. It can be understood that the driving integrated circuit 200 may also include other units that perform necessary functions, and these units can also be implemented by one or more other units integrated with the corresponding functions.

[0039] In addition, Figure 1BIt is a block diagram showing another display panel and a driving integrated circuit for driving the display panel according to an embodiment of the present disclosure. Figure 1B is the same as Figure 1A in most configurations, so some block diagrams with the same configuration are omitted. The difference between it and Figure 1A is that a bilateral driving structure is adopted. As shown in the figure, symmetric GOA circuits 120 and 120' are provided on both sides of the pixel array 110, and the two GOA circuits jointly drive the gates of the pixel array 110.

[0040] To better understand the benefits of the present disclosure, the following will take the GOA circuit 120 as an example and describe the specific circuit structure and driving principle in detail in combination with Figures 2 to 4

[0041] Figure 2 is a schematic structural diagram showing the GOA circuit 120 according to an embodiment of the present disclosure. As Figure 2 shown, the GOA circuit 120 is composed of a plurality of cascaded gate driving units, and each gate driving unit is coupled to a corresponding pixel row in the pixel array 110, so as to realize the progressive scanning of the pixel array 110 through a signal transmission mode similar to a shift register. Specifically, the driving integrated circuit 200 sends a frame scan start signal (such as an STV signal) to the first-stage gate driving unit 121 in the GOA circuit 120 as an input signal to start the gate driving unit 121, so that the gate driving unit 121 can output a driving signal G1 for performing the refresh operation of the corresponding pixel row according to the region refresh control (MAFR_CTRL) signal and the gate clock (GCK1-GCKn) signal received from the driving integrated circuit 200, and the driving signal G1 output by the first-stage gate driving unit 121 also serves as an input signal for the second-stage gate driving unit 122 to start the gate driving unit 122, and the driving signal G2 output by the second-stage gate driving unit 122 also serves as a reset signal for the first-stage gate driving unit 121 to end the refresh operation of the first-stage gate driving unit 121.

[0042] More specifically, Figure 3The figure shows an example circuit diagram of the first-stage gate driving unit 121 in the GOA circuit 120. This example is described by taking the gate driving unit with a 4T1C structure as an example, that is, each gate driving unit may include four thin-film transistors T1 to T4 and one capacitor C. Before the first-stage gate driving unit 121 receives the STV signal, the PU node is initially at a low potential and the transistor T3 is in an off state. In response to the STV signal as the input signal (input) of the first-stage gate driving unit 121, the transistor T1 is turned on, causing the potential of the PU node coupled to the capacitor C to be pulled up, and then the transistor T3 is turned on. At this time, when the GCK1 outputs a high-level signal, the potential of the PU node is further pulled up, causing the source of the transistor T3 to output current and generating a high-level output signal (output). On the other hand, as described above, in response to the driving signal G2 of the second-stage gate driving unit 122 as a reset signal being input to the PD node, the transistors T2 and T4 are turned on, grounding (GND) the capacitor C for discharging, and the level of the output signal becomes low. In this way, the output signal can be further logically operated with the MAFR_CTRL signal through the logic operation module 1210 to generate the gate driving signal (G1) provided by the gate driving unit 121 to the pixel array 110, so as to apply the high / low level gate driving signal to the corresponding gate line, thereby realizing the gating of the corresponding pixel row. Further, as described above, the gate driving signal (G1) output by the first-stage gate driving unit 121 also serves as the input signal of the next-stage gate driving unit to start the gate driving unit 122. And so on, the gate driving signals output by each gate driving unit except the first stage and the last stage in multiple cascaded gate driving units will serve as the input signal of the next-stage gate driving unit and the reset signal of the previous-stage gate driving unit. The first-stage gate driving unit takes the frame scan start signal as its input signal and does not output a reset signal, and the last-stage gate driving unit can be reset by an additional (e.g., from a redundant unit) reset signal.

[0043] However, for a display panel such as based on multi-region frame rate control or adaptive frame rate, there may be frames in the display panel that do not perform a refresh operation. For example, the current frame to be displayed is a static picture, while the traditional driving method still continuously outputs a control signal for performing a refresh operation to the display panel, which will cause unnecessary power consumption in the display panel.

[0044] Specifically, Figure 4 is a signal timing diagram showing the traditional method for controlling the refresh operation of the display panel. As Figure 4As shown, taking the driving logic with the low level of the MAFR_Ctrl signal as the valid state as an example, for the first frame, all the MAFR_Ctrl signals are set to the low level, then the pixels corresponding to all regions in this first frame need to perform the refresh operation. For the second frame, part of the MAFR_Ctrl signals are set to the low level, then the pixels corresponding to part of the regions in this second frame need to perform the refresh operation, where the pixel rows corresponding to the high-level MAFR_Ctrl signals do not perform the refresh operation. However, for the third frame, all the MAFR_Ctrl signals are set to the high level, then the pixels corresponding to all regions in this third frame do not perform the refresh operation, that is, the current third frame does not need to perform the refresh operation, but in this case, the STV signal is still output, causing the switching elements in the GOA circuit 120 (such as (such as Figure 3 T1 in) to be turned on and off unnecessarily, thus causing additional switching losses. In addition, during the period when the MAFR_Ctrl signal is in the invalid state, the logic level of the continuously input GCK signal toggles frequently, resulting in a large amount of parasitic losses in the parasitic capacitance of the transistor (such as Figure 3 Cgd between the gate and drain of T3 in), increasing the power consumption in the GOA circuit 120, and further causing an increase in the overall power consumption and heat generation problem of the display panel. Thus, it can be seen that for the case where the current frame does not need to be refreshed, there are still unnecessary power consumptions in the display panel, and this problem also exists in the display panel based on other frame refresh technologies.

[0045] To solve at least the above problems, the present disclosure proposes a driving method and a driving integrated circuit for dynamically adjusting the frame scan start signal and the gate clock signal. Among them, for the frame that does not need to be refreshed, the frame scan start signal is not provided to the display panel, thereby reducing the switching losses of the gate driving circuit, and further reducing the parasitic losses in the circuit by dynamically adjusting the frequency or logic level of the gate clock signal, and ensuring normal display.

[0046] The following will be combined with Figures 5 to 8 to describe each embodiment of the driving method according to the embodiments of the present disclosure.

[0047] Figure 5 is an overall flowchart showing the driving method for driving a display panel according to an embodiment of the present disclosure. As Figure 5 shown, the method 500 may include the following steps:

[0048] In step S501, frame refresh information for controlling the refresh operation of the display panel is obtained. Such frame refresh information can indicate whether to perform a refresh operation on at least a part of the current frame in an explicit or implicit manner. For example, it indicates to perform a refresh operation on the entire current frame, or on different parts of the current frame, or not to perform a refresh operation on the entire current frame. As described above, the driving integrated circuit can be configured to receive frame refresh information from an external device or other components of the device (such as a processor in an electronic device), or can derive from the display data for displaying the current frame frame refresh information indicating whether to perform a refresh operation on at least a part of the current frame.

[0049] In step S502, it is determined whether to perform a refresh operation on the current frame according to the frame refresh information. For example, the interface unit 230 of the driving integrated circuit 200 can further include a signal decoder (not shown), which can decode information such as frame refresh information received from the outside indicating whether to perform a refresh operation on the current frame to determine whether to perform a refresh operation on the current frame. As described above, it can be determined according to the obtained frame refresh information. For example, a refresh operation is performed on all regions of the current frame (for example, corresponding to Figure 4 the first frame in Figure 4 ), a refresh operation is performed on a part of the regions of the current frame (for example, corresponding to Figure 4 the second frame in

[0050] ), or no refresh operation is performed on all regions of the current frame (for example, corresponding to Figure 5 the third frame in Figure 6 ). Figure 7 .

[0051] Specifically, as Figure 6 shown, for the third frame determined not to require a refresh operation according to the frame refresh information, the driving integrated circuit does not send a frame scan start signal to the gate driving circuit of the display panel (such as the gate driving circuit of the GOA circuit 120). As described above in combination with Figures 2 - 3 , at this time, since there is no frame scan start signal as a trigger signal for starting the gate scan, the corresponding switching element in the gate driving circuit (for example, Figure 2T1 to T4) do not perform switching operations, and thus no corresponding switching losses are generated, which can effectively reduce the power consumption of the display panel. Correspondingly, the gate driving circuit also does not output gate driving signals G1 to GN. Therefore, regardless of the logic level of the MAFR_Ctrl signal, no refresh operation is performed on the pixel array displaying the current frame. Additionally or alternatively, the driving integrated circuit can also fix the gate clock signal sent to the display panel to a specific voltage level, such as fixing it to a constant high or low level. At this time, since the logic level of the clock signal does not flip, the charging and discharging behavior of the parasitic capacitance (such as Figure 2 Cgd in) inside the gate driving circuit is effectively suppressed, thereby reducing the parasitic loss, and thus the power consumption of the display panel can be further reduced.

[0052] In addition, in some application scenarios, if the logic level of the clock signal is kept from flipping during the period of not refreshing the current frame, the charges in the capacitive elements of the display panel may not be released. In this case, if the next frame needs to be refreshed and the clock signal is flipped again from the fixed constant level, these charges in the circuit may perform undesired charging and discharging behaviors due to the effect of capacitive coupling, resulting in display abnormalities such as false lighting.

[0053] Therefore, considering that the above-mentioned situations may occur, as Figure 7 shown, instead of fixing the gate clock signal to a constant high or low voltage, the driving integrated circuit can reduce the frequency of the sent gate clock signal, such as reducing it to 1 / 2 or 1 / 3 of the original frequency. Since the loss of the parasitic capacitance is positively correlated with the frequency, the parasitic loss can be reduced as the frequency of the gate clock signal decreases. For example, for a display panel with 1024 rows of pixels, in order to display the current frame at a frame rate of 60Hz, 1024 rows need to be scanned, and the frequency of the corresponding GCK signal is the frame rate × the number of rows, that is, 60 × 1024 = 61440Hz. If the frequency of the GCK signal is reduced to 1 / 3 of this frequency, that is, 20480Hz, the loss caused by the parasitic capacitance can be significantly reduced, and at the same time, the charge release mechanism in the display panel is maintained. For certain types or application scenarios of display panels, this driving method of this embodiment can be selectively used or combined to reduce the power consumption of the display panel.

[0054] On the other hand, when the obtained frame refresh information indicates that a refresh operation is to be performed on the current frame (for example, a refresh operation is performed on all regions or only on some regions), step S505 is entered, and the driving integrated circuit sends a frame scan start signal, as well as a region refresh control signal and a gate clock signal to the display panel. As described above, the driving integrated circuit can send a frame scan start signal to the gate driving circuit (for example, the GOA circuit 120) of the display panel to start the execution of the refresh operation, and send a region refresh control signal and a gate clock signal, so that the gate driving circuit performs corresponding refresh operations based on the refresh control signal and the gate clock signal.

[0055] In step S506, in response to receiving the frame scan start signal from the driving integrated circuit, the gate driving circuit performs a refresh operation based on the region refresh control signal and the gate clock signal. As described above, taking the GOA circuit as an example, the first-stage gate driving unit receives the frame scan start signal to start the gate driving unit, and outputs a driving signal for performing a refresh operation on the corresponding pixel row according to the refresh control signal and the gate clock signal, and the output driving signal is used as the input signal of the next-stage gate driving unit, and the output signal of the next-stage gate driving unit is used as its own reset signal, and so on, to perform a refresh operation on the pixel array row by row.

[0056] Still taking Figure 3 the shown gate driving unit as an example, when the signal Output is active high, MAFR_Ctrl is active low, and the gate driving signal G1 is active low, the logic circuit therein may include an inverter and an "OR" gate. For example, the signal Output is input to the input terminal of the inverter, and the output terminal of the inverter and MAFR_Ctrl are respectively input to the two input terminals of the "OR" gate. Thus, when Output = 1 and MAFR_Ctrl = 0, G1 = 0, that is, when MAFR needs to refresh the first row, a driving signal for scanning the pixels of the first row is output; when Output = 1 and MAFR_Ctrl = 1, G1 = 1, that is, when MAFR does not need to refresh the first row, a driving signal for scanning the pixels of the first row is not output. It should be understood that the structure of this logic circuit is only an example, and the structure of the logic circuit can be designed as needed according to the specific structure of the driving circuit and the driving configuration of the pixel array, etc.

[0057] As can be seen, according to the above driving method for driving a display panel of the present disclosure, a driving scheme based on a dynamic frame start scan signal is provided, that is, for frames that do not need to be refreshed, no frame start scan signal is provided, thereby reducing the switching loss in the circuit. Moreover, according to the above driving method for driving a display panel of the present disclosure, a driving scheme based on a dynamic gate clock signal is further proposed. For frames that do not need to be refreshed, the frequency of the gate clock signal is reduced or fixed at a specific level, thereby further reducing the parasitic loss in the circuit.

[0058] Next, a specific application scenario of the driving method according to an embodiment of the present disclosure will be described in conjunction with Figure 8 In this example, the driving method described above in the present disclosure is applied to a display panel based on multi-region frame rate control. It can be understood that the technical solution of the present disclosure can also be applied to display panels with other frame refresh technologies such as adaptive frame rate.

[0059] Figure 8 is a schematic diagram showing a display panel based on multi-region frame rate control according to an embodiment of the present disclosure. As Figure 8 shown, the display panel 100 is playing a video on a certain video website. The upper part of the display panel 100 is the area where the video is being played, and the picture displayed in this area is dynamically changing, that is, corresponding to the dynamic area 101 of the display panel 100. The lower part of the display panel 100 is the comment area of the video, and the picture displayed in this area basically does not change, that is, corresponding to the static area 102 of the display panel 100. In this scenario, for a plurality of consecutive frames within a period of time, only the plurality of pixels (pixels in rows L1 to Lm) corresponding to the dynamic area 101 in the pixel array 110 of the display panel 100 need to be refreshed, while the plurality of pixels (pixels in rows Lm + 1 to Ln) corresponding to the static area 102 in the display panel 100 do not need to be refreshed. To implement this multi-region frame rate control, the above-mentioned STV, GCK, and MAFR_Ctrl signals can be used to control the GOA circuit 120 according to an embodiment of the present disclosure to drive the corresponding pixel rows, and at the same time, the driving method according to an embodiment of the present disclosure is applied to reduce the overall power consumption of the display panel.

[0060] First, for the frames that only perform refresh operations on a partial area (i.e., the static area 102) as described above, reference can be made to Figure 6Execute the driving method of the present disclosure according to the signal timing of the second frame in []. Specifically, the driving integrated circuit 200 provides an STV signal for starting a refresh operation, a GCK signal determined based on the frame rate to be displayed and the number of pixel rows, and a MAFR_Ctrl signal corresponding to the refresh area to the GOA circuit 120 of the display panel 100. In response to the STV signal received by the first-stage gate driving unit 121 of the GOA circuit 120 from the driving integrated circuit 200, start the refresh operation of the pixels in the L1th row, and output a gate driving signal G1 to the gate line corresponding to the pixels in the L1th row according to the logic levels of the MAFR_Ctrl signal and the GCK signal, and sequentially start and execute the refresh operations of the pixels in the L1th to Lmth rows until the logic level of the MAFR_Ctrl signal is set to an invalid state (i.e., flipped to a high level). In addition, since the logic level of the MAFR_Ctrl signal is set to an invalid state, the output signal in the corresponding gate driving unit does not output a gate driving signal after logical operation with the MAFR_Ctrl signal, so that the pixels in the (Lm + 1)th to Lnth rows do not perform a refresh operation. In this way, a refresh operation is performed on the dynamic area 101 in the display panel while keeping the static area 102 not refreshed, thereby realizing different frame rate controls for multiple areas.

[0061] In addition, for a frame in which no refresh operation is performed on the entire area, for example, when the entire display panel displays a comment area, reference can be made to Figure 6 、 7 Execute the driving method of the present disclosure according to the signal timing of the third frame in []. Specifically, when the frame refresh information indicates that no refresh operation is to be performed on the current frame, the driving integrated circuit 200 does not provide an STV signal for starting a refresh operation to the display panel 100, and optionally, fixes the GCK signal to a specific voltage level or reduces the frequency of the GCK signal. As described above, since the GOA circuit 120 does not receive the STV signal, the switching elements (e.g., Figure 2 T1 to T4 in []) in the gate driving unit therein will not be turned on in response to the STV signal, thus avoiding additional switching losses. And when the GCK signal is fixed to a specific voltage level, since the logic level of the clock signal does not flip, the charging and discharging behaviors of the parasitic capacitances (e.g., Figure 2 Cgd in []) inside the gate driving circuit are effectively suppressed, thereby reducing the parasitic losses, and thus the power consumption of the display panel can be further reduced. In addition, for certain types of display panels or application scenarios, in order to avoid possible display abnormalities, the frequency of sending the GCK signal can be reduced instead of fixing it to a specific voltage level, so as to maintain the charge release mechanism in the display panel while reducing the losses caused by parasitic capacitances.

[0062] In the above example, the regions with different frame rates in the display panel based on multi-region frame rate control are divided into two regions. It can be understood that in other examples, depending on the specific application scenario, the regions with different frame rates in the display panel can also be divided into more regions, or the entire display panel can use the same frame rate. Moreover, it can be understood that in other examples, depending on the specific application scenario, any region in the display panel can be designated as the region that needs to be refreshed. For example, it can be the pixels from row L1 to row Lm of the display panel, the pixels from row LN-n to row LN of the display panel, or the pixels from row Lp to row Lp+q in the middle of the display panel; or it can also be the pixels from column Ca to Ca+b in rows L1 to Lm, the pixels from column Ca to Ca+b in rows LN-n to LN of the display panel, and the pixels from column Ca to Ca+b in rows Lp to Lp+q in the middle of the display panel (where N is the total number of rows of the display panel, and m, n, p, q, a, b are all integers).

[0063] As can be seen from the above description, the driving method of the present disclosure can be applied to a display panel based on multi-region frame rate control, thereby utilizing the multi-region frame rate control technology to achieve local refreshing of the display panel, so as to reduce the power consumption of the display panel to a certain extent while ensuring smooth video playback. In addition, for frames that do not need to be refreshed, the power consumption of the gate driving circuit is reduced through a driving scheme based on dynamic STV, and the overall power consumption of the display panel is further reduced through a driving scheme based on dynamic GCK while ensuring normal display.

[0064] Next, examples of a driving integrated circuit for driving a display panel and a display device including the display panel and the driving integrated circuit according to an embodiment of the present disclosure will be described.

[0065] According to an embodiment of the present disclosure, the driving integrated circuit may include: a module for determining whether to perform a refreshing operation on the current frame to be displayed on the display panel, and a module for sending the above signals for the refreshing operation to the display panel, such as including a frame scan start signal and a gate clock signal. In addition, according to an embodiment of the present disclosure, the driving integrated circuit may further include a module for obtaining frame refresh information, and the frame refresh command indicates whether to perform a refreshing operation on the current frame to be displayed on the display panel, so that the driving integrated circuit can determine whether to perform a refreshing operation on at least part of the regions in the current frame according to the obtained frame refresh information, and depending on whether the current frame or at least part of the regions therein need to be refreshed, perform the above driving method according to the present disclosure. The driving integrated circuit can execute the driving method described above in conjunction with FIGS. 1 to 7, which will not be elaborated here.

[0066] In addition, according to an embodiment of the present disclosure, a display device may include a display panel and a driving integrated circuit as described above, wherein the display panel may further include a gate driving circuit such as the GOA circuit 120 described above in connection with FIGS. 1 to 3.

[0067] In addition, the present disclosure may also provide a computer-readable storage medium storing computer instructions and a computer program product including the computer instructions. When the computer program instructions are executed by a processor, the steps executed by the processor described above are implemented, which are consistent with the corresponding contents of the embodiments described above in connection with FIGS. 1 to 7. It should be understood that each component or module in the above device may be implemented by hardware, may be implemented by software, and may also be implemented by a combination of hardware and software.

[0068] It should be noted that in the present disclosure, since the disclosed technical solution does not focus on the improvement of the structure of the display panel, the display panel and the screen will not be strictly distinguished in the present disclosure. For example, in the examples herein, the display panel 100 may refer to the screens of various display devices, which may include, for example, smart phones, smart TVs, electronic picture frames, tablet computers, laptop computers, etc.

[0069] In addition, other types of gate driving circuits in the art may also be adopted for the display panel of the present disclosure, and the gate driving circuit may be provided separately from the driving integrated circuit, or the gate driving circuit may be integrated into the driving integrated circuit. In addition, in other examples, the driving integrated circuit of the present disclosure may be a separate integrated circuit or may also be integrated into the display panel.

[0070] In addition, only the signals related to the core technical solution of the present disclosure are shown in the respective drawings of the present disclosure. Each element in the drawings may also input and output other signals not shown, such as signals such as the high-level voltage VGH and the low-level voltage VGL output by the driving power supply. In addition, the signal lines in the respective drawings are only schematic, and they may represent the transmission paths of one or more signals. For example, the clock signal may include more than one signal, such as a forward clock signal and a reverse clock signal (CLKF and CLKB, not shown), and the MAFR_Ctrl signal may also include multiple signals for controlling the pixels to perform multiple reset actions (MAFR_Ctrl1, MAFR_Ctrl2, …, MAFR_Ctrln, not shown).

[0071] The driving method, driving integrated circuit, and display device for driving a display panel according to the present disclosure have been exemplarily described with reference to the accompanying drawings. Through the above driving method and driving integrated circuit of the present disclosure, it is possible to adjust the behavior of sending relevant signals to the display panel according to whether the current frame or at least some regions thereof need to perform a refresh operation, so that when there is no need to perform a refresh operation on the current frame, the circuit power consumption caused by parasitic capacitance and the like in the display panel can be reduced, thereby reducing the overall power consumption of the display panel.

[0072] The advantages, benefits, effects, etc. mentioned in the embodiments of the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. Additionally, the specific details disclosed above are only for illustrative and easy-to-understand purposes and not limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation. It should also be noted that in the devices and methods of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0073] For ordinary operators in the art, all or any part of the method and device of the present disclosure can be implemented in any computing device (including a processor, storage medium, etc.) or a network of computing devices in the form of hardware, firmware, software, or a combination thereof. The hardware can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array signal (FPGA), or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but alternatively, the processor can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration. The software can exist in any form of tangible computer-readable storage medium. By way of example and not limitation, such a tangible computer-readable storage medium can include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other tangible medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer. As used herein, a disk includes a compact disk (CD), a laser disk, an optical disk, a digital versatile disk (DVD), a floppy disk, and a Blu-ray disk.

[0074] The block diagrams of the elements, components, devices, apparatuses, and systems involved in the embodiments of the present disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these elements, components, devices, apparatuses, and systems can be connected, arranged, and configured in any manner.

[0075] In addition, the scope of the present disclosure claimed is not limited to the specific aspects of the processes, machines, manufactures, compositions of events, means, methods, and acts described above. Current or later-developed processes, machines, manufactures, compositions of events, means, methods, or acts that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized.

[0076] Furthermore, words such as "including", "comprising", "having", etc. are open-ended terms that mean "including but not limited to" and can be used interchangeably with each other. The words "or" and "and" used herein mean "and / or" and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein means "such as but not limited to" and can be used interchangeably with it.

[0077] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving method for driving a display panel, the driving method comprising: Determining whether to perform a refresh operation on a current frame to be displayed on the display panel; as well as When it is determined that the refresh operation is not to be performed on the current frame, no frame scan start signal is sent to the display panel.

2. The driving method according to claim 1, further comprising: When it is determined that a refresh operation is not performed on the current frame, the frequency of the gate clock signal sent to the display panel is reduced.

3. The driving method according to claim 1, further comprising: When it is determined that a refresh operation is not performed on the current frame, a gate clock signal sent to the display panel is fixed to a specific voltage level.

4. The driving method according to claim 1, further comprising: Acquire frame refresh information, where the frame refresh information indicates whether to perform a refresh operation on at least a portion of the area in the current frame; as well as According to the frame refresh information, determining whether to perform a refresh operation on at least a partial area of ​​the current frame to be displayed by the display panel; wherein, When it is determined that the refresh operation is not performed on all areas in the current frame, the frame scan start signal is not sent to the display panel, and the frequency of the gate clock signal is reduced or the gate clock signal is fixed to a specific voltage level.

5. The driving method according to claim 4, further comprising: When it is determined to perform a refresh operation on at least a partial area in the current frame, the frame scan start signal is sent to the display panel to start the refresh operation on at least the partial area.

6. The driving method according to claim 5, further comprising: When it is determined to perform a refresh operation on at least a portion of the area in the current frame, the frame scan start signal is sent to the array integrated gate drive circuit of the display panel, and a refresh control signal and the gate clock signal are sent; The integrated gate drive circuit on the array is composed of a plurality of cascaded gate drive units. In response to the first-level gate drive unit in the integrated gate drive circuit on the array receiving the frame scan start signal, the integrated gate drive circuit on the array performs a refresh operation on at least a portion of the area based on the refresh control signal and the gate clock signal.

7. A driver integrated circuit for driving a display panel, comprising: A module for determining whether to perform a refresh operation on a current frame to be displayed on the display panel; as well as a module for sending a frame scan start signal for starting the refresh operation and a gate clock signal for performing the refresh operation to the display panel, When it is determined that the refresh operation is not to be performed on the current frame, the driving integrated circuit does not send the frame scanning start signal to the display panel.

8. The driver integrated circuit according to claim 7, wherein: When it is determined that the refresh operation is not to be performed on the current frame, the driving integrated circuit reduces the frequency of the gate clock signal or fixes the gate clock signal to a specific voltage level.

9. The driver integrated circuit according to claim 7 or 8, further comprising: a module for acquiring frame refresh information, wherein the frame refresh information indicates whether to perform a refresh operation on at least a portion of the area in the current frame, and the driver integrated circuit determines whether to perform a refresh operation on at least a portion of the area in the current frame according to the frame refresh information; and When it is determined that no refresh operation is performed on all areas in the current frame, the driving integrated circuit does not send the frame scanning start signal to the display panel, and reduces the frequency of the gate clock signal or fixes the gate clock signal to a specific voltage level.

10. A display device, comprising: The display panel comprises an on-array integrated gate driving circuit, wherein the on-array integrated gate driving circuit is composed of a plurality of cascaded gate driving units; and a driver integrated circuit configured to receive frame refresh information indicating whether to perform a refresh operation on at least a portion of a current frame to be displayed on the display panel, and to send a frame scan start signal for starting the refresh operation to the integrated gate drive circuit on the array, Among them, when the frame refresh information indicates that no refresh operation is performed on all areas in the current frame, the driver integrated circuit does not send the frame scan start signal to the integrated gate drive circuit on the array, and / or the driver integrated circuit reduces the frequency of the gate clock signal or fixes the gate clock signal to a specific voltage level.

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