Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel, a driving method thereof and a display device. The display panel comprises a plurality of scanning lines extending in the first direction and arranged in the second direction and a plurality of data lines extending in the second direction and arranged in the first direction. When the display panel displays a frame of display picture, the scanning signal end sequentially provides scanning signals for the scanning lines in the second direction, and meanwhile, the data signal end provides first data signals and second data signals for the data lines; wherein the polarities of the first data signal and the second data signal are opposite, the first data signal and the second data signal are alternated, and the sum of the loading times of the first data signal and the loading times of the second data signal is greater than or equal to three times. By adjusting the data signal ends to output the data signals with opposite polarities and adjusting the loading times of the data signals with different polarities, the leakage current difference between the sub-pixels in the head row and the tail row is reduced, the problem of tail-end flickering is solved, and the overall display effect of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device. Background Art

[0002] With the development of display technologies, the requirements for the display effects of display products in all walks of life are getting higher and higher. In some display products, when the display panel displays at a low refresh rate, due to factors such as coupling capacitance and leakage, the panel has uneven display brightness and flicker.

[0003] Therefore, how to solve the above problems has become one of the technical problems to be urgently solved at the present stage. Summary of the Invention

[0004] The present invention provides a display panel, a driving method thereof, and a display device, so as to reduce the transistor leakage current phenomenon of the display panel, reduce the flicker phenomenon of the display panel, and ensure the display effect of the display panel.

[0005] In a first aspect, the present invention provides a display panel, including a plurality of scan lines extending along a first direction and arranged in a second direction, and a plurality of data lines extending along the second direction and arranged in the first direction. At least one end of the scan line is electrically connected to a scan signal terminal, one end of the data line is electrically connected to a data signal terminal, and the first direction intersects the second direction;

[0006] When the display panel displays a frame of display picture, the scan signal terminal sequentially provides scan signals to the scan lines along the second direction, and at the same time, the data signal terminal provides a first data signal and a second data signal to the data lines;

[0007] Wherein, the polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times.

[0008] In a second aspect, the present invention provides a driving method for a display panel, which is applicable to any of the display panels in the first aspect, and the driving method includes;

[0009] During the display time of a frame of display picture, sequentially load scan signals to the scan lines along the second direction, and at the same time, load a first data signal and a second data signal to each of the data lines;

[0010] Wherein, the polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times.

[0011] In a third aspect, the present invention provides a display device, including the display panel according to any one of the first aspect.

[0012] According to the technical solution of the embodiment of the present invention, a display panel includes a plurality of scan lines extending along a first direction and arranged in a second direction, and a plurality of data lines extending along the second direction and arranged in the first direction. At least one end of the scan line is electrically connected to a scan signal terminal, one end of the data line is electrically connected to a data signal terminal, and the first direction intersects the second direction. When the display panel displays a frame of a display image, the scan signal terminal sequentially provides scan signals to the scan lines along the second direction, and at the same time, the data signal terminal provides a first data signal and a second data signal to the data lines. Among them, the polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate, and the sum of the loading times of the first data signal and the loading times of the second data signal is greater than or equal to three times. By adjusting the data signals with opposite polarities output by the data signal terminal and adjusting the loading times of the data signals with different polarities, the leakage current difference between the sub-pixels of the head and tail rows is reduced, the problem of tail-end flicker is improved, and the overall display effect of the display panel is improved.

[0013] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 A timing diagram provided for the prior art;

[0016] Figure 2 A structural diagram of a display panel provided for an embodiment of the present invention;

[0017] Figure 3 Another timing diagram provided for an embodiment of the present invention;

[0018] Figure 4 Another timing diagram provided for an embodiment of the present invention;

[0019] Figure 5 Another timing diagram provided for an embodiment of the present invention;

[0020] Figure 6Schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 7 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 8 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 9 Schematic diagram of the inversion result of pixel electrodes within the display time of one frame of a display screen provided by an embodiment of the present invention;

[0024] Figure 10 Flowchart of a driving method for a display panel provided by an embodiment of the present invention;

[0025] Figure 11 Schematic diagram of another inversion result of pixel electrodes within the display time of one frame of a display screen provided by an embodiment of the present invention;

[0026] Figure 12 Schematic diagram of another inversion result of pixel electrodes within the display time of one frame of a display screen provided by an embodiment of the present invention;

[0027] Figure 13 Schematic diagram of another timing provided by an embodiment of the present invention;

[0028] Figure 14 Schematic diagram of another timing provided by an embodiment of the present invention;

[0029] Figure 15 Schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0030] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] Figure 1 A timing diagram provided for the prior art Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention Figure 3 Another timing diagram provided by an embodiment of the present invention Figure 4 Another timing diagram provided by an embodiment of the present invention Figure 5 Another timing diagram provided by an embodiment of the present invention, as Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 shown, the display panel 100 includes a plurality of scan lines 101 extending along the first direction X and arranged in the second direction Y, and a plurality of data lines 103 extending along the second direction Y and arranged in the first direction X. At least one end of the scan line 101 is electrically connected to the scan signal terminal 102, one end of the data line 103 is electrically connected to the data signal terminal 104, and the first direction X intersects with the second direction Y. When the display panel 100 displays a frame of display image, the scan signal terminal 102 sequentially provides scan signals to the scan lines 101 along the second direction Y, and at the same time the data signal terminal 104 provides a first data signal and a second data signal to the data lines 103. Among them, the polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times.

[0033] Among them, the display panel 100 includes a plurality of scan lines 101 extending in the first direction X and arranged in the second direction Y. During the operation of the display panel 100, the scan lines 101 output scan signals line by line. The display panel 100 also includes a plurality of data lines 103 extending in the second direction Y and arranged in the first direction X. The same data line 103 writes data signals to a plurality of sub-pixels 105 arranged along the second direction Y one by one. The display panel 100 also includes sub-pixels 105 arranged in an array. The sub-pixels 105 are located in the area defined by the insulating intersection of the scan lines 101 and the data lines 103. One scan line 101 is electrically connected to a plurality of sub-pixels 105 arranged along the second direction Y, and one data line 103 is electrically connected to a plurality of sub-pixels 105 arranged along the second direction Y. When a scan line 101 outputs a scan signal, the transistor 1051 in the corresponding row of sub-pixels 105 is driven to conduct, and the sub-pixels 105 receive the data signals output by the corresponding data line 103, and then display. The display panel 100 also includes a scan signal terminal 102 and a data signal terminal 104. The scan signal terminal 102 can be integrated on the display panel 100 or bonded to the driving chip of the display panel 100. The gate driving circuit in the display panel includes a plurality of cascaded shift registers, and the output terminals of each shift register are electrically connected to the scan lines 101 in the display panel one by one. At this time, the output terminal of each shift register can be understood as a scan signal terminal 102. The data signal terminal 104 can be bonded to the driving chip of the display panel 100. The data signals in the display panel are usually generated by the driving chip. The data signal terminal 104 can be understood as the data signal output terminal or data signal output pad on the driving chip for transmitting data signals. A frame of display image includes a data writing stage and a holding stage. The refreshing stage is the data writing stage of the current frame. The holding stage is the stage of maintaining the display after the data writing of the current frame is completed and before the data writing of the next frame. The holding stage means that all thin film transistors 1051 in the display panel 100 are turned off to provide a stable voltage for the sub-pixels 105. Such as Figure 1As shown, along the second direction Y, there are differences in the write times of the hold signals corresponding to different pixel rows, such that the waveform of the hold signal corresponding to the first pixel row is the same as that of the data signal. At this time, there is no voltage difference between the hold signal and the data signal corresponding to the first pixel row during the display time of the entire frame image, that is, the voltages at both ends of the thin-film transistor 1051 are the same. At this time, it can be considered that there is no leakage current in the first pixel row; the waveforms of the hold signals corresponding to the middle pixel rows are half opposite to those of the data signals. At this time, within one frame display image, there is a voltage difference between the hold signals and the data signals corresponding to the middle pixel rows within 1 / 2 frame. That is, within one frame time, the voltages at both ends of the thin-film transistor 1051 are different for half of the time, resulting in leakage current within 1 / 2 frame of one frame display image; the waveforms of the hold signals corresponding to the last pixel row are opposite to those of the data signals. At this time, within one frame display image, the voltage differences between the hold signals and the data signals corresponding to the sub-pixels in the last pixel row are all the same. That is, within one frame time, the voltages at both ends of the thin-film transistor 1051 are always different. Since the voltage difference exists throughout one frame display image, there is leakage current throughout one frame display image. That is, compared with the first row and the middle rows, the leakage current between the sub-pixels 105 and the corresponding data lines 103 in the last pixel row is the largest. That is, along the negative direction -Y of the second direction and from the first pixel row to the last pixel row, the degree of leakage current gradually increases, resulting in a gradual increase in the leakage current from the first row (far end) to the last row (near end) during one frame display image, that is, the voltage jitter from the first row to the last row gradually increases, showing a phenomenon of lighter jitter at the far end and heavier jitter at the near end, thereby affecting the stability of the display image and causing obvious flickering at the lower pixel rows. To solve the above problems, when the display panel 100 displays one frame display image, at least one end of the scan line 101 is electrically connected to the scan signal terminal 102. The scan signal terminal 102 sequentially provides scan signals to the scan line 101 along the negative direction -Y of the second direction. At the same time, one end of the data line 103 is electrically connected to the data signal terminal 104. The data signal terminal 104 provides a first data signal and a second data signal with opposite polarities to the data line 103. The first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times, increasing the change period of the data signal polarity, which can effectively reduce the difference between the waveform of the hold signal corresponding to the sub-pixels 105 in the last row and the waveform of the data signal, reduce the degree of leakage current corresponding to the sub-pixels 105 in the last row, reduce the difference in the degree of leakage current between the first and the last rows, and improve the flickering phenomenon. Exemplarily, the polarity of the first data signal is positive, and the polarity of the second data signal is negative, such as Figure 3As shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to three. The first data signal is loaded twice and the second data signal is loaded once, or the first data signal is loaded once and the second data signal is loaded twice. At this time, in the first-row sub-pixel 105, there is a waveform of the holding signal that is different from the waveform of the data signal for 1 / 3 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 1 / 3 of a frame, resulting in leakage current in 1 / 3 of a frame within one frame of the display screen. In the middle-row sub-pixel 105, there is a waveform of the holding signal that is different from the waveform of the data signal for 1 / 2 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 1 / 2 of a frame, resulting in leakage current in 1 / 2 of a frame within one frame of the display screen. In the last-row sub-pixel 105, there is a waveform of the holding signal that is the same as the waveform of the data signal for 1 / 3 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 2 / 3 of a frame, resulting in leakage current in 2 / 3 of a frame within one frame of the display screen. Compared with the prior art where there is leakage current in the entire frame in the last-row sub-pixel 105, the leakage current phenomenon in the last-row sub-pixel is effectively improved. Moreover, setting the leakage current in the first 1 / 3 of a frame is equivalent to shortening the leakage current difference between the first-row and last-row sub-pixels 105 that exists for one frame time to the leakage current difference that exists within 1 / 3 of a frame time, reducing the time of voltage fluctuation and improving the problem of tail-end flicker.

[0034] Or as Figure 4 As shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than three. For example, the sum of the loading times is five. The first data signal is loaded three times and the second data signal is loaded twice, or the first data signal is loaded twice and the second data signal is loaded three times. At this time, in the first-row sub-pixel 105, there is a waveform of the holding signal that is different from the waveform of the data signal for 2 / 5 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 2 / 5 of a frame, resulting in leakage current in 2 / 5 of a frame within one frame of the display screen. In the middle-row sub-pixel 105, there is a waveform of the holding signal that is different from the waveform of the data signal for 1 / 2 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 1 / 2 of a frame, resulting in leakage current in 1 / 2 of a frame within one frame of the display screen. In the last-row sub-pixel 105, there is a waveform of the holding signal that is the same as the waveform of the data signal for 2 / 5 of a frame. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal for 3 / 5 of a frame, resulting in leakage current in 3 / 5 of a frame within one frame of the display screen. The leakage current phenomenon in the last-row sub-pixel is effectively improved, which is equivalent to shortening the leakage current difference between the first-row and last-row sub-pixels 105 that exists for one frame time to the leakage current difference that exists within 1 / 5 of a frame time, further reducing the leakage current difference between the first-row and last-row sub-pixels 105 and improving the problem of tail-end flicker.

[0035] Or asFigure 5 As shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than three. For example, the sum of the number of times is seven, the first data signal is loaded four times, the second data signal is loaded three times, the first data signal is loaded three times, and the second data signal is loaded four times. At this time, in the first-row sub-pixel 105, there are 3 / 7 frames where the waveform of the holding signal is different from the waveform of the data signal. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal in 3 / 7 frames, resulting in leakage current in 3 / 7 frames within one frame of the display screen; in the middle-row sub-pixel 105, there are 1 / 2 frames where the waveform of the holding signal is different from the waveform of the data signal. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal in 1 / 2 frames, resulting in leakage current in 1 / 2 frames within one frame of the display screen; in the last-row sub-pixel 105, there are 3 / 7 frames where the waveform of the holding signal is the same as the waveform of the data signal. At this time, it can be considered that there is a voltage difference between the holding signal and the data signal in 4 / 7 frames, resulting in leakage current in 4 / 7 frames within one frame of the display screen; effectively improving the leakage current phenomenon in the last-row sub-pixels, which is equivalent to shortening the leakage current difference existing for one frame time between the first-row and last-row sub-pixels 105 to the leakage current difference existing within 1 / 7 frame time, further reducing the leakage current difference between the first-row and last-row sub-pixels 105 and improving the problem of tail-end flicker. The sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded can be selected according to actual design requirements, and the embodiments of the present invention do not make specific limitations. By adjusting the number of times the data signal is inverted in one frame of the display screen, the more the number of inversions, the greater the similarity between the waveform of the holding frame and the waveform of the data signal in the last-row sub-pixel 105, and thus the smaller the leakage current difference between the first row and the last row, and the better the overall display effect of the display panel 100.

[0036] It can be understood that for the holding signal of the middle row, its writing time is in the middle of one frame. Figure 3 Among them, since the data signal is at a low level when the middle-row holding signal is written, the holding signal of the previous frame is at a high level. Figure 4 Among them, since the data signal is at a high level when the middle-row holding signal is written, the holding signal of the previous frame is at a low level. Figure 5 Among them, since the data signal is at a low level when the middle-row holding signal is written, the holding signal of the previous frame is at a high level.

[0037] In an embodiment of the present invention, when the display panel displays a frame of display screen, the scanning signal terminal sequentially provides scanning signals to the scanning lines along the second direction, and at the same time, the data signal terminal provides a first data signal and a second data signal to the data lines. The polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate. The sum of the loading times of the first data signal and the loading times of the second data signal is greater than or equal to three times, reducing the leakage current difference between the sub-pixels of the head and tail rows, improving the problem of tail-end flicker, and improving the overall display effect of the display panel.

[0038] Optionally, continue to refer to Figure 3 , the durations of the first data signal and the second data signal provided by the data signal terminal 104 are the same, and the absolute values of the voltages are equal. Adjusting the duration t1 of the first data signal and the duration t2 of the second data signal to be the same, and adjusting the absolute values of the voltages of the first data signal and the second data signal to be the same reduces the difficulty of data signal control and reduces the driving complexity of the display panel 100. Exemplarily, as Figure 3 shown, taking the absolute value of the voltage as 5V for display, the first data signal is +5V and the second data signal is -5V; or the first data signal is -5V and the second data signal is +5V. The voltage values of the first data signal and the second data signal can be selected according to actual design requirements, and the embodiments of the present invention do not make specific limitations.

[0039] Optionally, Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 7 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The display panel 100 includes an array substrate 106 and a counter substrate 107 disposed opposite to each other. The scanning lines 101, the data lines 103, the scanning signal terminal 102, and the data signal terminal 104 are all disposed on the array substrate 106.

[0040] Among them, the display panel 100 can be applicable to different types of display panels 100. For example, as Figure 6 shown, the display panel 100 can be a liquid crystal display panel 100. The display panel 100 includes an array substrate 106 and a counter substrate 107 disposed opposite to each other. The counter substrate 107 can be a color filter substrate; the display panel 100 further includes a liquid crystal layer 108 located between the array substrate 106 and the counter substrate 107. As Figure 7 shown, the display panel 100 can also be an OLED display panel 100. At this time, the counter substrate 107 can be a cover plate. As Figure 8As shown, the display panel 100 can also be a Micro LED display panel 100 or a MiniLED display panel 100. In this case, the counter substrate 107 can be a cover plate. For different types of display panels 100, the array substrate 106 is provided with pixel driving circuits. The pixel driving circuits are provided with active layers, gate layers, and source-drain layers. Exemplarily, taking the scanning signal terminal 102 as the output terminal of the shift register and being arranged on the same layer as the scanning line 101 for display, the scanning line 101 and the scanning signal terminal 102 can be arranged on the same layer as the gate layer, and taking the data signal terminal 104 as the data output terminal of the driving chip and being arranged on the same layer as the data line 103 for display, the data line 103 and the data signal terminal 104 can be arranged on the same layer as the source-drain layer, reducing the film layer thickness of the display panel 100 and facilitating the thin and light design of the display panel 100.

[0041] Optionally, continue to refer to Figure 2 , the array substrate further includes a plurality of sub-pixels 105 arranged in an array. The sub-pixels 105 include thin film transistors 1051 and pixel electrodes 1052. The control ends of the thin film transistors 1051 in one row of sub-pixels 105 are electrically connected to one scanning line 101, the first ends of the thin film transistors 1051 in one column of sub-pixels 105 are electrically connected to one data line 103, and the second ends of the thin film transistors 1051 are electrically connected to the pixel electrodes 1052 of the corresponding sub-pixels 105.

[0042] Among them, the scanning line 101 is electrically connected to the scanning signal terminal 102 of the gate driving unit. One scanning line 101 is electrically connected to the control ends of the thin film transistors 1051 in one row of sub-pixels 105, and one scanning line 101 can control the on-off of the thin film transistors 1051 connected thereto. The data line 103 is electrically connected to the data signal terminal 104 of the source driving unit. One data line 103 is electrically connected to the first ends of the thin film transistors 1051 in one column of sub-pixels 105. During the data writing stage, when a scanning signal is loaded on the scanning line 101, a data voltage is transmitted to the pixel electrode 1052 connected to the data line 103 to charge the pixel electrode 1052.

[0043] Optionally, Figure 9 is a schematic diagram of the pixel electrode inversion result within the display time of one frame of display image provided by an embodiment of the present invention. As shown in Figure 2 and Figure 9 , the display panel 100 includes at least two scanning line groups 109. The scanning line groups 109 include at least two scanning lines 101 arranged continuously along the second direction Y. When the display panel 100 displays one frame of display image, the data signal terminal 104 provides a first data signal and a second data signal to the same data line 103 corresponding to at least two adjacent scanning signal groups respectively.

[0044] Among them, multiple scan lines 101 extending along the first direction X are provided in the display panel 100. The scan lines 101 can be divided into at least two scan line groups 109. Each scan line group 109 includes at least two scan lines 101 arranged continuously along the second direction Y. When the display panel 100 displays a frame of display image, for the data signal terminal 104 to provide a first data signal and a second data signal to the same data line 103 corresponding to at least two adjacent scan signal groups respectively, so that the polarities of the loaded data signals of every two adjacent scan signal line groups are opposite. Exemplarily, as Figure 9 shown, the display panel 100 includes three scan line groups. One scan line group includes two scan lines (corresponding to two rows of pixel electrodes 1052). The polarity of the first data signal is positive, and the polarity of the second data signal is negative. Along the second direction Y, the same data line corresponding to the three scan line groups is loaded with the first data signal, the second data signal, and the first data signal respectively; or the same data line corresponding to the three scan line groups is loaded with the second data signal, the first data signal, and the second data signal respectively. After a frame of display image ends, the voltage polarities of the pixel electrodes 1052 corresponding to two adjacent scan line groups are made different. When the display panel is a liquid crystal display panel, that is, line inversion is achieved, effectively reducing power consumption and ensuring display quality.

[0045] Optionally, continue to refer to Figure 2 and Figure 9 , the scan line groups 109 include the same number of scan lines 101. So that along the second direction Y, the number of sub-pixels 105 corresponding to each scan line group 109 is the same. When the display panel 100 displays a frame of display image, the data signal terminal 104 provides the first data signal and the second data signal to the same data line 103 corresponding to at least two adjacent scan signal groups for the same duration, reducing the control difficulty of the data signal and ensuring the display effect of the display panel 100.

[0046] Optionally, continue to refer to Figure 2 , the display panel 100 includes a display area 1001 and a non-display area 1002. Part of the area of the scan line 101 and part of the area of the data line 103 are located in the display area 1001. The scan signal terminal 102 and the data signal terminal 104 are located in the non-display area 1002. At least one end of the scan line 101 extends to the non-display area 1002 and is electrically connected to the scan signal terminal 102, and one end of the data line 103 extends to the non-display area 1002 and is electrically connected to the data signal terminal 104.

[0047] Among them, the non-display area 1002 of the display panel 100 is at least partially disposed around the display area 1001. The scanning lines 101 and the data lines 103 can be disposed in the display area 1001, and the scanning signal terminals 102 electrically connected to the scanning lines 101 and the data signal terminals 104 electrically connected to the data lines 103 are disposed in the non-display area 1002, so as to avoid the scanning signal terminals 102 and the data signal terminals 104 occupying the area of the display area 1001 and ensure the display area of the display area 1001.

[0048] Based on the same inventive concept, an embodiment of the present invention further provides a driving method for a display panel, or it can be understood that the driving method for the display panel can drive the display panel provided by the above embodiment. Therefore, the driving method for the display panel also has the beneficial effects of the above display panel. The same parts can be understood with reference to the above explanation of the display panel and will not be repeated hereinafter. Figure 10 It is a flowchart of a driving method for a display panel provided by an embodiment of the present invention, as Figure 10 shown, the driving method includes:

[0049] S101, within the display time of a frame of display picture, sequentially load scanning signals to the scanning lines along the second direction, and simultaneously load a first data signal and a second data signal to each data line; wherein, the polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times.

[0050] Among them, continuing to refer to Figure 2 , when the display panel displays a frame of display picture, at least one end of the scanning line 101 is electrically connected to the scanning signal terminal 102, and the scanning signal terminal 102 sequentially provides scanning signals to the scanning line 101 along the second direction Y. At the same time, one end of the data line 103 is electrically connected to the data signal terminal 104, and the data signal terminal 104 provides a first data signal and a second data signal with opposite polarities to the data line 103. The first data signal and the second data signal alternate, and the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is greater than or equal to three times. By reasonably setting the number of times the first data signal and the second data signal are loaded, the difference between the holding signal waveform corresponding to the trailing sub-pixel 105 and the data signal waveform can be effectively reduced, the difference in the leakage current degree between the first and last rows can be reduced, and the flicker phenomenon can be improved. Exemplarily, the polarity of the first data signal is positive, and the polarity of the second data signal is negative. As Figure 3 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to three times; or as Figure 4 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to five times, or as Figure 5As shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to seven times, both of which can effectively reduce the leakage current difference between the sub-pixels 105 at the head and tail rows, and improve the problem of tail-end flicker. The sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded can be selected according to actual design requirements, and the embodiments of the present invention do not make specific limitations. By adjusting the number of inversions of the data signal in a frame of display screen, the more the number of inversions, the greater the similarity between the waveform of the hold frame and the waveform of the data signal in the sub-pixels 105 of the tail row, the smaller the leakage current of the sub-pixels in the tail row, and thus the smaller the leakage current difference between the head and tail rows, and the better the overall display effect of the display panel 100.

[0051] In the embodiments of the present invention, by adjusting the waveform of the data signal, a first data signal and a second data signal with opposite polarities and alternating are provided, effectively reducing the difference between the waveform of the hold signal corresponding to the sub-pixels in the tail row and the waveform of the data signal, reducing the difference in the leakage current levels between the head and tail rows, improving the flicker phenomenon, and ensuring the display effect of the display panel 1.

[0052] Optionally, Figure 11 is a schematic diagram of the inversion result of the pixel electrode within the display time of a frame of display screen provided by the embodiments of the present invention. As Figure 2 and Figure 11 shown, within the display time of the same frame of display screen, adjacent two data lines 103 are respectively loaded with the first data signal and the second data signal.

[0053] Among them, by respectively loading the first data signal and the second data signal with different polarities on adjacent two data lines 103 within the display time of the same frame of display screen, after the end of a frame of display screen, the voltage polarities of the pixel electrodes 1052 corresponding to the adjacent two data lines 103 are made different. When the display panel 100 is a liquid crystal display panel 100, that is, column inversion is achieved to eliminate the problems of visual effects and inversion disturbance caused by different polarities in different regions, and ensure the display quality of the display panel 100.

[0054] Optionally, Figure 12 is a schematic diagram of the inversion result of the pixel electrode within the display time of a frame of display screen provided by the embodiments of the present invention. As Figure 2 and Figure 12 shown, during the display time of adjacent frames of display screen, the same data line 103 sequentially loads the first data signal and the second data signal.

[0055] Among them, in the display screens of adjacent frames, for the same data line 103, a first data signal and a second data signal with different polarities are sequentially loaded. Exemplarily, the adjacent frame display screens include a first frame display screen and a second frame display screen. In the first frame display screen, all sub-pixels 105 are written with the first data signal, and in the second frame display screen, all sub-pixels 105 are written with the second data signal. When the display panel 100 is a liquid crystal display panel 100, frame inversion is achieved, reducing the display power consumption and ensuring the display quality of the display panel 100.

[0056] Optionally, continue to refer to Figure 2 and Figure 9 , the display panel 100 includes at least two scan line groups 109. The scan line group 109 includes at least two scan lines 101 arranged continuously along the second direction Y. During the display time of the same frame display screen, the same data line 103 corresponding to at least two adjacent scan signal groups is respectively loaded with the first data signal and the second data signal.

[0057] Among them, multiple scan lines 101 extending along the first direction X are provided in the display panel 100. The scan lines 101 can be regionally divided to form at least two scan line groups 109. Each scan line group 109 includes at least two scan lines 101 arranged continuously along the second direction Y. When the display panel 100 displays a frame display screen, for the data signal terminal 104, the same data line 103 corresponding to at least two adjacent scan signal groups is respectively provided with the first data signal and the second data signal, so that the polarities of the loaded data signals of every two adjacent scan signal line groups are opposite. As Figure 9 shown, the display panel 100 includes three scan line groups 109. The polarity of the first data signal is positive, and the polarity of the second data signal is negative. Along the second direction Y, the same data line 103 corresponding to the three scan line groups 109 is respectively loaded with the first data signal, the second data signal, and the first data signal; or the same data line 103 corresponding to the three scan line groups 109 is respectively loaded with the second data signal, the first data signal, and the second data signal. After a frame display screen ends, the voltage polarities of the pixel electrodes 1052 corresponding to two adjacent scan line groups 109 are different. When the display panel 100 is a liquid crystal display panel 100, line inversion is achieved, effectively reducing the power consumption and ensuring the display quality.

[0058] Optionally, continue to refer to Figure 3 , Figure 4 and Figure 5 , during the display time of the same frame, the polarity inversion time intervals of the data signals loaded on each data line 103 are kept consistent.

[0059] Among them, within the display time of the same frame, when the polarity of the data signal in the data line 103 is inverted, the loading time of the first data signal and the loading time of the second data signal can be adjusted to be the same, reducing the control difficulty of the data signal and the driving complexity of the display panel 100.

[0060] Optionally, Figure 13 Another timing diagram provided by an embodiment of the present invention, Figure 14 Another timing diagram provided by an embodiment of the present invention. Continuing to refer to Figure 3 、 Figure 4 、 Figure 5 、 Figure 13 and Figure 14 , Table 1 exemplarily shows the relationship between the sum n of the number of times the first data signal is loaded and the number of times the second data signal is loaded within one frame, which are 3, 4, 5, 6, 7, 8, 9, and 10 respectively, and the worst leakage current situation. The worst leakage current situation can be understood as the leakage current situation corresponding to the pixel row with the largest proportion of the waveform of the hold signal being different from the waveform of the data signal within one frame. When the sum n of the number of times the first data signal is loaded and the number of times the second data signal is loaded within one frame is odd, for example, when the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded within one frame is 3, the number of times the first data signal is loaded is 2 times, and the number of times the second data signal is loaded is 1 time. At this time, within one frame, the hold signal corresponding to the first pixel row has a waveform different from the waveform of the data signal for 1 / 3 of a frame, the hold signal corresponding to the middle pixel row has a waveform different from the waveform of the data signal for 1 / 2 of a frame, and the hold signal corresponding to the last pixel row has a waveform different from the waveform of the data signal for 2 / 3 of a frame. At this time, it is considered that the leakage current of the last pixel row is the worst, that is, the maximum leakage current situation is the leakage current of the last pixel row. When n is odd, it can be deduced by analogy, and no more details will be described here. When the sum n of the number of times the first data signal is loaded and the number of times the second data signal is loaded within one frame is even, for example, when the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded within one frame is 6, the number of times the first data signal is loaded is 3 times, and the number of times the second data signal is loaded is 3 times. At this time, within one frame, the hold signal corresponding to the first pixel row has a waveform different from the waveform of the data signal for 1 / 2 of a frame, the hold signal corresponding to the middle pixel row has a waveform different from the waveform of the data signal for 4 / 6 of a frame, and the hold signal corresponding to the last pixel row has a waveform different from the waveform of the data signal for 1 / 2 of a frame. At this time, it is considered that the leakage current of the middle pixel row is the worst, that is, the maximum leakage current situation is the leakage current of the middle pixel row. When n is even, it can be deduced by analogy, and no more details will be described here.

[0061] It can be understood that for the hold signal of the middle row, its writing time is in the middle of one frame. Figure 13 In , since the data signal at the previous moment is high level when the hold signal of the middle row is written, the hold signal of the previous frame is low-high level.Figure 14 In this case, since the data signal of the previous moment is kept at a high level when the middle row holds the signal writing, the hold signal of the previous frame is at a low level.

[0062] Loading the first data signal and the second data signal onto each data line 103 includes: the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is n, where n is an integer greater than or equal to 3; when n is odd, the first data signal is loaded onto the data line 103 for the first and last times; when n is even, the first data signal is loaded onto the data line 103 for the first time, and the second data signal is loaded onto the data line 103 for the last time.

[0063] Exemplarily, the first data signal and the second data signal are sequentially loaded onto each data line 103. The polarity of the first data signal is positive, and the polarity of the second data signal is negative. As Figure 3 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is 3; as Figure 4 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is 5; as Figure 5 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is 7; the number of times the above data signals are loaded are all odd. At this time, the data signals loaded for the first and last times are both the first data signal.

[0064] Or as Figure 7 shown, the sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to six times. The first data signal is loaded three times, and the second data signal is loaded three times. At this time, in the first row sub-pixels 105, there are 3 / 6 frames in which the waveform of the hold signal is different from the waveform of the data signal. In the middle row sub-pixels 105, there are 4 / 6 frames in which the waveform of the hold signal is the same as the waveform of the data signal. In the last row sub-pixels 105, there are 3 / 6 frames in which the waveform of the hold signal is the same as the waveform of the data signal. There is no leakage current difference between the first and last row sub-pixels 105, and there is a slight difference between the first row and the middle row, improving the display flicker problem. The sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is equal to ten times. The first data signal is loaded five times, and the second data signal is loaded five times. At this time, in the first row sub-pixels 105, there are 5 / 10 frames in which the waveform of the hold signal is different from the waveform of the data signal. In the middle row sub-pixels 105, there are 6 / 10 frames in which the waveform of the hold signal is the same as the waveform of the data signal. There is no leakage current difference between the first and last row sub-pixels 105, and there is a slight difference between the first row and the middle row, improving the display flicker problem. The number of times the above data signals are loaded are all even. At this time, the data signal loaded for the first time is the first data signal, and the data signal loaded for the last time is the second data signal.

[0065] In summary, by adjusting the number of times of polarity inversion of the waveform of the data signal so that the number of times of loading of the first data signal and the number of times of loading of the second data signal are odd or even numbers greater than or equal to 3, even in the worst case of leakage current, there are still parts of the waveform of the signal that are the same as the waveform of the data signal, effectively improving the transistor leakage current phenomenon of the display panel, reducing the flicker phenomenon of the display panel, and ensuring the display effect of the display panel.

[0066] Table 1 Relationship between the sum n of the number of times of loading of the first data signal and the number of times of loading of the second data signal within one frame and the worst case of leakage current

[0067]

[0068] Among them, when the sum n of the number of times of loading of the first data signal and the number of times of loading of the second data signal within one frame is odd, the leakage current situation of the last row of pixel rows is the worst case of leakage current. When the sum n of the number of times of loading of the first data signal and the number of times of loading of the second data signal within one frame is even, the leakage current situation of the middle row of pixel rows is the worst case of leakage current. The larger the sum of the number of times of loading of the first data signal and the number of times of loading of the second data signal within one frame, the closer the worst case of leakage current is to 1 / 2, the smaller the leakage current difference between each pixel row, and the lighter the flicker situation. However, the change frequency of the data signal is limited, and the number of times of change of the data signal can be selected according to the actual situation during specific implementation.

[0069] Optionally, continue to refer to Figure 2 , the display panel 100 includes a plurality of sub-pixels 105 arranged in an array. The sub-pixel 105 includes a thin-film transistor 1051 and a pixel electrode 1052. The control ends of the thin-film transistors 1051 in one row of sub-pixels 105 are electrically connected to a scanning line 101. The first ends of the thin-film transistors 1051 in one column of sub-pixels 105 are electrically connected to a data line 103. The second ends of the thin-film transistors 1051 are electrically connected to the pixel electrode 1052 located in the same sub-pixel 105. When the scanning signal is loaded on the scanning line 101, the thin-film transistor 1051 electrically connected to the scanning line 101 is turned on, and each data line 103 loads the data signal corresponding to the brightness to be displayed to the pixel electrode 1052.

[0070] Among them, the display panel 100 further includes sub-pixels 105 arranged in an array. The sub-pixels 105 are located in the area defined by the insulating intersection of the scanning lines 101 and the data lines 103. The sub-pixels 105 include thin-film transistors 1051 and pixel electrodes 1052. The second end of the thin-film transistor 1051 is electrically connected to the pixel electrode 1052 of the same sub-pixel 105. One scanning line 101 is electrically connected to the control ends of multiple thin-film transistors 1051 arranged along the second direction Y, and one data line 103 is electrically connected to the first ends of multiple thin-film transistors 1051 arranged along the second direction Y. When a scanning signal is output on one row of scanning lines 101, it drives the corresponding row of thin-film transistors 1051 to conduct and turn on. The turned-on thin-film transistors 1051 receive the data signals corresponding to the brightness to be displayed output by the corresponding data lines 103 and output them to the pixel electrodes 1052, thereby realizing the display of the corresponding sub-pixels 105.

[0071] Optionally, continuing to refer to Figure 2 , within the display time of a frame of display screen, the pixel electrode 1052 maintains the same voltage, and the voltage is the voltage corresponding to the written data signal. During the holding stage of the pixel electrode 1052 within the display time of a frame of display screen, the pixel electrode 1052 maintains the same voltage. The value of this voltage can be the same as the written data signal or different from the written data signal, ensuring the stable display of the sub-pixel 105 until the next frame of data signal is transmitted.

[0072] Figure 15 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. As Figure 15 shown, the display device 200 includes the display panel 100 described in the above embodiment.

[0073] It should be noted that since the display device provided by this embodiment has the same or corresponding beneficial effects as the display panel 100 of the above embodiment, it will not be elaborated here. The display device 200 provided by the embodiment of the present invention can be Figure 15 the mobile phone shown, or any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The embodiment of the present invention does not make special limitations on this.

[0074] The above specific implementation manners do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that: comprising a plurality of scan lines extending along a first direction and arranged in a second direction and a plurality of data lines extending along the second direction and arranged in the first direction, at least one end of the scan line is electrically connected to a scan signal end, one end of the data line is electrically connected to a data signal end, and the first direction intersects with the second direction; When the display panel displays a frame of display picture, the scan signal end provides scan signals to the scan lines in sequence along the second direction, and the data signal end provides the data lines with first data signals and second data signals; The polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal are alternating, and the sum of the number of loading times of the first data signal and the number of loading times of the second data signal is greater than or equal to three times.

2. The display panel according to claim 1, characterized in that: The first data signal and the second data signal provided by the data signal terminal have the same duration and the same voltage absolute value.

3. The display panel according to claim 1, characterized in that: It comprises an array substrate and a counter substrate which are arranged opposite to each other. The scan line, the data line, the scan signal end and the data signal end are all arranged on the array substrate.

4. The display panel according to claim 3, characterized in that: The array substrate also includes a plurality of sub-pixels arranged in an array, wherein the sub-pixels include thin film transistors and pixel electrodes, wherein the control ends of the thin film transistors in a row of the sub-pixels are electrically connected to a scanning line, the first ends of the thin film transistors in a column of the sub-pixels are electrically connected to a data line, and the second ends of the thin film transistors are electrically connected to the pixel electrodes corresponding to the sub-pixels.

5. The display panel according to claim 1, characterized in that: The display panel includes at least two scan line groups, and the scan line group includes at least two scan lines arranged continuously along the second direction. When the display panel displays a frame of display picture, the data signal end provides the first data signal and the second data signal to the same data line corresponding to at least two adjacent scan signal groups.

6. The display panel according to claim 5, characterized in that: The scan line group includes the same number of scan lines.

7. The display panel according to claim 1, characterized in that: The display panel includes a display area and a non-display area, a partial area of ​​the scan line and a partial area of ​​the data line are located in the display area, the scan signal terminal and the data signal terminal are located in the non-display area, at least one end of the scan line extends to the non-display area and is electrically connected to the scan signal terminal, and one end of the data line extends to the non-display area and is electrically connected to the data signal terminal.

8. A method for driving a display panel, characterized in that: Applicable to the display panel according to any one of claims 1 to 7, the driving method comprises: During the display time of one frame of display picture, scanning signals are sequentially applied to the scanning lines along the second direction, and the first data signal and the second data signal are simultaneously applied to each of the data lines; The polarities of the first data signal and the second data signal are opposite, and the first data signal and the second data signal are alternating, and the sum of the number of loading times of the first data signal and the number of loading times of the second data signal is greater than or equal to three times.

9. The driving method according to claim 8, characterized in that: During the display time of the same frame of display picture, two adjacent data lines are loaded with the first data signal and the second data signal respectively.

10. The driving method according to claim 8, characterized in that: During the display time of adjacent frames, the first data signal and the second data signal are sequentially loaded on the same data line.

11. The driving method according to claim 8, characterized in that: The display panel includes at least two scan line groups, and the scan line group includes at least two scan lines arranged continuously along the second direction. During the display time of the same frame of display image, the same data line corresponding to at least two adjacent scan signal groups is loaded with the first data signal and the second data signal respectively.

12. The driving method according to claim 8, characterized in that: During the display time of the same frame, the polarity inversion time interval of the data signal loaded on each data line remains consistent.

13. The driving method according to claim 12, characterized in that: Loading the first data signal and the second data signal to each of the data lines comprises: The sum of the number of times the first data signal is loaded and the number of times the second data signal is loaded is n, where n is an integer greater than or equal to 3; When n is an odd number, the first data signal is loaded to the data line for the first time and the last time; When n is an even number, the first data signal is loaded to the data line for the first time, and the second data signal is loaded to the data line for the last time.

14. The driving method according to claim 8, characterized in that: The display panel comprises a plurality of sub-pixels arranged in an array, wherein the sub-pixels comprise thin film transistors and pixel electrodes, wherein control ends of the thin film transistors in a row of the sub-pixels are electrically connected to a scan line, first ends of the thin film transistors in a column of the sub-pixels are electrically connected to a data line, and second ends of the thin film transistors are electrically connected to the pixel electrode located in the same sub-pixel; When the scan line is loaded with a scan signal, the thin film transistor electrically connected to the scan line is turned on, and each of the data lines loads a data signal corresponding to the brightness to be displayed to the pixel electrode.

15. The driving method according to claim 14, characterized in that: During the display time of a frame of display picture, the pixel electrode maintains the same voltage, which is the voltage corresponding to the written data signal.

16. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 7.

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