Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a data line and a plurality of sub-pixels, and each sub-pixel comprises a pixel circuit; the display panel comprises a frequency adjustable area, a pixel circuit in the frequency adjustable area comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series between a data line and a data access end of a sub-pixel, a grid electrode of the first transistor is connected with a scanning signal, and a grid electrode of the second transistor is connected with a control signal; the working modes of the pixel circuits comprise a first mode and a second mode, the pixel circuit working in the first mode is a first pixel circuit, and the pixel circuit working in the second mode is a second pixel circuit; the refresh rates of scanning signals accessed by the first pixel circuit and the second pixel circuit are the same, and the control signals accessed by the first pixel circuit and the second pixel circuit are different. According to the embodiment of the invention, frequency division display of the display panel can be realized.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies and the increasing requirements of consumers for display panels, the functions integrated in display panels are becoming more and more diverse. For example, for the same display panel, different refresh rates are required in different display scenarios. For instance, for the display of game and movie images, the display panel is required to display at a high refresh rate, while for the display of text, time information, etc., the display panel is required to display at a low refresh rate. Therefore, how to achieve frequency division display of a display panel is a research hotspot in this field. Summary of the Invention

[0003] Embodiments of this application provide a display panel and a display device that can achieve frequency division display of the display panel.

[0004] In a first aspect, embodiments of this application provide a display panel, including: data lines, multiple data lines are arranged along a first direction, the data lines extend along a second direction, and the first direction intersects with the second direction; multiple sub-pixels, the sub-pixels include pixel circuits; the display panel includes a frequency adjustable area, and the pixel circuits in the frequency adjustable area include a first transistor and a second transistor. The first transistor and the second transistor are connected in series between the data line and the data access terminal of the sub-pixel. The gate of the first transistor is connected to a scan signal, and the gate of the second transistor is connected to a control signal; the working modes of the pixel circuits include a first mode and a second mode. The pixel circuits operating in the first mode are first pixel circuits, and the pixel circuits operating in the second mode are second pixel circuits; the refresh rates of the scan signals accessed by the first pixel circuits and the second pixel circuits are the same, and the control signals accessed by the first pixel circuits and the second pixel circuits are different.

[0005] In a first aspect, embodiments of this application provide a display device, including the display panel as described in the embodiments of the first aspect.

[0006] According to the display panel and the display device provided by the embodiments of the present application, the pixel circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series between the data line and the data access terminal of the sub-pixel. The first transistor is controlled by a scan signal, and the second transistor is controlled by a control signal. Moreover, the first pixel circuit operates in the first mode, and the second pixel circuit operates in the second mode. The refresh rates of the scan signals accessed by the first pixel circuit and the second pixel circuit are the same, and the control signals accessed by the first pixel circuit and the second pixel circuit are different. In this way, without changing the scan signal, by differentially designing the control signals accessed by the first pixel circuit and the second pixel circuit, it is possible to achieve that the sub-pixels belonging to the first pixel circuit and the sub-pixels belonging to the second pixel circuit can be displayed at different refresh rates, thereby realizing the frequency-divided display of the display panel. In addition, in the embodiments of the present application, only the control signal needs to be differentiated, so that the display panel can support frequency-divided display only in a partitioned manner in the first direction. Description of the Drawings

[0007] By reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings, other features, objectives, and advantages of the present application will become more obvious. Among them, the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0008] Figure 1 Shows a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0009] Figure 2 Shows another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 3 Shows a schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0011] Figure 4 Shows another schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0012] Figure 5 Shows a schematic timing diagram of a display panel provided by an embodiment of the present application;

[0013] Figure 6 Shows another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 7 Shows another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 8 Shows another schematic timing diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 9Shows another schematic structural diagram of the display panel provided by the embodiments of the present application;

[0017] Figure 10 Shows another schematic structural diagram of the display panel provided by the embodiments of the present application;

[0018] Figure 11 Shows a schematic layout structure diagram of a partial area of the display panel provided by the embodiments of the present application;

[0019] Figure 12 Shows Figure 11 A schematic cross-sectional structure diagram in the B1B2 direction in;

[0020] Figure 13 Shows another timing schematic diagram of the display panel provided by the embodiments of the present application;

[0021] Figure 14 Shows another timing schematic diagram of the display panel provided by the embodiments of the present application;

[0022] Figure 15 Shows a schematic structural diagram of a display device provided by the embodiments of the present application. Detailed implementation manners

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0024] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0025] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0026] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In the embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or it may refer to two components being electrically connected via one or more other components. The term "drive" may refer to "control" or "operation". The term "part" may refer to "local". The term "end" may refer to "end segment" or "end edge". The display panel may be a display device or a module / part of a display device.

[0028] Without departing from the spirit or scope of the present application, various modifications and variations can be made to the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0029] The display panel is composed of a vertical and horizontal array of sub-pixel matrices. During the display process, a scan signal is output by the gate driving circuit to scan each row of sub-pixels row by row. The gate driving circuit includes a plurality of cascaded shift registers. The scan signal output by the shift register controls whether the data signal of the sub-pixels connected thereto can be written, and the scan signal output by the shift register is transmitted to the next-stage shift register, so as to be able to scan each row of sub-pixels row by row.

[0030] In the related art, the up / down frequency division display of the display panel is achieved by modifying the gate driving circuit, while the left / right frequency division display of the display panel cannot be achieved.

[0031] The embodiments of the present application provide a display panel and a display device. The following will describe the embodiments of the display panel and the display device with reference to the accompanying drawings.

[0032] Such as Figure 1 Or Figure 2As shown in the figure, the display panel 100 provided by the embodiment of the present application includes sub-pixels 1, data lines DL, scan lines SL, a gate driving circuit 2, and a bonding area 3.

[0033] A plurality of data lines DL are arranged along the first direction X, and the data lines DL extend along the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is the row direction, and the second direction Y is the column direction. Of course, the row direction and the column direction can be interchanged. The sub-pixels 1 are electrically connected to the data lines DL, and the data lines DL are electrically connected to the bonding area 3. The bonding area 3 includes bonding terminals, and the bonding terminals are electrically connected to the data lines DL and the display driving chip. The data signals provided by the display driving chip are transmitted to the data lines DL through the bonding terminals in the bonding area 3, and then transmitted to the sub-pixels 1.

[0034] The scan lines LS extend along the first direction X, and a plurality of scan lines LS are arranged along the second direction. The sub-pixels 1 are electrically connected to the scan lines LS, and the scan lines LS are electrically connected to the gate driving circuit 2. The scan signals provided by the gate driving circuit 2 are transmitted to the sub-pixels 1 through the scan lines LS.

[0035] Exemplarily, a plurality of sub-pixels 1 arranged in the first direction X form a sub-pixel row 1a, and a plurality of sub-pixels 1 arranged in the second direction Y form a sub-pixel column 1b. A plurality of sub-pixels 1 in the same sub-pixel row 1a are electrically connected to the same scan line LS, and a plurality of sub-pixels 1 in the same sub-pixel column 1b are electrically connected to the same data line DL.

[0036] The sub-pixel 1 includes a pixel circuit 10. The display panel includes a frequency adjustable area QA. The display refresh rate of the frequency adjustable area QA is adjustable, that is, the frequency adjustable area QA supports multiple refresh rates for display.

[0037] As an example, as Figure 1 or Figure 2 shown, the frequency adjustable area QA is the entire display area AA of the display panel. In this example, the display refresh rate of the entire display area is adjustable.

[0038] As another example, the frequency adjustable area QA is a partial display area of the display panel. In this example, the display refresh rate of the partial display area is adjustable.

[0039] As Figure 3 or Figure 4As shown in the figure, the pixel circuit 10 within the frequency adjustable region QA includes a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 are connected in series between the data line DL and the data access terminal 101 of the sub-pixel. The gate of the first transistor T1 is connected to the scan signal Gate, and the gate of the second transistor T is connected to the control signal V. It can be understood that the gate of the first transistor T1 is electrically connected to the scan line LS, and the gate of the first transistor T1 accesses the scan signal Gate through the scan line LS. The display panel further includes a control signal line SW. The gate of the second transistor T is electrically connected to the control signal line SW, and the gate of the second transistor T accesses the control signal through the control signal line SW.

[0040] As an example, as Figure 3 shown, the second transistor T2 is electrically connected between the first transistor T1 and the data line DL. Specifically, the first pole of the second transistor T2 is electrically connected to the data line DL, the second pole of the second transistor T2 is electrically connected to the first pole of the first transistor T1, and the second pole of the first transistor T1 is electrically connected to the data access terminal 101. In this example, when the first transistor T1 is turned on and the second transistor T2 is turned off, it is possible to prevent the data signal on the data line DL from being transmitted to the first pole of the first transistor T1, thereby avoiding affecting the voltage on the data access terminal 101.

[0041] As an example, as Figure 4 shown, the first transistor T1 is electrically connected between the second transistor T2 and the data line DL. Specifically, the first pole of the first transistor T1 is electrically connected to the data line DL, the second pole of the first transistor T1 is electrically connected to the first pole of the second transistor T2, and the second pole of the second transistor T2 is electrically connected to the data access terminal 101.

[0042] It can be understood that the scan signal Gate and the control signal V jointly control whether the data signal on the data line DL can be written into the data access terminal 101 of the sub-pixel. When both the first transistor T1 and the second transistor T2 are turned on, the data signal on the data line DL can be written into the data access terminal 101 of the sub-pixel; when at least one of the first transistor T1 and the second transistor T2 is turned off, the data signal on the data line DL cannot be written into the data access terminal 101 of the sub-pixel. Within a unit time, the higher the frequency at which the data signal on the data line DL is written into the data access terminal 101 of the sub-pixel, the higher the data refresh rate of the sub-pixel, and the sub-pixel is displayed at a high refresh rate. Conversely, within a unit time, the lower the frequency at which the data signal on the data line DL is written into the data access terminal 101 of the sub-pixel, the lower the data refresh rate of the sub-pixel, and the sub-pixel is displayed at a low refresh rate.

[0043] As Figure 1 or Figure 2As shown, the operating modes of the pixel circuits include a first mode and a second mode. The pixel circuit operating in the first mode is the first pixel circuit 11, and the pixel circuit operating in the second mode is the second pixel circuit 12. The refresh rates of the scan signals Gate applied to the first pixel circuit 11 and the second pixel circuit 12 are the same, and the control signals V applied to the first pixel circuit 11 and the second pixel circuit 12 are different.

[0044] It can be understood that within a unit time, the number of times the first transistor T1 in the first pixel circuit 11 and the second pixel circuit 12 is turned on is the same. Within a unit time, the conduction durations of the second transistor T2 in the first pixel circuit 11 and the second pixel circuit 12 are different.

[0045] Exemplarily, the duration of a single conduction pulse (for example, the conduction pulse is a high-level pulse) of the scan signal Gate applied to the first pixel circuit 11 and the second pixel circuit 12 is the same.

[0046] As an example, as Figure 5 shown, Figure 5 is schematically illustrated with the high level as the conduction level and the low level as the cut-off level. The conduction level is the level that controls the transistor to conduct, and the cut-off level is the level that controls the transistor to turn off. For example, the display panel includes k sub-pixel rows, where k is an integer greater than 1. The scan signals applied to the k sub-pixel rows are respectively labeled as G_1 to G_k. The conduction pulses of the scan signals G_1 to G_k are transmitted step by step to scan each sub-pixel row row by row. In each sub-frame, the scan signals G_1 to G_k each include a conduction pulse. In this way, in each sub-frame, the first transistor in the first pixel circuit and the second pixel circuit is turned on once.

[0047] Figure 5 In, the first control signal V1 is the control signal applied to the gate of the second transistor T2 in the first pixel circuit 11, and the second control signal V2 is the control signal applied to the gate of the second transistor T2 in the second pixel circuit 12. For example, the first control signal V1 is at the conduction level in each sub-frame f, the second control signal V2 is at the conduction level in some sub-frames, and the second control signal V2 is at the cut-off level in another part of the sub-frames. In this way, the second transistor in the first pixel circuit conducts in each sub-frame, and the second transistor in the second pixel circuit only conducts in some sub-frames. It can be understood that in this example, the data signal on the data line DL can be written into the data input terminal connected to the first pixel circuit in each sub-frame, and the data signal on the data line DL can only be written into the data input terminal connected to the second pixel circuit in some sub-frames. The data refresh rate corresponding to the first pixel circuit is greater than the data refresh rate corresponding to the second pixel circuit, so that the sub-pixels belonging to the first pixel circuit can be displayed at a high refresh rate, and the sub-pixels belonging to the second pixel circuit can be displayed at a low refresh rate, thereby realizing the frequency-divided display of the display panel.

[0048] According to the display panel provided by the embodiments of the present application, the pixel circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected in series between the data line and the data access terminal of the sub-pixel. The first transistor is controlled by a scan signal, and the second transistor is controlled by a control signal. The first pixel circuit operates in the first mode, and the second pixel circuit operates in the second mode. The refresh rates of the scan signals accessed by the first pixel circuit and the second pixel circuit are the same, and the control signals accessed by the first pixel circuit and the second pixel circuit are different. In this way, without changing the scan signal, by differentiating the control signals accessed by the first pixel circuit and the second pixel circuit, it is possible to achieve that the sub-pixels belonging to the first pixel circuit and the sub-pixels belonging to the second pixel circuit can be displayed at different refresh rates, thereby realizing the frequency division display of the display panel. In addition, in the embodiments of the present application, only the control signal needs to be differentiated, so that the display panel can support the frequency division display only in a partitioned manner in the first direction.

[0049] In some embodiments, as Figure 1 shown, the frequency adjustable region QA includes a first display region A1 and a second display region A2. The first pixel circuit 11 is located in the first display region A1, and the second pixel circuit 12 is located in the second display region A2.

[0050] The first display region A1 and the second display region A2 are different regions of the display panel. As an example, the first display region A1 and the second display region A2 are arranged in the first direction. As another example, the first display region A1 and the second display region A2 are arranged in the second direction Y.

[0051] The first display region A1 includes the first pixel circuit 11, and the second display region A2 includes the second pixel circuit 12. It can be understood that the refresh rates of the scan signals accessed by the first display region A1 and the second display region A2 are the same, and the control signals accessed by the first display region A1 and the second display region A2 are different. In this way, the first display region A1 and the second display region A2 can be displayed at different refresh rates, enabling the display panel to support partitioned frequency division display.

[0052] In some embodiments, as Figure 6 shown, the first display region A1 and the second display region A2 are arranged along the first direction X. The gate of the second transistor T2 in the first pixel circuit 11 is electrically connected to the first control signal line SW1, and the gate of the second transistor T2 in the second pixel circuit 12 is electrically connected to the second control signal line SW2. The first control signal line SW1 is used to transmit the first control signal, and the second control signal line SW2 is used to transmit the second control signal.

[0053] The first display region A1 and the second display region A2 are different regions of the display panel in the first direction X. For example,Figure 6 In this case, the first display area A1 is located on the left side, and the second display area A2 is located on the right side. In this way, the first display area A1 and the second display area A2 can be displayed at different refresh rates, so that the display panel supports left-right partition frequency display.

[0054] In some embodiments, please refer to Figure 7 and Figure 8 , the operating mode of the pixel circuit further includes a third mode, and the pixel circuit operating in the third mode is the third pixel circuit 13; the refresh rates of the scan signals accessed by the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are the same, and the control signals accessed by the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are different; the frequency adjustable area further includes a third display area A3, the first display area A1 and the second display area A2 are arranged along the first direction X, the third display area A3 is arranged with at least one of the first display area A1 and the second display area A2 in the second direction Y, the third pixel circuit 13 is located in the third display area A3, and the gate of the second transistor T2 in the third pixel circuit 13 is electrically connected to the third control signal line SW3.

[0055] The third control signal line SW3 is used to transmit a third control signal.

[0056] For example, the display panel includes h sub-pixel columns. The 1st to h1th sub-pixel columns in the 1st to m1th sub-pixel rows are located in the first display area A1, the (h1 + 1)th to hth sub-pixel columns in the 1st to m1th sub-pixel rows are located in the second display area A2, and the (m1 + 1)th to mth sub-pixel rows are located in the third display area A3, where m1 is a value greater than 1 and less than m, and h1 is a value greater than 1 and less than h.

[0057] Exemplarily, taking Figure 8 as an example, Figure 8 The same parts as Figure 5 will not be described in detail again. The differences include: Figure 8Among them, the first control signal V1 is the control signal applied to the gate of the second transistor T2 in the first pixel circuit 11, the second control signal V2 is the control signal applied to the gate of the second transistor T2 in the second pixel circuit 12, and the third control signal V3 is the control signal applied to the gate of the second transistor T2 in the third pixel circuit 13. For example, a frame refresh period T includes 3 sub-frames f. The first control signal V1 is at a conductive level in each sub-frame f; the second control signal V2 is at a conductive level in 2 sub-frames and at a cut-off level in another sub-frame; the third control signal V3 is at a conductive level in 1 sub-frame and at cut-off levels in the other 2 sub-frames. In this way, the second transistor in the first pixel circuit is turned on in each sub-frame, the second transistor in the second pixel circuit is turned on only in 2 sub-frames, and the second transistor in the third pixel circuit is turned on only in 1 sub-frame. It can be understood that in this example, the data signal on the data line DL can be written into the data input terminal connected to the first pixel circuit in each sub-frame, the data signal on the data line DL can be written into the data input terminal connected to the second pixel circuit only in 2 sub-frames, and the data signal on the data line DL can be written into the data input terminal connected to the third pixel circuit only in 1 sub-frame. The data refresh rate corresponding to the first pixel circuit is greater than that corresponding to the second pixel circuit, and the data refresh rate corresponding to the second pixel circuit is greater than that corresponding to the third pixel circuit, so that the first display area can be displayed at the highest refresh rate, the refresh rate of the second display area is the second highest, and the refresh rate of the third display area is the lowest.

[0058] In this embodiment, the first display area and the second display area are arranged in the first direction, and the third display area is arranged in the second direction with at least one of the first display area and the second display area. For example, the first direction is the left-right direction and the second direction is the up-down direction, so that the display panel supports not only left-right sub-area frequency division display but also up-down sub-area frequency division display.

[0059] In some embodiments, as Figure 9 shown, the frequency adjustable area QA includes at least one sub-display area A11. The sub-display area A11 includes a plurality of sub-pixel columns 1b, and the sub-pixel columns 1b include a plurality of sub-pixels 1 arranged in the second direction.

[0060] A plurality of sub-pixel columns 1b in the sub-display area A11 are arranged in one-to-one correspondence with a plurality of control signal lines SW, and the control signal lines SW are used to transmit control signals.

[0061] In this embodiment, a plurality of sub-pixels in the same column and within the same sub-display area share one control signal line, which can simplify the structure.

[0062] Exemplarily, a plurality of control signal lines corresponding to the same sub-display area can be electrically connected to each other. That is to say, the control signals applied to the same sub-display area are the same.

[0063] Exemplarily, the control signal lines corresponding to different sub-displays can be disconnected from each other. That is to say, the control signals accessed by different sub-display areas can be different. In this way, the data refresh rates of different sub-display areas can be independently controlled to better achieve zoned and frequency-divided display.

[0064] For example, Figure 9 shows four sub-display areas A11. The four sub-display areas A11 are respectively A11_1 to A11_4. The four sub-display areas A11_1 to A11_4 respectively correspond to a control signal line SW_1, a control signal line SW_2, a control signal line SW_3, and a control signal line SW_4. A plurality of control signal lines SW_1 are electrically connected to each other, a plurality of control signal lines SW_2 are electrically connected to each other, a plurality of control signal lines SW_3 are electrically connected to each other, a plurality of control signal lines SW_4 are electrically connected to each other, and the control signal lines SW_1, SW_2, SW_3, and SW_4 are disconnected from each other.

[0065] In some other embodiments, as Figure 10 shown, the frequency adjustable area QA includes at least one sub-display area A11. The sub-display area A11 includes a plurality of sub-pixel columns 1b. The sub-pixel columns 1b include a plurality of sub-pixels 1 arranged along the second direction.

[0066] A plurality of sub-pixel columns within the same sub-display area A11 are electrically connected to the same control signal line SW. The control signal line SW is used to transmit control signals.

[0067] In this embodiment, a plurality of sub-pixel columns within the same sub-display area share the same control signal line, which can further simplify the structure. Moreover, the number of control signal lines is reduced, which can effectively optimize the pixel aperture of the display panel.

[0068] It can be understood that in this embodiment, the control signals accessed by the same sub-display area are the same.

[0069] Exemplarily, the control signal lines corresponding to different sub-displays can be disconnected from each other. That is to say, the control signals accessed by different sub-display areas can be different. In this way, the data refresh rates of different sub-display areas can be independently controlled to better achieve zoned and frequency-divided display.

[0070] For example, Figure 10Four sub-display areas A11 are shown, and the four sub-display areas A11 are A11_1 to A11_4 respectively. The four sub-display areas A11_1 to A11_4 respectively correspond to control signal lines SW_1, control signal line SW_2, control signal line SW_3, and control signal line SW_4. The control signal line SW_1 is electrically connected to a plurality of sub-pixel columns in the sub-display area A11_1, the control signal line SW_2 is electrically connected to a plurality of sub-pixel columns in the sub-display area A11_2, the control signal line SW_3 is electrically connected to a plurality of sub-pixel columns in the sub-display area A11_3, and the control signal line SW_4 is electrically connected to a plurality of sub-pixel columns in the sub-display area A11_4. Moreover, the control signal lines SW_1, SW_2, SW_3, and SW_4 are disconnected from each other.

[0071] In some embodiments, please continue to refer to Figure 10 , the sub-pixels include sub-pixels of multiple light-emitting colors. For example, the sub-pixels include a first sub-pixel 1_1, a second sub-pixel 1_2, and a third sub-pixel 1_3 with different light-emitting colors. The light emitted by the first sub-pixel 1_1, the second sub-pixel 1_2, and the third sub-pixel 1_3 can form white light. Under a white screen, the brightness ratio of the first sub-pixel 1_1 is the smallest. The sub-pixel column where the first sub-pixel 1_1 is located is the first sub-pixel column 1b1, the sub-pixel column where the second sub-pixel 1_2 is located is the first sub-pixel column 1b2, and the sub-pixel column where the third sub-pixel 1_3 is located is the first sub-pixel column 1b3.

[0072] The data line electrically connected to the first sub-pixel column 1b1 is the first data line DL1, and the control signal line SW is adjacent to the first data line DL1. Here, "adjacent" means that in the first direction X, there is no other data line between the control signal line SW and the first data line DL1 electrically connected to the first sub-pixel column 1b1.

[0073] For example, the control signal line SW_1 and the first data line DL1 in the sub-display area A11_1 are arranged adjacent to each other, the control signal line SW_2 and the first data line DL1 in the sub-display area A11_2 are arranged adjacent to each other, the control signal line SW_3 and the first data line DL1 in the sub-display area A11_3 are arranged adjacent to each other, and the control signal line SW_4 and the first data line DL1 in the sub-display area A11_4 are arranged adjacent to each other.

[0074] As an example, under a white screen, the brightness ratio of the green sub-pixels is greater than the brightness ratio of the red sub-pixels, and the brightness ratio of the red sub-pixels is greater than the brightness ratio of the blue sub-pixels. The first sub-pixel includes a blue sub-pixel.

[0075] For sub-pixels with a smaller brightness ratio, the size of the pixel aperture has little impact on the overall white screen display effect. In this embodiment, by arranging the control signal line adjacent to the first data line electrically connected to the first sub-pixel with the smallest brightness ratio, the impact of the control signal line on the white screen display effect can be minimized as much as possible.

[0076] In some embodiments, please continue to refer to Figure 10 , the control signal line SW extends along the second direction Y, and the display panel further includes a first connection line 21 extending along the first direction X. Sub-pixels in the same row within the same sub-display area A11 are electrically connected to the same control signal line SW through the first connection line 21.

[0077] In this embodiment, by providing the first connection line, sub-pixels in the same row can be connected to the same control signal line.

[0078] Exemplarily, sub-pixels in different rows within the same sub-display area A11 are electrically connected to the same control signal line SW through different first connection lines 21. The first connection lines 21 in different sub-display areas A11 are disconnected from each other.

[0079] In some embodiments, as Figure 11 shown, the first connection line 21 and the scan line SL are located in the first metal layer M1; the data line DL and the control signal line SW are located in the second metal layer M2. The first metal layer M1 and the second metal layer M2 are insulated from each other.

[0080] The first connection line 21 and the scan line SL extend along the first direction X, and the data line DL and the control signal line SW extend along the second direction Y. The first connection line 21 can be electrically connected to the control signal line SW through a via.

[0081] In some embodiments, please refer to Figure 11 and Figure 12 , the display panel further includes a semiconductor layer 30. The semiconductor layer 30 includes the active layer t11 of the first transistor T1 and the active layer t12 of the second transistor T2. The data line DL overlaps with the active layer of the transistor electrically connected thereto. For example, Figure 11 shows that the data line DL is electrically connected to the first pole of the second transistor T2, the second pole of the second transistor T2 is electrically connected to the first transistor T1, and the data line DL overlaps with the active layer t12 of the second transistor T2. Here, "overlap" means that the data line DL is directly connected to the active layer t12 of the second transistor T2, rather than through a via. In this embodiment, by overlapping the data line DL with the active layer of the transistor electrically connected thereto, via holes can be avoided, and the manufacturing process can be simplified.

[0082] Exemplarily, both the first transistor T1 and the second transistor T2 are N-type transistors. For example, the materials of the active layer t11 of the first transistor T1 and the active layer t12 of the second transistor T2 include indium gallium zinc oxide (IGZO) or a-si.

[0083] Exemplarily, the display panel includes a substrate 40, a first metal layer M1 is located between the semiconductor layer 30 and the substrate 40, an insulating layer 50 is disposed between the first metal layer M1 and the semiconductor layer 30, and the second metal layer M2 and the semiconductor layer 30 are located on the same layer. During the manufacturing process, the first metal layer is first formed, then the insulating layer 50 is fabricated, then the semiconductor layer 30 is prepared, and then the second metal layer M2 is fabricated. It can be understood that in this example, the first transistor and the second transistor are of the bottom-gate structure. Exemplarily, the display panel includes a liquid crystal display panel.

[0084] In some embodiments, as Figure 11 shown, the first transistor T1 and the second transistor T2 are electrically connected through a second connection line 22, and the second connection line 22 is located in the second metal layer M2. Exemplarily, the second connection line 22 overlaps with the active layer t11 of the first transistor T1 and the active layer t12 of the second transistor T2.

[0085] Exemplarily, as Figure 11 shown, the display panel further includes a light-shielding layer BM, and the light-shielding layer BM overlaps with the scan line SL and the first transistor T1 and the second transistor T2.

[0086] In some embodiments, as Figure 5 or Figure 13 shown, one frame refresh period T of the pixel circuit includes n sub-frames f, where n is greater than 1. The data refresh rate of the first pixel circuit is greater than that of the second pixel circuit. That is to say, within one frame refresh period T, the number of times the first pixel circuit writes a data signal to the data access terminal it is connected to is greater than the number of times the second pixel circuit writes a data signal to the data access terminal it is connected to.

[0087] For example, Figure 5 taking the control signal accessed by the first pixel circuit as V1 and the control signal accessed by the second pixel circuit as V2 as an example, the control signal V1 accessed by the first pixel circuit is at a conductive level (such as a high level) in n1 sub-frames, and the control signal V1 accessed by the first pixel circuit is at a cut-off level in n2 sub-frames, where n1 + n2 = n. The control signal V2 accessed by the second pixel circuit is at a conductive level in n3 sub-frames, and the control signal V2 accessed by the second pixel circuit is at a cut-off level in n4 sub-frames, where n3 + n4 = n, and n1, n2, n3, and n4 are all integers; n1 > n3.

[0088] Figure 5 where n2 = 0, n1 = n = 2; n3 = n4 = 1. Taking the duration corresponding to 30H for each sub-frame f as an example, Figure 5 In the example shown, the data refresh rate of the first pixel circuit is 60HZ, and the data refresh rate of the second pixel circuit is 30HZ.

[0089] For another example, Figure 13 taking the control signal connected to the first pixel circuit as V_1 and the control signal connected to the second pixel circuit as V_2 as an example, Figure 13 where n2 = 0, n1 = n = 6; n3 = n4 = 3. Taking the duration corresponding to 30H for each sub-frame f as an example, Figure 13 In the example shown, the data refresh rate of the first pixel circuit is 180HZ, and the data refresh rate of the second pixel circuit is 90HZ.

[0090] For another example, Figure 13 taking the control signal connected to the first pixel circuit as V_3 and the control signal connected to the second pixel circuit as V_4 as an example, Figure 13 where n1 = 2, n2 = 4, n = 6; n3 = 1, n4 = 5. Taking the duration corresponding to 30H for each sub-frame f as an example, Figure 13 In the example shown, the data refresh rate of the first pixel circuit is 60HZ, and the data refresh rate of the second pixel circuit is 30HZ.

[0091] Within each sub-frame, the gate driving circuit scans each row of sub-pixels line by line, and the first transistor in the first sub-pixel and the second sub-pixel conducts once within each sub-frame.

[0092] In this embodiment, the control signal connected to the first pixel circuit is at a conductive level within n1 sub-frames, and the control signal connected to the second pixel circuit is at a cut-off level within n3 sub-frames, where n1 is greater than n3, such that the data refresh rate of the first pixel circuit is greater than that of the second pixel circuit.

[0093] Exemplarily, such as Figure 13As shown, the second transistor controlled by the control signal V_1 is electrically connected to the data line DL_1, the second transistor controlled by the control signal V_2 is electrically connected to the data line DL_2, the second transistor controlled by the control signal V_3 is electrically connected to the data line DL_3, and the second transistor controlled by the control signal V_4 is electrically connected to the data line DL_4. When the control signal is at the conductive level (e.g., high level vgh), data signals are normally transmitted on the data line corresponding to this control signal. When the control signal is at the cut-off level (e.g., low level vgl), the data line corresponding to this control signal stops transmitting data signals. That is to say, the pin of the display driver chip connected to the data line corresponding to this control signal stops outputting data signals, thus saving power consumption.

[0094] In some embodiments, as Figure 14 shown, Figure 14 taking the control signal accessed by the first pixel circuit as V1 and the control signal accessed by the second pixel circuit as V2 as an example, the control signal V1 accessed by the first pixel circuit is at the conductive level (e.g., high level) in n1 sub-frames, and the control signal V1 accessed by the first pixel circuit is at the cut-off level in n2 sub-frames, where n1 + n2 = n. The control signal V2 accessed by the second pixel circuit is at the conductive level in n3 sub-frames, and the control signal V2 accessed by the second pixel circuit is at the cut-off level in n4 sub-frames, where n3 + n4 = n, and n1, n2, n3, and n4 are all integers; n1 > n3. When 1 < n1 < n, there is a cut-off level between at least two conductive levels of the control signal V1 accessed by the first pixel circuit; and / or when 1 < n3 < n, there is a cut-off level between at least two conductive levels of the control signal V2 accessed by the second pixel circuit.

[0095] Exemplarily, Figure 14 taking n1 = n2 = 3, n3 = 2, and n4 = 4 as an example, within the entire period T, the conductive level and the cut-off level of the control signal V1 accessed by the first pixel circuit can be alternately set; in the first 3 sub-frames f, the conductive level and the cut-off level of the control signal V2 accessed by the second pixel circuit can be alternately set; in the last 3 sub-frames, the control signal V2 accessed by the second pixel circuit remains at the cut-off level.

[0096] The pixel circuit writes the data signal on the data line to the data input terminal. When the data input terminal is not written with a signal for a long time, there may be a leakage current, resulting in a sudden change in the brightness of the sub-pixel. In the embodiments of the present application, there is a cut-off level between the conductive levels of the control signal within the period T, which can prevent the data input terminal from not being written with a signal for a long time, thereby avoiding a sudden change in the brightness of the sub-pixel due to the leakage current.

[0097] In some embodiments, the display panel includes a first data refresh stage and a second data refresh stage. The first mode is the first data refresh stage, and the second mode is the second data refresh stage.

[0098] The first data refresh stage and the second data refresh stage are two different time periods. Exemplarily, in the first data refresh stage, the control signal accessed by the second transistor in each pixel circuit is at a conductive level; that is, in the first data refresh stage, the second transistors in each pixel circuit are all turned on. In the second data refresh stage, the control signal accessed by the second transistor in each pixel circuit is at a cut-off level; that is, in the second data refresh stage, the second transistors in each pixel circuit are all turned off.

[0099] In this embodiment, the display panel can support time-division and frequency-division display.

[0100] In some embodiments, the display panel includes a liquid crystal display panel. The sub-pixel includes a pixel electrode, and the pixel electrode is electrically connected to the data access terminal. When the first transistor and the second transistor are both turned on, the data signal on the data line is written into the data input terminal through the first transistor and the second transistor, and the data signal at the data input terminal is transmitted to the pixel electrode. The liquid crystal display panel further includes a common electrode and liquid crystal. The common electrode is connected to a common voltage, and an electric field is generated between the pixel electrode and the common electrode. The electric field controls the flipping of the liquid crystal, thereby controlling the brightness of the sub-pixel.

[0101] Of course, in other examples, the display panel includes an Organic Light-Emitting Diode (OLED) display panel or other types of display panels. Taking the display panel including an OLED display panel as an example, the pixel circuit further includes a driving transistor, and the data input terminal is electrically connected to the gate or source or drain of the driving transistor, and the data signal is written into the gate of the driving transistor.

[0102] This application also provides a display device, including the display panel provided by this application. Please refer to Figure 15 , Figure 15 which is a schematic structural diagram of a display device provided by an embodiment of this application. Figure 5 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of this application. Figure 15 Taking a mobile phone as an example only in the embodiment, the display device 1000 is described. It can be understood that the display device provided by the embodiments of this application can be other display devices with a display function such as wearable products, computers, televisions, in-vehicle display devices, etc. This application does not make specific limitations in this regard. The display device provided by the embodiments of this application has the beneficial effects of the display panel provided by the embodiments of this application. For specific descriptions of the display panel, reference can be made to the above embodiments. Details are not described herein again in this embodiment.

[0103] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: Data lines, a plurality of the data lines are arranged along a first direction, the data lines extend along a second direction, and the first direction and the second direction intersect; a plurality of sub-pixels, the sub-pixels comprising pixel circuits; The display panel comprises a frequency adjustable region, the pixel circuit in the frequency adjustable region comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series between the data line and the data access terminal of the sub-pixel, the gate of the first transistor is connected to a scanning signal, and the gate of the second transistor is connected to a control signal; The working mode of the pixel circuit includes a first mode and a second mode, the pixel circuit working in the first mode is a first pixel circuit, and the pixel circuit working in the second mode is a second pixel circuit; The scan signals connected to the first pixel circuit and the second pixel circuit have the same refresh rate, and the control signals connected to the first pixel circuit and the second pixel circuit are different.

2. The display panel according to claim 1, characterized in that: The frequency adjustable area is a partial display area of ​​the display panel; Alternatively, the frequency adjustable area is the entire display area of ​​the display panel.

3. The display panel according to claim 1 or 2, characterized in that: The frequency adjustable area includes a first display area and a second display area. The first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area.

4. The display panel according to claim 3, characterized in that: The first display area and the second display area are arranged along the first direction; A gate of the second transistor in the first pixel circuit is electrically connected to a first control signal line, and a gate of the second transistor in the second pixel circuit is electrically connected to a second control signal line.

5. The display panel according to claim 4, characterized in that: The working mode of the pixel circuit further includes a third mode, and the pixel circuit working in the third mode is a third pixel circuit; The refresh rates of the scanning signals connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit are the same, and the control signals connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit are different; The frequency adjustable area also includes a third display area, which is arranged in the second direction with at least one of the first display area and the second display area. The third pixel circuit is located in the third display area, and the gate of the second transistor in the third pixel circuit is electrically connected to the third control signal line.

6. The display panel according to claim 1 or 2, characterized in that: The frequency adjustable area includes at least one sub-display area, the sub-display area includes a plurality of sub-pixel columns, and the sub-pixel columns include a plurality of the sub-pixels arranged along the second direction; The plurality of sub-pixel columns and the plurality of control signal lines in the sub-display area are arranged in one-to-one correspondence, and the control signal lines are used to transmit the control signals.

7. The display panel according to claim 1 or 2, characterized in that: The frequency adjustable area includes at least one sub-display area, the sub-display area includes a plurality of sub-pixel columns, and the sub-pixel columns include a plurality of the sub-pixels arranged along the second direction; A plurality of sub-pixel columns in the same sub-display area are electrically connected to a same control signal line, and the control signal line is used to transmit the control signal.

8. The display panel according to claim 7, characterized in that: The sub-pixels include sub-pixels of multiple light-emitting colors. Under a white screen, the brightness of the first sub-pixel among the sub-pixels of multiple light-emitting colors accounts for the smallest proportion; the sub-pixel column where the first sub-pixel is located is a first sub-pixel column, the data line electrically connected to the first sub-pixel column is a first data line, and the control signal line is adjacent to the first data line.

9. The display panel according to claim 7, characterized in that: The control signal line extends along the second direction, and the display panel further includes a first connection line extending along the first direction, and the sub-pixels in the same row in the same sub-display area are electrically connected to the same control signal line through the first connection line.

10. The display panel according to claim 9, characterized in that: The first connection line and the scan line are located in a first metal layer; the data line and the control signal line are located in a second metal layer.

11. The display panel according to claim 10, characterized in that: The display panel further includes a semiconductor layer, the semiconductor layer includes active layers of the first transistor and the second transistor, and the data line overlaps the active layers of the transistors to which the data line is electrically connected.

12. The display panel according to claim 10, characterized in that: The first transistor and the second transistor are electrically connected via a second connecting line, and the second connecting line is located in the second metal layer.

13. The display panel according to claim 1, characterized in that: One picture refresh cycle of the pixel circuit includes n subframes, where n is greater than 1; The data refresh rate of the first pixel circuit is greater than the data refresh rate of the second pixel circuit; The control signal connected to the first pixel circuit is at an on level in n1 subframes and at an off level in n2 subframes, n1+n2=n; The control signal connected to the second pixel circuit is at an on level in n3 subframes and at an off level in n4 subframes, n3+n4=n, and n1, n2, n3, and n4 are all integers; n1>n3.

14. The display panel according to claim 13, characterized in that: In the case of 1<n1<n, at least two on-levels of the control signal connected to the first pixel circuit are separated by an off-level; And / or, in the case of 1<n3<n, at least two on-levels of the control signal connected to the second pixel circuit are separated by an off-level.

15. The display panel according to claim 1 or 2, characterized in that: The display panel includes a first data refresh phase and a second data refresh phase, the first mode is the first data refresh phase, and the second mode is the second data refresh phase.

16. The display panel according to claim 1 or 2, characterized in that: The second transistor is electrically connected between the first transistor and the data line.

17. The display panel according to claim 1, characterized in that: The display panel includes a liquid crystal display panel, the sub-pixel includes a pixel electrode, and the pixel electrode is electrically connected to the data access terminal.

18. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 17.

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