A High-Speed Parallel Viterbi Decoding Method and System

Abstract

The present invention relates to the field of channel decoding technology. A high-speed parallel Viterbi decoding method and system are provided. The method comprises the following steps: caching the parallel soft decision outputs of baseband demodulation using a ping-pong buffer unit to generate #imgabs0# parallel block data; adjusting the puncturing position of the #imgabs1# parallel block data using a puncture code pattern detection module; generating parallel BM data corresponding to the #imgabs2# parallel block data using a parallel BM calculation module; performing addition, comparison, and selection operations on the parallel BM data using a parallel ACS module to obtain a parallel ACS result; updating the survivor path based on the parallel ACS result using a parallel survivor path update module; and outputting the convolution decoding result using a backtracking decoding module based on a survivor path table lookup. The method addresses the throughput bottleneck, multi-rate adaptive defects, imbalance between energy efficiency and cost, low signal-to-noise ratio performance loss, and serial processing efficiency limitations found in existing Viterbi decoding technologies.

Description

Technical Field

[0001] The present invention relates to the technical field of channel decoding, and in particular to a high-speed parallel Viterbi decoding method and system. Background Art

[0002] As a highly efficient error correction technology, convolutional coding is widely used in data transmission systems such as satellite and mobile communications due to its strong resistance to burst errors and low encoding and decoding complexity. By flexibly adjusting the coding rate, convolutional coding can adapt to different channel characteristics, effectively improving the anti-interference and fault tolerance capabilities of communication systems. However, traditional maximum likelihood decoding algorithms, due to the need to traverse a large number of state transition paths, result in high decoding latency and high resource consumption, making them difficult to meet the real-time requirements of high-speed data transmission systems. The Viterbi decoding algorithm significantly reduces computational complexity by optimizing path selection through dynamic programming, but its hardware implementation still faces throughput bottlenecks. For example, existing FPGA solutions only support a throughput of 40Mbps at a 200MHz clock, making them difficult to adapt to ultra-high-speed scenarios.

[0003] To improve throughput, fully parallel Viterbi decoding schemes employ GPUs to achieve high parallelism, but this results in a dramatic increase in hardware costs and low energy efficiency. Furthermore, existing FPGA-based parallel decoding schemes often employ hard-decision inputs, sacrificing decoding gain at low signal-to-noise ratios and failing to address the synchronization issue between the decoding clock and the system clock. While segmented parallel decoding algorithms double throughput through caching and soft-decision parallel inputs, they fail to account for the impact of varying coding rates and are unable to adapt to the rate switching requirements of highly dynamic, beyond-horizon fading channels, limiting their applicability in complex channel environments.

[0004] Existing technologies use punctured codes to flexibly adjust the coding rate by adjusting the puncturing pattern. However, traditional decoders lack efficient pattern detection and dynamic adjustment mechanisms for puncturing positions, making multi-rate adaptive decoding difficult. Furthermore, the serial processing of survivor path storage and backtracking decoding further limits throughput. Therefore, a parallel Viterbi decoding method that balances high throughput, low resource overhead, and multi-rate adaptability is urgently needed to meet the stringent real-time and anti-interference performance requirements of high-speed data transmission systems. Summary of the Invention

[0005] The present invention aims to provide a high-speed parallel Viterbi decoding method and system, aiming to solve the problems existing in the existing Viterbi decoding technology, such as throughput bottleneck, multi-rate adaptation defect, energy efficiency and cost imbalance, low signal-to-noise ratio performance loss and serial processing efficiency limitation.

[0006] The present invention is achieved through the following technical solutions:

[0007] A high-speed parallel Viterbi decoding method comprises the following steps:

[0008] The parallel soft decision output of baseband demodulation is cached by the ping-pong buffer unit to generate Parallel block data;

[0009] Adjustment through the puncture code pattern detection module The location of the supplementary punching of parallel block data;

[0010] Generated by parallel BM calculation module Parallel BM data corresponding to the parallel block data;

[0011] The parallel ACS module performs addition, comparison and selection operations on the parallel BM data to obtain the parallel ACS result;

[0012] Based on the parallel ACS results, the survivor path update is completed through the parallel survivor path update module;

[0013] Output the convolution decoding result according to the surviving path lookup table through the backtracking decoding module;

[0014] Among them, the It is determined by the logic delay value of the parallel ACS module and the maximum possible number of supplementary puncture positions.

[0015] Optionally, the parallel soft decision output of baseband demodulation is cached by the ping-pong cache unit to generate The specific process of parallel block data is as follows:

[0016] The parallel soft symbol data output by baseband demodulation is recorded as , The baseband demodulation output soft decision symbols, Indicates the starting position of the current soft symbol sequence, and outputs the buffered data through the ping-pong buffer unit , the cached data The expression of is shown in the following formula (1):

[0017]

[0018] in, Indicates the cache length; represents the useful decoding input length, and An integer multiple of 8; represents the backtracking depth, and An integer multiple of 8;

[0019] According to the cache data output by the ping-pong cache unit , using the serial-to-parallel conversion unit to cache data Convert to Parallel block data , No. The road data is expressed as follows:

[0020]

[0021] in, Indicates the effective block length, and satisfy ; Indicates the number of parallel operations.

[0022] Optionally, the puncture code pattern detection module adjusts The specific process of filling the puncture position of the parallel block data is as follows:

[0023] According to the preset Bit rate Different supplementary puncture positions are configured for the road block data; is the number of preset candidate puncture patterns that meet ;

[0024] Regarding the The block data after the road patching and punching is parallelized to perform branch metric calculation, addition and comparison operation and survivor path update to generate Road decoding result;

[0025] The The decoding results are re-encoded and compared with the original input data for bit errors, and the puncturing pattern with the least bit errors is selected;

[0026] Adjust according to the selected punching mode The location of the puncture for the parallel block data; Road filling punching mode and The mapping relationship between parallel blocks is determined by the actual bit rate requirement.

[0027] Optionally, the parallel BM calculation module generates The specific process of parallel BM data corresponding to parallel block data is as follows:

[0028] For the Parallel block data , at each decoding Soft symbol sequence input to the branch metric calculation unit , The expression of is shown in the following formula (3):

[0029]

[0030] Output matrix according to the locally stored state transition codeword , calculate the branch metric value of the current time step , No. The expression of the branch metric value is shown in the following formula (4):

[0031]

[0032] in, Indicates the In the parallel block, The branch metric value of each branch; Indicates the first Line code word; Indicates Euclidean distance calculation; Indicates the branch index in each state; The index representing the current state; Indicates the constraint length of convolutional coding;

[0033] Arrange the branch metrics in the order of state transition to generate Parallel BM data .

[0034] Optionally, the specific process of performing the addition, comparison, and selection operations on the parallel BM data through the parallel ACS module to obtain the parallel ACS result is:

[0035] When decoding When the state of each parallel block is cumulatively measured Perform initialization operations and set all state cumulative metrics to 0;

[0036] When decoding, the beat is satisfied When the branch metric The state cumulative metrics are accumulated as shown in the following formula (5):

[0037]

[0038] When decoding When, for each state Select the path corresponding to the minimum cumulative metric, update the state cumulative metric and the optimal state vector , as shown in the following formula (6):

[0039]

[0040] in, Indicates the The block in Time-lapse status The previous state corresponding to the minimum path;

[0041] The optimal state vector generated at each beat The output is sent to the parallel surviving path update module to complete the dynamic optimization of the state path.

[0042] Optionally, the specific process of completing the survivor path update by the parallel survivor path update module based on the parallel ACS result is:

[0043] initialization Survivor path storage matrix of parallel blocks is an all-zero matrix;

[0044] At each decoding , according to the optimal state vector output by the parallel ACS module , will The surviving path storage matrix of each block is updated according to the following formula (8):

[0045]

[0046] Among them, the new state of each row Insert to the beginning of the current path, and the remaining path elements shift backward;

[0047] When decoding When , output the updated survivor path matrix To the backtracking decoding module, it is used for the final state selection and decoding output of the backtracking path.

[0048] Optionally, the specific process of outputting the convolution decoding result by looking up a table according to the survivor path through the backtracking decoding module is:

[0049] initialization The decoding output buffer of the parallel block is ;

[0050] According to the parallel ACS module, The cumulative state measurement , determine the current state of each block , as shown in the following formula (9):

[0051]

[0052] From the survivor path matrix Backtracking time by time to get the previous state , and update the current state to , while decreasing the time ;

[0053] According to the state transfer Query the local decoding table and output the corresponding four-bit decoding result , until the backtracking is completed ;

[0054] The decoding results of each block are cut off according to the effective length of the redundant part to generate Parallel effective decoding output ;in, is the effective block length; is the bit rate.

[0055] Based on the same inventive concept, the present invention further provides a high-speed parallel Viterbi decoding system for implementing the high-speed parallel Viterbi decoding method, comprising:

[0056] The block buffer module is configured to buffer the parallel soft decision outputs of baseband demodulation through the ping-pong buffer unit to generate Parallel block data;

[0057] The puncture code pattern detection module is configured to detect Bitrate adjustment The puncturing position of the parallel block data is determined, and the optimal puncturing pattern is selected through bit error comparison;

[0058] Parallel BM calculation module, configured to calculate the state transition codeword output matrix The branch metric value of the parallel block data is used to generate parallel BM data;

[0059] A parallel ACS module is configured to perform addition, comparison, and selection operations on the parallel BM data to generate a state accumulation metric and a preferred state vector;

[0060] a parallel survivor path update module configured to dynamically update the survivor path storage matrix according to the preferred state vector and output the path matrix when the decoding time beat ends;

[0061] The backtracking decoding module is configured to backtrack time by time based on the survivor path matrix and the local decoding table, and output The effective decoding result after parallel truncation of redundancy;

[0062] Wherein, the system further includes:

[0063] The serial-to-parallel conversion unit is integrated into the block cache module and is used to convert cache data into Parallel block data;

[0064] The error comparison unit is integrated into the punctured code pattern detection module and is used to perform error statistics on the re-encoding result and the original input data;

[0065] The local decoding table storage unit is integrated into the backtracking decoding module and stores the four-bit decoding output corresponding to the state transition.

[0066] Based on the same inventive concept, the present invention also provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the above-mentioned high-speed parallel Viterbi decoding method.

[0067] Based on the same inventive concept, the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the high-speed parallel Viterbi decoding method described above is implemented.

[0068] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0069] The parallel soft decision output of baseband demodulation is cached by the ping-pong cache unit to generate multi-channel parallel block data, and the data is processed by parallel processing modules such as the parallel BM calculation module and the parallel ACS module, which significantly improves the parallelism of decoding and thus greatly improves the decoding throughput. It can better adapt to ultra-high-speed data transmission scenarios and meet the strict real-time requirements of high-speed data transmission systems.

[0070] Compared with the fully parallel Viterbi decoding scheme that uses GPU to achieve high parallelism but with a sharp increase in hardware cost and low energy efficiency, the present invention implements parallel decoding based on hardware platforms such as FPGA. While ensuring high throughput, it effectively controls hardware cost and resource overhead, thereby improving the energy efficiency of the system.

[0071] A puncture code pattern detection module is set up to adjust the puncture position of parallel block data, realizing dynamic detection of puncture code patterns and flexible adjustment of puncture positions, thereby supporting multi-rate adaptive decoding, adapting to different channel characteristics and rate switching requirements under highly dynamic and beyond-horizon fading channels, and enhancing the applicability of the decoding method in complex channel environments.

[0072] A parallel survivor path update module is used to complete the survivor path update, avoiding the throughput limitation of traditional serial processing and further improving the decoding efficiency. At the same time, the backtracking decoding module outputs the convolution decoding result according to the survivor path lookup table, ensuring the decoding accuracy and taking into account the decoding performance while achieving high throughput.

[0073] By rationally designing the decoding process and modules, the synchronization problem between the decoding clock and the system clock is effectively solved, ensuring the coordination between the decoding process and the overall operation of the system, and improving the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 11 is a flow chart of a high-speed parallel Viterbi decoding method according to an embodiment of the present invention;

[0075] Figure 2 Schematic diagram of the structure of a high-speed parallel Viterbi decoding system according to an embodiment of the present invention;

[0076] Figure 3 Schematic diagram of the working process of a high-speed parallel Viterbi decoding system according to an embodiment of the present invention;

[0077] Figure 4 A schematic diagram of a block cache process according to an embodiment of the present invention;

[0078] Figure 5 Schematic diagram of the puncture code pattern detection process according to an embodiment of the present invention;

[0079] Figure 6 Schematic diagram of the parallel BM calculation process according to an embodiment of the present invention;

[0080] Figure 7 A schematic diagram of a parallel ACS process according to an embodiment of the present invention;

[0081] Figure 8 A schematic diagram of a parallel survivor path update process according to an embodiment of the present invention;

[0082] Figure 9 Schematic diagram of the backtracking decoding output process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0083] The following is a specific implementation method with reference to the accompanying drawings.

[0084] Reference Figure 1 、 Figure 3 , a high-speed parallel Viterbi decoding method, comprising the following steps:

[0085] Step 1: Buffer the parallel soft decision output of baseband demodulation through the ping-pong buffer unit to generate parallel block data; wherein, the It is determined by the logic delay value of the parallel ACS (Add-Compare-Select) module and the maximum possible number of supplementary puncture positions.

[0086] In some embodiments, reference Figure 4 , the parallel soft decision output of baseband demodulation is cached by the ping-pong buffer unit to generate The specific process of parallel block data is as follows:

[0087] The parallel soft symbol data output by baseband demodulation is recorded as , The baseband demodulation output soft decision symbols, Indicates the starting position of the current soft symbol sequence, and outputs the buffered data through the ping-pong buffer unit , the cached data The expression of is shown in the following formula (1):

[0088]

[0089] in, Indicates the cache length; represents the useful decoding input length, and An integer multiple of 8; represents the backtracking depth, and It is an integer multiple of 8 and is determined by engineering experience;

[0090] According to the cache data output by the ping-pong cache unit , using the serial-to-parallel conversion unit to cache data Convert to Parallel block data , No. The road data is expressed as follows (2):

[0091]

[0092] in, Indicates the effective block length, and satisfy , the specific value is determined by engineering experience; Indicates the parallel number, which is determined by the logical delay value of the parallel ACS module and the maximum number of possible puncturing positions.

[0093] Step 2: Adjust the code through the puncture code detection module The location of the supplementary punching of parallel block data.

[0094] In some embodiments, reference Figure 5 , adjusted by the puncture code pattern detection module The specific process of filling the puncture position of the parallel block data is as follows:

[0095] According to the preset Bit rate Different supplementary puncture positions are configured for the road block data; among them, is the number of preset candidate puncture patterns that meet , which can be obtained according to the existing technology;

[0096] Regarding the The block data after the road patching and punching is parallelly executed with branch metric calculation, addition and comparison operation and survivor path update to generate Road decoding result;

[0097] The The decoding results are re-encoded and compared with the original input data for bit errors, and the puncturing pattern with the least bit errors is selected;

[0098] Adjust according to the selected punching mode The location of the puncture for the parallel block data; Road filling punching mode and The mapping relationship between parallel blocks is determined by the actual bit rate requirement.

[0099] Step 3: Generate through parallel BM (BranchMetric, abbreviation of branch metric) calculation module Parallel BM data corresponding to the parallel block data.

[0100] In some embodiments, reference Figure 6 , generated by parallel BM calculation modules The specific process of parallel BM data corresponding to parallel block data is as follows:

[0101] For the Parallel block data , at each decoding Input branch metric calculation unit (such as Figure 3 BMU1, BMU2, ..., BMU N ) soft symbol sequence , The expression of is shown in the following formula (3):

[0102]

[0103] Output matrix according to the locally stored state transition codeword , calculate the branch metric value of the current time step , No. The expression of the branch metric value is shown in the following formula (4):

[0104]

[0105] in, Indicates the In the parallel block, The branch metric value of each branch; Indicates the first Line code word; Indicates Euclidean distance calculation; Indicates the branch index in each state; The index representing the current state; Indicates the constraint length of convolutional coding;

[0106] Arrange the branch metrics in the order of state transition to generate Parallel BM data .

[0107] Step 4: Perform addition, comparison and selection operations on the parallel BM data through the parallel ACS module to obtain the parallel ACS result.

[0108] In some embodiments, reference Figure 7 The specific process of performing addition, comparison and selection operations on the parallel BM data through the parallel ACS module to obtain the parallel ACS result is as follows:

[0109] When decoding When the state of each parallel block is cumulatively measured Perform initialization operations (via Figure 3 ACS1, ACS2, ..., ACS N Perform initialization operation), all state cumulative metric values are set to 0;

[0110] When decoding, the beat is satisfied When the branch metric Accumulate the state cumulative metrics (via Figure 3 ACS1, ACS2, ..., ACS N Perform the accumulation operation), as shown in the following formula (5):

[0111]

[0112] When decoding When, for each state Select the path corresponding to the minimum cumulative metric, update the state cumulative metric and the optimal state vector , as shown in the following formula (6):

[0113]

[0114] in, Indicates the The block in Time-lapse status The previous state corresponding to the minimum path; Indicates the corresponding cumulative measurement value of the previous state;

[0115] The optimal state vector generated at each beat The output is sent to the parallel surviving path update module to complete the dynamic optimization of the state path.

[0116] Step 5: Based on the parallel ACS results, the survivor path update is completed through the parallel survivor path update module.

[0117] In some embodiments, reference Figure 8 Based on the parallel ACS results, the specific process of completing the survivor path update through the parallel survivor path update module is as follows:

[0118] The surviving path storage matrix is shown in the following formula (7):

[0119]

[0120] initialization Survivor path storage matrix of parallel blocks is an all-zero matrix, that is, when the decoding of the surviving path update module is hour, is an all-zero matrix;

[0121] At each decoding , according to the optimal state vector output by the parallel ACS module , will The surviving path storage matrix of each block is updated according to the following formula (8):

[0122]

[0123] Among them, the new state of each row Insert to the beginning of the current path, and the remaining path elements shift backward;

[0124] When decoding When , output the updated survivor path matrix To the backtracking decoding module, it is used for the final state selection and decoding output of the backtracking path.

[0125] Step 6: Output the convolution decoding result by looking up the table based on the surviving path through the backtracking decoding module.

[0126] In some embodiments, reference Figure 9 The specific process of outputting the convolution decoding result through the backtracking decoding module according to the surviving path table lookup is as follows:

[0127] initialization The decoding output buffer of the parallel block is ;

[0128] According to the parallel ACS module, The cumulative state measurement , determine the current state of each block , as shown in the following formula (9):

[0129]

[0130] From the survivor path matrix Backtracking time by time to get the previous state , and update the current state to , while decreasing the time ;

[0131] According to the state transfer Query the local decoding table and output the corresponding four-bit decoding result , until the backtracking is completed ;right Initialize and wait for the next backtracking decoding. Parallel block data , the final redundant decoding output is expressed as follows (10):

[0132]

[0133] The decoding results of each block are cut off according to the effective length of the redundant part to generate Parallel effective decoding output ;in, is the effective block length; is the bit rate.

[0134] Based on the same inventive concept, corresponding to any of the above embodiments, refer to Figure 2 The present invention provides a high-speed parallel Viterbi decoding system for implementing the aforementioned high-speed parallel Viterbi decoding method, comprising:

[0135] The block buffer module is configured to buffer the parallel soft decision outputs of baseband demodulation through the ping-pong buffer unit to generate Parallel block data;

[0136] The puncture code pattern detection module is configured to detect Bitrate adjustment The puncturing position of the parallel block data is determined, and the optimal puncturing pattern is selected through bit error comparison;

[0137] Parallel BM calculation module, configured to calculate the state transition codeword output matrix The branch metric value of the parallel block data is used to generate parallel BM data;

[0138] A parallel ACS module is configured to perform addition, comparison, and selection operations on the parallel BM data to generate a state accumulation metric and a preferred state vector;

[0139] a parallel survivor path update module configured to dynamically update the survivor path storage matrix according to the preferred state vector and output the path matrix when the decoding time beat ends;

[0140] The backtracking decoding module is configured to backtrack time by time based on the survivor path matrix and the local decoding table, and output The effective decoding result after parallel truncation of redundancy;

[0141] Wherein, the system further includes:

[0142] The serial-to-parallel conversion unit is integrated into the block cache module and is used to convert cache data into Parallel block data;

[0143] The error comparison unit is integrated into the punctured code pattern detection module and is used to perform error statistics on the re-encoding result and the original input data;

[0144] The local decoding table storage unit is integrated into the backtracking decoding module and stores the four-bit decoding output corresponding to the state transition.

[0145] Based on the same inventive concept, corresponding to any of the above embodiments, the present invention provides an electronic device, including a memory and a processor, the memory being used to store a computer program, and the processor running the computer program to enable the electronic device to execute the high-speed parallel Viterbi decoding method of the embodiment.

[0146] Optionally, the above-mentioned electronic device may be a server.

[0147] In addition, this embodiment further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the high-speed parallel Viterbi decoding method of the embodiment is implemented.

[0148] It is understood that the processor in the embodiments of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0149] The method steps in the embodiments of the present invention can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0150] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted via a storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A high-speed parallel Viterbi decoding method, characterized in that: The following steps are involved: The parallel soft decision output of baseband demodulation is cached by the ping-pong buffer unit to generate Parallel block data; The parallel soft decision output of baseband demodulation is cached by the ping-pong cache unit to generate The specific process of parallel block data is as follows: The parallel soft symbol data output by baseband demodulation is recorded as , output cache data through the ping-pong cache unit , the cached data The expression of is shown in the following formula (1): in, Indicates the cache length; represents the useful decoding input length, and An integer multiple of 8; represents the backtracking depth, and An integer multiple of 8; According to the cache data output by the ping-pong cache unit , using the serial-to-parallel conversion unit to cache data Convert to Parallel block data , No. The road data is expressed as follows (2): in, Indicates the effective block length, and satisfy ; Indicates the number of parallel operations; Adjustment through the puncture code pattern detection module The location of the supplementary punching of parallel block data; Generated by parallel BM calculation module Parallel BM data corresponding to the parallel block data; The parallel ACS module performs addition, comparison and selection operations on the parallel BM data to obtain the parallel ACS result; Based on the parallel ACS results, the survivor path update is completed through the parallel survivor path update module; Output the convolution decoding result according to the surviving path lookup table through the backtracking decoding module; Among them, the It is determined by the logic delay value of the parallel ACS module and the maximum possible number of supplementary puncture positions.

2. The high-speed parallel Viterbi decoding method according to claim 1, wherein: The puncture code pattern detection module adjusts The specific process of filling the puncture position of the parallel block data is as follows: According to the preset Bit rate Different supplementary puncture positions are configured for the road block data; among them, is the number of preset candidate puncture patterns that meet ; Regarding the The block data after the road patching and punching is parallelized to perform branch metric calculation, addition and comparison operation and survivor path update to generate Road decoding result; The The decoding results are re-encoded and compared with the original input data for bit errors, and the puncturing pattern with the least bit errors is selected; Adjust according to the selected punching mode The location of the puncture for the parallel block data; Road filling punching mode and The mapping relationship between parallel blocks is determined by the actual bit rate requirement.

3. The high-speed parallel Viterbi decoding method according to claim 1, wherein: The parallel BM calculation module generates The specific process of parallel BM data corresponding to parallel block data is as follows: For the Parallel block data , at each decoding Soft symbol sequence input to the branch metric calculation unit , The expression of is shown in the following formula (3): Output matrix according to the locally stored state transition codeword , calculate the branch metric value of the current time step , No. The expression of the branch metric value is shown in the following formula (4): in, Indicates Euclidean distance calculation; Indicates the constraint length of convolutional coding; Arrange the branch metrics in the order of state transition to generate Parallel BM data .

4. The high-speed parallel Viterbi decoding method according to claim 3, wherein: The specific process of performing addition, comparison and selection operations on the parallel BM data through the parallel ACS module to obtain the parallel ACS result is as follows: When decoding When the state of each parallel block is cumulatively measured Perform initialization operations and set all state cumulative metrics to 0; When decoding, the beat is satisfied When the branch metric The state cumulative metrics are accumulated as shown in the following formula (5): When decoding When, for each state Select the path corresponding to the minimum cumulative metric, update the state cumulative metric and the optimal state vector , as shown in the following formula (6): in, Indicates the The block in Time-lapse status The previous state corresponding to the minimum path; The optimal state vector generated at each beat The output is sent to the parallel surviving path update module to complete the dynamic optimization of the state path.

5. The high-speed parallel Viterbi decoding method according to claim 4, wherein: The specific process of completing the survivor path update by the parallel survivor path update module based on the parallel ACS result is as follows: initialization Survivor path storage matrix of parallel blocks is an all-zero matrix; At each decoding , according to the optimal state vector output by the parallel ACS module , will The surviving path storage matrix of each block is updated according to the following formula (7): Among them, the new state of each row Insert to the beginning of the current path, and the remaining path elements shift backward; When decoding When , output the updated survivor path matrix To the backtracking decoding module, it is used for the final state selection and decoding output of the backtracking path.

6. The high-speed parallel Viterbi decoding method according to claim 5, wherein: The specific process of outputting the convolution decoding result by looking up the table based on the survivor path through the backtracking decoding module is as follows: initialization The decoding output buffer of the parallel block is ; According to the parallel ACS module, The cumulative state measurement , determine the current state of each block , as shown in the following formula (8): From the survivor path matrix Backtracking time by time to get the previous state , and update the current state to , while decreasing the time ; According to the state transfer Query the local decoding table and output the corresponding four-bit decoding result , until the backtracking is completed ; The decoding results of each block are cut off according to the effective length of the redundant part to generate Parallel effective decoding output ;in, is the effective block length; is the bit rate.

7. A high-speed parallel Viterbi decoding system, configured to implement the high-speed parallel Viterbi decoding method according to any one of claims 1 to 6, characterized in that: include: The block buffer module is configured to buffer the parallel soft decision outputs of baseband demodulation through the ping-pong buffer unit to generate Parallel block data; The puncture code pattern detection module is configured to detect Bitrate adjustment The puncturing position of the parallel block data is determined, and the optimal puncturing pattern is selected through bit error comparison; Parallel BM calculation module, configured to calculate the state transition codeword output matrix The branch metric value of the parallel block data is used to generate parallel BM data; A parallel ACS module is configured to perform addition, comparison, and selection operations on the parallel BM data to generate a state accumulation metric and a preferred state vector; a parallel survivor path update module configured to dynamically update the survivor path storage matrix according to the preferred state vector and output the path matrix when the decoding time beat ends; The backtracking decoding module is configured to backtrack time by time based on the survivor path matrix and the local decoding table, and output The effective decoding result after parallel truncation of redundancy; Wherein, the system further includes: The serial-to-parallel conversion unit is integrated into the block cache module and is used to convert cache data into Parallel block data; The error comparison unit is integrated into the punctured code pattern detection module and is used to perform error statistics on the re-encoding result and the original input data; The local decoding table storage unit is integrated into the backtracking decoding module and stores the four-bit decoding output corresponding to the state transition.

8. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the high-speed parallel Viterbi decoding method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the high-speed parallel Viterbi decoding method according to any one of claims 1 to 6 is implemented.

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