AXI interconnection device, system, method, electronic device, storage medium and product

Abstract

The embodiments of the present invention disclose an AXI interconnection device, system, method, electronic device, storage medium, and product, belonging to the field of computer technology. The device includes: a first AXI slave device, configured to receive first AXI channel information from a first AXI master device; a framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; a control module, configured to send the first frame to a sending module and store the first frame in a storage module; a sending module, configured to send the first frame to a receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into first AXI channel information based on the frame structure; the control module is further configured to, when the receiving end detects an error in the first frame, retrieve the first frame from the storage module and send the first frame retrieved from the storage module to the sending module to resend the first frame. The retransmission mechanism improves data accuracy and communication accuracy and precision.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly to an Advanced Extensible Interface (AXI) interconnection device, system, method, electronic device, storage medium, and product. Background Art

[0002] AXI is a high-performance bus protocol for internal module communication within systems on chips (SoCs) and field-programmable gate arrays (FPGAs), offering high bandwidth and low latency. The AXI protocol divides read and write operations into multiple independent channels: read address (AR), write address (AW), write data (W), read data (R), and write response (B). This allows simultaneous read and write operations, maximizing interface bandwidth.

[0003] In the current AXI protocol, data transmission errors can occur, and improving data accuracy in AXI interconnects is a key focus in the industry. Furthermore, AXI masters and slaves are directly connected. AXI is a parallel interface bus consisting of multiple (typically five, for example) independent channels. Consequently, the interface between AXI masters and slaves has numerous signals and pins, resulting in a large footprint for chip implementation. Summary of the Invention

[0004] The present invention provides an AXI interconnection device, system, method, electronic device, storage medium and product, which help to improve data accuracy.

[0005] The technical solutions of the embodiments of the present invention are as follows:

[0006] An AXI interconnection device is connected between a first AXI master device and a receiving end, the AXI interconnection device comprising:

[0007] a first AXI slave device, configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device;

[0008] a framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure;

[0009] The device further includes a control module, a sending module and a storage module, wherein:

[0010] The control module is configured to send the first frame to the sending module and store the first frame in the storage module;

[0011] The sending module is configured to send the first frame to the receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure;

[0012] The control module is further configured to obtain the first frame from the storage module and send the first frame obtained from the storage module to the sending module when the receiving end detects that the first frame is erroneous, so that the sending module resends the first frame obtained from the storage module to the receiving end.

[0013] In one embodiment, the control module is configured to schedule the first frame based on a predetermined scheduling method before sending the first frame to the sending module, wherein the scheduling method includes at least one of the following:

[0014] First-come-first-served scheduling method; priority scheduling method; shortest job first scheduling method; time slice round-robin scheduling method; high response ratio priority scheduling method; fair scheduling method; hybrid scheduling method based on priority and time slice.

[0015] In one embodiment, the control module is configured to, upon receiving a negative acknowledgement (NACK) signal including a sequence number of the first frame from the receiving end, determine that the receiving end has detected an error in the first frame, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device.

[0016] In one embodiment, it includes:

[0017] The alarm module is configured to issue an alarm message when the control module does not receive an acknowledgment (ACK) signal or the NACK signal from the receiving end within a predetermined time threshold, or when the number of retransmissions of the first frame exceeds a predetermined number threshold.

[0018] In one embodiment, the control module is configured to send all frames stored in the storage module starting from the sequence number to the sending module when receiving the NACK signal from the receiving end, so that the sending module sends all the frames to the receiving end.

[0019] In one embodiment, the control module is configured to control the first AXI slave device to resume receiving AXI channel information from the first AXI master device when the sending module completes sending all the frames to the receiving end and no NACK signal containing at least one sequence number in all the frames is received from the receiving end.

[0020] In one embodiment, the control module is used to wait for a first predetermined time when receiving the NACK signal from the receiving end, and send all frames stored in the storage module with the sequence number as the starting point to the sending module, wherein the receiving end turns off the data receiving function when sending the NACK signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

[0021] In one embodiment, the system includes a receiving module and a de-framing module, wherein:

[0022] The receiving module is configured to receive a second frame from a transmitting end, where the second frame is generated by the transmitting end based on the second AXI channel information framed by the frame structure; when an error is detected in the second frame, not send the second frame to the deframing module, generate a NACK signal including a sequence number of the second frame, and send the NACK signal to the transmitting end so that the transmitting end resends the second frame based on the NACK signal; and when the second frame is detected to be correct, send the second frame to the deframing module;

[0023] The deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure.

[0024] An AXI interconnection system includes a first chip and a second chip;

[0025] The first chip includes a first AXI master device, a first AXI slave device, a first framing module, a first control module, a first storage module and a first sending module;

[0026] The second chip includes a first receiving module, a first deframing module, a second AXI master device and a second AXI slave device;

[0027] The first AXI slave device is configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; the first framing module is configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; the first control module is configured to send the first frame to the first sending module and store the first frame in the first storage module; and the first sending module is configured to send the first frame.

[0028] The first receiving module is configured to receive the first frame, and when detecting that the first frame is erroneous, send a first NACK signal including a sequence number of the first frame to the first control module; and when detecting that the first frame is correct, send the first frame to the first deframing module; the first deframing module is configured to deframe the first frame into first AXI channel information based on the frame structure, and send the first AXI channel information to the second AXI master device; the second AXI master device is configured to send the first AXI channel information to the second AXI slave device based on a handshake mechanism with the second AXI slave device;

[0029] The first control module is further configured to, upon receiving the first NACK signal, obtain the first frame from the first storage module and send the first frame obtained from the first storage module to the first sending module, so that the first sending module resends the first frame obtained from the first storage module.

[0030] In one embodiment, the second chip includes a third AXI master device, a third AXI slave device, a second framing module, a second control module, a second storage module, and a second sending module;

[0031] The first chip includes a second receiving module, a second deframing module, a fourth AXI master device and a fourth AXI slave device;

[0032] wherein the third AXI slave device is configured to receive second AXI channel information from the third AXI master device based on a handshake mechanism with the third AXI master device; the second framing module is configured to frame the second AXI channel information into a second frame based on the frame structure; the second control module is configured to send the second frame to the second sending module and store the second frame in the second storage module; and the second sending module is configured to send the second frame;

[0033] The second receiving module is configured to receive the second frame, and when detecting that the second frame is erroneous, send a second NACK signal including a sequence number of the second frame to the second control module; and when detecting that the second frame is correct, send the second frame to the second deframing module; the second deframing module is configured to deframe the second frame into second AXI channel information based on the frame structure, and send the second AXI channel information to the fourth AXI master device; the fourth AXI master device is configured to send the second AXI channel information to the fourth AXI slave device based on a handshake mechanism with the fourth AXI slave device;

[0034] The second control module is further configured to, upon receiving the second NACK signal, obtain the second frame from the second storage module and send the second frame obtained from the second storage module to the second sending module, so that the second sending module resends the second frame obtained from the second storage module.

[0035] An AXI interconnection method, comprising:

[0036] receiving first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device;

[0037] Framing the first AXI channel information into a first frame based on a predetermined frame structure;

[0038] The first frame is sent to a receiving end and stored in a storage module, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; when the receiving end detects that the first frame is erroneous, the first frame is obtained from the storage module and the first frame obtained from the storage module is resent to the receiving end.

[0039] In one embodiment, it includes:

[0040] When a NACK signal including the sequence number of the first frame is received from the receiving end, it is determined that the receiving end detects an error in the first frame and stops receiving AXI channel information from the first AXI master device.

[0041] In one embodiment, it includes:

[0042] When the NACK signal is received from the receiving end, wait for a first predetermined time and send all frames stored in the storage module with the sequence number as the starting point to the receiving end, wherein the receiving end turns off the data receiving function when sending the NACK signal and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

[0043] An electronic device, comprising:

[0044] Memory;

[0045] processor;

[0046] The memory stores an application program executable by the processor, which is used to enable the processor to execute any of the above-mentioned AXI interconnection methods.

[0047] A computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, cause the processor to perform any of the above-described AXI interconnection methods.

[0048] A program product includes a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned AXI interconnection methods.

[0049] As can be seen from the above technical solution, in an embodiment of the present invention, a first AXI slave device is configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; a framing module is configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; a control module is configured to send the first frame to a transmitting module and store the first frame in a storage module; the transmitting module is configured to send the first frame to a receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; the control module is further configured to, when the receiving end detects an error in the first frame, retrieve the first frame from the storage module and send the first frame retrieved from the storage module to the transmitting module, so that the transmitting module retransmits the first frame retrieved from the storage module to the receiving end. It can be seen that in this embodiment of the present invention, a backup is performed for each transmitted data frame, and erroneous data frames are retransmitted, thereby implementing a retransmission mechanism in the AXI interconnect, which can improve data accuracy, thereby improving the accuracy and precision of signal communication.

[0050] In addition, the embodiments of the present invention accurately control the turning off and on of the data receiving function of the receiving end, the stopping and resuming of the first AXI slave device receiving AXI channel information from the first AXI master device, and the first predetermined time and the second predetermined time, thereby ensuring that the data received during the retransmission process of the receiving end will not be repeated or omitted, thereby improving the integrity of the data.

[0051] Moreover, the embodiments of the present invention implement information interaction with the receiving end in a framing and deframing manner, and can adjust (usually reduce) the bit width of the transmitting signal line of the first frame as needed, which is beneficial to reducing the number of signal lines and can significantly reduce the chip pin area during interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 FIG. 1 is an exemplary schematic diagram of an AXI interconnection in the related art.

[0053] Figure 2 FIG. 1 is a first exemplary schematic diagram of an AXI interconnect device according to an embodiment of the present invention.

[0054] Figure 3 FIG. 4 is an exemplary diagram of a frame structure according to an embodiment of the present invention.

[0055] Figure 4 FIG. 1 is a second exemplary schematic diagram of an AXI interconnect device according to an embodiment of the present invention.

[0056] Figure 5 Schematic diagram of an AXI interconnection system according to an embodiment of the present invention.

[0057] Figure 6 Schematic diagram of an AXI interconnection method according to an embodiment of the present invention.

[0058] Figure 7 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0060] For the sake of brevity and intuitiveness in description, the solution of the present invention is explained below by describing several representative implementations. A large number of details in the implementations are only used to help understand the solution of the present invention. However, it is obvious that the technical solution of the present invention may not be limited to these details when implemented. In order to avoid unnecessarily obscuring the solution of the present invention, some implementations are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0061] The AXI protocol divides read and write operations into multiple independent channels, including a read address (AR) channel, a write address (AW) channel, a write data (W) channel, a read data (R) channel, and a write response (B) channel, allowing read and write operations to be performed simultaneously.

[0062] Figure 1 FIG. 1 is an exemplary schematic diagram of an AXI interconnection in the related art. Figure 1In the AXI architecture, AXI masters and slaves related to the same read and write operations are directly interconnected. Multiple independent unidirectional channels exist between the AXI master and slave, each with specific functions and signaling. For example: a write address channel, used by the AXI master to send the address and related control information for a write operation to the AXI slave; a write data channel, used by the AXI master to send write data to the AXI slave; a write response channel, used by the AXI slave to send a response to a write operation to the AXI master, indicating whether the write operation was successful; a read address channel, used by the AXI master to send the address and related control information for a read operation to the AXI slave; and a read data channel, used by the AXI slave to send read data to the AXI master.

[0063] Because each channel contains many signals (for example, the write address channel can include: the write address (AWADDR); the burst length (AWLEN) signal, indicating the number of data transferred in a single write operation; the data size (AWSIZE) signal, indicating the size of each data element (e.g., 32 bits, 64 bits); the burst type (AWBURST) signal, indicating fixed, incrementing, wraparound, etc.; the valid (AWVALID) signal, indicating the validity of address and control information; and the ready (AWREADY) signal, indicating that the AXI slave is ready to receive address information). This leads to a large number of signal lines between directly connected AXI masters and slaves, resulting in a large number of pins. In particular, when the AXI master and slave are located on separate chips, the chip area must be increased to accommodate the large number of pins, reducing chip maintainability.

[0064] Moreover, data may be erroneous during signal transmission between the AXI master device and the AXI slave device, and it is difficult to guarantee data accuracy based on related technologies.

[0065] In this embodiment of the present invention, a retransmission mechanism is implemented in an AXI interconnect. Compared to related technologies, when data errors are confirmed, the erroneous data can be accurately retransmitted, thereby ensuring data accuracy and improving the accuracy and precision of signal communication. Furthermore, in scenarios where a retransmission mechanism is in place, this embodiment of the present invention ensures that data frames received by the receiving end are not duplicated or omitted, further improving data integrity.

[0066] Furthermore, in the embodiments of the present invention, information exchange between AXI master and slave devices is achieved based on framing and deframing. Compared with related technologies, this helps reduce pin requirements and is particularly beneficial for AXI interconnection between chips.

[0067] The above disclosure details the technical defects in the related art, the causes of these defects, and the analytical process for overcoming them. In reality, the understanding of these technical defects is not common knowledge in the field, but rather a novel discovery made by the inventors during their research. Furthermore, the tracing of the causes of these defects and the analytical process for overcoming them are the result of gradual analysis conducted by the inventors during their actual research and are not common knowledge in the field.

[0068] Figure 2 FIG2 is an exemplary schematic diagram of an AXI interconnect device according to an embodiment of the present invention. The AXI interconnect device is connected between a first AXI master device and a receiving end. The receiving end may include a second AXI master device, a second AXI slave device, a receiving module, and a deframing module.

[0069] The first AXI master device and the second AXI slave device are participants in the same read operation or the same write operation. For example, in a read operation, the first AXI master device reads data from the second AXI slave device; in a write operation, the first AXI master device writes data to the second AXI slave device.

[0070] The AXI interconnect device includes: a first AXI slave device, which is used to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device. A framing module, which is used to frame the first AXI channel information into a first frame based on a predetermined frame structure. The AXI interconnect device also includes a control module, a sending module and a storage module. The control module is used to send the first frame to the sending module and store the first frame in the storage module. The sending module is used to send the first frame to the receiving module in the receiving end, wherein the first frame is detected by the receiving module in the receiving end. After the receiving module successfully detects the first frame, the deframing module in the receiving end deframes the first frame into the first AXI channel information based on the frame structure. The control module is also used to obtain the first frame from the storage module when the receiving module in the receiving end detects that the first frame is erroneous, and send the first frame obtained from the storage module to the sending module, so that the sending module resends the first frame obtained from the storage module to the receiving module in the receiving end.

[0071] As can be seen, when the control module sends the first frame to the transmitting module, it stores the first frame in the storage module. A backup of the first frame is implemented in the storage module. If an error occurs in the first frame, the first frame is retrieved from the storage module, and the receiving module retransmits the first frame retrieved from the storage module. Therefore, the embodiments of the present invention implement a retransmission mechanism in AXI interconnects, reducing data transmission errors and improving data accuracy, thereby enhancing the accuracy and precision of signal communication.

[0072] In one embodiment, when the framing module frames the first AXI channel information into a first frame, it may store a check bit determined based on a predetermined check method in a predetermined position of the frame structure (e.g., a frame header, a frame trailer, or a payload). For example, the check method may include:

[0073] (1) Parity check:

[0074] In odd parity, the sum of the data bits and the check bit is an odd number. For example, consider 4 bits of data (1011), with 3 1s. To make the sum odd, the check bit should be 0 (because 3 + 0 = 3, which is an odd number). If the sum of the data and the check bit received by the receiver is not an odd number, it indicates that an error occurred during data transmission. Even parity is similar to odd parity, requiring the sum of the data bits and the check bit to be even. Again, consider 4 bits of data (1011), with 3 1s. To make the sum even, the check bit should be 1 (because 3 + 1 = 4, which is an even number). If the sum of the data and the check bit received by the receiver is not an even number, it indicates that an error occurred during data transmission.

[0075] (2) Cyclic Redundancy Check (CRC):

[0076] CRC is a checksum based on polynomial division. The sender treats the data as a polynomial and divides it by a predefined generator polynomial. The remainder is appended to the data and sent as a checksum. The receiver then divides the received data (including the checksum) by the same generator polynomial. If the remainder is 0, the data is considered correct.

[0077] (3) Longitudinal redundancy check:

[0078] In longitudinal redundancy checking, data is arranged by column and parity is checked on each column to generate a check byte. The transmitter sends the data and the check byte together. The receiver performs a column-by-column parity check on the received data and compares the parity result with the sender's check byte to determine whether the data is correct.

[0079] (4) Checksum:

[0080] In a checksum, data is divided into bytes (or bits), and a sum operation is performed on these bytes (or bits). The result is appended to the data and sent as a checksum. The receiving end performs the same sum operation on the received data and compares the result with the sender's checksum to determine whether the data is correct.

[0081] (5) Redundancy check:

[0082] Redundancy checking improves data transmission reliability by adding redundant data. For example, data can be sent multiple times, and the receiving end can determine whether the data is correct by comparing the multiple transmissions.

[0083] (6) Verification code:

[0084] A checksum is a piece of verification data generated using a specific algorithm and appended to the original data. The receiving end verifies the received data using the same algorithm to determine if it is correct. Common checksums include CRC and Hamming checksums.

[0085] (7) Interleaving check:

[0086] Interleaving and verification is a method that interleaves data and then verifies it. For example, data is interleaved according to a certain rule and then verified. The receiving end deinterleaves the received data and then verifies it to determine whether the data is correct.

[0087] At the receiving end: After receiving the first frame, the receiving module in the receiving end checks the parity bit. For example, if the parity is odd, the receiving module calculates the sum of the data bits and the parity bit to determine whether it is an odd number; if the parity is even, the receiving module determines whether the sum is even. If the check result does not meet the parity check rules (the odd parity sum is not odd, and the even parity sum is not even), the receiving module determines that an error occurred during the transmission of the first frame. Furthermore, the deframing module deframes the first frame that has been checked correctly to obtain the first AXI channel information. The first AXI channel information is transmitted to the second AXI master device, where the second AXI master device transmits the first AXI channel information to the second AXI slave device based on a handshake mechanism with the second AXI slave device.

[0088] It can be seen that after the framing processing by the framing module, the bit width of the signal line used to transmit the first frame in the sending module can be reduced to any bit position, which is beneficial to reducing the number of signal lines and significantly reducing the chip pin area during interconnection.

[0089] In one embodiment, the bit width of the signal lines of the transmitting module is smaller than the bit width of the signal lines between the first AXI slave device and the first AXI master device. For example, when the first AXI master device, the first AXI slave device, the framing module, the control module, the alarm module, the storage module, and the transmitting module are integrated into a first chip, the number of pins of the transmitting module used to transmit the first frame to the second AXI slave device outside the chip can be reduced as needed (for example, in extreme cases, even to 1 bit), thereby reducing the pin area of the first chip.

[0090] In one embodiment, the receiving module, the deframing module, the second AXI master device, and the second AXI slave device may be integrated into a second chip different from the first chip.

[0091] It can be seen that based on Figure 2 The AXI interconnection device shown enables a first AXI master device to send first AXI channel information to a second AXI slave device. Moreover, during data transmission, data accuracy is improved based on a retransmission mechanism, thereby improving the accuracy and precision of communication.

[0092] In the AXI protocol, data exchange between an AXI master and an AXI slave is achieved through a handshake mechanism based on the VALID and READY signals. This handshake mechanism ensures reliable and flexible data transmission and applies to all channels of the AXI protocol (including the read address channel, read data channel, write address channel, write data channel, and write response channel). The core of the handshake mechanism is the synchronization of data transmission using the VALID and READY signals. The VALID signal is sent by the source to indicate that data or control information is ready for reception. The READY signal is sent by the destination to indicate that the destination is ready to receive data. Data transfer occurs on the rising clock edge when both the VALID and READY signals are high. The handshake mechanism ensures that data is transferred only when both the source and destination are ready. The source can be an AXI master or an AXI slave, and the destination can also be an AXI master or an AXI slave.

[0093] The handshake mechanism in each channel is described below.

[0094] (1) Write address channel: The AXI master device pulls up the AWVALID signal to indicate that the write address and control information are valid; the AXI slave device pulls up the AWREADY signal to indicate that it can receive address information.

[0095] (2) Write data channel: The AXI master device pulls up the WVALID signal to indicate that the write data is valid; the AXI slave device pulls up the WREADY signal to indicate that it can receive data.

[0096] (3) Write response channel: AXI slave device pulls up the BVALID signal to indicate that the write response is valid; the AXI master device pulls up the BREADY signal to indicate that the response can be received.

[0097] (4) Read address channel: The AXI master device pulls up the ARVALID signal to indicate that the read address and control information are valid; the AXI slave device pulls up the ARREADY signal to indicate that it can receive address information.

[0098] (5) Read data channel: The AXI slave device pulls up the RVALID signal to indicate that the read data is valid; the AXI master device pulls up the RREADY signal to indicate that it can receive data.

[0099] exist Figure 2 In the embodiment, the first AXI slave device receives first AXI channel information from the first AXI master device based on a handshake mechanism in the AXI connection with the first AXI master device. For example, the first AXI channel information may be implemented as: write address channel information, write data channel information, and read address channel information.

[0100] For example, write address channel information may include: the AWID signal, used to distinguish write transactions; the write address (AWADDR) signal; the burst length (AWLEN) signal, indicating the number of data transferred in a write operation; the data size (AWSIZE) signal, indicating the size of each data (such as 32 bits, 64 bits); the burst type signal (AWBURST); the AWVALID signal, indicating that the address and control information are valid; the AWREADY signal, indicating that the AXI slave device is ready to receive address information, etc. Write data channel information may include: the WID signal, used to identify the write transaction corresponding to the write data; the write data (WDATA); the byte enable (WSTRB) signal, used to indicate which specific bytes are valid; the WLAST signal, used to indicate that the current data is the last data in the burst transfer; the data valid (WVALID) signal, used to indicate that the data is valid; and the ready (WREADY) signal, indicating that the AXI slave device is ready to receive data. The read address channel information may include: an ARID signal, used to distinguish read transactions; a read address (ARADDR); a burst length (ARLEN) signal; an ARSIZE signal, indicating the size of each data; a burst type signal (AWBURST); an ARVALID signal, indicating that the address and control information are valid; and an ARREADY signal, indicating that the AXI slave device is ready to receive address information.

[0101] exist Figure 2 In this example, the receiving end's data comes from two sources: the primary data path (data obtained by the control module from the framing module and sent to the transmitting module when the data is error-free) and retransmitted data from the storage module when the data is error-prone. The primary data path may contain multiple data paths (because it includes multiple unidirectional channels). When more than one data path in the primary data path needs to be sent simultaneously, embodiments of the present invention can automatically initiate arbitration to ensure signal transmission according to a pre-set scheduling method.

[0102] In one embodiment, the control module is used to schedule the first frame based on a predetermined scheduling method before sending the first frame to the sending module, wherein the scheduling method includes at least one of the following: first-come-first-served scheduling method; priority scheduling method; shortest job first scheduling method; time slice round-robin scheduling method; high response ratio priority scheduling method; fair scheduling method; and a hybrid scheduling method based on priority and time slice.

[0103] The above exemplary descriptions are typical examples of the scheduling method and the verification method. Those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the scope of protection of the embodiments of the present invention.

[0104] After receiving the first frame, the receiving module in the receiving end can generate an ACK signal or a NACK signal based on the detection results of the first frame and send the ACK signal or NACK signal to the control module. Among them, NACK is a negative feedback signal, indicating that the receiving module detected an error in the first frame; ACK signal indicates that the receiving module detected the first frame correctly.

[0105] In one embodiment, the control module is configured to, upon receiving a NACK signal including the sequence number of the first frame from the receiving end, determine that the receiving end has detected an error in the first frame, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device. For example, upon receiving the first frame, the receiving module at the receiving end checks the parity bit of the first frame. If the check result indicates that the first frame has an error, the receiving module at the receiving end sends a NACK signal including the sequence number of the first frame to the control module. Upon receiving the NACK signal, the control module controls the first AXI slave device to stop receiving AXI channel information from the first AXI master device, thereby ensuring that the first AXI slave device does not continue to receive new AXI channel information when a data error occurs.

[0106] In one embodiment, the AXI device includes an alarm module configured to issue an alarm message when the control module does not receive an ACK signal or a NACK signal from the receiving end within a predetermined time threshold, or when the number of retransmissions of the first frame exceeds a predetermined number threshold. Therefore, when the control module does not receive an ACK signal or a NACK signal from the receiving end within the predetermined time threshold, or when the number of retransmissions of the first frame exceeds the predetermined number threshold, a major fault such as a transmission link error is determined to have occurred, and an alarm message is issued.

[0107] Preferably, the storage module has a predetermined capacity to buffer multiple data frames, thereby improving the efficiency of the retransmission process. In one embodiment, the control module is used to send all frames stored in the storage module starting from the sequence number to the sending module when a NACK signal is received from the receiving end, so that the sending module sends all frames to the receiving end. For example: Assume that the sequence numbers of the data frames transmitted via the main data path are 1 to 15. Correspondingly, the sequence numbers of the data frames stored in the storage module are 1 to 15. Based on the NACK signal received from the receiving end, the control module determines that the frame with sequence number 12 is erroneous. The control module sends the data frames with sequence numbers 12 to 15 to the sending module, so that the sending module sequentially sends the data frames with sequence numbers 12 to 15 to the receiving end.

[0108] In one embodiment, the control module is configured to control the first AXI slave device to resume receiving AXI channel information from the first AXI master device when the sending module completes sending all frames to the receiving end and no NACK signal containing at least one sequence number in all frames is received from the receiving end.

[0109] For example, assume that the control module determines, based on a NACK signal received from the receiving end, that the sequence number of the first frame experiencing an error is 12. The data frames stored in the storage module are sequenced from 1 to 15. The data frames with sequence numbers 12 to 15 are sent to the transmitting module, which then sequentially transmits the data frames with sequence numbers 12 to 15 to the receiving end. Furthermore, while the transmitting module is transmitting the data frames with sequence numbers 12 to 15 to the receiving end, the control module does not receive a NACK signal from the receiving end that includes at least one of the sequence numbers 12 to 15. The control module determines that the retransmission process has successfully completed and controls the first AXI slave device to resume receiving AXI channel information from the first AXI master device. Therefore, after the retransmission process is completed, the first AXI slave device resumes receiving AXI channel information from the first AXI master device.

[0110] In one embodiment, the control module is used to wait for a first predetermined time when a NACK signal is received from the receiving end, and send all frames stored in the storage module with the sequence number as the starting point to the sending module, wherein the receiving end turns off the data receiving function when sending the NACK signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

[0111] Therefore, the receiving end can prevent duplicate data reception by immediately disabling its data reception function when sending a NACK signal. For example, assume the receiving end detects an error in frame 12 sent via the primary data path and generates a NACK signal containing sequence number 12. However, it takes time for this NACK signal to reach the control module. If the receiving end's data reception function is not promptly disabled, the receiving end may receive a frame 13 sent via the primary data path during this time. During the subsequent data retransmission process, all frames starting with sequence number 12 (assuming sequence numbers 12 to 15) in the storage module will be retransmitted. The receiving end may then receive frame 13 through the retransmission mechanism, resulting in duplicate frames of sequence number 13. In this embodiment of the present invention, the receiving end disables its data reception function when sending a NACK signal for sequence number 12. Data frames greater than the current sequence number 12 (if any) are discarded, effectively preventing potential retransmissions during subsequent data retransmissions.

[0112] Moreover, based on the ingenious design that the first predetermined time is greater than the second predetermined time, it can also be ensured that the data packets received by the receiving end are data packets during the retransmission period and will not be missed, thereby improving the integrity of the data.

[0113] For example, suppose the receiving end detects an error in frame number 12, sent via the primary data path, and generates a NACK signal containing sequence number 12. The receiving end disables data reception when sending the NACK signal and then enables it five seconds later. If, within these five seconds, the control module initiates a data retransmission process, all frames starting with sequence number 12 (assuming sequence numbers 12 through 15) in the storage module will be retransmitted. However, since the receiving end's data reception function has not yet been enabled, several frames from sequence numbers 12 through 15 cannot be sent to the receiving end, resulting in data loss. In this embodiment of the present invention, the control module executes the data retransmission process only after the five seconds have passed, thereby preventing data loss during retransmission.

[0114] In one embodiment, the timing of the first predetermined time and the second predetermined time is achieved based on statistical processing of the time period. For example, when a NACK signal is generated, the receiving end waits for P clock cycles before receiving data (i.e., before the end of P clock cycles, the receiving end discards the received data and resumes data reception after the end of P clock cycles). The control module waits for Q clock cycles before sending data to the receiving end (i.e., before the end of Q clock cycles, the control module will not transmit any data in the storage module to the receiving end), and will not receive data from the main data path until the end of Q clock cycles, and then resume data transmission, where Q is greater than P. The reasons for implementing the above processing include at least: (1) The NACK signal is a single-bit serial code value, and it takes time for the control module to parse the sequence number therein, resulting in the control module being unable to immediately detect the error alarm. (2) There is usually a line delay in the interconnection between chips, and before resuming normal data transmission, waiting time is required to improve the accuracy of data communication.

[0115] In one embodiment, an AXI interconnect device includes a receiving module and a deframing module, wherein: the receiving module is configured to receive a second frame from a transmitting end, the second frame being generated by the transmitting end by framing second AXI channel information based on a frame structure; when an error is detected in the second frame, the receiving module does not send the second frame to the deframing module, generates a NACK signal including a sequence number of the second frame, and sends the NACK signal to the transmitting end, so that the transmitting end resends the second frame based on the NACK signal; when the second frame is detected to be correct, the receiving module sends the second frame to the deframing module; and the deframing module is configured to deframe the second frame into second AXI channel information based on the frame structure. As can be seen, considering that data communication is generally bidirectional, embodiments of the present invention also provide an AXI interconnect device that supports bidirectional communication.

[0116] Figure 3 FIG. 1 is an exemplary diagram of a frame structure according to an embodiment of the present invention. Figure 3As shown, the frame structure includes a frame header field, a frame trailer field, N parity bits, and N AXI channel information fields (preferably, N is an expandable positive integer). The frame header field carries the type of AXI channel information. For example, different information encodings can be used to indicate that the current frame structure is a specific channel type among multiple AXI channels (e.g., a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel). The N AXI channel information fields correspond to N types of AXI channel information for each of the N channels. Each AXI channel information field can carry a signal from the corresponding AXI channel information. The N parity bits correspond one-to-one with the N AXI channel information fields and are used to store the check results of the corresponding AXI channel information fields (e.g., the check results can be implemented as parity check results or CRC check results, etc.). Generally, if at least one parity bit fails the test, the frame is considered to be erroneous. During framing, the AXI channel information is arranged according to a preset frame structure. During deframing, the relevant AXI channel information can be successfully parsed based on this frame structure.

[0117] The first AXI channel information may include write address channel information, write data channel information and read address channel information. Figure 3 The frame structure shown can carry the first AXI channel information in the first frame. Figure 3 The channel types supported by the frame structure shown may also include a write response channel and a read data channel. Therefore, based on the frame structure, the first AXI slave device may return write response channel information and read data channel information to the first AXI master device.

[0118] based on Figure 3 In the frame structure shown, the receiver can calculate the check bits of each AXI channel information field and compare the calculated check bits with the check bits in the frame. If at least one check bit does not compare successfully, the frame can be considered to be in error.

[0119] The above exemplary descriptions are typical examples of frame structures. Those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the scope of protection of the embodiments of the present invention.

[0120] exist Figure 2 In the invention, an AXI interconnect device for transmitting first AXI channel information from a first AXI master device to a second AXI slave device is described. Considering that data communication is usually bidirectional, an embodiment of the present invention further proposes an AXI interconnect device that supports bidirectional communication.

[0121] Figure 4 FIG. 1 is a second exemplary schematic diagram of an AXI interconnect device according to an embodiment of the present invention. Figure 4The AXI interconnect device shown can enable a first AXI master device connected to the AXI interconnect device to send first AXI channel information to an AXI slave device outside the AXI interconnect device. Figure 4 The AXI interconnect device shown can also enable an AXI master device outside the AXI interconnect device to send second AXI channel information to a fourth AXI slave device connected to the AXI interconnect device.

[0122] The AXI interconnection device includes a first AXI slave device, a framing module, a control module, an alarm module, a storage module, a sending module, a receiving module, a deframing module and a fourth AXI master device.

[0123] according to Figure 4 As shown in the sending direction: the first AXI slave device in the AXI interconnect device receives the first AXI channel information from the first AXI master device based on the handshake mechanism with the first AXI master device. The framing module frames the first AXI channel information into a first frame based on a predetermined frame structure. The control module sends the first frame to the sending module and stores the first frame in the storage module. The sending module sends the first frame to the receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure. When the receiving end detects that the first frame is erroneous, the control module receives a first NACK signal containing the sequence number of the first frame from the receiving end. The control module obtains the first frame from the storage module and sends the first frame obtained from the storage module to the sending module, so that the sending module resends the first frame obtained from the storage module to the receiving end.

[0124] In the receiving end outside the AXI interconnect device, the first frame is received and deframed into first AXI channel information based on the frame structure. The deframed first AXI channel information can be sent to the second AXI master device in the receiving end ( Figure 4 not shown), wherein the second AXI master device is based on the second AXI slave device ( Figure 4 The handshake mechanism (not shown) is used to send the first AXI channel information to the second AXI slave device, thereby completing the communication process from the first AXI master device to the second AXI slave device.

[0125] according to Figure 4 In the receiving direction, the receiving module receives a second frame from outside the AXI interconnect device, wherein the second frame is framed by a third AXI master device ( Figure 4The fourth AXI master device generates the second AXI channel information based on the second AXI channel information sent by the third AXI master device (not shown). The deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure. The fourth AXI master device transmits the second AXI channel information to the fourth AXI slave device based on a handshake mechanism with the fourth AXI slave device, thereby completing the communication process from the third AXI master device to the fourth AXI slave device.

[0126] The embodiment of the present invention further provides an AXI interconnection system, which is suitable for implementing a bidirectional communication process between AXI master and slave devices between chips.

[0127] Figure 5 Schematic diagram of an AXI interconnection system according to an embodiment of the present invention. Figure 5 As shown, the AXI interconnect system includes a first chip and a second chip. The first chip includes a first AXI master device, a first AXI slave device, a first framing module, a first control module, a first storage module, a first alarm module, and a first sending module. The second chip includes a first receiving module, a first deframing module, a second AXI master device, and a second AXI slave device. The second chip also includes a third AXI master device, a third AXI slave device, a second framing module, a second control module, a second storage module, a second alarm module, and a second sending module. The first chip also includes a second receiving module, a second deframing module, a fourth AXI master device, and a fourth AXI slave device.

[0128] Respective parity check units are provided in the first transmitting module, the second transmitting module, the first receiving module, and the second receiving module, respectively. Odd or even check operations can be selected through software configuration to improve circuit flexibility. While transmitting data, the first transmitting module and the second transmitting module perform a parity check on each data packet in the frame structure based on the parity check unit, and fill the check result in the frame tail area of each data packet. The more data packets a frame structure contains, the more accurate the check result. Storing the check result at the end of the packet instead of requiring a separate interconnect signal line can reduce the number of signal lines during interconnection. The AXI signal lines can be arranged so that the idle fields are used to store check bits, which can further improve data transmission efficiency. While receiving data, the first receiving module and the second receiving module perform a parity check on each data packet in the frame structure based on the parity check unit, and compare the check result with the check result in the frame structure to determine whether the data frame is erroneous.

[0129] (1): The first AXI master device in the first chip can actively initiate a communication process to the second AXI slave device in the second chip.

[0130] For example, the first AXI slave device receives first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device. The following description takes the first AXI channel information as write address channel information as an example.

[0131] The first framing module frames the write address channel information into a first frame based on a predetermined frame structure. The first control module transmits the first frame to the first transmitting module, and stores the first frame in the first storage module. The first transmitting module transmits the first frame using a signal line, wherein the bit width of the signal line of the first transmitting module is smaller than the bit width of the signal line between the first AXI slave device and the first AXI master device.

[0132] The first receiving module receives the first frame and determines whether the first frame is erroneous.

[0133] (1) When there is no error in the first frame, the first receiving module generates an ACK signal containing the sequence number of the first frame and sends the ACK signal to the first control module; the first deframing module deframes the first frame into write address channel information based on the same frame structure and sends the write address channel information to the second AXI master device; the second AXI master device sends the write address channel information to the second AXI slave device based on the handshake mechanism with the second AXI slave device.

[0134] (2) When the first frame is erroneous, the first receiving module generates a first NACK signal including the sequence number of the first frame, sends the first NACK signal to the first control module, and turns off the data receiving function. When the second predetermined time expires, the first receiving module turns on the data receiving function again.

[0135] When the first control module receives the first NACK signal, it waits for a first predetermined time, and then sends all frames stored in the first storage module starting from the sequence number of the first frame to the first sending module, so that the first sending module sends all frames stored in the first storage module starting from the sequence number of the first frame to the receiving end, wherein the first predetermined time is greater than the second predetermined time.

[0136] When the first control module does not receive any ACK signal or any NACK signal within a predetermined time threshold or the number of retransmissions of a certain frame exceeds a predetermined number threshold, the first alarm module issues an alarm message.

[0137] Based on a similar framing and deframing method, the first AXI master device may also actively send write data associated with the write address channel information to the second AXI slave device.

[0138] The second AXI slave device transmits a data write response message to the second AXI master device based on a handshake mechanism with the second AXI master device. The second AXI master device transmits the response message to the second framing module. The second framing module frames the response message into frames based on the same frame structure. The second control module transmits the framed response message to the second transmitting module and stores the framed response message in the second storage module.

[0139] The second sending module sends the frame formed by the response message. The second receiving module receives the frame formed by the response message and determines whether the frame formed by the response message is erroneous.

[0140] (1) When there is no error in the frame formed by framing the response message, the second receiving module generates an ACK signal including the sequence number of the frame formed by framing the response message, and sends the ACK signal to the second control module; the second deframing module deframes the frame formed by framing the response message into response information based on the same frame structure, and sends the response information to the first AXI slave device; the first AXI slave device sends the response message to the first AXI master device based on the handshake mechanism with the first AXI master device.

[0141] (2) When an error occurs in the frame formed by framing the response message, the second receiving module generates a second NACK signal including the sequence number of the frame formed by framing the response message, sends the second NACK signal to the second control module, and turns off the data receiving function. When the second predetermined time expires, the second receiving module turns on the data receiving function again.

[0142] After receiving the second NACK signal, the second control module waits for a first predetermined time, and then sends all frames stored in the second storage module starting from the sequence number of the frame framed by the response message to the second sending module, so that the second sending module sends all the frames to the receiving end, wherein the first predetermined time is greater than the second predetermined time.

[0143] (2): The third AXI master device in the second chip can actively initiate a communication process to the fourth AXI slave device in the first chip.

[0144] For example, the third AXI master device sends the second AXI channel information to the third AXI slave device based on the handshake mechanism with the third AXI master device. The following description takes the second AXI channel information as read address channel information as an example.

[0145] The second framing module frames the read address channel information into a second frame based on a predetermined frame structure. The second control module transmits the second frame to the second transmitting module, and stores the second frame in the second storage module. The second transmitting module transmits the second frame using a signal line, wherein the bit width of the signal line of the second transmitting module is smaller than the bit width of the signal line between the third AXI slave device and the third AXI master device.

[0146] The second receiving module receives the second frame and determines whether the second frame is erroneous.

[0147] (1) When there is no error in the second frame, the second receiving module generates an ACK signal including the sequence number of the second frame and sends the ACK signal to the second control module; the second deframing module deframes the second frame into read address channel information based on the same frame structure and sends the read address channel information to the fourth AXI master device; the fourth AXI master device sends the read address channel information to the fourth AXI slave device based on the handshake mechanism with the fourth AXI slave device.

[0148] (2) When the second frame is erroneous, the second receiving module generates a second NACK signal including the sequence number of the second frame, sends the second NACK signal to the second control module, and turns off the data receiving function. When the second predetermined time expires, the second receiving module turns on the data receiving function again.

[0149] After receiving the second NACK signal, the second control module waits for a first predetermined time, and then sends all frames stored in the second storage module starting from the sequence number of the second frame to the second sending module, so that the second sending module sends all frames stored in the second storage module starting from the sequence number of the second frame to the second receiving module, wherein the first predetermined time is greater than the second predetermined time.

[0150] When the second control module does not receive any ACK signal or any NACK signal within a predetermined time threshold, or the number of retransmissions of a certain frame exceeds a predetermined number threshold, the second alarm module issues an alarm message.

[0151] The fourth AXI slave device transmits read data associated with the read address channel information to the fourth AXI master device based on a handshake mechanism with the fourth AXI master device. The fourth AXI master device transmits the read data to the first framing module. The first framing module frames the read data into frames based on the same frame structure. The first control module transmits the framed read data to the first transmitting module and stores the framed read data in the first storage module.

[0152] The first sending module sends the frame formed by the read data. The first receiving module receives the frame formed by the read data and determines whether the frame formed by the read data is erroneous.

[0153] (1) When there is no error in the frame formed by the read data, the first receiving module generates an ACK signal including the sequence number of the frame formed by the read data, and sends the ACK signal to the first control module; the first deframing module deframes the frame formed by the read data into read data based on the same frame structure, and sends the read data to the third AXI slave device; the third AXI slave device sends the read data to the third AXI master device based on the handshake mechanism with the third AXI master device.

[0154] (2) When an error occurs in a frame formed by reading the data, the first receiving module generates a first NACK signal including the sequence number of the frame formed by reading the data, sends the first NACK signal to the first control module, and turns off the data receiving function. When the second predetermined time expires, the first receiving module turns on the data receiving function again.

[0155] After receiving a NACK signal, the first control module waits for a first predetermined time, and then sends all frames stored in the first storage module starting from the sequence number of the frame into which the read data is framed to the first sending module, so that the first sending module sends all the frames to the receiving end, wherein the first predetermined time is greater than the second predetermined time.

[0156] The embodiment of the present invention also proposes an AXI interconnection method. Figure 6 Schematic diagram of an AXI interconnection method according to an embodiment of the present invention. Figure 6 The method shown can be executed by a processor. For example, the processor can be implemented as any one of: a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU). Figure 6 As shown, the method includes:

[0157] Step 601: Receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device.

[0158] Step 602: Based on a predetermined frame structure, the first AXI channel information is framed into a first frame.

[0159] Step 603: Send a first frame to the receiving end and store the first frame in a storage module. The first frame is detected at the receiving end and, after successful detection, is deframed into first AXI channel information based on the frame structure. When the receiving end detects that the first frame is erroneous, the first frame is obtained from the storage module and resent to the receiving end.

[0160] In one embodiment, the method includes: when a NACK signal including a sequence number of the first frame is received from the receiving end, determining that the receiving end detects an error in the first frame, and stopping receiving AXI channel information from the first AXI master device.

[0161] In one embodiment, the method includes: when a NACK signal is received from a receiving end, waiting for a first predetermined time, sending all frames stored in a storage module with a sequence number as a starting point to the receiving end, wherein the receiving end turns off a data receiving function when sending the negative confirmation signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

[0162] In summary, in this embodiment of the present invention, when data errors occur, retransmission of the erroneous data is implemented, thus realizing a retransmission mechanism within the AXI interconnect, which can improve data accuracy and, consequently, the accuracy and precision of signal communication. Furthermore, this embodiment of the present invention precisely controls the disabling and enabling of the data reception function at the receiving end, the stopping and resuming of the reception of AXI channel information from the first AXI master by the first AXI slave device, and the precise control of the first and second predetermined times. This ensures that data frames received by the receiving end are not duplicated or omitted, thereby improving data integrity.

[0163] Moreover, in an embodiment of the present invention, the first AXI master device and the second AXI slave device are not directly interconnected. Instead, based on an AXI interconnection device between the first AXI master device and the second AXI slave device, information interaction between the first AXI master device and the second AXI slave device is achieved in a framing and deframing manner. The bit width of the signal line used to send the first frame can be adjusted as needed, which is beneficial to reducing the number of signal lines and can significantly reduce the chip pin area during interconnection.

[0164] An embodiment of the present invention further provides an electronic device having a processor-memory architecture. Figure 7 FIG is a structural diagram of an electronic device according to an embodiment of the present invention. Figure 7As shown, the electronic device includes a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701. When the computer program is executed by the processor 701, any of the above AXI interconnection methods is implemented. Specifically, the memory 702 can be implemented as a variety of storage media such as an electrically erasable programmable read-only memory (EEPROM), a flash memory (Flash memory), and a programmable read-only memory (PROM). The processor 701 can be implemented as including one or more central processing units or one or more field programmable gate arrays, wherein the field programmable gate array integrates one or more central processing unit cores. Specifically, the central processing unit or central processing unit core can be implemented as a CPU, GPU, GPGPU, MCU, or DSP, etc.

[0165] It should be noted that not all steps and modules in the above processes and structure diagrams are required, and certain steps or modules can be omitted based on actual needs. The execution order of the steps is not fixed and can be adjusted as needed. The division of the modules is merely for the convenience of describing the functional division adopted. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can be implemented by the same module. These modules can be located in the same device or in different devices.

[0166] The hardware modules in each embodiment may be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent module or logic device (e.g., a dedicated processor, such as an FPGA or ASIC) to perform a specific operation. For example, a specific operation can be performed in various types of chips (e.g., artificial intelligence chips). A hardware module may also include a programmable logic device or module (e.g., a general-purpose processor or other programmable processor) temporarily configured by software to perform a specific operation. The decision on whether to implement a hardware module mechanically, using a dedicated permanent module, or using a temporarily configured module (e.g., configured by software) can be made based on cost and time considerations.

[0167] The present invention also provides a machine-readable storage medium storing instructions for causing a machine to execute the method described herein. Specifically, a system or device equipped with a storage medium storing software program code that implements the functions of any of the aforementioned embodiments can be provided, and a computer (or CPU or MPU) of the system or device can be configured to read and execute the program code stored in the storage medium. Furthermore, instructions based on the program code can be used to cause an operating system, etc., operating on the computer to perform some or all of the actual operations. The program code read from the storage medium can also be written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer. Subsequently, based on the program code instructions, a CPU, etc., installed in the expansion board or expansion unit can be configured to perform some or all of the actual operations, thereby implementing the functions of any of the aforementioned embodiments. Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, and DVD+RWs), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code can be downloaded from a server computer or cloud via a communication network.

[0168] In this document, "schematic" means "serving as an example, instance or illustration", and any diagram or embodiment described as "schematic" in this document should not be interpreted as a more preferred or more advantageous technical solution. In order to keep the drawings simple, each figure only schematically shows the parts related to the present invention, and does not represent its actual structure as a product. In addition, in order to keep the drawings simple and easy to understand, in some figures, only one of the components with the same structure or function is schematically drawn, or only one of them is marked. In this document, "one" does not mean that the number of relevant parts of the present invention is limited to "only one", and "one" does not mean excluding the situation where the number of relevant parts of the present invention is "more than one". In this document, "upper", "lower", "front", "back", "left", "right", "inside", "outside" and the like are only used to indicate the relative positional relationship between the relevant parts, rather than to limit the absolute positions of these relevant parts.

[0169] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. An AXI interconnect device, characterized in that: Connected between the first AXI master device and the receiving end, the AXI interconnection device includes: a first AXI slave device, configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; a framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; The device further includes a control module, a sending module and a storage module, wherein: The control module is configured to send the first frame to the sending module and store the first frame in the storage module; The sending module is configured to send the first frame to the receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; wherein after the framing processing by the framing module, the bit width of the signal line used for transmitting the first frame in the sending module is reduced to an arbitrary bit position; The control module is further configured to, when receiving a negative acknowledgment signal including the sequence number of the first frame from the receiving end, determine that the receiving end has detected an error in the first frame, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device; wait for a first predetermined time, and send all frames stored in the storage module starting with the sequence number to the sending module, so that the sending module resends all the frames to the receiving end; wherein the receiving end turns off a data receiving function when sending the negative acknowledgment signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

2. The device according to claim 1, characterized in that The control module is configured to schedule the first frame based on a predetermined scheduling mode before sending the first frame to the sending module, wherein the scheduling mode includes at least one of the following: First-come-first-served scheduling method; priority scheduling method; shortest job first scheduling method; time slice round-robin scheduling method; high response ratio priority scheduling method; fair scheduling method; hybrid scheduling method based on priority and time slice.

3. The device according to claim 1, characterized in that include: The alarm module is configured to issue an alarm message when the control module does not receive the confirmation signal or the negative confirmation signal from the receiving end within a predetermined time threshold, or when the number of retransmissions of the first frame exceeds a predetermined number threshold.

4. The device according to claim 1, characterized in that The control module is configured to control the first AXI slave device to resume receiving AXI channel information from the first AXI master device when the sending module completes sending all the frames to the receiving end and no negative confirmation signal including at least one sequence number in all the frames is received from the receiving end.

5. The device according to any one of claims 1 to 4, characterized in that It includes a receiving module and a de-framing module, wherein: The receiving module is configured to receive a second frame from a transmitting end, where the second frame is generated by the transmitting end based on the second AXI channel information framed by the frame structure; when detecting that the second frame is erroneous, not sending the second frame to the deframing module, generating a negative acknowledgment signal including a sequence number of the second frame, and sending the negative acknowledgment signal to the transmitting end, so that the transmitting end resends the second frame based on the negative acknowledgment signal; and when detecting that the second frame is correct, sending the second frame to the deframing module; The deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure.

6. An AXI interconnection system, characterized in that: comprising a first chip and a second chip; The first chip includes a first AXI master device, a first AXI slave device, a first framing module, a first control module, a first storage module and a first sending module; The second chip includes a first receiving module, a first deframing module, a second AXI master device and a second AXI slave device; The first AXI slave device is configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; the first framing module is configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; The first control module is configured to send the first frame to the first sending module and store the first frame in the first storage module; the first sending module is configured to send the first frame; wherein after the framing process by the first framing module, the bit width of the signal line used to transmit the first frame in the first sending module is reduced to an arbitrary bit position; The first receiving module is configured to receive the first frame, and when detecting that the first frame is erroneous, send a first negative confirmation signal including the sequence number of the first frame to the first control module, and when detecting that the first frame is correct, send the first frame to the first deframing module; The first deframing module is configured to deframe the first frame into first AXI channel information based on the frame structure, and send the first AXI channel information to the second AXI master device; the second AXI master device is configured to send the first AXI channel information to the second AXI slave device based on a handshake mechanism with the second AXI slave device; The first control module is further configured to, upon receiving the first negative acknowledgement signal, determine that the first receiving module has detected an error in the first frame, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device; wait for a first predetermined time, and send all frames stored in the first storage module starting with the sequence number to the first sending module, so that the first sending module resends all the frames to the first receiving module, wherein the first receiving module turns off a data receiving function when sending the first negative acknowledgement signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

7. The system according to claim 6, characterized in that The second chip includes a third AXI master device, a third AXI slave device, a second framing module, a second control module, a second storage module and a second sending module; The first chip includes a second receiving module, a second deframing module, a fourth AXI master device and a fourth AXI slave device; The third AXI slave device is configured to receive second AXI channel information from the third AXI master device based on a handshake mechanism with the third AXI master device; and the second framing module is configured to frame the second AXI channel information into a second frame based on the frame structure. The second control module is configured to send the second frame to the second sending module and store the second frame in the second storage module; The second sending module is used to send the second frame; The second receiving module is configured to receive the second frame, and when detecting that the second frame is erroneous, send a second negative acknowledgement signal including a sequence number of the second frame to the second control module; and when detecting that the second frame is correct, send the second frame to the second deframing module; the second deframing module is configured to deframe the second frame into second AXI channel information based on the frame structure, and send the second AXI channel information to the fourth AXI master device; the fourth AXI master device is configured to send the second AXI channel information to the fourth AXI slave device based on a handshake mechanism with the fourth AXI slave device; The second control module is further configured to, upon receiving the second negative acknowledgement signal, determine that the second receiving module has detected an error in the second frame, and control the third AXI slave device to stop receiving AXI channel information from the third AXI master device; wait for a first predetermined time, and send all frames stored in the second storage module starting with the sequence number to the second sending module, so that the second sending module resends all the frames to the second receiving module, wherein the second receiving module turns off a data receiving function when sending the second negative acknowledgement signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

8. An AXI interconnection method, characterized in that: include: receiving first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; Framing the first AXI channel information into a first frame based on a predetermined frame structure; Sending the first frame to a receiving end and storing the first frame in a storage module, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; wherein after the framing process, the bit width of a signal line used to transmit the first frame is reduced to an arbitrary bit position; When a negative acknowledgement signal including the sequence number of the first frame is received from the receiving end, it is determined that the receiving end has detected an error in the first frame, and the first AXI slave device is controlled to stop receiving AXI channel information from the first AXI master device; after a first predetermined time, all frames stored in the storage module starting with the sequence number are sent to the sending module, so that the sending module resends all the frames to the receiving end; The receiving end turns off a data receiving function when sending the negative confirmation signal, and turns on the data receiving function after a second predetermined time, wherein the first predetermined time is greater than the second predetermined time.

9. An electronic device, characterized in that: include: Memory; processor; The memory stores an application program executable by the processor, which is used to enable the processor to execute the AXI interconnection method according to claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, enable the processor to execute the AXI interconnection method according to claim 8.

11. A program product comprising a computer program, characterized in that When the computer program is executed by a processor, the AXI interconnection method according to claim 8 is implemented.

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