Display device

Abstract

According to one embodiment, a display device includes: a first lower electrode; a rib having a plurality of first pixel openings overlapping the first lower electrode; a partition wall; a plurality of first organic layers that respectively pass through the plurality of first pixel openings, are in contact with the first lower electrode, and emit light in response to the application of a voltage; and a plurality of first upper electrodes covering the plurality of first organic layers, respectively. The partition wall includes a lower portion disposed above the rib, and an upper portion having an end portion protruding from a side surface of the lower portion. The partition wall includes: a plurality of first openings overlapping the plurality of first pixel openings, respectively; and a first partition wall disposed between the plurality of first pixel openings.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023 - 213895 filed on December 19, 2023, and incorporates by reference all the descriptions recited in the Japanese patent application. Technical field

[0003] Embodiments of the present invention relate to a display device. Background art

[0004] In recent years, a display device using an organic light - emitting diode (OLED) as a display element has been put into practical use. In such a display device, a technology capable of improving the yield is required. Summary of the invention

[0005] Generally, according to an embodiment, a display device includes: a first lower electrode; ribs having a plurality of first pixel openings overlapping the first lower electrode; a partition wall; a plurality of first organic layers that respectively pass through the plurality of first pixel openings and contact the first lower electrode, and emit light according to the application of a voltage; and a plurality of first upper electrodes that respectively cover the plurality of first organic layers. The partition wall includes a lower portion disposed above the ribs and an upper portion having an end portion protruding from a side surface of the lower portion. In addition, the partition wall includes: a plurality of first openings respectively overlapping the plurality of first pixel openings; and a first partition wall disposed between the plurality of first pixel openings.

[0006] According to another embodiment, a display device includes: a first lower electrode; ribs having a first pixel opening overlapping the first lower electrode; a partition wall; a first organic layer that passes through the first pixel opening and contacts the first lower electrode, and emits light according to the application of a voltage; and a first upper electrode that covers the first organic layer. The partition wall includes a lower portion disposed above the ribs and an upper portion having an end portion protruding from a side surface of the lower portion. In addition, the partition wall includes: a first opening overlapping the first pixel opening; and a first partition wall that overlaps the first pixel opening and is separated from an edge portion of the first opening.

[0007] According to each embodiment, a display device capable of improving the yield can be provided. Brief description of the drawings

[0008] Figure 1 It is a diagram showing a configuration example of the display device according to the first embodiment.

[0009] Figure 2 It is a schematic plan view showing an example of the layout of sub - pixels according to the first embodiment.

[0010] Figure 3 is a schematic cross-sectional view of a display device along line III-III in Figure 2 .

[0011] Figure 4 is a diagram showing an example of a layer structure applicable to an organic layer.

[0012] Figure 5 is Figure 2 a schematic top view of the partition wall shown.

[0013] Figure 6 is a schematic cross-sectional view of a display device along line IV-IV in Figure 2 .

[0014] Figure 7 is a schematic top view showing another example of the layout of sub-pixels in the first embodiment.

[0015] Figure 8 is Figure 7 a schematic top view of the partition wall shown.

[0016] Figure 9 is a schematic top view showing an example of the layout of sub-pixels in the second embodiment.

[0017] Figure 10 is Figure 9 a schematic top view of the partition wall shown.

[0018] Figure 11 is a schematic top view showing another example of the layout of sub-pixels in the second embodiment.

[0019] Figure 12 is Figure 11 a schematic top view of the partition wall shown. DETAILED DESCRIPTION

[0020] Several embodiments will be described with reference to the accompanying drawings.

[0021] The present disclosure is merely an example, and appropriate modifications that are easily conceivable by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the drawings are sometimes shown schematically compared to the actual embodiment, but this is only an example and does not limit the interpretation of the present invention. Further, in this specification and each drawing, components that perform the same or similar functions as the components described in the accompanying drawings that have appeared previously may be given the same reference numerals, and repeated detailed descriptions may be appropriately omitted.

[0022] Note that in the drawings, for ease of understanding, the X-axis, Y-axis, and Z-axis orthogonal to each other are described as needed. The direction along the X-axis is referred to as the X-direction (the second direction), the direction along the Y-axis is referred to as the Y-direction (the first direction), and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, observing various elements parallel to the Z-direction is referred to as a top view.

[0023] The display device of each embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, a vehicle-mounted device, a tablet terminal, a smart phone, a mobile phone terminal, and a wearable terminal.

[0024] [First Embodiment]

[0025] Figure 1 FIG. shows a configuration example of the DSP of the display device according to the first embodiment. The display device DSP has an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0026] In the present embodiment, the shape of the substrate 10 in a top view is rectangular. However, the shape of the substrate 10 in a top view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0027] The display area DA includes a plurality of pixels PX arranged in a matrix in the X-direction and the Y-direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may further include other color sub-pixels SP such as white on the basis of the sub-pixels SP1, SP2, and SP3, or instead of one of the sub-pixels SP1, SP2, and SP3.

[0028] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements made of thin film transistors, for example.

[0029] In the display area DA, a plurality of scan lines GL for supplying a scan signal to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines SL for supplying an image signal to the pixel circuit 1 of each sub-pixel SP, and a plurality of power supply lines PL are arranged. In Figure 1 the example, the scan lines GL and the power supply lines PL extend in the X-direction, and the signal lines SL extend in the Y-direction.

[0030] The gate electrode of pixel switch 2 is connected to scanning line GL. The source electrode of pixel switch 2 is connected to signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of driving transistor 3 and capacitor 4. The source electrode of driving transistor 3 is connected to power line PL and capacitor 4. The drain electrode of driving transistor 3 is connected to display element DE.

[0031] Furthermore, the structure of pixel circuit 1 is not limited to the illustrated example. For example, pixel circuit 1 may also include more thin film transistors and capacitors.

[0032] Figure 2 It is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3 of the first embodiment. In Figure 2 the example shown, sub-pixels SP2 and SP3 are arranged in the X direction with respect to sub-pixel SP1 respectively. Moreover, sub-pixels SP2 and SP3 are arranged in the Y direction.

[0033] When sub-pixels SP1, SP2, and SP3 are in this layout, columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction are formed in display area DA.

[0034] It should be noted that the layout of sub-pixels SP1, SP2, and SP3 or the sizes of sub-pixels SP1, SP2, and SP3 are not limited to Figure 2 the example. As another example, sub-pixels SP1, SP2, and SP3 may also be arranged in the X direction. Additionally, the sizes of at least two of sub-pixels SP1, SP2, and SP3 may be equal.

[0035] Rib 5 is arranged in display area DA. Rib 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3 respectively. Pixel opening AP1 includes pixel openings AP11 and AP12. Pixel openings AP11 and AP12 are each an example of the first pixel opening. Pixel opening AP2 is an example of the second pixel opening.

[0036] In Figure 2 the example, pixel openings AP11 and AP12 are arranged in the Y direction. Additionally, pixel opening AP11 is adjacent to pixel opening AP3 in the X direction, and pixel opening AP12 is adjacent to pixel opening AP2 in the X direction.

[0037] In Figure 2In the example, the area of the pixel aperture AP11 is equal to the area of the pixel aperture AP12. Additionally, the area of each of the pixel apertures AP11 and AP12 is smaller than the area of the pixel aperture AP2 and larger than the area of the pixel aperture AP3. Moreover, the total area of the pixel apertures AP11 and AP12 (the total area of the pixel aperture AP1) is larger than the pixel apertures AP2 and AP3.

[0038] It should be noted that the area of the pixel aperture AP11 may be different from the area of the pixel aperture AP12. Additionally, the area of each of the pixel apertures AP11 and AP12 may be larger or smaller than the area of each of the pixel apertures AP2 and AP3.

[0039] The partition 6 is disposed in the display area DA. The partition 6 is disposed above the rib portion 5 and overlaps with the rib portion 5 as a whole. In Figure 2 In the example, the partition 6 has the same planar shape as the rib portion 5. That is, the partition 6 includes openings A1, A2, and A3 in the sub-pixels SP1, SP2, and SP3, respectively. The opening A1 includes openings A11 and A12. The openings A11, A12, A2, and A3 coincide with the pixel apertures AP11, AP12, AP2, and AP3, respectively. The openings A11 and A12 are each an example of the first opening. The opening A2 is an example of the second opening.

[0040] In Figure 2 In the example, the area of the opening A11 is equal to the area of the opening A12. Additionally, the area of each of the openings A11 and A12 is smaller than the area of the opening A2 and larger than the area of the opening A3. Moreover, the total area of the openings A11 and A12 (the total area of the opening A1) is larger than the openings A2 and A3.

[0041] It should be noted that the area of the opening A11 may be different from the area of the opening A12. Additionally, the area of each of the openings A11 and A12 may be larger or smaller than the area of each of the openings A2 and A3.

[0042] The partition 6 includes a partition 6A (the first partition) and a partition 6B (the second partition). The partition 6A is disposed between the pixel aperture AP11 and the pixel aperture AP12. In Figure 2 In the example, the partition 6A is composed of a first portion 6Aa extending in the X direction between the opening A11 and the opening A12.

[0043] The partition 6B is disposed between the pixel aperture AP1 and the pixel aperture AP2. In Figure 2 In the example, the partition 6B is disposed between the pixel aperture AP12 and the pixel aperture AP2. The partition 6B extends in the Y direction and intersects with the partition 6A. It should be noted that in Figure 2In the example, the first part 6Aa of the adjacent wall 6B is orthogonal to the adjacent wall 6A, but is not limited to this example.

[0044] The sub-pixel SP1 has a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that respectively coincide with the pixel opening AP1. The sub-pixel SP2 has a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that respectively coincide with the pixel opening AP2. The sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively coincide with the pixel opening AP3.

[0045] The portions of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 that coincide with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The portions of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 that coincide with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The portions of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 that coincide with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may also include a cover layer described later.

[0046] The pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 (refer to Figure 1 ) are respectively arranged below the lower electrodes LE1, LE2, and LE3. The lower electrode LE1 passes through the contact hole CH1 and is connected to the pixel circuit 1 of the sub-pixel SP1. The lower electrode LE2 passes through the contact hole CH2 and is connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 passes through the contact hole CH3 and is connected to the pixel circuit 1 of the sub-pixel SP3. In Figure 2 's example, the contact holes CH1, CH2, and CH3 as a whole coincide with the rib 5 and the adjacent wall 6, but are not limited to this example.

[0047] Figure 3 is a schematic cross-sectional view of the display device DSP along the III-III line in Figure 2 . Above the substrate 10, a circuit layer 11 is arranged. The circuit layer 11 includes Figure 1 various circuits or wirings such as the pixel circuit 1, the scan line GL, the signal line SL, and the power line PL shown. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film that planarizes the unevenness generated by the circuit layer 11.

[0048] The lower electrodes LE1, LE2, and LE3 are arranged above the organic insulating layer 12. The rib 5 is arranged above the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although inFigure 3 is not shown in the cross-section, but the lower electrodes LE1, LE2, and LE3 pass through the contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12 respectively ( Figure 2 refer to) and are connected to the pixel circuit 1 of the circuit layer 11.

[0049] The partition wall 6 includes a lower portion 61 having conductivity disposed on the rib portion 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. Thus, both end portions of the upper portion 62 protrude more than the side surfaces of the lower portion 61. This shape of the partition wall 6 is called a hanging shape.

[0050] In Figure 3 the example of, the lower portion 61 has a bottom layer 63 disposed on the rib portion 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Additionally, in Figure 3 the example of, both end portions of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0051] Furthermore, in Figure 3 the example of, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the shaft layer 64. The second top layer 66 is disposed on the first top layer 65. The second top layer 66 can be formed thinner than the first top layer 65 as shown in the figure. Additionally, the second top layer 66 can have a smaller width than the first top layer 65. When the partition wall 6 has the Figure 3 configuration shown, Figure 2 the openings A11, A12, A2, and A3 shown respectively correspond to the regions surrounded by the end portions of the first top layer 65.

[0052] The organic layer OR1 passes through the pixel opening AP1 and covers the lower electrode LE1. The upper electrode UE1 covers the organic layer OR1 and is opposed to the lower electrode LE1. The organic layer OR2 passes through the pixel opening AP2 and covers the lower electrode LE2. The upper electrode UE2 covers the organic layer OR2 and is opposed to the lower electrode LE2. The organic layer OR3 passes through the pixel opening AP3 and covers the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0053] The display element DE1 includes a cover layer CP1 covering the upper electrode UE1. The display element DE2 includes a cover layer CP2 covering the upper electrode UE2. The display element DE3 includes a cover layer CP3 covering the upper electrode UE3. The cover layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the light acquisition efficiency of the organic layers OR1, OR2, and OR3.

[0054] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cover layer CP1 is referred to as a stacked film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cover layer CP2 is referred to as a stacked film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cover layer CP3 is referred to as a stacked film FL3.

[0055] A part of the stacked film FL1 is located above the upper portion 62. This part is separated from the part around the partition wall 6 in the stacked film FL1 (the part constituting the display element DE1). Similarly, a part of the stacked film FL2 is located above the upper portion 62, and this part is separated from the part around the partition wall 6 in the stacked film FL2 (the part constituting the display element DE2). Moreover, a part of the stacked film FL3 is located above the upper portion 62, and this part is separated from the part around the partition wall 6 in the stacked film FL3 (the part constituting the display element DE3).

[0056] Sealing layers SE11, SE12, and SE13 are respectively disposed in the sub-pixels SP1, SP2, and SP3. The sealing layer SE11 continuously covers the cover layer CP1 and the partition wall 6 around the sub-pixel SP1. The sealing layer SE12 continuously covers the cover layer CP2 and the partition wall 6 around the sub-pixel SP2. The sealing layer SE13 continuously covers the cover layer CP3 and the partition wall 6 around the sub-pixel SP3.

[0057] In Figure 3 this example, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE12 on this partition wall 6. In addition, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE13 on this partition wall 6.

[0058] The sealing layers SE11, SE12, and SE13 are covered by a resin layer RS1. The resin layer RS1 is covered by a sealing layer SE2. The sealing layer SE2 is covered by a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least over the entire display area DA, and a part thereof is also provided in the peripheral area SA.

[0059] A covering member such as a polarizing plate, a touch panel, a protective film, or a cover glass may also be disposed above the resin layer RS2. Such a covering member may also be bonded to the resin layer RS2 via an adhesive layer such as an OCA (Optical Clear Adhesive).

[0060] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The ribs 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the ribs 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin, for example.

[0061] The lower electrodes LE1, LE2, LE3 have, for example, a reflective layer formed of silver, and a pair of conductive oxide layers covering the upper surface and the lower surface of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide), for example.

[0062] Figure 4 FIG. is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, OR3. The organic layers OR1, OR2, OR3 are constituted by a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in the Z direction in this order. However, the organic layers OR1, OR2, OR3 may also have other structures such as a so-called tandem structure including a plurality of light-emitting layers EML.

[0063] The cover layers CP1, CP2, CP3 have, for example, a laminated structure in which a plurality of transparent layers are superimposed. These transparent layers may include a layer formed of an inorganic material and a layer formed of an organic material. In addition, these transparent layers have different refractive indexes from each other. For example, the refractive indexes of these transparent layers are different from the refractive indexes of the upper electrodes UE1, UE2, UE3 and the refractive indexes of the sealing layers SE11, SE12, SE13. The cover layers CP1, CP2, CP3 each have a function as an optical adjustment layer that improves the light extraction efficiency of the light emitted from the organic layers OR1, OR2, OR3. In addition, at least one of the cover layers CP1, CP2, CP3 may be omitted.

[0064] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of, for example, different metal materials from each other. As the metal material for the bottom layer 63, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum tungsten alloy (MoW), or molybdenum niobium alloy (MoNb) can be used. As the metal material for the shaft layer 64 (Al), for example, aluminum, aluminum neodymium alloy (AlNd), aluminum yttrium alloy (AlY), or aluminum silicon alloy (AlSi) can be used. In addition, at least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of multiple layers. Further, the shaft layer 64 may include a layer formed of an insulating material.

[0065] For example, the first top layer 65 of the partition wall 6 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. As the metal material for the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum tungsten alloy, or molybdenum niobium alloy can be used. As the conductive oxide for the second top layer 66, for example, ITO or IZO can be used. In addition, the upper part 62 may have a single-layer structure formed of a specific material. Moreover, the upper part 62 may include a layer formed of an insulating material.

[0066] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the lower part 61, respectively. That is, the partition wall 6 functions as a wiring for supplying the common voltage to the upper electrodes UE1, UE2, and UE3. Pixel voltages corresponding to the video signals of the signal lines SL are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0067] The organic layers OR1, OR2, and OR3 emit light by applying a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength range. As another example, the light-emitting layer EML of the organic layer OR2 may emit light in the red wavelength range, and the light-emitting layer EML of the organic layer OR3 may emit light in the green wavelength range.

[0068] Further, as another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may also emit light of the same color (e.g., white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer EML into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. Additionally, the display device DSP may also include a layer including quantum dots that generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3 when excited by the light emitted by the light-emitting layer EML.

[0069] Figure 5 is Figure 2 a schematic plan view of the partition wall 6 shown. Here, as Figure 5 shown, the widths of the opening A11 along the X direction and the Y direction are defined as widths W1x and W1y, respectively, and the widths of the opening A12 along the X direction and the Y direction are defined as widths W2x and W2y, respectively. Additionally, the width of the first portion 6Aa along the Y direction is defined as width WAa, and the width of the partition wall 6B along the X direction is defined as width WB.

[0070] In the present embodiment, the width W1x is equal to the width W2x (W1x = W2x), and the width W1y is equal to the width W2y (W1y = W2y). That is, in the Figure 5 example, the areas of the openings A11 and A12 are equal. It should be noted that the size relationship between the width W1x and the width W2x, and the size relationship between the width W1y and the width W2y are not limited to this example. The width W1x may be different from the width W2x, and the width W1y may be different from the width W2y.

[0071] In the present embodiment, the total width (W1y + W2y + WAa) of the widths W1y, W2y, and WAa is larger than at least one of the widths W1x and W2x (both widths W1x and W2x in the Figure 5 example). The width WAa is smaller than the width WB (WAa < WB).

[0072] Figure 6 is a schematic cross-sectional view of the display device DSP along the Figure 2 IV-IV line in. It should be noted that the substrate 10, the circuit layer 11, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are omitted from the illustration.

[0073] In the following description, the portion of the rib 5 that coincides with the partition wall 6A is referred to as the rib 5A. The rib 5A is disposed above the lower electrode LE1. The first portion 6Aa is disposed above the rib 5A. The first portion 6Aa is disposed between the pixel opening AP11 and the pixel opening AP12. The partition wall 6A (the first portion 6Aa) is in a hanging shape, the same as the other portions of the partition wall 6. In the sub-pixel SP1, the stacked film FL1 is partitioned by the first portion 6Aa.

[0074] The two organic layers OR1 partitioned by the first portion 6Aa respectively pass through the pixel openings AP11 and AP12 and contact the lower electrode LE1. The two upper electrodes UE1 partitioned by the first portion 6Aa respectively cover the two organic layers OR1. The two cover layers CP1 partitioned by the first portion 6Aa respectively cover the two upper electrodes UE1. A part of the stacked film FL1 is located above the upper portion 62 of the partition wall 6A. This part is separated from the part (the part constituting the display element DE1) around the partition wall 6A in the stacked film FL1. The sealing layer SE11 continuously covers the partition wall 6A and the cover layer CP1.

[0075] Here, some effects exhibited by the present embodiment will be described. In the manufacturing process of the display device DSP, the stacked film FL1 is formed over the entire display area DA by vapor deposition. Then, a sealing layer SE11 covering the stacked film FL1 is formed. Next, patterning is performed on these stacked film FL1 and the sealing layer SE11. Specifically, the portions of the stacked film FL1 and the sealing layer SE11 disposed in the sub-pixel SP1 are left, and the portions disposed in the sub-pixels SP2 and SP3 are removed. After that, the stacked film FL2 and the sealing layer SE12 are formed in the sub-pixel SP2 according to the same steps. Also, the stacked film FL3 and the sealing layer SE13 are formed in the sub-pixel SP3 according to the same steps.

[0076] The adhesion between the stacked film FL1 formed by vapor deposition and the lower electrode LE1 is weak, and peeling may occur during the manufacturing process of the display device DSP. This peeling may cause deterioration in the yield of the display device DSP.

[0077] Peeling of the stacked film FL1 is likely to occur in a region where the stacked film FL1 is formed continuously and over a wide range. In this regard, in the display device DSP of the present embodiment, the opening A1 is partitioned into openings A11 and A12 by the first portion 6Aa of the partition wall 6A. Thus, the stacked film FL1 formed in the sub-pixel SP1 is partitioned by the first portion 6Aa. Therefore, compared with the case where the partition wall 6A is not provided, the range in which the stacked film FL1 is continuously formed in the sub-pixel SP1 becomes smaller, and the stacked film FL1 becomes less likely to peel. Therefore, the yield of the display device DSP can be improved.

[0078] In the present embodiment, the area of the opening A1 (the total area of the openings A11 and A12) is larger than the areas of the openings A2 and A3. Therefore, among the openings A1, A2, and A3, the above-mentioned peeling is likely to occur in the opening A1. For this reason, by partitioning the opening A1 with the partition wall 6A, the risk of the above-mentioned peeling can be effectively suppressed. However, it is not limited to this example, and at least one of the openings A2 and A3 may also be partitioned by a partition wall. Thereby, the effect of suppressing peeling can be further improved.

[0079] In addition, in the present embodiment, the width WAa of the first part 6Aa that partitions the laminated film FL1 is smaller than the width WB of the partition wall 6B disposed between the pixel openings AP1 and AP2. As the width WAa of the first part 6Aa increases, the width of the rib 5A also increases. Therefore, the pixel opening AP1 becomes smaller, and the aperture ratio of the sub-pixel SP1 decreases. Therefore, by reducing the width WAa of the first part 6Aa, a decrease in the aperture ratio of the sub-pixel SP1 can be suppressed.

[0080] It should be noted that, in the present embodiment, the lower electrode LE1 and the opening A1 are shaped to have a long side in the Y direction. In addition, the first part 6Aa extends in the X direction. Moreover, the opening A1 is partitioned by the first part 6Aa such that the openings A11 and A12 are arranged in the Y direction. It is not limited to this example, and the first part 6Aa may also extend in the Y direction. That is, the opening A1 may be partitioned by the first part 6Aa such that the openings A11 and A12 are arranged in the X direction.

[0081] In addition, in the present embodiment, the opening A1 is partitioned into two by the partition wall 6A, but it may also be partitioned into three or more. In this case, the opening may be partitioned by a plurality of partition walls parallel to each other, or the opening may be partitioned by partition walls intersecting each other as described later.

[0082] Figure 7 It is a schematic top view showing another example of the layout of the sub-pixels SP1, SP2, and SP3 of the first embodiment. The same reference numerals are given to the same or similar elements as those in the above-described display device DSP, and repeated descriptions are appropriately omitted.

[0083] The pixel opening AP1 includes pixel openings AP11, AP12, AP13, and AP14. In Figure 7 the example, the pixel openings AP11 and AP13 are arranged in the X direction, the pixel openings AP12 and AP14 are arranged in the X direction, the pixel openings AP11 and AP12 are arranged in the Y direction, and the pixel openings AP13 and AP14 are arranged in the Y direction. In addition, in Figure 7In the example, the areas of the pixel apertures AP11, AP12, AP13, and AP14 are equal. It should be noted that the areas of the pixel apertures AP11, AP12, AP13, and AP14 may also be different.

[0084] The opening A1 includes openings A11, A12, A13, and A14. The openings A11, A12, A13, and A14 respectively coincide with the pixel apertures AP11, AP12, AP13, and AP14. Additionally, in Figure 7 the example, the areas of the openings A11, A12, A13, and A14 are equal. It should be noted that the areas of the openings A11, A12, A13, and A14 may also be different.

[0085] The partition wall 6A is the same as that in Figure 2 the example and has a first portion 6Aa. The first portion 6Aa is disposed between the pixel aperture AP11 and the pixel aperture AP12, and between the pixel aperture AP13 and the pixel aperture AP14. The partition wall 6A further has a second portion 6Ab. The second portion 6Ab is disposed between the pixel aperture AP11 and the pixel aperture AP13, and between the pixel aperture AP12 and the pixel aperture AP14. In Figure 7 the example, the first portion 6Aa extends in the X direction. Additionally, the second portion 6Ab extends in the Y direction and intersects the first portion 6Aa.

[0086] Figure 8 is Figure 7 a schematic plan view of the partition wall 6 shown. Here, as Figure 8 shown, the width along the X direction of the second portion 6Ab is defined as the width WAb. In Figure 8 the example, the width WAb is smaller than the width WB (WAb < WB). Similar to the width WAa of the first portion 6Aa, by reducing the width WAb of the second portion 6Ab, a decrease in the aperture ratio of the sub-pixel SP1 can be suppressed.

[0087] In Figure 7 and Figure 8 the example, the opening A1 is partitioned into four by the first portion 6Aa and the second portion 6Ab. That is, since the number of openings partitioned is more than that in Figure 2 the example, the stacked film FL1 formed on the sub-pixel SP1 during the manufacturing process of the display device DSP becomes less likely to peel off. It should be noted that Figure 7 and Figure 8 the structure of the partition wall 6A shown can also be applied to the sub-pixels SP2 and SP3.

[0088] [Second Embodiment]

[0089] Figure 9 This is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3 in the second embodiment. The same or similar elements as those in the display device DSP of the first embodiment are denoted by the same reference numerals, and repeated descriptions are appropriately omitted.

[0090] In the present embodiment, the rib 5 includes an island-shaped rib 5A separated from the edge E1 of the pixel opening AP1. The rib 5A is disposed above the lower electrode LE1. The partition wall 6 coincides with the pixel opening AP1 and includes an island-shaped partition wall 6A separated from the edge E2 of the opening A1. The partition wall 6A is disposed above the rib 5A. The rib 5A and the partition wall 6A have a shape in which the corners in a top view are formed in a rounded shape. It should be noted that each corner of the rib 5A and the partition wall 6A may also be formed into a right angle. In addition, the rib 5A and the partition wall 6A may be formed into a circular shape or an elliptical shape. In Figure 9 the example, the area of the opening A1 is larger than the area of the opening A2. The pixel opening AP1 is an example of the first pixel opening. The opening A1 is an example of the first opening. The partition wall 6A is an example of the first partition wall.

[0091] Figure 10 is Figure 9 a schematic top view of the partition wall 6 shown. Here, as Figure 10 shown, the distances between the two sides E2y parallel to the Y direction and sandwiching the partition wall 6A and the center O of the partition wall 6A in the edge E2 of the opening A1 are defined as distances Dx1 and Dx2, respectively. In addition, the distances between the two sides E2x parallel to the X direction and sandwiching the partition wall 6A and the center O of the partition wall 6A in the edge E2 of the opening A1 are defined as distances Dy1 and Dy2, respectively. Moreover, the widths of the partition wall 6A along the X direction and the Y direction are defined as widths WAx and WAy, respectively.

[0092] In the present embodiment, the distance Dx1 is equal to the distance Dx2 (Dx1 = Dx2), and the distance Dy1 is equal to the distance Dy2 (Dy1 = Dy2). That is, the partition wall 6A is disposed at the center of the opening A11 in the X direction and the Y direction. It should be noted that, not limited to the above example, the partition wall 6A may also be disposed at a position offset from the center of the opening A11. The distance obtained by adding the distance Dy1 and the distance Dy2 is larger than the distance obtained by adding the distance Dx1 and the distance Dx2 (Dy1 + Dy2 > Dx1 + Dx2). The widths WAx and Way are smaller than the width WB (WAx, WAy < WB).

[0093] In the second embodiment, similarly to the first embodiment, peeling of the stacked film can be suppressed, and the yield of the display device DSP can be improved.

[0094] In addition, in the second embodiment, by separating the partition wall 6A from the edge portion of the opening A1, the aperture ratio of the sub-pixel SP1 can be increased compared to the first embodiment.

[0095] Figure 11 FIG. is a schematic plan view showing another example of the layout of the sub-pixels SP1, SP2, and SP3 in the second embodiment. The rib portion 5 includes a plurality of rib portions 5A. The partition wall 6 includes a plurality of partition walls 6A. In Figure 11 the example, the rib portion 5 and the partition wall 6 each include three rib portions 5A and partition walls 6A, respectively. It should be noted that the number of each of the plurality of rib portions 5A and the plurality of partition walls 6A is not limited to three, and may be two or four or more.

[0096] In Figure 11 the example, the plurality of rib portions 5A and the plurality of partition walls 6A are arranged along the Y direction. It should be noted that the plurality of rib portions 5A and the plurality of partition walls 6A may be arranged along the X direction, or may be arranged along the X direction and the Y direction, respectively.

[0097] Figure 12 is Figure 11 a schematic plan view of the partition wall 6 shown. The distances between the centers O of the partition walls 6A adjacent to each other along the Y direction among the three partition walls 6A arranged along the Y direction are defined as distances D1 and D2, respectively. In the present embodiment, the distance D1 is equal to the distance D2 (D1 = D2). That is, the plurality of partition walls 6A are arranged at equal intervals along the Y direction.

[0098] In the present embodiment as well, similar to the above-described embodiment, peeling of the laminated film can be suppressed, and the yield of the display device DSP can be improved. In addition, in the present embodiment, a plurality of partition walls 6A are arranged along the direction (Y direction) in which the long side of the opening A1 extends. As a result, the partition walls 6A are appropriately dispersed in the opening A1, so that the effect of suppressing the above-described peeling is improved.

[0099] Based on the display devices disclosed in the above-described embodiments, all display devices that can be implemented by a person skilled in the art by appropriately changing the design belong to the scope of the present invention as long as they include the gist of the present invention.

[0100] In the scope of the idea of the present invention, various modifications can be conceived by a person skilled in the art, and it should be understood that these modifications also belong to the scope of the present invention. For example, modifications obtained by a person skilled in the art by appropriately adding, deleting, or changing the design of the constituent elements, or by adding, omitting, or changing the conditions of the process with respect to the above-described embodiments are included in the scope of the present invention as long as they have the gist of the present invention.

[0101] In addition, with regard to other effects brought about by the forms described in the above embodiments, those that can be clearly derived from the description of this specification or that can be appropriately conceived by those skilled in the art should of course be understood to be brought about by the present invention.

Claims

1. A display device, characterized in that: have: 1st lower electrode; a rib having a plurality of first pixel openings overlapping with the first lower electrode; a partition wall including a lower portion disposed above the rib portion and an upper portion having an end portion protruding from a side surface of the lower portion; a plurality of first organic layers, which respectively pass through the plurality of first pixel openings to contact the first lower electrode and emit light in response to application of a voltage; as well as a plurality of first upper electrodes respectively covering the plurality of first organic layers, The partition wall comprises: a plurality of first openings respectively overlapping with the plurality of first pixel openings; as well as A first partition wall is disposed between the plurality of first pixel openings.

2. The display device according to claim 1, characterized in that The first lower electrode has a shape having long sides in a first direction, Two first openings among the plurality of first openings are arranged in a first direction, The first partition wall has a first portion extending along a second direction intersecting the first direction between the two first openings.

3. The display device according to claim 2, characterized in that: A total width of the two first openings and the first portion along the first direction is larger than a width of at least one of the two first openings along the second direction.

4. The display device according to claim 2, characterized in that: Also available: a second lower electrode, which is adjacent to the first lower electrode in the second direction; a second organic layer that emits light of a different color from that of the first organic layer in response to application of a voltage; as well as a second upper electrode covering the second organic layer, The rib has a second pixel opening that overlaps with the second lower electrode. The second organic layer passes through the second pixel opening and contacts the second lower electrode. The next door also includes: a second opening overlapping the second pixel opening; as well as A second partition wall is disposed between the first pixel opening and the second pixel opening.

5. The display device according to claim 4, characterized in that: A width of the first portion along the first direction is smaller than a width of the second partition wall along the second direction.

6. The display device according to claim 4, characterized in that: The first portion is orthogonal to the second partition wall.

7. The display device according to claim 4, characterized in that: The area of ​​the first opening is smaller than the area of ​​the second opening.

8. The display device according to claim 4, characterized in that: The total area of ​​the plurality of first openings is larger than the area of ​​the second openings.

9. The display device according to claim 2, characterized in that: Two first openings among the plurality of first openings are arranged in the second direction, The first partition wall has a second portion disposed between the two first openings arranged in the second direction. The second portion intersects with the first portion.

10. A display device, characterized in that: have: 1st lower electrode; a rib having a first pixel opening overlapping with the first lower electrode; a partition wall including a lower portion disposed above the rib portion and an upper portion having an end portion protruding from a side surface of the lower portion; a first organic layer that passes through the first pixel opening and contacts the first lower electrode, and emits light in response to application of a voltage; as well as a first upper electrode covering the first organic layer, The partition wall comprises: a first opening overlapping the first pixel opening; as well as The first partition wall overlaps with the first pixel opening and is separated from an edge portion of the first opening.

11. The display device according to claim 10, characterized in that: The width of the first opening along a first direction is greater than the width of the first opening along a second direction intersecting the first direction. The first partition wall is arranged at the center of the first opening in the first direction.

12. The display device according to claim 11, characterized in that: The first partition wall is arranged at the center of the first opening in the second direction.

13. The display device according to claim 10, characterized in that: Also available: a second lower electrode adjacent to the first lower electrode; a second organic layer that emits light of a different color from that of the first organic layer in response to application of a voltage; as well as a second upper electrode covering the second organic layer, The rib has a second pixel opening that overlaps with the second lower electrode. The second organic layer passes through the second pixel opening and contacts the second lower electrode. The next door also includes: a second opening overlapping the second pixel opening; A second partition wall is disposed between the first pixel opening and the second pixel opening.

14. The display device according to claim 13, characterized in that: The width of the first partition wall is smaller than the width of the second partition wall.

15. The display device according to claim 13, characterized in that: The area of ​​the first opening is larger than the area of ​​the second opening.

16. The display device according to claim 10, characterized in that: The partition wall includes a plurality of first partition walls.

17. The display device according to claim 16, characterized in that: The width of the first opening along a first direction is greater than the width of the first opening along a second direction intersecting the first direction. The plurality of first partition walls are arranged along the first direction.

18. The display device according to claim 17, characterized in that: The plurality of first partition walls are arranged at equal intervals.

19. The display device according to claim 1 or 10, characterized in that: The first organic layer includes a light-emitting layer that emits blue light.

20. The display device according to claim 4 or 13, characterized in that: The first organic layer includes a light-emitting layer that emits blue light, The second organic layer includes a light-emitting layer that emits green or red light.

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