Display panel mother board, display panel and display device

Abstract

The invention discloses a display panel mother board, a display panel and a display device.The display panel mother board is provided with at least two panel areas, the display panel mother board comprises a plurality of sub-pixels, the sub-pixels are arranged in each panel area, and the sub-pixels in the at least two panel areas are arranged differently; a plurality of test signal ends are arranged in each panel area, the test signal ends in the panel areas are electrically connected with the corresponding sub-pixels, the test signal ends are used for participating in driving the sub-pixels to emit light, and the test signal ends in each panel area are arranged in the same way.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to a display panel mother board, a display panel, and a display device. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, TVs, laptops, and desktop computers due to their advantages of high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices. In the preparation process of traditional display panels, the light-emitting pixel patterning is usually achieved through a Fine Mask Mask (FMM). The FMM technology is mature and has rich mass production experience. However, the FMM technology also has problems such as limited precision, high development cost, and long development cycle. The maskless technology eliminates the limitations of traditional OLED processes on display screen size, resolution, and other screen body performances, and has the advantages of high performance, full-domain size, and agile delivery. Patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN117580403A, CN118678743A, CN118660490A, CN118678724A, CN118678806A, CN118742084A, CN118946184A record the relevant content of the maskless technology for reference.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Embodiments of this application provide a display panel mother board, a display panel, and a display device, aiming to improve the test efficiency of the display panel mother board.

[0005] An embodiment of the first aspect of this application provides a display panel mother board. The display panel mother board has at least two panel areas. The display panel mother board includes: a plurality of sub-pixels, and a plurality of sub-pixels are arranged in each panel area, and the arrangements of the sub-pixels in at least two panel areas are different; a plurality of test signal terminals, and a plurality of test signal terminals are arranged in each panel area. The test signal terminals in the panel area are electrically connected to the corresponding sub-pixels, and the test signal terminals are used to participate in driving the sub-pixels to emit light. Among them, the arrangements of the test signal terminals in each panel area are the same.

[0006] An embodiment of the second aspect of this application provides a display panel, which is prepared from the display panel mother board of the above embodiment.

[0007] An embodiment of the third aspect of the present application provides a display device, including the display panel of the above embodiment.

[0008] In a display panel mother board provided by an embodiment of the present application, the display panel mother board has at least two panel regions. The display panel mother board includes a plurality of sub-pixels and a plurality of test signals. A plurality of sub-pixels are arranged in each panel region, and the sub-pixels can be used to achieve light-emitting display. The arrangements of the sub-pixels in at least two panel regions are different, so that different panel regions with different sub-pixel arrangements can be used to form display panels with different sub-pixel arrangements, that is, a single display panel mother board can be used to form at least two display panels with different sub-pixel arrangements, which can facilitate the improvement of the preparation efficiency of the display panel.

[0009] A plurality of test signal terminals are arranged in each panel region. The test signal terminals in the panel region are electrically connected to the corresponding sub-pixels. The test signal terminals can be used to participate in driving the light emission of the sub-pixels, so that the test of the display panel mother board can be realized through the test signal terminals.

[0010] By setting the arrangements of the test signal terminals in each panel region to be the same, in the process of testing the display panel mother board, the same set of test devices can be used to test each panel region with different sub-pixel arrangements in the display panel mother board, so as to better improve the preparation efficiency of the display panel mother board and better reduce the cost of the test device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0012] Figure 1 is a partial cross-sectional view of a display panel provided by an embodiment of the present application; Figure 2 is a schematic structural diagram of a display panel mother board and a test device provided by an embodiment of the present application; Figure 3 is a partial structural diagram of a display panel mother board and a test device provided by an embodiment of the present application; Figure 4 is a partial structural diagram of a display panel mother board and a test device provided by another embodiment of the present application; Figure 5 is a partial structural diagram of a display panel mother board provided by an embodiment of the present application; Figure 6It is a schematic diagram of a partial structure of a display panel mother board provided by another embodiment of the present application; Figure 7 It is a schematic timing diagram of a test driving method for a display panel mother board provided by an embodiment of the present application; Figure 8 It is a schematic flowchart of a test method for a display panel mother board provided by an embodiment of the present application; Figure 9 It is a schematic diagram of a partial structure of a display panel mother board provided by still another embodiment of the present application.

[0013] Explanation of reference numerals: 10. Display panel mother board; 100. Substrate; 110. Substrate; 120. First insulating layer; 130. Second insulating layer; 140. Third insulating layer; 200. Pixel definition layer; 201. Pixel opening 300. Isolation structure; 301. Isolation opening; 301a. First opening; 301b. Second opening; 301c. Third opening; 310. First isolation part; 320. Second isolation part; 330. Conductive part; 400. Sub-pixel; 400a. Pixel group; 401. First type of sub-pixel; 402. Second type of sub-pixel; 403. Third type of sub-pixel; 410. Driving circuit; 411. Transistor; 411a. Gate; 411b. Source-drain; 412. Storage capacitor; 412a. First electrode plate; 412b. Second electrode plate; 420. Light-emitting device; 421. First electrode; 422. Light-emitting functional layer; 423. Second electrode; 500. Test signal terminal; 500a. Test group; 501. Control terminal group; 502. Switch terminal group; 503. Lighting terminal group; 510. First type of test signal terminal; 511. First type of control signal terminal; 512. First type of switch signal terminal; 513. First type of lighting signal terminal; 520. Second type of test signal terminal; 521. Second type of control signal terminal; 522. Second type of switch signal terminal; 523. Second type of lighting signal terminal; 530. Third type of test signal terminal; 531. Third type of control signal terminal; 532. Third type of switch signal terminal; 533. Third type of lighting signal terminal; 600. Test control transistor; 610. First type of control transistor; 620. Second type of control transistor; 630. Third type of control transistor; 700. Test switch transistor; 700a. Switch group; 710. First type of switch transistor; 720. Second type of switch transistor; 730. Third type of switch transistor; DL. Data signal line; CL. Connection line; SL1, control signal line; SL1a, first type of control signal line; SL1b, second type of control signal line; SL1c, third type of control signal line; SL2, switch signal line; SL2a, first type of switch signal line; SL2b, second type of switch signal line; SL2c, third type of switch signal line; SL3, lighting signal line; SL3a, first type of lighting signal line; SL3b, second type of lighting signal line; SL3c, third type of lighting signal line; PA, panel area; PA1, first type of panel area; PA2, second type of panel area; TD, test device; TD1, main body part; TD2, adapter part; TD21, signal transmission end; TD21a, first type of control transmission end; TD21b, second type of control transmission end; TD21c, third type of control transmission end; TD21d, first type of switch transmission end; TD21e, second type of switch transmission end; TD21f, third type of switch transmission end; TD21g, first type of lighting transmission end; TD21h, second type of lighting transmission end; TD21i, third type of lighting transmission end; X, first direction; Y, second direction; Z, thickness direction. Detailed implementation manners

[0014] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0015] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the elements.

[0016] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0017] Embodiments of the present application provide a display panel mother board, a display panel, and a display device. The following will describe each embodiment of the display panel mother board, the display panel, and the display device with reference to the accompanying drawings.

[0018] Figure 1 is a partial cross-sectional view of a display panel provided by an embodiment of the present application, Figure 2 is a schematic structural diagram of a display panel mother board 10 and a test device TD provided by an embodiment of the present application, Figure 3 is a partial structural diagram of a display panel mother board 10 and a test device TD provided by an embodiment of the present application, Figure 4 is a partial structural diagram of a display panel mother board 10 and a test device TD provided by another embodiment of the present application. In the figure, the X direction can be denoted as the first direction X, the Y direction in the figure can be denoted as the second direction Y, and the Z direction in the figure can be denoted as the thickness direction Z of the display panel mother board 10. The first direction X, the second direction Y, and the thickness direction Z of the display panel mother board 10 can intersect pairwise. Exemplarily, the first direction X, the second direction Y, and the thickness direction Z of the display panel mother board 10 can be perpendicular to each other pairwise.

[0019] As Figures 1 to 4 shown, an embodiment of the first aspect of the present application provides a display panel mother board 10. The display panel mother board 10 has at least two panel regions PA. The display panel mother board 10 includes: a plurality of sub-pixels 400. A plurality of sub-pixels 400 are provided in each panel region PA. The arrangement of the sub-pixels 400 in at least two panel regions PA is different; a plurality of test signal terminals 500. A plurality of test signal terminals 500 are provided in each panel region PA. The test signal terminals 500 in the panel region PA are electrically connected to the corresponding sub-pixels 400. The test signal terminals 500 are used to participate in driving the sub-pixels 400 to emit light. Among them, the arrangement of the test signal terminals 500 in each panel region PA is the same.

[0020] In a display panel mother board 10 provided by an embodiment of the present application, the display panel mother board 10 has at least two panel regions PA.

[0021] Optionally, the display panel mother board 10 can be used to fabricate a display panel. For example, the display panel mother board 10 can be used to fabricate a display panel that uses the light-emitting principle of an organic light-emitting diode to achieve light emission.

[0022] Optionally, adjacent panel regions PA may be spaced apart. A single panel region PA can be used to form a single display panel, that is, the display panel mother board 10 can be used to fabricate multiple display panels. Among them, multiple display panels can be fabricated by processing techniques such as cutting the display panel mother board 10.

[0023] Exemplarily, by processing techniques such as cutting the display panel mother board 10, each panel region PA can be separated. A single panel region PA can be used to form a single display panel. Among them, a complete single panel region PA can be used to form a single complete display panel, or after separating the panel region PA, some structures within the panel region PA (such as the test signal terminal 500 in the panel region PA described later) can also be removed to make the remaining structures in a single panel region PA form a single complete display panel.

[0024] Optionally, multiple display panel regions PA can be arranged in an array in the first direction X and the second direction Y. For example, multiple display panel regions PA can be spaced apart in the first direction X. Or, for example, multiple display panel regions PA can be spaced apart in the second direction Y.

[0025] The display panel mother board 10 includes multiple sub-pixels 400 and multiple test signal terminals 500. Multiple sub-pixels 400 are provided in each panel region PA, and the sub-pixels 400 can be used to achieve light-emitting display.

[0026] Optionally, after processing techniques such as cutting the display panel mother board 10 to fabricate multiple display panels, the sub-pixels 400 can be retained in the fabricated display panels, and the sub-pixels 400 can be used to achieve the light-emitting display of the display panels.

[0027] Optionally, the sub-pixels 400 can utilize the light-emitting principle of organic light-emitting diodes to achieve light-emitting display.

[0028] Optionally, the sub-pixels 400 may include a light-emitting device 420 and a driving circuit 410 connected to the light-emitting device 420, and the driving circuit 410 can be used to participate in driving the light-emitting device 420 to emit light.

[0029] Optionally, the display panel mother board 10 may further include a substrate 100. The driving circuit 410 can be disposed within the substrate 100, and the light-emitting device 420 can be disposed on one side of the substrate 100.

[0030] Optionally, the driving circuit 410 may include a transistor 411, a storage capacitor 412, and signal lines for connecting various devices in the driving circuit 410. Exemplarily, the transistor 411 may include a semiconductor, a gate 411a, and source / drain electrodes 411b. The storage capacitor 412 includes a first electrode plate 412a and a second electrode plate 412b.

[0031] Optionally, the substrate 100 may include a first insulating layer 120, a second insulating layer 130, and a third insulating layer 140 which are stacked. As an example, the gate 411a and the first electrode plate 412a may be located on the side of the first insulating layer 120 facing the substrate 110, the second electrode plate 412b may be located between the first insulating layer 120 and the second insulating layer 130, and the source / drain electrodes 411b may be located between the second insulating layer 130 and the third insulating layer 140.

[0032] Optionally, in the direction away from the substrate 100, the light-emitting device 420 may include a first electrode 421, a light-emitting functional layer 422, and a second electrode 423 which are stacked in sequence.

[0033] Optionally, the light-emitting functional layer 422 may include a hole injection layer (Hole Inject Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), a light-emitting structure, an electron injection layer (Electron Inject Layer, EIL), and an electron transport layer (Electron Transport Layer, ETL).

[0034] Optionally, the first electrode 421 and the second electrode 423 may serve as pixel electrodes, and one of the first electrode 421 and the second electrode 423 may serve as an anode, and the other may serve as a cathode to drive the light-emitting functional layer 422 to emit light. In the embodiments of the present application, the first electrode 421 is taken as an example of the anode and the second electrode 423 as the cathode for illustration.

[0035] Optionally, the plurality of sub-pixels 400 include a first type of sub-pixel 401, a second type of sub-pixel 402, and a third type of sub-pixel 403 with different light-emitting colors, so that the display panel formed by using the display panel mother board 10 can achieve color display. Exemplarily, the light-emitting color of the first type of sub-pixel 401 is red, the light-emitting color of the second type of sub-pixel 402 is green, and the light-emitting color of the third type of sub-pixel 403 is blue.

[0036] Optionally, a single first-type sub-pixel 401, a single second-type sub-pixel 402, and a single third-type sub-pixel 403 form a single pixel group 400a. The number of pixel groups 400a can be multiple, and multiple pixel groups 400a can be arranged in an array in the first direction X and the second direction Y. For example, multiple pixel groups 400a can be arranged at intervals in the first direction X. Again, for example, multiple pixel groups 400a can be arranged at intervals in the second direction Y.

[0037] The arrangement of the sub-pixels 400 in at least two panel regions PA is different, so that different panel regions PA with different arrangements of the sub-pixels 400 can be used to form display panels with different arrangements of the sub-pixels 400, that is, a single display panel mother board 10 can be used to form at least two display panels with different arrangements of the sub-pixels 400, which can facilitate the improvement of the preparation efficiency of the display panel.

[0038] Optionally, the display panel mother board 10 can have two panel regions PA with different arrangements of the sub-pixels 400, or have more than two panel regions PA with different arrangements of the sub-pixels 400. For the convenience of description, in the following embodiments, the display panel mother board 10 having two panel regions PA with different arrangements of the sub-pixels 400 is taken as an example for illustration.

[0039] Exemplarily, the panel region PA includes a first-type panel region PA1 and a second-type panel region PA2, and the arrangement of the sub-pixels 400 in the first-type panel region PA1 can be different from the arrangement of the sub-pixels 400 in the second-type panel region PA2.

[0040] Optionally, the fact that the arrangement of the sub-pixels 400 in at least two panel regions PA is different can mean that the relative positions of the first-type sub-pixels 401, the second-type sub-pixels 402, and the third-type sub-pixels 403 in the pixel groups 400a in at least two panel regions PA are different.

[0041] Optionally, the arrangement among the first-type sub-pixels 401, the second-type sub-pixels 402, and the third-type sub-pixels 403 in the first-type panel region PA1 is different from the arrangement among the first-type sub-pixels 401, the second-type sub-pixels 402, and the third-type sub-pixels 403 in the second-type panel region PA2.

[0042] Optionally, in the pixel group 400a within the first type of panel region PA1 and the second type of panel region PA2, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are arranged at intervals in the first direction X. The different arrangements of the sub-pixels 400 in at least two panel regions PA may mean that the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the first direction X within the first type of panel region PA1 is different from the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the first direction X within the second type of panel region PA2.

[0043] Exemplarily, in the pixel group 400a within the first type of panel region PA1, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are arranged in sequence along the first direction X. For example, as Figure 3 shown, in the pixel group 400a within the first type of panel region PA1, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are arranged in sequence in the left-to-right direction; in the pixel group 400a within the second type of panel region PA2, the second type of sub-pixels 402, the first type of sub-pixels 401, and the third type of sub-pixels 403 are arranged in sequence along the first direction X. For example, as Figure 4 shown, in the pixel group 400a within the second type of panel region PA2, the second type of sub-pixels 402, the first type of sub-pixels 401, and the third type of sub-pixels 403 are arranged in sequence in the left-to-right direction.

[0044] Optionally, the shapes of the respective panel regions PA with different arrangements of sub-pixels 400 may also be different. Exemplarily, the shapes of the first type of panel region PA1 and the second type of panel region PA2 may be different. For example, the first type of panel region PA1 may be square, and the second type of panel region PA2 may be circular.

[0045] Optionally, the arrangement densities of the sub-pixels 400 in the respective panel regions PA with different arrangements of sub-pixels 400 may also be different. Exemplarily, the arrangement density of the sub-pixels 400 within the first type of panel region PA1 is different from the arrangement density of the sub-pixels 400 within the second type of panel region PA2. For example, the arrangement density of the sub-pixels 400 within the first type of panel region PA1 may be less than the arrangement density of the sub-pixels 400 within the second type of panel region PA2.

[0046] Optionally, the arrangement density of the sub-pixels 400 in a certain panel region PA may refer to the ratio between the number of sub-pixels 400 within a certain panel region PA and the area of that panel region PA.

[0047] Optionally, the display panel may further include an isolation structure 300 disposed on one side of the substrate 100, the isolation structure 300 may enclose an isolation opening 301, the light emitting device 420 may be at least partially located in the isolation opening 301, and the isolation structure 300 may be used to participate in dividing the sub-pixels 400 of the display panel. Exemplarily, the second electrode 423 and the light emitting function layer 422 of the light emitting device 420 may be at least partially located in the isolation opening 301.

[0048] Optionally, the isolation opening 301 may include a first opening 301a, a second opening 301b and a third opening 301c, the first type of sub-pixel 401 may be at least partially located in the first opening 301a, the second type of sub-pixel 402 may be at least partially located in the second opening 301b, and the third type of sub-pixel 403 may be at least partially located in the third opening 301c.

[0049] Optionally, since the sub-pixels 400 and the isolation openings 301 are arranged corresponding to each other, that is, the arrangement of the first opening 301a, the second opening 301b and the third opening 301c in any panel area PA can be the same as the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402 and the third type of sub-pixels 403 in the panel area PA, the arrangement of the isolation openings 301 of each panel area PA with different arrangements of sub-pixels 400 can also be different. Exemplarily, the arrangement of the first opening 301a, the second opening 301b and the third opening 301c in the first type of panel area PA1 is different from the arrangement of the first opening 301a, the second opening 301b and the third opening 301c in the second type of panel area PA2.

[0050] Optionally, the isolation structure 300 includes a first isolation portion 310 and a second isolation portion 320 located on a side of the first isolation portion 310 facing away from the substrate 100 , and the second isolation portion 320 is disposed protruding from the first isolation portion 310 toward the isolation opening 301 .

[0051] By setting the second isolation portion 320 protruding from the first isolation portion 310 toward the isolation opening 301, when preparing the light-emitting device 420, part of the material of the light-emitting device 420 (for example, the material of the light-emitting functional layer 422 and the material of the second electrode 423) can be directly vapor-deposited on the entire surface, and the second isolation portion 320 can block at least part of the material used to prepare the light-emitting device 420 to separate the material of the light-emitting device 420 between adjacent sub-pixels 400, so as to form a plurality of light-emitting devices 420 that are spaced apart and located in different isolation openings 301, so that when preparing the light-emitting device 420, there is no need to set a mask with high precision, for example, when vapor-depositing part of the material of the light-emitting device 420, there is no need to set a high-precision metal mask (Fine Metal Mask, FMM), so that the production and preparation cost of the display panel motherboard 10 can be reduced.

[0052] At the same time, since there is no need to set a mask with high precision when preparing the light-emitting device 420, when preparing sub-pixels 400 with different arrangements in different panel areas PA in the display panel motherboard 10, there is no need to set a plurality of mask plates with high precision corresponding to each panel area PA with different arrangements of sub-pixels 400, thereby facilitating the formation of at least two panel areas PA with different arrangements of sub-pixels 400 on a single display panel motherboard 10, thereby effectively reducing the preparation cost of the display panel motherboard 10.

[0053] Optionally, the material of the isolation structure 300 may include a conductive material, and the second electrode 423 may be connected to the isolation structure 300 , so that the second electrodes 423 of adjacent sub-pixels 400 can be electrically connected through the isolation structure 300 to facilitate control of the second electrode 423 .

[0054] Optionally, the second electrode 423 may be connected to the first isolation portion 310 , so that the second electrodes 423 of adjacent sub-pixels 400 may be electrically connected through the first isolation portion 310 .

[0055] Optionally, the isolation structure 300 further includes a conductive portion 330 disposed on the side of the first isolation portion 310 facing the substrate 100, the conductive portion 330 may be disposed protruding from the first isolation portion 310 toward the isolation opening 301, and the second electrode 423 may be connected to the conductive portion 330. By disposing the conductive portion 330 protruding from the first isolation portion 310 toward the isolation opening 301, a larger area may be provided on the conductive portion 330 to facilitate connection with the second electrode 423, thereby facilitating electrical connection between the second electrode 423 and the isolation structure 300.

[0056] Optionally, the display panel may further include a pixel definition layer 200 disposed on one side of the substrate 100, the pixel definition layer 200 may be provided with a pixel opening 201 connected to the isolation opening 301, a portion of the structure of the light emitting device 420 may be located in the pixel opening 201, another portion of the light emitting device 420 may be located in the isolation opening 301, and the pixel definition layer 200 may also be used to participate in dividing the sub-pixels 400 of the display panel. Exemplarily, the second electrode 423 and the light emitting function layer 422 of the light emitting device 420 may extend from the pixel opening 201 to the isolation opening 301, and at least a portion of the surface of the first electrode 421 facing away from the substrate 100 may be exposed from the pixel opening 201 and connected to the light emitting function layer 422 in the pixel opening 201.

[0057] Optionally, the number of the isolation openings 301 and the number of the pixel openings 201 may be plural, and a single isolation opening 301 may be connected to a single pixel opening 201 .

[0058] Optionally, there are many ways to set the relative position between the pixel definition layer 200 and the isolation structure 300, for example, Figure 1 As shown, the isolation structure 300 can be arranged on the side of the pixel definition layer 200 away from the substrate 100, that is, the isolation structure 300 can be directly arranged on the pixel definition layer 200. Or for example, the pixel definition layer 200 can be provided with a groove structure (not shown in the figure), and at least part of the isolation structure 300 can be located in the groove structure, so that the isolation structure 300 is not easy to have an excessive height compared to the substrate 100, thereby being able to better reduce the thickness of the display panel motherboard 10. For ease of description, the following embodiments are described by taking the isolation structure 300 arranged on the side of the pixel definition layer 200 away from the substrate 100 as an example.

[0059] Multiple test signal terminals 500 are provided in each panel area PA. The test signal terminals 500 in the panel area PA are electrically connected to the corresponding sub-pixels 400. The test signal terminals 500 can be used to drive the sub-pixels 400 to emit light, so that the display panel motherboard 10 can be tested through the test signal terminals 500.

[0060] Optionally, the test signal terminal 500 may be connected to the driving circuit 410 in the sub-pixel 400, so that the test signal terminal 500 can drive the light-emitting device 420 to emit light through the driving circuit 410. Exemplarily, the test signal terminal 500 may be used to transmit a data signal (Data signal) to the driving circuit 410 in the sub-pixel 400 to participate in driving the sub-pixel 400 to emit light.

[0061] Optionally, the test signal terminal 500 can be used to participate in testing the display effect of the display panel motherboard 10. Exemplarily, the test signal terminal 500 can be used to participate in the lighting test of the display panel motherboard 10 to test the display effect of the display panel motherboard 10 after lighting (for example, spectrum, chromaticity, color difference, dark spots, bright spots, bright lines, etc.).

[0062] Optionally, a test device TD may be connected to the test signal terminal 500 , so that the test device TD can transmit a data signal to the sub-pixel 400 through the test signal terminal 500 to participate in driving the sub-pixel 400 to emit light, thereby implementing testing of the display panel motherboard 10 .

[0063] Optionally, the test device TD may include a main part TD1 and a transition part TD2, and the transition part TD2 may be arranged on at least one side of the main part TD1 in the second direction Y. For example, in a single test device TD, the transition part TD2 may be arranged on the same side of the main part TD1 in the second direction Y.

[0064] Optionally, a single transfer portion TD2 may be used to transmit a data signal to a single panel area PA to participate in driving the sub-pixel 400 in the single panel area PA to emit light. Exemplarily, a single transfer portion TD2 may have a plurality of signal transmission terminals TD21, a single signal transmission terminal TD21 may be used to connect to a single test signal terminal 500, and the main body portion TD1 may be used to send a signal to the test signal terminal 500 through the signal transmission terminal TD21, so that the test signal terminal 500 may be used to transmit a data signal to the driving circuit 410 in the sub-pixel 400 to participate in driving the sub-pixel 400 to emit light, thereby realizing the test of the display panel motherboard 10.

[0065] Optionally, the test signal terminal 500 may be disposed on one side of the substrate 100 , or a slot structure may be provided in the substrate 100 , and the test signal terminal 500 may be exposed from the slot structure in the substrate 100 to facilitate connection between the test device TD and the test signal terminal 500 .

[0066] Optionally, there may be a plurality of transfer portions TD2 , and the plurality of transfer portions TD2 may be spaced apart in the first direction X, so that a single testing device TD may test a plurality of panel areas PA spaced apart in the first direction X at the same time.

[0067] Optionally, the transition part TD2 may include a flexible printed circuit (FPC) so that the transition part TD2 may have good deformation ability, so as to facilitate the connection between the signal transmission terminal TD21 in the transition part TD2 and the test signal terminal 500 in the display panel motherboard 10 .

[0068] Optionally, the spacing between adjacent display panel areas PA may be the same or different, and the present application does not specifically limit it. When the spacing between adjacent display panel areas PA is different, the transition part TD2 including the flexible circuit board may undergo a certain deformation to facilitate the connection of each transition part TD2 in the test device TD with each panel area PA.

[0069] Optionally, the testing device TD may further include an optical instrument, which can be used to obtain optical information of the display panel motherboard 10 after the transfer part TD2 drives at least part of the sub-pixels 400 in the display panel motherboard 10 to emit light, so as to detect the display effect of the display panel motherboard 10.

[0070] Optionally, the optical instrument may include a camera, an optical probe, or other instrument for obtaining optical information. The optical instrument may be used to obtain optical information such as spectrum, chromaticity, color difference, dark spots, bright spots, and bright lines of the sub-pixels 400 in the display panel motherboard 10.

[0071] Optionally, there are many ways to arrange the first type panel area PA1 and the second type panel area PA2. Figure 2 As shown, the first type panel area PA1 can be located on the same side of the second type panel area PA2 in the first direction X, so that the first type panel area PA1 can be arranged more concentratedly in one area, and the second type panel area PA2 can be arranged more concentratedly in one area, which is conducive to the optical instrument to obtain optical information of different display panel areas PA more independently. Or for example, the first type panel area PA1 and the second type panel area PA2 can be alternately distributed in the first direction X (not shown in the figure), so that when the shapes of the first type panel area PA1 and the second type panel area PA2 are different, by setting the first type panel area PA1 and the second type panel area PA2 to be alternately distributed in the first direction X, it can be beneficial to improve the arrangement density of the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10.

[0072] By setting the arrangement of the test signal terminals 500 in each panel area PA to be the same, during the test process of the display panel motherboard 10, the same set of test equipment TD can be used to test each panel area PA with different sub-pixel 400 arrangements in the display panel motherboard 10, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the test equipment TD.

[0073] Exemplarily, by setting the arrangement of the test signal terminals 500 in each panel area PA to be the same, during the test of the display panel motherboard 10, the arrangement of the signal transmission terminals TD21 of each adapter part TD2 in the test device TD can be made the same, so that the same set of test devices TD can be used to test the various panel areas PA with different sub-pixel 400 arrangements in the display panel motherboard 10, so that during the test of the display panel motherboard 10, the various panel areas PA in the display panel motherboard 10 can be normally lit to present a picture of the desired color, and no cross-color will occur between the various panel areas PA with different sub-pixel 400 arrangements, thereby better improving the preparation efficiency of the display panel motherboard 10 and better reducing the cost of the test device TD.

[0074] Figure 5 is a partial structural diagram of a display panel motherboard 10 provided in an embodiment of the present application, Figure 6 It is a schematic diagram of a partial structure of a display panel motherboard 10 provided in another embodiment of the present application.

[0075] like Figures 3 to 6As shown, in some alternative embodiments, the multiple test signal terminals 500 include a first type of test signal terminal 510 corresponding to the first type of sub-pixels 401, a second type of test signal terminal 520 corresponding to the second type of sub-pixels 402, and a third type of test signal terminal 530 corresponding to the third type of sub-pixels 403. The arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520, and the third type of test signal terminal 530 within the first panel region PA1 is the same as the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520, and the third type of test signal terminal 530 within the second panel region PA2.

[0076] Optionally, the first type of test signal terminal 510 corresponding to the first type of sub-pixels 401 may refer to that the first type of test signal terminal 510 can be used to participate in driving the light emission of the first type of sub-pixels 401. For example, the first type of test signal terminal 510 can be used to transmit data signals to the first type of sub-pixels 401 to participate in driving the light emission of the first type of sub-pixels 401.

[0077] The second type of test signal terminal 520 corresponding to the second type of sub-pixels 402 may refer to that the second type of test signal terminal 520 can be used to participate in driving the light emission of the second type of sub-pixels 402. For example, the second type of test signal terminal 520 can be used to transmit data signals to the second type of sub-pixels 402 to participate in driving the light emission of the second type of sub-pixels 402.

[0078] The third type of test signal terminal 530 corresponding to the third type of sub-pixels 403 may refer to that the third type of test signal terminal 530 can be used to participate in driving the light emission of the third type of sub-pixels 403. For example, the third type of test signal terminal 530 can be used to transmit data signals to the third type of sub-pixels 403 to participate in driving the light emission of the third type of sub-pixels 403.

[0079] In these alternative embodiments, by setting the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520, and the third type of test signal terminal 530 within the first panel region PA1 to be the same as the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520, and the third type of test signal terminal 530 within the second panel region PA2, during the testing process of the display panel mother board 10, the same set of test device TD can be used to test the first panel region PA1 and the second panel region PA2 in the display panel mother board 10, thereby being able to better improve the preparation efficiency of the display panel mother board 10 and being able to better reduce the cost of the test device TD.

[0080] In some optional embodiments, a single first-type test signal terminal 510, a single second-type test signal terminal 520, and a single third-type test signal terminal 530 constitute a single test group 500a. In the test group 500a within the first-type panel area PA1 and the second-type panel area PA2, the first-type test signal terminal 510, the second-type test signal terminal 520, and the third-type test signal terminal 530 are spaced apart in the first direction X.

[0081] Optionally, the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 is the same as the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2, which may mean that the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the first type of panel area PA1 in the first direction X may be the same as the arrangement among the first type of test signal terminal 510, the second type of test signal terminal 520 and the third type of test signal terminal 530 in the second type of panel area PA2 in the first direction X.

[0082] Exemplarily, in the test group 500a in the first type panel area PA1 and the second type panel area PA2, the first type test signal end 510, the second type test signal end 520 and the third type test signal end 530 are all arranged in sequence along the first direction X. For example, as shown in the aforementioned figures, in the test group 500a in the first type panel area PA1 and the second type panel area PA2, the first type test signal end 510, the second type test signal end 520 and the third type test signal end 530 are all arranged in sequence from left to right.

[0083] Optionally, the plurality of signal transmission ends TD21 in a single transfer portion TD2 may be arranged at intervals in the first direction X.

[0084] In these optional embodiments, by setting the first type test signal terminal 510, the second type test signal terminal 520 and the third type test signal terminal 530 in the test group 500a within the first type panel area PA1 and the second type panel area PA2 to be spaced apart in the first direction X, the signal transmission terminal TD21 of each transfer part TD2 in the test device TD can be spaced apart along the first direction X, so that the first type panel area PA1 and the second type panel area PA2 in the display panel motherboard 10 can be tested conveniently using the same set of test devices TD, thereby better improving the preparation efficiency of the display panel motherboard 10.

[0085] In some alternative embodiments, the first type of test signal terminal 510, the second type of test signal terminal 520, and the third type of test signal terminal 530 each include a control signal terminal, a switch signal terminal, and a lighting signal terminal. The display panel mother board 10 further includes a test control transistor 600, a test switch transistor 700, and a connection line CL. The test control transistor 600 and the test switch transistor 700 are provided in each panel area PA. In a single panel area PA, the control terminal of the test control transistor 600 is connected to the control signal terminal, the sub-pixel 400 is connected to the first terminal of the test control transistor 600, the second terminal of the test control transistor 600 is connected to the first terminal of the test switch transistor 700, the control terminal of the test switch transistor 700 is connected to the switch signal terminal, and the second terminal of the test switch transistor 700 is connected to the lighting signal terminal.

[0086] Optionally, the control terminal of any transistor described in the embodiments of the present application may refer to the gate of the transistor.

[0087] Optionally, among the first terminal and the second terminal of any transistor described in the embodiments of the present application, one of them may refer to the source of the source-drain of the transistor, and the other may refer to the drain of the source-drain of the transistor. The present application does not make specific limitations on this.

[0088] Optionally, any transistor described in the embodiments of the present application may be a P-type transistor or an N-type transistor. The present application does not make specific limitations on this.

[0089] Optionally, the test control transistor 600, the test switch transistor 700, and the connection line CL may be provided in the substrate 100.

[0090] In these alternative embodiments, the test control transistor 600 can be used as a demultiplexer circuit (demux circuit) in the panel area PA. Under the action of the test device TD, the control signal terminal can provide a signal to the control terminal of the test control transistor 600 to control the conduction and cut-off of the test control transistor 600. The switch signal terminal can provide a signal to the control terminal of the test switch transistor 700 to control the conduction and cut-off of the test switch transistor 700. When both the test control transistor 600 and the test switch transistor 700 are conducting, the lighting signal terminal can provide a data signal to the sub-pixel 400 via the test switch transistor 700 and the test control transistor 600 to drive the sub-pixel 400 to emit light, thereby realizing the test of the display panel mother board 10.

[0091] In some alternative embodiments, the test signal terminal 500, the test control transistor 600, the test switch transistor 700, and the connection line CL are all disposed on the same side of the sub-pixel 400 in the second direction Y. A plurality of sub-pixels 400 having the same emission color are spaced apart in the second direction Y. The sub-pixels 400 located in the same column in the second direction Y are connected to the first end of the same test control transistor 600.

[0092] Optionally, within a single panel area PA, the sub-pixels 400 located in the same column in the second direction Y may have the same emission color.

[0093] Optionally, the display panel further includes a data signal line DL. The sub-pixels 400 located in the same column in the second direction Y are connected to the first end of the same test control transistor 600 through a single data signal line DL.

[0094] Optionally, the data signal line DL extends at least partially along the second direction Y.

[0095] In these alternative embodiments, by disposing the test signal terminal 500, the test control transistor 600, the test switch transistor 700, and the connection line CL on the same side of the sub-pixel 400 in the second direction Y, it is convenient for the test device TD to drive the emission of the sub-pixels 400 within the panel area PA from one side of the panel area PA in the second direction Y. By disposing the test signal terminal 500, the test control transistor 600, the test switch transistor 700, and the connection line CL on the same side of the sub-pixel 400 in the second direction Y, and by connecting the sub-pixels 400 located in the same column in the second direction Y to the first end of the same test control transistor 600, a single test control transistor 600 can be used to control the emission of the same-color sub-pixels 400 located in the same column in the second direction Y, thereby facilitating the testing of the display panel mother board 10.

[0096] In some alternative embodiments, the first type of test signal terminal 510 includes a first type of control signal terminal 511, a first type of switch signal terminal 512, and a first type of lighting signal terminal 513. The second type of test signal terminal 520 includes a second type of control signal terminal 521, a second type of switch signal terminal 522, and a second type of lighting signal terminal 523. The third type of test signal terminal 530 includes a third type of control signal terminal 531, a third type of switch signal terminal 532, and a third type of lighting signal terminal 533. The test control transistor 600 includes a first type of control transistor 610, a second type of control transistor 620, and a third type of control transistor 630. The test switch transistor 700 includes a first type of switch transistor 710, a second type of switch transistor 720, and a third type of switch transistor 730.

[0097] A single first - type sub - pixel 401, a single second - type sub - pixel 402, and a single third - type sub - pixel 403 form a single pixel group 400a. A single first - type control transistor 610, a single first - type switching transistor 710, a single second - type switching transistor 720, and a single third - type switching transistor 730 form a single switching group 700a.

[0098] In a single panel area PA, the control terminal of the first - type control transistor 610 is connected to the first - type control signal terminal 511, the control terminal of the second - type control transistor 620 is connected to the second - type control signal terminal 521, the control terminal of the third - type control transistor 630 is connected to the third - type control signal terminal 531. The first - type sub - pixel 401 is connected to the first terminal of the first - type control transistor 610, the second - type sub - pixel 402 is connected to the first terminal of the second - type control transistor 620, the third - type sub - pixel 403 is connected to the first terminal of the third - type control transistor 630. The second terminals of each test control transistor 600 connected to the sub - pixels 400 within the same pixel group 400a are all connected to the first terminals of each test switching transistor 700 in the switching group 700a through the same connection line CL. The control terminal of the first - type switching transistor 710 is connected to the first - type switching signal terminal 512, the control terminal of the second - type switching transistor 720 is connected to the second - type switching signal terminal 522, the control terminal of the third - type switching transistor 730 is connected to the third - type switching signal terminal 532. The second terminal of the first - type switching transistor 710 is connected to the first - type lighting signal terminal 513, the second terminal of the second - type switching transistor 720 is connected to the second - type lighting signal terminal 523, and the second terminal of the third - type switching transistor 730 is connected to the third - type lighting signal terminal 533.

[0099] Optionally, the control signal terminals described in the foregoing embodiments may include a first - type control signal terminal 511, a second - type control signal terminal 521, and a third - type control signal terminal 531. The switching signal terminals described in the foregoing embodiments may include a first - type switching signal terminal 512, a second - type switching signal terminal 522, and a third - type switching signal terminal 532. The lighting signal terminals described in the foregoing embodiments may include a first - type lighting signal terminal 513, a second - type lighting signal terminal 523, and a third - type lighting signal terminal 533.

[0100] Optionally, the signal transmission terminal TD21 may include a first - type control transmission terminal TD21a, a second - type control transmission terminal TD21b, a third - type control transmission terminal TD21c, a first - type switching transmission terminal TD21d, a second - type switching transmission terminal TD21e, a third - type switching transmission terminal TD21f, a first - type lighting transmission terminal TD21g, a second - type lighting transmission terminal TD21h, and a third - type lighting transmission terminal TD21i.

[0101] The first type of control transmission terminal TD21a can be used to connect to the first type of control signal terminal 511 to control the conduction and cutoff of the first type of control transistor 610 through the first type of control signal terminal 511. The second type of control transmission terminal TD21b can be used to connect to the second type of control signal terminal 521 to control the conduction and cutoff of the second type of control transistor 620 through the second type of control signal terminal 521. The third type of control transmission terminal TD21c can be used to connect to the third type of control signal terminal 531 to control the conduction and cutoff of the third type of control transistor 630 through the third type of control signal terminal 531.

[0102] The first type of switch transmission terminal TD21d can be used to connect to the first type of switch signal terminal 512 to control the conduction and cutoff of the first type of switch transistor 710 through the first type of switch signal terminal 512. The second type of switch transmission terminal TD21e can be used to connect to the second type of switch signal terminal 522 to control the conduction and cutoff of the second type of switch transistor 720 through the second type of switch signal terminal 522. The third type of switch transmission terminal TD21f can be used to connect to the third type of switch signal terminal 532 to control the conduction and cutoff of the third type of switch transistor 730 through the third type of switch signal terminal 532.

[0103] The first type of lighting transmission terminal TD21g can be used to connect to the first type of lighting signal terminal 513 to provide a data signal to the first type of sub-pixel 401 through the first type of lighting signal terminal 513. The second type of lighting transmission terminal TD21h can be used to connect to the second type of lighting signal terminal 523 to provide a data signal to the second type of sub-pixel 402 through the second type of lighting signal terminal 523. The third type of lighting transmission terminal TD21i can be used to connect to the third type of lighting signal terminal 533 to provide a data signal to the third type of sub-pixel 403 through the third type of lighting signal terminal 533.

[0104] In these alternative embodiments, under the action of the test device TD, the first type of control signal terminal 511, the second type of control signal terminal 521, and the third type of control signal terminal 531 can respectively provide signals to the control terminals of the first type of control transistor 610, the second type of control transistor 620, and the third type of control transistor 630 to respectively control the conduction and cutoff of the first type of control transistor 610, the second type of control transistor 620, and the third type of control transistor 630. The first type of switch signal terminal 512, the second type of switch signal terminal 522, and the third type of switch signal terminal 532 can respectively provide signals to the control terminals of the first type of switch transistor 710, the second type of switch transistor 720, and the third type of switch transistor 730 to respectively control the conduction and cutoff of the first type of switch transistor 710, the second type of switch transistor 720, and the third type of switch transistor 730. During the test process of the display panel mother board 10, each panel area PA in the display panel mother board 10 can be normally lit to present a picture of the required color, and color bleeding does not occur between the panel areas PA with different sub-pixel 400 arrangements.

[0105] When both the first type of control transistor 610 and the first type of switch transistor 710 are conducting, the first type of lighting signal terminal 513 can provide a data signal to the first type of sub-pixel 401 via the first type of switch transistor 710 and the first type of control transistor 610 to drive the first type of sub-pixel 401 to emit light. At this time, the second type of control transistor 620, the second type of switch transistor 720, the third type of control transistor 630, and the third type of switch transistor 730 can all be in the cutoff state, and the second type of lighting signal terminal 523 may not transmit a data signal (for example, at this time, the signal in the second type of lighting signal terminal 523 can be a non-data signal, and the non-data signal can cause the sub-pixel 400 not to emit light), and the third type of lighting signal terminal 533 may not transmit a data signal (for example, at this time, the signal in the third type of lighting signal terminal 533 can be a non-data signal), so that the panel area PA can present a red picture, which can facilitate the test device TD to detect the display effect of the first type of sub-pixel 401 in the display panel mother board 10.

[0106] When both the second - type control transistor 620 and the second - type switching transistor 720 are turned on, the second - type lighting signal terminal 523 can provide a data signal to the second - type sub - pixel 402 via the second - type switching transistor 720 and the second - type control transistor 620 to drive the emission of the second - type sub - pixel 402. At this time, the first - type control transistor 610, the first - type switching transistor 710, the third - type control transistor 630, and the third - type switching transistor 730 can all be in the cut - off state, and the first - type lighting signal terminal 513 may not transmit a data signal (for example, the signal in the first - type lighting signal terminal 513 can be a non - data signal at this time), and the third - type lighting signal terminal 533 may not transmit a data signal (for example, the signal in the third - type lighting signal terminal 533 can be a non - data signal at this time), so that the panel area PA can present a green screen, which is convenient for the test device TD to detect the display effect of the second - type sub - pixel 402 in the display panel mother board 10.

[0107] When both the third - type control transistor 630 and the third - type switching transistor 730 are turned on, the third - type lighting signal terminal 533 can provide a data signal to the third - type sub - pixel 403 via the third - type switching transistor 730 and the third - type control transistor 630 to drive the emission of the third - type sub - pixel 403. At this time, the first - type control transistor 610, the first - type switching transistor 710, the second - type control transistor 620, and the second - type switching transistor 720 can all be in the cut - off state, and the first - type lighting signal terminal 513 may not transmit a data signal (for example, the signal in the first - type lighting signal terminal 513 can be a non - data signal at this time), and the second - type lighting signal terminal 523 may not transmit a data signal (for example, the signal in the second - type lighting signal terminal 523 can be a non - data signal at this time), so that the panel area PA can present a blue screen, which is convenient for the test device TD to detect the display effect of the third - type sub - pixel 403 in the display panel mother board 10.

[0108] Among them, by setting that the second ends of the respective test control transistors 600 connected to the sub - pixels 400 within the same pixel group 400a are all connected to the first ends of the respective test switching transistors 700 in the switch group 700a through the same connection line CL, it is possible to better reduce the space occupied by the signal lines in the panel area PA, which is convenient for the display panel mother board 10 to be used for preparing a display panel in a wearable device with a smaller size.

[0109] Figure 7 It is a schematic timing diagram of a test driving method for a display panel mother board 10 provided by an embodiment of the present application. Figure 7 In it, T1 can indicate the test state, T1a can indicate the first stage, T1b can indicate the second stage, and T1c can indicate the third stage.

[0110] Such as Figure 7As shown, in some alternative embodiments, the display panel mother board 10 has a test state, and the test state has a first stage, a second stage, and a third stage.

[0111] Optionally, the first stage, the second stage, and the third stage may not overlap with each other, and the present application does not specifically limit the sequence of the first stage, the second stage, and the third stage. Exemplarily, the first stage may be before the second stage, and the third stage may be after the second stage; or, the first stage may be before the third stage, and the second stage may be after the third stage; or, the second stage may be before the first stage, and the third stage may be after the first stage; or, the second stage may be before the third stage, and the first stage may be after the third stage; or, the third stage may be before the first stage, and the second stage may be after the first stage; or, the third stage may be before the second stage, and the first stage may be after the second stage.

[0112] Optionally, a single test state of the display panel mother board 10 may have multiple first stages, multiple second stages, and multiple third stages. Among them, the first stage, the second stage, and the third stage may be carried out alternately.

[0113] In these alternative embodiments, in the test state, the test device TD can light up each panel area PA in the display panel mother board 10 to test the display effect of the display panel mother board 10. Among them, in the first stage, the second stage, and the third stage, the panel area PA in the display panel mother board 10 may present different display pictures.

[0114] In some alternative embodiments, in the first stage, the first type of control signal terminals 511 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the first type of control transistor 610 to conduct, and the first type of switch signal terminals 512 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the first type of switch transistor 710 to conduct.

[0115] Exemplarily, in the first stage, the signal provided by the first type of control signal terminal 511 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminal of the first type of control transistor 610 jumps to an effective level, so that the first type of control transistor 610 conducts, and the signal provided by the first type of switch signal terminal 512 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminal of the first type of switch transistor 710 jumps to an effective level, so that the first type of switch transistor 710 conducts.

[0116] Optionally, in the first stage, the first type of lighting signal terminals 513 in the first type of panel area PA1 and the second type of panel area PA2 can both be used to provide data signals to the first type of sub-pixels 401 via the first type of switching transistors 710 and the first type of control transistors 610 to drive the light emission of the first type of sub-pixels 401.

[0117] Optionally, in the first stage, the second type of control signal terminals 521 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the cut-off of the second type of control transistors 620, the third type of control signal terminals 531 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the cut-off of the third type of control transistors 630, the second type of switching signal terminals 522 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the cut-off of the second type of switching transistors 720, and the third type of switching signal terminals 532 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the cut-off of the third type of switching transistors 730.

[0118] Exemplarily, in the first stage, the signals provided by the second type of control signal terminals 521 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the second type of control transistors 620 jump to an invalid level to make the second type of control transistors 620 cut off, the signals provided by the third type of control signal terminals 531 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the third type of control transistors 630 jump to an invalid level to make the third type of control transistors 630 cut off, and the signals provided by the second type of switching signal terminals 522 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the second type of switching transistors 720 jump to an invalid level to make the second type of switching transistors 720 cut off, and the signals provided by the third type of switching signal terminals 532 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the third type of switching transistors 730 jump to an invalid level to make the third type of switching transistors 730 cut off.

[0119] Optionally, in the first stage, the second type of lighting signal terminals 523 in the first type of panel area PA1 and the second type of panel area PA2 can both stop providing data signals to the second type of sub-pixels 402, and the third type of lighting signal terminals 533 in the first type of panel area PA1 and the second type of panel area PA2 both stop providing data signals to the third type of sub-pixels 403.

[0120] In these alternative embodiments, in the first stage, the first type of sub-pixels 401 in the first type of panel region PA1 and the second type of panel region PA2 are all lit, and the second type of sub-pixels 402 and the third type of sub-pixels 403 in the first type of panel region PA1 and the second type of panel region PA2 are not lit, so that at this time, the first type of panel region PA1 and the second type of panel region PA2 of the display panel mother board 10 can both present a red picture, which can facilitate the test device TD to simultaneously detect the display effects of the first type of sub-pixels 401 in the first type of panel region PA1 and the second type of panel region PA2 of the display panel mother board 10 under the same test driving timing.

[0121] In some alternative embodiments, in the second stage, the second type of control signal terminals 521 in the first type of panel region PA1 and the second type of panel region PA2 are both used to control the second type of control transistors 620 to conduct, and the second type of switch signal terminals 522 in the first type of panel region PA1 and the second type of panel region PA2 are both used to control the second type of switch transistors 720 to conduct.

[0122] Exemplarily, in the second stage, the signals provided by the second type of control signal terminals 521 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the second type of control transistors 620 jump to an effective level to make the second type of control transistors 620 conduct, and the signals provided by the second type of switch signal terminals 522 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the second type of switch transistors 720 jump to an effective level to make the second type of switch transistors 720 conduct.

[0123] Optionally, in the second stage, the second type of lighting signal terminals 523 in the first type of panel region PA1 and the second type of panel region PA2 are both used to provide data signals to the second type of sub-pixels 402 via the second type of switch transistors 720 and the second type of control transistors 620 to drive the second type of sub-pixels 402 to emit light.

[0124] Optionally, in the second stage, the first type of control signal terminals 511 in the first type of panel region PA1 and the second type of panel region PA2 can both be used to control the first type of control transistors 610 to cut off, the third type of control signal terminals 531 in the first type of panel region PA1 and the second type of panel region PA2 are both used to control the third type of control transistors 630 to cut off, the first type of switch signal terminals 512 in the first type of panel region PA1 and the second type of panel region PA2 are both used to control the first type of switch transistors 710 to cut off, and the third type of switch signal terminals 532 in the first type of panel region PA1 and the second type of panel region PA2 are both used to control the third type of switch transistors 730 to cut off.

[0125] Exemplarily, in the second stage, the signals provided by the first type of control signal terminals 511 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the first type of control transistors 610 jump to an invalid level, so that the first type of control transistors 610 are turned off. The signals provided by the third type of control signal terminals 531 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the third type of control transistors 630 jump to an invalid level, so that the third type of control transistors 630 are turned off. Also, the signals provided by the first type of switch signal terminals 512 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the first type of switch transistors 710 jump to an invalid level, so that the first type of switch transistors 710 are turned off. The signals provided by the third type of switch signal terminals 532 in the first type of panel area PA1 and the second type of panel area PA2 to the control terminals of the third type of switch transistors 730 jump to an invalid level, so that the third type of switch transistors 730 are turned off.

[0126] Optionally, in the second state, the first type of lighting signal terminals 513 in the first type of panel area PA1 and the second type of panel area PA2 can stop providing data signals to the first type of sub-pixels 401. The third type of lighting signal terminals 533 in the first type of panel area PA1 and the second type of panel area PA2 all stop providing data signals to the third type of sub-pixels 403.

[0127] In these alternative embodiments, in the second stage, the second type of sub-pixels 402 in the first type of panel area PA1 and the second type of panel area PA2 are all lit, and the first type of sub-pixels 401 and the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 are not lit. At this time, the first type of panel area PA1 and the second type of panel area PA2 of the display panel mother board 10 can present a green picture, which is convenient for the test device TD to simultaneously detect the display effects of the second type of sub-pixels 402 in the first type of panel area PA1 and the second type of panel area PA2 of the display panel mother board 10 under the same test driving timing.

[0128] In some alternative embodiments, in the third stage, the third type of control signal terminals 531 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the third type of control transistors 630 to conduct, and the third type of switch signal terminals 532 in the first type of panel area PA1 and the second type of panel area PA2 are both used to control the third type of switch transistors 730 to conduct.

[0129] Exemplarily, in the third stage, the signals provided by the third type of control signal terminals 531 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the third type of control transistors 630 jump to the effective level, so that the third type of control transistors 630 are turned on, and the signals provided by the third type of switch signal terminals 532 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the third type of switch transistors 730 jump to the effective level, so that the third type of switch transistors 730 are turned on.

[0130] Optionally, in the third stage, the third type of lighting signal terminals 533 in the first type of panel region PA1 and the second type of panel region PA2 can be used to provide data signals to the third type of sub-pixels 403 via the third type of switch transistors 730 and the third type of control transistors 630 to drive the emission of the third type of sub-pixels 403.

[0131] Optionally, in the third stage, the first type of control signal terminals 511 in the first type of panel region PA1 and the second type of panel region PA2 are all used to control the cut-off of the first type of control transistors 610, the second type of control signal terminals 521 in the first type of panel region PA1 and the second type of panel region PA2 are all used to control the cut-off of the second type of control transistors 620, the first type of switch signal terminals 512 in the first type of panel region PA1 and the second type of panel region PA2 are all used to control the cut-off of the first type of switch transistors 710, and the second type of switch signal terminals 522 in the first type of panel region PA1 and the second type of panel region PA2 are all used to control the cut-off of the second type of switch transistors 720.

[0132] Exemplarily, in the third stage, the signals provided by the first type of control signal terminals 511 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the first type of control transistors 610 jump to the invalid level, so that the first type of control transistors 610 are cut off, the signals provided by the second type of control signal terminals 521 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the second type of control transistors 620 jump to the invalid level, so that the second type of control transistors 620 are cut off, and the signals provided by the first type of switch signal terminals 512 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the first type of switch transistors 710 jump to the invalid level, so that the first type of switch transistors 710 are cut off, and the signals provided by the second type of switch signal terminals 522 in the first type of panel region PA1 and the second type of panel region PA2 to the control terminals of the second type of switch transistors 720 jump to the invalid level, so that the second type of switch transistors 720 are cut off.

[0133] Optionally, in the third stage, the first type of lighting signal terminals 513 in the first type of panel area PA1 and the second type of panel area PA2 can stop providing data signals to the first type of sub-pixels 401, and the second type of lighting signal terminals 523 in the first type of panel area PA1 and the second type of panel area PA2 can stop providing data signals to the second type of sub-pixels 402.

[0134] In these optional embodiments, in the third stage, the third type of sub-pixels 403 in both the first type of panel area PA1 and the second type of panel area PA2 are lit, and the first type of sub-pixels 401 and the second type of sub-pixels 402 in both the first type of panel area PA1 and the second type of panel area PA2 are not lit, so that at this time, both the first type of panel area PA1 and the second type of panel area PA2 of the display panel mother board 10 can present a blue screen, which is convenient for the test device TD to simultaneously detect the display effects of the third type of sub-pixels 403 in the first type of panel area PA1 and the second type of panel area PA2 of the display panel mother board 10 under the same test driving timing.

[0135] In some optional embodiments, the first direction X can be the row direction in which the sub-pixels 400 are arranged, and the second direction Y can be the column direction in which the sub-pixels 400 are arranged. In the test state, scan signals can be provided to the sub-pixels 400 in each row one by one, so as to light the sub-pixels 400 in each row one by one.

[0136] Optionally, the test state further includes a scanning stage. The scanning stages of the sub-pixels 400 in each row may not overlap with each other, and the present application does not specifically limit the order of the scanning stages of the sub-pixels 400 in each row. Exemplarily, the scanning stage of the i-th row of sub-pixels 400 may be before the scanning stage of the (i + 1)-th row of sub-pixels 400, where i can be a positive integer and i ≥ 1.

[0137] Optionally, the scanning stage of any row of sub-pixels 400 can at least partially overlap with at least one first stage, at least one second stage, and at least one third stage, so that when a scan signal is provided to any row of sub-pixels 400, any sub-pixel 400 in that row of sub-pixels 400 can be lit (for example, when a certain row of sub-pixels 400 is in the scanning stage and at this time is in the first stage of the test state, the first type of sub-pixels 401 in that row of sub-pixels 400 can be lit).

[0138] Figure 8 It is a schematic flow chart of a method for testing a display panel mother board provided by an embodiment of the present application.

[0139] As Figure 8As shown in the figure, based on the display panel mother board 10 in the test state described in the foregoing embodiments, the embodiments of the present application further provide a test method for the display panel mother board. The test method for the display panel mother board can be used to test the display panel mother board 10 in any of the foregoing embodiments. The test method for the display panel mother board includes: Step S10: Provide an effective level to the control terminal of the first type of control transistor 610 through the first type of control signal terminal 511 in the first type of panel area PA1 and the second type of panel area PA2, so that the first type of control transistor 610 is turned on, and provide an effective level to the control terminal of the first type of switch transistor 710 through the first type of switch signal terminal 512 in the first type of panel area PA1 and the second type of panel area PA2, so that the first type of switch transistor 710 is turned on.

[0140] Optionally, when the first type of control transistor 610 is controlled to be turned on through the first type of control signal terminal 511 in the first type of panel area PA1 and the second type of panel area PA2, and the first type of switch transistor 710 is controlled to be turned on through the first type of switch signal terminal 512 in the first type of panel area PA1 and the second type of panel area PA2, the display panel mother board 10 can be made to be in the first stage in any of the foregoing embodiments.

[0141] Optionally, step S10 may further include: providing a data signal to the first type of lighting signal terminal 513 in the first type of panel area PA1 and the second type of panel area PA2. By providing a data signal to the first type of lighting signal terminal 513 in the first type of panel area PA1 and the second type of panel area PA2, the data signal can drive the first type of sub-pixel 401 to emit light via the first type of switch transistor 710 and the first type of control transistor 610.

[0142] Step S20: Provide an effective level to the control terminal of the second type of control transistor 620 through the second type of control signal terminal 521 in the first type of panel area PA1 and the second type of panel area PA2, so that the second type of control transistor 620 is turned on, and provide an effective level to the control terminal of the second type of switch transistor 720 through the second type of switch signal terminal 522 in the first type of panel area PA1 and the second type of panel area PA2, so that the second type of switch transistor 720 is turned on.

[0143] Optionally, when the second type of control transistor 620 is controlled to be turned on through the second type of control signal terminal 521 in the first type of panel area PA1 and the second type of panel area PA2, and the second type of switch transistor 720 is controlled to be turned on through the second type of switch signal terminal 522 in the first type of panel area PA1 and the second type of panel area PA2, the display panel mother board 10 can be made to be in the second stage in any of the foregoing embodiments.

[0144] Optionally, step S20 may further include: providing a data signal to the second type of lighting signal terminals 523 in the first type of panel region PA1 and the second type of panel region PA2. By providing the data signal through the second type of lighting signal terminals 523 in the first type of panel region PA1 and the second type of panel region PA2, the data signal can drive the emission of the second type of sub-pixels 402 via the second type of switching transistors 720 and the second type of control transistors 620.

[0145] Step S30: Provide an effective level to the control terminal of the third type of control transistor 630 through the third type of control signal terminals 531 in the first type of panel region PA1 and the second type of panel region PA2, so that the third type of control transistor 630 is turned on, and provide an effective level to the control terminal of the third type of switching transistor 730 through the third type of switching signal terminals 532 in the first type of panel region PA1 and the second type of panel region PA2, so that the third type of switching transistor 730 is turned on.

[0146] Optionally, when the third type of control transistor 630 is controlled to be turned on through the third type of control signal terminals 531 in the first type of panel region PA1 and the second type of panel region PA2, and the third type of switching transistor 730 is controlled to be turned on through the first type of panel region PA1 and the second type of panel region PA2, the display panel mother board 10 can be made to be in the third stage in any of the foregoing embodiments.

[0147] Optionally, step S30 may further include: providing a data signal to the third type of lighting signal terminals 533 in the first type of panel region PA1 and the second type of panel region PA2. By providing the data signal to the third type of lighting signal terminals 533 in the first type of panel region PA1 and the second type of panel region PA2, the data signal can drive the emission of the third type of sub-pixels 403 via the third type of switching transistors 730 and the third type of control transistors 630.

[0148] In some optional embodiments, the arrangement among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 in the first type of panel region PA1 is the same as the arrangement among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 in the second type of panel region PA2.

[0149] The arrangement among the first type of switching signal terminals 512, the second type of switching signal terminals 522, and the third type of switching signal terminals 532 in the first type of panel region PA1 is the same as the arrangement among the first type of switching signal terminals 512, the second type of switching signal terminals 522, and the third type of switching signal terminals 532 in the second type of panel region PA2.

[0150] The arrangement among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 within the first type of panel area PA1 is the same as the arrangement among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 within the second type of panel area PA2.

[0151] In these alternative embodiments, by setting the same arrangement among the respective test signal terminals 500 within the first type of panel area PA1 and the second type of panel area PA2, during the testing process of the display panel mother board 10, the same set of test devices TD can be used to test the first type of panel area PA1 and the second type of panel area PA2 in the display panel mother board 10. Thus, the preparation efficiency of the display panel mother board 10 can be improved well, and the cost of the test device TD can be reduced well.

[0152] In some alternative embodiments, within the first type of panel area PA1 and the second type of panel area PA2, the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 are spaced apart in the first direction X.

[0153] Optionally, the arrangement among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 within the first type of panel area PA1 being the same as the arrangement among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 within the second type of panel area PA2 may mean that the arrangement in the first direction X among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 within the first type of panel area PA1 is the same as the arrangement in the first direction X among the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 within the second type of panel area PA2.

[0154] Exemplarily, within the first type of panel area PA1 and the second type of panel area PA2, the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 are all arranged in sequence along the first direction X. For example, as shown in the foregoing drawings, within the first type of panel area PA1 and the second type of panel area PA2, the first type of control signal terminals 511, the second type of control signal terminals 521, and the third type of control signal terminals 531 are all arranged in sequence along the direction from left to right.

[0155] In some alternative embodiments, within the first type of panel area PA1 and the second type of panel area PA2, the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 are spaced apart in the first direction X.

[0156] Optionally, the arrangement among the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 in the first type of panel area PA1 is the same as the arrangement among the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 in the second type of panel area PA2. This may mean that the arrangement in the first direction X among the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 in the first type of panel area PA1 is the same as the arrangement in the first direction X among the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 in the second type of panel area PA2.

[0157] Exemplarily, in the first type of panel area PA1 and the second type of panel area PA2, the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 are all arranged in sequence along the first direction X. For example, as shown in the foregoing drawings, in the first type of panel area PA1 and the second type of panel area PA2, the first type of switch signal terminals 512, the second type of switch signal terminals 522, and the third type of switch signal terminals 532 are all arranged in sequence in the direction from left to right.

[0158] In some optional embodiments, in the first type of panel area PA1 and the second type of panel area PA2, the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 are arranged at intervals in the first direction X.

[0159] Optionally, the arrangement among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 in the first type of panel area PA1 is the same as the arrangement among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 in the second type of panel area PA2. This may mean that the arrangement in the first direction X among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 in the first type of panel area PA1 is the same as the arrangement in the first direction X among the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 in the second type of panel area PA2.

[0160] Exemplarily, in the first type of panel area PA1 and the second type of panel area PA2, the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 are all arranged in sequence along the first direction X. For example, as shown in the foregoing drawings, in the first type of panel area PA1 and the second type of panel area PA2, the first type of lighting signal terminals 513, the second type of lighting signal terminals 523, and the third type of lighting signal terminals 533 are all arranged in sequence in the direction from left to right.

[0161] In some alternative embodiments, a single first - type control signal terminal 511, a single second - type control signal terminal 521, and a single third - type control signal terminal 531 form a control terminal group 501; a single first - type switch signal terminal 512, a single second - type switch signal terminal 522, and a single third - type switch signal terminal 532 form a switch terminal group 502; a single first - type lighting signal terminal 513, a single second - type lighting signal terminal 523, and a single third - type lighting signal terminal 533 form a lighting terminal group 503. The arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the first - type panel area PA1 is the same as the arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the second - type panel area PA2.

[0162] Optionally, the test group 500a described in the foregoing embodiments may include the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503.

[0163] In these alternative embodiments, by setting the arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the first - type panel area PA1 to be the same as the arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the second - type panel area PA2, during the testing process of the display panel mother board 10, the same set of test device TD can be used to test the first - type panel area PA1 and the second - type panel area PA2 in the display panel mother board 10. Thus, the preparation efficiency of the display panel mother board 10 can be improved well, and the cost of the test device TD can be reduced well.

[0164] In some alternative embodiments, within the first - type panel area PA1 and the second - type panel area PA2, the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 are spaced apart in the first direction X.

[0165] Optionally, the fact that the arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the first - type panel area PA1 is the same as the arrangement among the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the second - type panel area PA2 may mean that the arrangement of the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the first - type panel area PA1 in the first direction X is the same as the arrangement of the control terminal group 501, the switch terminal group 502, and the lighting terminal group 503 within the second - type panel area PA2 in the first direction X.

[0166] Exemplarily, in the first type of panel area PA1 and the second type of panel area PA2, the lighting terminal group 503, the switch terminal group 502, and the control terminal group 501 are arranged in sequence along the first direction X. For example, as shown in the foregoing drawings, in the first type of panel area PA1 and the second type of panel area PA2, the lighting terminal group 503, the switch terminal group 502, and the control terminal group 501 are arranged in sequence along the direction from left to right.

[0167] In some optional embodiments, the distance between adjacent first type of test signal terminals 510 and second type of test signal terminals 520 in the first type of panel area PA1 is equal to the distance between adjacent first type of test signal terminals 510 and second type of test signal terminals 520 in the second type of panel area PA2, and / or, the distance between adjacent first type of test signal terminals 510 and third type of test signal terminals 530 in the first type of panel area PA1 is equal to the distance between adjacent first type of test signal terminals 510 and third type of test signal terminals 530 in the second type of panel area PA2, and / or, the distance between adjacent second type of test signal terminals 520 and third type of test signal terminals 530 in the first type of panel area PA1 is equal to the distance between adjacent second type of test signal terminals 520 and third type of test signal terminals 530 in the second type of panel area PA2.

[0168] Optionally, the distance between adjacent first type of control signal terminals 511 and second type of control signal terminals 521 in the first type of panel area PA1 is equal to the distance between adjacent first type of control signal terminals 511 and second type of control signal terminals 521 in the second type of panel area PA2.

[0169] Optionally, the distance between adjacent second type of control signal terminals 521 and third type of control signal terminals 531 in the first type of panel area PA1 is equal to the distance between adjacent second type of control signal terminals 521 and third type of control signal terminals 531 in the second type of panel area PA2.

[0170] Optionally, the distance between adjacent first type of switch signal terminals 512 and second type of switch signal terminals 522 in the first type of panel area PA1 is equal to the distance between adjacent first type of switch signal terminals 512 and second type of switch signal terminals 522 in the second type of panel area PA2.

[0171] Optionally, the distance between adjacent second type of switch signal terminals 522 and third type of switch signal terminals 532 in the first type of panel area PA1 is equal to the distance between adjacent second type of switch signal terminals 522 and third type of switch signal terminals 532 in the second type of panel area PA2.

[0172] Optionally, the distance between adjacent first type lighting signal terminals 513 and second type lighting signal terminals 523 in the first type panel area PA1 is equal to the distance between adjacent first type lighting signal terminals 513 and second type lighting signal terminals 523 in the second type panel area PA2.

[0173] Optionally, the distance between adjacent second type lighting signal terminals 523 and third type lighting signal terminals 533 in the first type panel area PA1 is equal to the distance between adjacent second type lighting signal terminals 523 and third type lighting signal terminals 533 in the second type panel area PA2.

[0174] In these optional embodiments, by setting the distances between corresponding adjacent two test signal terminals 500 in the first type panel area PA1 and the second type panel area PA2 to be equal, during the test process of the display panel mother board 10, the same set of test device TD can be used to test the first type panel area PA1 and the second type panel area PA2 in the display panel mother board 10, thereby being able to better improve the preparation efficiency of the display panel mother board 10 and being able to better reduce the cost of the test device TD.

[0175] In some optional embodiments, the first type control transistor 610, the second type control transistor 620, and the third type control transistor 630 are arranged at intervals in the first direction X, and / or, the first type switch transistor 710, the second type switch transistor 720, and the third type switch transistor 730 are arranged at intervals in the first direction X.

[0176] In this optional embodiment, by setting the test control transistors 600 to be arranged at intervals in the first direction X and setting the test switch transistors 700 to be arranged at intervals in the first direction X, it is convenient for each test control transistor 600 to be connected to multiple columns of sub-pixels 400 arranged at intervals in the first direction X.

[0177] In some optional embodiments, the arrangement of the first type switch transistor 710, the second type switch transistor 720, and the third type switch transistor 730 in the first type panel area PA1 is the same as the arrangement of the first type switch transistor 710, the second type switch transistor 720, and the third type switch transistor 730 in the second type panel area PA2.

[0178] Optionally, the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the first - type panel region PA1 is the same as the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the second - type panel region PA2. This can mean that the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the first - type panel region PA1 in the first direction X is the same as the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the second - type panel region PA2 in the first direction X.

[0179] Exemplarily, in the first - type panel region PA1 and the second - type panel region PA2, the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 are arranged in sequence along the first direction X. For example, as shown in the foregoing figures, in the first - type panel region PA1 and the second - type panel region PA2, the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 are arranged in sequence in the direction from left to right.

[0180] In this optional embodiment, by setting the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the first - type panel region PA1 to be the same as the arrangement among the first - type switching transistors 710, the second - type switching transistors 720, and the third - type switching transistors 730 in the second - type panel region PA2, it is convenient to connect each test signal terminal 500 to each test switching transistor 700 in the first - type panel region PA1 and the second - type panel region PA2 when the arrangements of the test signal terminals 500 in each panel region PA are the same.

[0181] As Figure 5 and Figure 6 shown, in some optional embodiments, the arrangement among the first - type control transistors 610, the second - type control transistors 620, and the third - type control transistors 630 in the first - type panel region PA1 is different from the arrangement among the first - type control transistors 610, the second - type control transistors 620, and the third - type control transistors 630 in the second - type panel region PA2.

[0182] Optionally, the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first panel area PA1 is different from the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second panel area PA2. This may mean that the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first panel area PA1 in the first direction X is different from the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second panel area PA2 in the first direction X.

[0183] Exemplarily, when in the pixel group 400a in the first panel area PA1, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are arranged in sequence along the first direction X, and in the pixel group 400a in the second panel area PA2, the second type of sub-pixels 402, the first type of sub-pixels 401, and the third type of sub-pixels 403 are arranged in sequence along the first direction X, in the first panel area PA1, the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 are all arranged in sequence along the first direction X, and in the second panel area PA2, the second type of control transistors 620, the first type of control transistors 610, and the third type of control transistors 630 are all arranged in sequence along the first direction X.

[0184] In these alternative embodiments, since the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the first type of panel area PA1 is different from the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the second type of panel area PA2, therefore, by setting the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel area PA1 to be different from the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel area PA2, the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel area PA1 can be set according to the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the first type of panel area PA1, so as to facilitate the connection of each test control transistor 600 in the first type of panel area PA1 to the corresponding sub-pixel 400. It also enables the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel area PA2 to be set according to the arrangement of the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 in the second type of panel area PA2, so as to facilitate the connection of each test control transistor 600 in the second type of panel area PA2 to the corresponding sub-pixel 400.

[0185] Figure 9 It is a schematic partial structure diagram of a display panel mother board 10 provided by another embodiment of the present application.

[0186] As Figure 5 and Figure 9 shown, in some alternative embodiments, the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel area PA1 is the same as the arrangement of the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel area PA2.

[0187] Optionally, the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel region PA1 is the same as the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel region PA2. This can mean that the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel region PA1 in the first direction X is the same as the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel region PA2 in the first direction X.

[0188] Exemplarily, when in the pixel group 400a in the first type of panel region PA1, the first type of sub-pixels 401, the second type of sub-pixels 402, and the third type of sub-pixels 403 are arranged in sequence along the first direction X, and in the pixel group 400a in the second type of panel region PA2, the second type of sub-pixels 402, the first type of sub-pixels 401, and the third type of sub-pixels 403 are arranged in sequence along the first direction X, in the first type of panel region PA1 and the second type of panel region PA2, the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 are all arranged in sequence along the first direction X.

[0189] In these optional embodiments, by setting the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the first type of panel region PA1 to be the same as the arrangement among the first type of control transistors 610, the second type of control transistors 620, and the third type of control transistors 630 in the second type of panel region PA2, it is convenient for the design of the display panel mother board 10.

[0190] In some optional embodiments, the display panel further includes a control signal line SL1, a switch signal line SL2, and a lighting signal line SL3. In a single panel region PA, the control end of the test control transistor 600 is connected to the control signal end through the control signal line SL1, the control end of the test switch transistor 700 is connected to the switch signal end through the switch signal line SL2, and the second end of the test switch transistor 700 is connected to the lighting signal end through the lighting signal line SL3. Among them, at least part of the control signal line SL1 extends along the first direction X, and / or at least part of the switch signal line SL2 extends along the first direction X, and / or at least part of the lighting signal line SL3 extends along the first direction X.

[0191] Optionally, the control signal line SL1 may include a first type of control signal line SL1a connected to the control terminal of the first type of control transistor 610, a second type of control signal line SL1b connected to the control terminal of the second type of control transistor 620, and a third type of control signal line SL1c connected to the control terminal of the third type of control transistor 630.

[0192] Optionally, the switch signal line SL2 may include a first type of switch signal line SL2a connected to the control terminal of the first type of switch transistor 710, a second type of switch signal line SL2b connected to the control terminal of the second type of switch transistor 720, and a third type of switch signal line SL2c connected to the control terminal of the third type of switch transistor 730.

[0193] Optionally, the lighting signal line SL3 may include a first type of lighting signal line SL3a connected to the second terminal of the first type of switch transistor 710, a second type of lighting signal line SL3b connected to the second terminal of the second type of switch transistor 720, and a third type of lighting signal line SL3c connected to the second terminal of the third type of switch transistor 730.

[0194] In these optional embodiments, by arranging the control signal line SL1, the switch signal line SL2, and the lighting signal line SL3 to extend along the first direction X, it is convenient to connect each signal line to each test control transistor 600 and each test switch transistor 700 arranged in the first direction X, thereby improving the routing efficiency in the display panel mother board 10.

[0195] An embodiment of the second aspect of the present application provides a display panel, which can be formed by the display panel mother board 10 of the above embodiment. Since the display panel provided by the embodiment of the second aspect of the present application can be formed by the display panel mother board 10 of the above embodiment. Therefore, the display panel provided by the embodiment of the second aspect of the present application has the same or similar beneficial effects as the display panel mother board 10 of the corresponding embodiment of the first aspect, which will not be elaborated here.

[0196] Optionally, the display panel mother board 10 of any of the above embodiments can be processed by cutting or other processes to separate each panel area PA, so that a single panel area can be used to form a single display panel provided by the embodiment of the second aspect of the present application. Among them, a complete single panel area PA can be used to form a single complete display panel, or after separating the panel area PA, some structures within the panel area PA (such as the test signal terminal 500 in the panel area PA of any of the foregoing embodiments) can also be removed to make the structures retained in the single panel area form a single complete display panel.

[0197] An embodiment of the third aspect of the present application provides a display device, which includes the display panel of any of the above embodiments. Since the display device provided by the embodiment of the third aspect of the present application includes the display panel of any of the embodiments of the second aspect. Therefore, the display device provided by the embodiment of the third aspect of the present application has the beneficial effects of the display panel of any of the embodiments of the second aspect, which will not be elaborated herein.

[0198] The display device in the embodiments of the present application includes, but is not limited to, wearable devices with display functions (for example, watches, earphones, clothing, etc. with display functions), mobile phones, personal digital assistants (abbreviated as PDA), tablet computers, e-books, televisions, access control devices, smart landline phones, consoles, and other devices with display functions.

[0199] In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel motherboard, characterized in that: The display panel motherboard has at least two panel areas, and the display panel motherboard includes: A plurality of sub-pixels, each of the panel regions is provided with the plurality of sub-pixels, and the sub-pixels in at least two of the panel regions are arranged differently; A plurality of test signal terminals, each of which is provided in each panel region, the test signal terminals in the panel region are electrically connected to the corresponding sub-pixels, and the test signal terminals are used to participate in driving the sub-pixels to emit light, Wherein, the arrangement of the test signal terminals in each of the panel areas is the same.

2. The display panel motherboard according to claim 1, characterized in that: The plurality of sub-pixels include a first type of sub-pixels, a second type of sub-pixels, and a third type of sub-pixels having different luminous colors, and the panel area includes a first type of panel area and a second type of panel area. The arrangement of the first type of sub-pixels, the second type of sub-pixels and the third type of sub-pixels in the first type of panel area is different from the arrangement of the first type of sub-pixels, the second type of sub-pixels and the third type of sub-pixels in the second type of panel area; And / or, an arrangement density of the sub-pixels in the first type of panel area is different from an arrangement density of the sub-pixels in the second type of panel area.

3. The display panel motherboard according to claim 2, characterized in that: A single sub-pixel of the first type, a single sub-pixel of the second type, and a single sub-pixel of the third type constitute a single pixel group, and a plurality of the pixel groups are arranged at intervals in the first direction. In the pixel groups in the first type of panel area and the second type of panel area, the first type of sub-pixels, the second type of sub-pixels and the third type of sub-pixels are arranged at intervals in the first direction; in the pixel groups in the first type of panel area, the first type of sub-pixels, the second type of sub-pixels and the third type of sub-pixels are arranged in sequence along the first direction, In the pixel group within the second type of panel area, the second type of sub-pixels, the first type of sub-pixels and the third type of sub-pixels are arranged in sequence along the first direction.

4. The display panel motherboard according to claim 2, characterized in that: The plurality of test signal terminals include a first type of test signal terminal corresponding to the first type of sub-pixel, a second type of test signal terminal corresponding to the second type of sub-pixel, and a third type of test signal terminal corresponding to the third type of sub-pixel. The arrangement of the first type of test signal terminal, the second type of test signal terminal and the third type of test signal terminal in the first type of panel area is the same as the arrangement of the first type of test signal terminal, the second type of test signal terminal and the third type of test signal terminal in the second type of panel area.

5. The display panel motherboard according to claim 4, characterized in that: A single first-type test signal terminal, a single second-type test signal terminal, and a single third-type test signal terminal constitute a single test group. In the test group within the first-type panel area and the second-type panel area, the first-type test signal terminal, the second-type test signal terminal, and the third-type test signal terminal are spaced apart in the first direction. In the test groups within the first type of panel area and the second type of panel area, the first type of test signal ends, the second type of test signal ends, and the third type of test signal ends are arranged in sequence along the first direction.

6. The display panel motherboard according to claim 4, characterized in that: The spacing between the adjacent first-type test signal terminals and the second-type test signal terminals in the first-type panel area is equal to the spacing between the adjacent first-type test signal terminals and the second-type test signal terminals in the second-type panel area. and / or, the spacing between adjacent first-type test signal terminals and third-type test signal terminals in the first-type panel area is equal to the spacing between adjacent first-type test signal terminals and third-type test signal terminals in the second-type panel area, And / or, the spacing between adjacent second-type test signal ends and third-type test signal ends in the first-type panel area is equal to the spacing between adjacent second-type test signal ends and third-type test signal ends in the second-type panel area.

7. The display panel motherboard according to claim 4, characterized in that: The first type of test signal terminal, the second type of test signal terminal and the third type of test signal terminal all include a control signal terminal, a switch signal terminal and a lighting signal terminal. The display panel motherboard further includes a test control transistor, a test switch transistor and a connecting line, and each of the panel regions is provided with the test control transistor and the test switch transistor. In a single panel area, the control end of the test control transistor is connected to the control signal end, the sub-pixel is connected to the first end of the test control transistor, the second end of the test control transistor is connected to the first end of the test switch transistor, the control end of the test switch transistor is connected to the switch signal end, and the second end of the test switch transistor is connected to the lighting signal end.

8. The display panel motherboard according to claim 7, characterized in that: The test signal terminal, the test control transistor, the test switch transistor and the connecting line are all arranged on the same side of the sub-pixel in the second direction, and the multiple sub-pixels with the same luminous color are arranged at intervals in the second direction, and the sub-pixels located in the same column in the second direction are connected to the first end of the same test control transistor.

9. The display panel motherboard according to claim 7, characterized in that: The first type of test signal terminal includes a first type of control signal terminal, a first type of switch signal terminal and a first type of lighting signal terminal, the second type of test signal terminal includes a second type of control signal terminal, a second type of switch signal terminal and a second type of lighting signal terminal, and the third type of test signal terminal includes a third type of control signal terminal, a third type of switch signal terminal and a third type of lighting signal terminal. The test control transistors include a first type of control transistors, a second type of control transistors and a third type of control transistors, and the test switch transistors include a first type of switch transistors, a second type of switch transistors and a third type of switch transistors. A single first-type sub-pixel, a single second-type sub-pixel and a single third-type sub-pixel constitute a single pixel group, a single first-type control transistor, a single first-type switch transistor, a single second-type switch transistor and a single third-type switch transistor constitute a single switch group, In a single panel area, the control end of the first type of control transistor is connected to the first type of control signal end, the control end of the second type of control transistor is connected to the second type of control signal end, the control end of the third type of control transistor is connected to the third type of control signal end, the first type of sub-pixel is connected to the first end of the first type of control transistor, the second type of sub-pixel is connected to the first end of the second type of control transistor, the third type of sub-pixel is connected to the first end of the third type of control transistor, and the second end of each of the test control transistors connected to the sub-pixels in the same pixel group is connected to the first end of each of the test switch transistors in the switch group through the same connection line. The control end of the first type of switching transistor is connected to the first type of switching signal end, the control end of the second type of switching transistor is connected to the second type of switching signal end, the control end of the third type of switching transistor is connected to the third type of switching signal end, the second end of the first type of switching transistor is connected to the first type of lighting signal end, the second end of the second type of switching transistor is connected to the second type of lighting signal end, and the second end of the third type of switching transistor is connected to the third type of lighting signal end.

10. The display panel motherboard according to claim 9, characterized in that: The arrangement of the first type of control signal terminals, the second type of control signal terminals and the third type of control signal terminals in the first type of panel area is the same as the arrangement of the first type of control signal terminals, the second type of control signal terminals and the third type of control signal terminals in the second type of panel area. The arrangement of the first type of switch signal terminals, the second type of switch signal terminals and the third type of switch signal terminals in the first type of panel area is the same as the arrangement of the first type of switch signal terminals, the second type of switch signal terminals and the third type of switch signal terminals in the second type of panel area. The arrangement of the first type of lighting signal terminal, the second type of lighting signal terminal and the third type of lighting signal terminal in the first type of panel area is the same as the arrangement of the first type of lighting signal terminal, the second type of lighting signal terminal and the third type of lighting signal terminal in the second type of panel area.

11. The display panel motherboard according to claim 10, characterized in that: In the first type panel area and the second type panel area, the first type control signal end, the second type control signal end and the third type control signal end are arranged at intervals in the first direction, and / or, in the first type of panel area and the second type of panel area, the first type of switch signal end, the second type of switch signal end and the third type of switch signal end are arranged at intervals in the first direction, And / or, in the first type of panel area and the second type of panel area, the first type of lighting signal end, the second type of lighting signal end and the third type of lighting signal end are arranged at intervals in the first direction.

12. The display panel motherboard according to claim 9, characterized in that: A single first-type control signal terminal, a single second-type control signal terminal and a single third-type control signal terminal constitute a control terminal group. A single first-type switch signal terminal, a single second-type switch signal terminal and a single third-type switch signal terminal constitute a switch terminal group, A single first-type lighting signal terminal, a single second-type lighting signal terminal and a single third-type lighting signal terminal constitute a lighting terminal group. The arrangement of the control end group, the switch end group and the lighting end group in the first type panel area is the same as the arrangement of the control end group, the switch end group and the lighting end group in the second type panel area.

13. The display panel motherboard according to claim 12, characterized in that: In the first type panel area and the second type panel area, the control end group, the switch end group and the lighting end group are spaced apart in a first direction.

14. The display panel motherboard according to claim 9, characterized in that: The display panel motherboard has a test state, and the test state has a first stage, a second stage and a third stage. In the first stage, the first type of control signal terminals in the first type of panel area and the second type of panel area are both used to control the first type of control transistor to be turned on, and the first type of switch signal terminals in the first type of panel area and the second type of panel area are both used to control the first type of switch transistor to be turned on, In the second stage, the second type of control signal terminals in the first type of panel area and the second type of panel area are both used to control the conduction of the second type of control transistor, and the second type of switch signal terminals in the first type of panel area and the second type of panel area are both used to control the conduction of the second type of switch transistor. In the third stage, the third type of control signal ends in the first type of panel area and the second type of panel area are both used to control the conduction of the third type of control transistor, and the third type of switch signal ends in the first type of panel area and the second type of panel area are both used to control the conduction of the third type of switch transistor.

15. The display panel motherboard according to claim 9, characterized in that: The first type of control transistor, the second type of control transistor and the third type of control transistor are arranged at intervals in the first direction, And / or, the first type of switch transistors, the second type of switch transistors and the third type of switch transistors are arranged at intervals in the first direction.

16. The display panel motherboard according to claim 15, characterized in that: The arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the first type of panel area is the same as the arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the second type of panel area, Or, the arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the first type of panel area is different from the arrangement of the first type of control transistors, the second type of control transistors and the third type of control transistors in the second type of panel area.

17. The display panel motherboard according to claim 7, characterized in that: The display panel further comprises a control signal line, a switch signal line and a lighting signal line. In a single panel area, the control end of the test control transistor is connected to the control signal end through the control signal line, the control end of the test switch transistor is connected to the switch signal end through the switch signal line, and the second end of the test switch transistor is connected to the lighting signal end through the lighting signal line. Among them, at least part of the control signal lines extend along the first direction, and / or at least part of the switch signal lines extend along the first direction, and / or at least part of the lighting signal lines extend along the first direction.

18. The display panel motherboard according to any one of claims 1 to 17, characterized in that: The display panel includes a substrate and an isolation structure arranged on one side of the substrate, the isolation structure encloses an isolation opening, the sub-pixel includes a light-emitting device and a driving circuit connected to the light-emitting device, the light-emitting device is at least partially located in the isolation opening, the driving circuit is arranged in the substrate, the isolation structure includes a first isolation portion and a second isolation portion located on a side of the first isolation portion away from the substrate, the second isolation portion is arranged to protrude from the first isolation portion toward the isolation opening.

19. A display panel, characterized in that: The display panel motherboard is prepared by any one of claims 1 to 18.

20. A display device, characterized in that: Comprising the display panel as claimed in claim 19.

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