Broadband receiving digital beam former

Abstract

The invention relates to the technical field of signal processing, and discloses a broadband receiving digital beam former. The broadband receiving digital beam former comprises a plurality of receiving channels and an accumulation module. Wherein each receiving channel comprises an analog-to-digital converter which is used for sampling an input analog signal and outputting a plurality of parallel first digital signals according to a time sequence; the digital mixer is used for multiplying the plurality of paths of first digital signals with two paths of orthogonal local oscillation signals on carrier frequency generated by the numerical control oscillator to obtain a plurality of paths of second digital signals; the digital time delayer module is used for carrying out time delay on the plurality of paths of second digital signals to obtain a plurality of paths of third digital signals; and the accumulation module is used for adding the plurality of paths of third digital signals to obtain two paths of output signals after beam forming. According to the scheme, the resource utilization rate in the broadband digital beam forming system can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and particularly to a broadband receiving digital beamformer. Background Art

[0002] Digital Beamforming (DBF) forms a receiving beam during digital processing after the sensor completes A / D conversion. Therefore, the system can have a very high dynamic range. At the same time, digital beamforming can form multiple beams simultaneously and has higher reliability, which is the main research direction of future beamforming technology.

[0003] At present, the high-resolution algorithms for narrowband signals have tended to be mature. However, with the continuous advancement of technology, the environment in which signal processing is located has become increasingly complex, the signal density has been continuously increasing, and its frequency coverage range has also been continuously extended. This has greatly increased the distribution range and density of signals in the spatial and frequency domains. Narrowband communication technology is suitable for simple application scenarios because of its low cost and easy operation, but it can only transmit a small amount of data. Obviously, such characteristics are no longer able to meet the stringent requirements of modern communication in terms of transmission rate, accuracy, reliability, and transmission distance.

[0004] In contrast, broadband signals have significant advantages such as large information-carrying capacity, rapid transmission rate, and strong signal stability. Thus, moving towards broadband is one of the core trends in the development of future communication technologies. If the traditional narrowband beamforming algorithm implemented by a phase shifter is directly applied to broadband signals, signal dispersion will occur due to the difference between the upper and lower limits of the signal frequency. Therefore, broadband digital beamforming for broadband signals is required.

[0005] Digital beamforming requires a large amount of hardware resources and calculations, resulting in higher power consumption than analog beamforming. Especially for broadband signals with high data rates, when designing the system, methods such as parallelization need to be used to reduce the clock frequency, leading to a further increase in resource consumption. Summary of the Invention

[0006] In view of this, the present invention provides a broadband receiving digital beamformer to solve the problem of excessively high power consumption of traditional digital beamformers.

[0007] The present invention provides a broadband receiving digital beamformer, which includes: a plurality of receiving channels and an accumulation module;

[0008] Wherein each receiving channel includes:

[0009] An analog-to-digital converter for sampling the input analog signal and outputting a plurality of parallel first digital signals in chronological order;

[0010] A digital mixer for multiplying several first digital signals with local oscillator signals on two orthogonal carrier frequencies generated by a numerically controlled oscillator to obtain several second digital signals;

[0011] A digital time delay module for time-delaying the several second digital signals to obtain several third digital signals;

[0012] An accumulation module for adding the several third digital signals to obtain two output signals after beamforming.

[0013] The broadband receiving digital beamformer provided by the embodiment of the present invention can efficiently implement subsequent digital processing processes by sampling analog signals in an analog-to-digital converter and converting them into multiple parallel first digital signals, reducing the processing burden of a single processing unit and reducing the demand for hardware resources; the digital mixer multiplies the first digital signals output by the analog-to-digital converter with local oscillator signals on two orthogonal carrier frequencies generated by the numerically controlled oscillator, which not only realizes the frequency conversion of the first digital signals but also can separately extract the amplitude information and phase information of the first digital signals; the digital time delay applies a time delay to the second digital signals to obtain third digital signals, facilitating the implementation of beam pointing control; the accumulation module adds the signals after time delay of multiple channels to obtain two I and Q output signals after beamforming, which can realize beam enhancement and orientation.

[0014] In an optional implementation manner, each receiving channel of the broadband receiving digital beamformer further includes: a low-pass filter for performing low-pass filtering on the several second digital signals; the low-pass filter includes an anti-aliasing sampling filter.

[0015] By setting a low-pass filter including an anti-aliasing sampling filter, the broadband receiving digital beamformer provided by the embodiment of the present invention can filter out unwanted high-frequency harmonic signals, reduce the signal sampling rate, and relieve the resource consumption pressure in subsequent signal processing.

[0016] In an optional implementation manner, the digital time delay module includes: an integer time delay for storing several third signals into a register queue in chronological order and obtaining a delayed signal through shifting according to preset delay information; a fractional time delay including a fractional delay filter for simulating a delayed signal of a non-integer time unit.

[0017] In the broadband receiving digital beamformer provided by the embodiment of the present invention, the delay of integer samples is realized through a register queue and shift operations. This not only has a relatively simple implementation method and consumes less hardware resources, but also enables the integer time delay unit to have the characteristics of high precision and low error. The fractional delay filter is used to realize the delay of non-integer time units, enabling the fractional time delay unit to accurately control the fine-grained change of the delay. In this way, the digital time delay unit composed of the integer time delay unit and the fractional time delay unit can adapt to a wider range of signal processing scenarios.

[0018] In an alternative embodiment, the fractional time delay unit is an FIR filter.

[0019] For the broadband receiving digital beamformer provided by the embodiment of the present invention, selecting an FIR filter as the fractional time delay unit can have the advantages of high stability, simple design, flexible frequency response, etc., and can ensure the linear phase characteristic, avoiding the phase distortion of the output signal.

[0020] In an alternative embodiment, the impulse response of the fractional time delay unit is expressed as:

[0021] h id =sinc(n - D)

[0022] where n is the channel number, and D is the fractional part of the delay of the i-th array element relative to the reference array element.

[0023] For the broadband receiving digital beamformer provided by the embodiment of the present invention, by clarifying the impulse response of the fractional time delay unit, it is convenient to intuitively display and analyze the delay effect, which is beneficial to the control adjustment and performance optimization of the digital time delay unit.

[0024] In an alternative embodiment, the filter coefficients of the fractional time delay unit are calculated using the Chebyshev windowing method and stored separately.

[0025] For the broadband receiving digital beamformer provided by the embodiment of the present invention, selecting the Chebyshev windowing method to determine the filter coefficients of the fractional time delay unit can reduce the filter order, and thus can reduce the number of multipliers and resource consumption. In addition, compared with other windowing algorithms, selecting the Chebyshev window function can have lower delay fluctuations while ensuring the linear delay bandwidth.

[0026] In an alternative embodiment, the digital mixer is based on the CORDIC algorithm to realize the generation and mixing of the local oscillator signal.

[0027] The broadband receiving digital beamformer provided by the embodiment of the present invention uses a cordic algorithm structure to replace the multiplier structure of the traditional mixer, which can be completed only by using a shift and addition structure, reducing the number of multipliers in the circuit, not only saving the hardware cost, but also greatly reducing the overall power consumption of the digital mixer.

[0028] In an alternative embodiment, the anti-aliasing sampling filter includes a folded interpolation type HB-FIR filter; the folded interpolation type HB-FIR filter includes an HB-FIR filter that splits the original FIR filter into an odd number of parallel sub-filters through a folding structure and inserts zero values between adjacent sampling points; the coefficient of the center phase sub-filter of the folded interpolation type HB-FIR filter is 0.5, the coefficients of the even phase sub-filters except the coefficient of the center phase sub-filter are 0, and the coefficients of the odd phase sub-filters except the coefficient of the center phase sub-filter are even symmetric.

[0029] The broadband receiving digital beamformer provided by the embodiment of the present invention uses a folded interpolation type half-band low-pass filter in the anti-aliasing sampling filter part to replace the traditional low-pass filter. For the same filter cut-off frequency, the folded interpolation type FIR filter can save half of the multipliers compared with the direct type FIR filter and consumes fewer resources.

[0030] In an alternative embodiment, the anti-aliasing sampling filter includes a folded interpolation type 10th-order HB-FIR filter.

[0031] The broadband receiving digital beamformer provided by the embodiment of the present invention, the 10th-order HB-FIR filter can achieve a passband and stopband bandwidth of 500 MHz and a stopband suppression of -40 dB. It is a preferred filter structure that can meet most actual application scenarios.

[0032] In an alternative embodiment, the fractional time delay unit includes a 16th-order fractional delay filter.

[0033] The broadband receiving digital beamformer provided by the embodiment of the present invention, preferably a 16th-order fractional delay filter, can adopt a coefficient scaling method to ensure that the delay accuracy of the fractional time delay unit reaches 1 / 512 sampling periods, achieving a balance between high delay accuracy and low resource consumption.

[0034] The broadband receiving digital beamformer provided by one or more embodiments of the present invention can effectively reduce the resource utilization rate in the broadband digital beamforming system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings required for the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of a broadband receiving digital beamformer according to an embodiment of the present invention;

[0037] Figure 2 It is a schematic structural diagram of a folded interpolation type HB-FIR filter according to an embodiment of the present invention;

[0038] Figure 3 It is a schematic structural diagram of a fractional delay filter according to an embodiment of the present invention;

[0039] Figure 4 It is a schematic structural diagram of a single channel of a broadband receiving digital beamformer according to an embodiment of the present invention;

[0040] Figure 5 It is a schematic diagram of an application antenna array according to an embodiment of the present invention. Specific Embodiments

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0042] The broadband receiving digital beamformer provided by an embodiment of the present invention can be used in a variety of fields. For example, it can be used in a radar system for target detection and tracking; it can be used in a communication system for beamforming and interference coordination; it can be used in a direction finding and positioning system for high-precision direction finding, positioning, and tracking.

[0043] Please refer to Figure 1 , the broadband receiving digital beamformer provided by an embodiment of the present invention may include a plurality of receiving channels and an accumulation module. Among them, each receiving channel may include:

[0044] An analog-to-digital converter, configured to sample the input analog signal and output a plurality of parallel first digital signals in chronological order;

[0045] A digital mixer is used to multiply several first digital signals with local oscillator signals on two orthogonal carrier frequencies generated by a numerically controlled oscillator to obtain several second digital signals;

[0046] A digital time delay module is used to perform time delay on the several second digital signals to obtain several third digital signals;

[0047] An accumulation module is used to add the several third digital signals to obtain two output signals after beamforming.

[0048] In this embodiment, by sampling and converting an analog signal into multiple parallel first digital signals in an analog-to-digital converter, the subsequent digital processing process can be efficiently implemented, reducing the processing burden on a single processing unit and lowering the demand for hardware resources. The digital mixer multiplies the first digital signal output by the analog-to-digital converter with the local oscillator signals on two orthogonal carrier frequencies generated by a numerically controlled oscillator, which not only realizes the frequency conversion of the first digital signal but also can separately extract the amplitude information and phase information of the first digital signal; the digital time delay module applies a time delay to the second digital signal to obtain a third digital signal, facilitating the implementation of beam pointing control; the accumulation module adds the signals of multiple channels after time delay to obtain two I and Q output signals after beamforming, which can realize beam enhancement and directivity.

[0049] Specifically, after receiving an analog signal, the analog-to-digital converter can sample and quantize it, and divide the quantized signal into multiple parallel first digital signals according to the time sequence. The output of the analog-to-digital converter is multiple parallel digital signals.

[0050] The digital mixer can multiply the first digital signal output by the analog-to-digital converter with the local oscillator signals on two orthogonal carrier frequencies generated by a Numerically Controlled Oscillator (NCO) to obtain a baseband signal with zero intermediate frequency (i.e., the second digital signal) and a high-frequency harmonic signal.

[0051] The digital time delay module can perform time delay on the baseband signal with zero intermediate frequency after sampling and output a third digital signal delayed by a preset time.

[0052] The accumulation module can add the third digital signals of multiple channels after time delay to obtain two I and Q output signals after beamforming.

[0053] In some alternative embodiments, each of the receiving channels of the broadband receiving digital beamformer further includes a low-pass filter. The low-pass filter is used to perform low-pass filtering on a plurality of second digital signals. The low-pass filter may include an anti-aliasing sampling filter.

[0054] By providing a low-pass filter including an anti-aliasing sampling filter, unwanted high-frequency harmonic signals mixed in the second digital signals can be filtered out, the sampling rate of the second digital signals can be reduced, and the resource consumption pressure in subsequent signal processing can be alleviated.

[0055] In an alternative embodiment, the anti-aliasing sampling filter includes a folded interpolation type HB-FIR filter; the folded interpolation type HB-FIR filter includes an HB-FIR filter that splits the original FIR filter into an odd number of parallel sub-filters through a folding structure and inserts zero values between adjacent sampling points; the coefficient of the central phase sub-filter of the folded interpolation type HB-FIR filter is 0.5, the coefficients of the even-phase sub-filters other than the coefficient of the central phase sub-filter are 0, and the coefficients of the odd-phase sub-filters other than the coefficient of the central phase sub-filter are even-symmetric.

[0056] Specifically, the role of the anti-aliasing sampling filter module is to suppress the high-frequency components generated after mixing and the high-frequency noise that may cause aliasing in time-domain decimation. The anti-aliasing sampling filter is essentially a low-pass filter. To retain the non-distorted phase information, an FIR filter can be used to implement it. The folded interpolation type FIR filter can save half of the multipliers compared to the direct type FIR filter and consumes fewer resources. For example, a traditional low-pass filter of the same order (nth order) and the same cut-off frequency requires n multipliers, while the folded interpolation type half-band filter only requires (n - 1) / 2 multipliers. To further reduce resource consumption, a folded interpolation type FIR filter with an odd N can be selected as the anti-aliasing sampling filter.

[0057] Please refer to Figure 2 , in a practical application example, the coefficients of the even terms of the folded interpolation type HB-FIR filter except the central term can be set to 0, the coefficient of the central phase sub-filter can be set to 0.5, and the coefficients of the odd terms can be set to be even-symmetric. Since the coefficients of the even terms of the HB-FIR filter are 0, the multiplication operation can be directly omitted. The coefficient of the central phase sub-filter is fixed at 0.5 and can be implemented by means of shifting, further reducing the use of multiplier and adder resources compared to ordinary FIR filters. The passband and stopband of the HB-FIR filter are symmetric with respect to half of the Nyquist frequency. By using the folded interpolation type HB-FIR filter as the anti-aliasing sampling filter, the broadband receiving digital beamformer of the present invention can save a large amount of resources.

[0058] In a practical application example, the anti-aliasing sampling filter includes a 10th-order HB-FIR filter of the folding interpolation type, and the decimation factor can be 2. The 10th-order HB-FIR filter can achieve a passband and stopband bandwidth of 500 MHz, as well as a stopband suppression of -40 dB. It is a preferred filter structure that can meet most practical application scenarios.

[0059] In some embodiments, the digital mixer is based on the cordic algorithm to generate and mix the local oscillator signal.

[0060] The broadband receiving digital beamformer provided by the embodiments of the present invention uses a cordic algorithm structure to replace the multiplier structure of the traditional mixer. It can be completed only by using a structure of shifting and adding, which reduces the number of multipliers in the circuit. It not only saves the hardware cost but also greatly reduces the overall power consumption of the digital mixer.

[0061] Specifically, the cordic algorithm can simultaneously generate the local oscillator signal and mix the first digital signal with the local oscillator signal. The principle of the cordic algorithm is to realize the rotation of the signal through multiple iterations of shifting and adding. Compared with the traditional RAM look-up table method, the cordic algorithm does not need to use a large amount of storage resources to store phase values and their corresponding sine values, and at the same time, it does not need to use parallel multipliers to multiply the input signal by the found sine value to complete the mixing work.

[0062] In some optional embodiments, the digital time delay module includes: an integer time delay unit for storing several third signals into a register queue in chronological order and obtaining a delayed signal by shifting according to preset delay information; a fractional time delay unit including a fractional delay filter for simulating a delayed signal of a non-integer time unit.

[0063] In the broadband receiving digital beamformer provided by the embodiments of the present invention, the delay of integer samples is realized through a register queue and shifting operations. It not only has a relatively simple implementation method and less consumption of hardware resources, but also makes the integer time delay unit have the characteristics of high precision and low error; the delay of non-integer time units is realized by using a fractional delay filter, so that the fractional time delay unit can accurately control the fine-grained change of the delay. In this way, the digital time delay module composed of the integer time delay unit and the fractional time delay unit can adapt to a wider range of signal processing scenarios. For example, fields such as digital communication, speech processing, mathematical modeling of sound, and echo cancellation.

[0064] In an optional embodiment, the fractional time delay unit is an FIR filter.

[0065] The broadband receiving digital beamformer provided by the embodiment of the present invention selects an FIR filter as the fractional time delay device, which can have the advantages of high stability, simple design, flexible frequency response, etc., and ensures the linear phase characteristic, avoiding the phase distortion of the output signal.

[0066] In an alternative embodiment, the impulse response of the fractional time delay device is expressed as:

[0067] h id =sinc(n - D)

[0068] where n is the channel number, and D is the fractional part of the delay of the i-th array element relative to the reference array element.

[0069] The broadband receiving digital beamformer provided by the embodiment of the present invention facilitates the intuitive display and analysis of the delay effect by clarifying the impulse response of the fractional time delay device, which is beneficial to the control adjustment and performance optimization of the digital time delay device.

[0070] It should be noted that in this impulse response formula, when D is not an integer, the filter is non-causal and physically unrealizable. To solve this problem, there are various implementation methods such as the windowing method, the maximum flatness criterion method, and the Farrow structure filter method. Among them, to obtain an equal linear time delay bandwidth, the windowing method requires the least number of filter orders, so this method can be preferentially selected to calculate the filter coefficients. Commonly used windows include the Hamming window, the Chebyshev window, etc.

[0071] In a practical application example, the filter coefficients of the fractional time delay device are calculated using the Chebyshev windowing method and stored separately.

[0072] Selecting the Chebyshev windowing method to determine the filter coefficients of the fractional time delay device can reduce the filter order, and thus can reduce the number of multipliers and resource consumption. In addition, compared with other windowing algorithms, selecting the Chebyshev window function can have lower delay fluctuations while ensuring the linear time delay bandwidth.

[0073] In an alternative embodiment, the fractional time delay device includes a 16th-order fractional delay filter.

[0074] The broadband receiving digital beamformer provided by the embodiment of the present invention preferably uses a 16th-order fractional delay filter, which can adopt the coefficient scaling method to ensure that the delay accuracy of the fractional time delay device reaches 1 / 512 sampling periods, achieving a balance between high delay accuracy and low resource consumption.

[0075] Specifically, please refer to Figure 3, in terms of circuit implementation, for a fractional delay filter, a filter coefficient storage module can be designed to store 512 groups of coefficients, corresponding to time delays of the fractional time delay unit ranging from 0 to 1 sampling point respectively, so that the delay accuracy of the fractional time delay unit is 1 / 512 sampling period. According to the input delay information, the filter coefficient storage module can select the corresponding filter coefficients and output them to the fractional delay filter. By using the fractional delay filter with the filter coefficients set, the signal input to the fractional time delay unit can obtain different fractional time delays after being filtered.

[0076] To further reduce the resources occupied by the fractional delay filter, the filter coefficients can be scaled to limit the floating range of the filter coefficients corresponding to multipliers of different orders. According to the coefficient range corresponding to each order of multiplier after scaling, the number of bits of the multiplier can be flexibly selected, reducing the use of the multiplier and the burden of resource consumption. In particular, multiplying the filtered data by a gain can compensate for the amplitude loss caused by the coefficient scaling.

[0077] A broadband receiving digital beamformer provided by an embodiment of the present invention may include a number of receiving channels, and each single receiving channel may have 16 data transmission channels for parallel data transmission. The signal sampling rate of the broadband receiving digital beamformer may be 4 Gsps, the working clock may be 250 MHz, the signal modulation mode may be QPSK modulation, the working bandwidth B may be 500 MHz, and the radio frequency carrier frequency fc may be 3 GHz.

[0078] In this embodiment, please refer to Figure 4 and Figure 5 , the specific structure of each single channel of the broadband receiving digital beamformer may be as shown in Figure 4 . Among them, the decimation factor of the decimation filter bank may be 2. The broadband receiving digital beamformer can be used to process the signals generated by the antenna array shown in Figure 5 . Among them, the element spacing of the antenna array may be 4 cm.

[0079] Specifically, taking the 0th element as a reference, the signal received by the 0th element may be:

[0080] s0(t) = I(n)cos(2πf c n) + Q(n)sin(2πf c n)

[0081] The signal received by the ith element may be:

[0082] s i (t) = I(n + Δt i )cos(2πf c (n + Δt i)) + Q(n + Δt i )sin(2πf c (n + Δt i ))

[0083] where Δt i is the time interval between signals received by two adjacent array elements. Δt i depends on the element spacing d and the angle θ between the incident signal and the normal direction of the antenna array. The specific relationship is:

[0084]

[0085] where c is the speed of light.

[0086] The phase difference between adjacent array elements is denoted as and its formula is:

[0087]

[0088] In the digital mixer, the phase difference between different array elements at the carrier frequency can be compensated. Phase compensation is added to the frequency control word of the digital mixer to eliminate the phase difference at the carrier frequency. Then, using the cordic algorithm, the generation and mixing of the data local oscillator signal can be achieved simultaneously.

[0089] The local oscillator signals for mixing the received signal of the first array element are cos(2πf c (n + Δt)) and sin(2πf c (n + Δt)). The I-channel signal obtained after mixing is:

[0090]

[0091] The Q-channel signal obtained after mixing is:

[0092]

[0093] The function of the anti-aliasing and decimation filter module is to suppress 2f generated after mixing cHigh-frequency components on it, as well as high-frequency noise that may cause aliasing in time-domain decimation. The decimation filter is essentially a low-pass filter. To preserve the non-distorted phase information, an FIR filter can be used to implement it. The folded interpolated FIR filter can save half of the multipliers compared to the direct-form FIR filter and consume fewer resources. To further reduce resource consumption, a folded interpolated FIR filter with N being an odd number is selected for improvement. Set the even-numbered coefficients of this filter except the central term to 0, the coefficient of the central phase sub-filter to 0.5, and the odd-numbered coefficients to even symmetry. The filter with this structure is called the HB-FIR filter. The even-numbered coefficients of the HB-FIR filter are 0, and the multiplication operation can be directly omitted. The coefficient of the central phase sub-filter is fixed at 0.5 and can be implemented by shifting, which further reduces the use of multipliers and adders compared to ordinary FIR filters. The passband and stopband of the HB-FIR filter are symmetric with respect to half of the Nyquist frequency. Using the folded interpolated HB-FIR filter to achieve 2-fold decimation can save a large amount of resources.

[0094] In this embodiment, a 10th-order HB-FIR filter is used, with a passband and stopband bandwidth of 500 MHz, a stopband rejection of -40 dB, a decimation factor of 2, and the sampling rate of the signal output after decimation by the decimation filter is 2 Gsps. The theoretical value of the I-channel signal after low-pass filtering is:

[0095]

[0096] The Q-channel signal is:

[0097]

[0098] Input the delay required for each array element's received signal into the time-delay module. When the sampling period is T, the time delay to be compensated for the k-th array element can be expressed as:

[0099] τ k / T = L + Δ

[0100] L represents an integer multiple of the time delay, and Δ represents a fractional multiple of the sampling period time delay.

[0101] The integer multiple time-delay module successively stores continuous signals into the register queue and shifts the signals in the queue according to the input delay information to obtain the delayed signal.

[0102] The fractional time-delay module uses a fractional delay filter design. The role of the fractional delay filter is to simulate an ideal non-integer time unit delay device and is widely used in fields such as digital communication, speech processing, mathematical modeling of sound, and echo cancellation.

[0103] The fractional delay filter is implemented using the structure of an FIR filter. The impulse response of an ideal fractional delay filter can be expressed as:

[0104] h id = sinc(n - D)

[0105] When D is not an integer, the filter represented by the above formula is non-causal and physically unrealizable. To solve this problem, there are various implementation methods such as the windowing method, the maximum flatness criterion method, and the Farrow structure filter method. Among them, to obtain an equal linear delay bandwidth, the windowing method requires the fewest filter orders. Therefore, this method is selected to calculate the filter coefficients.

[0106] Perform windowing on the above formula. Commonly used windows include the Hamming window, the Chebyshev window, etc. In this embodiment, the Chebyshev window function is selected, which has lower delay fluctuations within the linear delay bandwidth.

[0107] This embodiment uses a 16th-order fractional delay filter and adopts a coefficient scaling method to ensure that the delay accuracy of the fractional time delay device reaches 1 / 512 sampling periods, achieving a balance between high delay accuracy and low resource consumption. For specific details, refer to the relevant description in the above text Figure 3 and will not be elaborated here.

[0108] The 16th-order fractional delay filter used in this embodiment has a linear delay bandwidth of 700 MHz at a sampling rate of 2 Gsps. The theoretical values of the I and Q channels of the signal after passing through the digital time delay device are:

[0109]

[0110]

[0111] The accumulation module adds and sums the delayed signals output by the digital time delay modules of multiple array element channels to obtain the output signal after beamforming.

[0112] In this embodiment, the broadband receiving digital beamformer can effectively complete the downconversion and beamforming of radio frequency signals.

[0113] The broadband receiving digital beamformer provided by this embodiment consumes less resources compared with the traditional structure, especially for a multi-channel parallel high-speed digital signal processing system, and the effect is more obvious. For the structure with 16 data transmission channels in parallel described in this example, a single data channel of the digital down-conversion module in the traditional structure requires 16 + 8×12 = 112 multipliers, while this example uses a cordic algorithm circuit and an HB-FIR filter, and only 64 multipliers are required for a single data channel. In the digital time delay module, this example always adopts a coefficient scaling method to implement the filter, and the multiplier IP in the XCZU47DR FPGA chip can be used for synthesis. In the obtained synthesis result, the occupancy of a single fractional delay filter on the LUT is reduced by 40% compared with the traditional method of directly inputting coefficients. In summary, the broadband receiving digital beamformer provided by this embodiment effectively reduces the resource utilization rate in the broadband digital beamforming system.

[0114] The broadband receiving digital beamformer provided by one or more embodiments of the present invention can effectively reduce the resource utilization rate in the broadband digital beamforming system and solve the problem of excessive power consumption of the traditional digital beamformer.

[0115] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments.

[0116] The above description is only for the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0117] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A broadband receiving digital beamformer, characterized in that: The broadband receiving digital beamformer comprises: a plurality of receiving channels and an accumulation module; Each of the receiving channels comprises: An analog-to-digital converter, used for sampling an input analog signal and outputting a plurality of parallel first digital signals according to a time sequence; A digital mixer, used for multiplying the plurality of first digital signals with local oscillator signals at two orthogonal carrier frequencies generated by a digitally controlled oscillator, respectively, to obtain a plurality of second digital signals; A digital time delay module, used for time delaying the plurality of second digital signals to obtain a plurality of third digital signals; The accumulation module is used to add the plurality of third digital signals to obtain two output signals after beamforming.

2. The broadband receiving digital beamformer according to claim 1, characterized in that: Each of the receiving channels further comprises: A low-pass filter is used to perform low-pass filtering on the plurality of second digital signals; the low-pass filter includes an anti-aliasing sampling filter.

3. The broadband receiving digital beamformer according to claim 1 or 2, characterized in that: The digital time delay module comprises: An integer time delayer, used for storing the plurality of third digital signals into a register queue in time sequence, and obtaining a delayed signal by shifting according to preset delay information; Fractional time delayers, including fractional time delay filters, are used to simulate delayed signals of non-integer time units.

4. The broadband receiving digital beamformer according to claim 3, characterized in that: The fractional time delay device is a FIR filter.

5. The broadband receiving digital beamformer according to claim 4, characterized in that: The impulse response of the fractional time delay can be expressed as: h id =sinc(n-D) Where n is the channel number and D is the fractional part of the delay of the ith array element relative to the reference array element.

6. The broadband receiving digital beamformer according to claim 5, characterized in that: The filter coefficients of the fractional time delay are calculated using the Chebyshev windowing method and stored separately.

7. The broadband receiving digital beamformer according to claim 1 or 2, characterized in that: The digital mixer is based on a cordic algorithm to achieve the generation and mixing of the local oscillator signal.

8. The broadband receiving digital beamformer according to claim 2, characterized in that: The anti-aliasing sampling filter includes a folded interpolation type HB-FIR filter; the folded interpolation type HB-FIR filter includes a HB-FIR filter that splits the original FIR filter into an odd number of parallel sub-filters through a folding structure and inserts zero values ​​between adjacent sampling points; the coefficient of the center phase sub-filter of the folded interpolation type HB-FIR filter is 0.5, the coefficient of the even phase sub-filter other than the coefficient of the center phase sub-filter is 0, and the coefficient of the odd phase sub-filter other than the coefficient of the center phase sub-filter is even symmetric.

9. The broadband receiving digital beamformer according to claim 8, characterized in that: The anti-aliasing sampling filter includes a folded interpolation type 10th order HB-FIR filter.

10. The broadband receiving digital beamformer according to claim 3, characterized in that: The fractional time delay device comprises a 16th order fractional time delay filter.

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